Method and device for quickly finding new and old data relationships in multiple memory banks

Abstract

An embodiment of the present application provides a method and device for quickly finding new and old data relationships in multiple memory banks, the method comprising: constructing an overall data relationship matrix based on a memory access request number, a memory bank number, and a memory access time, and taking the memory access request number of the same memory bank number and its corresponding memory access time as a group of data relationship matrices to obtain two groups of data relationship matrices; concurrently determining the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices, as the first, second, and third memory access request numbers, respectively; determining a first new data relationship based on the first memory access request number and its corresponding memory bank number; excluding the second target memory bank number or the third target memory bank number, and taking the memory access request number obtained after exclusion as the second new memory access request number, and taking its corresponding memory bank number as the second new data relationship, thereby solving the timing problem.

Description

Technical Field

[0001] The present application relates to the field of microprocessor architecture technology, and in particular to a method and device for quickly finding the new and old relationship of data in multiple memory banks. Background Art

[0002] In existing microprocessor architectures, the memory access unit is a part of the microprocessor that handles memory read and write operations. A multi-bank memory system generally refers to the internal organization of dynamic random access memory, where the memory is divided into multiple banks, each of which can be read and written independently. In a multi-bank access scenario, the memory access unit needs to coordinate access to different banks to achieve higher memory bandwidth and lower latency. For example:

[0003] In the memory bank interleaving technology, by interleaving access to different memory banks for consecutive addresses, read and write operations of multiple memory banks can be initiated simultaneously, thereby improving the parallelism of memory access.

[0004] In memory bank conflict resolution, when the target addresses of multiple memory requests are located in the same memory bank, the memory access unit needs to use a certain scheduling strategy to avoid memory bank conflicts, ensure the orderliness of memory access, and minimize the time waiting for the memory bank to be ready.

[0005] In the prefetch and cache strategy, the memory access unit may cooperate with the cache system to predictively access data in different memory banks and fill the cache in advance to reduce possible memory bank conflicts in the future and improve memory access performance.

[0006] In a multi-bank memory system, the memory access unit must also consider the newness and oldness of data when accessing memory. Scenarios requiring consideration of the newness and oldness of data across multiple banks typically occur in the following situations:

[0007] First, cache coherence: In a multi-core processor system, each core has its own memory access unit and cache system. When multiple cores simultaneously access shared memory areas distributed across different memory banks, to maintain cache coherence, the memory access unit must participate in the cache coherence protocol to determine and update the cached data, ensuring that all cores see the latest data.

[0008] Second, memory bank conflicts and access scheduling: When the target addresses of multiple memory requests fall into the same memory bank, and other memory banks have earlier memory requests waiting to be serviced, the memory access unit needs to make judgments and schedule to ensure that the first-in-first-out principle or other optimized scheduling strategies are followed to avoid errors caused by disrupting the access order of new and old data.

[0009] Third, prefetch and replacement strategies: In a multi-bank memory prefetch strategy, the memory access unit may need to analyze memory access patterns to preload data from different banks. In this case, the memory access unit needs to assess the data's recency and expected access order, and arrange prefetch operations appropriately to avoid needlessly replacing "young" data that will be used again.

[0010] Fourth, multi-channel memory access: If the processor supports multi-channel memory access, the memory access unit needs to consider the access timing between different channels when accessing multiple memory banks, ensure data consistency between channels, and optimize the utilization of memory banks and channels, so that access to new and old data can be carried out in an orderly manner, thereby improving system performance.

[0011] Therefore, for the combined scenario where a memory access unit needs to maintain a new-old relationship when accessing multiple memory banks, the following problems need to be solved:

[0012] Now a memory access unit needs to find the relationship between the first "youngest" and the second "youngest" data from N memory access requests, and each memory access request may belong to memory bank 0 or memory bank 1. If the first "youngest" data is found from memory bank 0, the second "youngest" data cannot be found from memory bank 0. It is necessary to exclude memory bank 0 (M memory access requests) and search again from the remaining NM memory access requests. In related technologies, such as Figure 1 As shown, for the memory access unit accessing multiple memory banks, it is necessary to maintain a combination scenario of new and old relationships. Figure 1 The combinational logic delay required to find the second "youngest" data relationship is roughly divided into three steps: First, a data relationship matrix is ​​input from N memory access requests with the memory bank 0 / memory bank 1 identifier. An age matrix algorithm is used to find the first "youngest" data relationship. Second, after obtaining the results of the first step, a comparison logic is used to exclude the interval (memory bank 0 / memory bank 1) in which the first "youngest" memory access request is found, resulting in a new data relationship matrix sequence. Third, the new data relationship matrix sequence obtained in the second step is used again to obtain the second "youngest" data relationship from NM memory access requests through the age matrix algorithm.

[0013] Therefore, related technologies require two age matrix algorithms and a comparison logic to find the second "youngest" data relationship. This results in an excessively long combination path and very poor timing. Summary of the Invention

[0014] Embodiments of the present application provide a method, apparatus, computer device, and storage medium for quickly finding the new and old relationships of data in multiple memory banks.

[0015] A first aspect of an embodiment of the present application provides a method for quickly finding the new and old relationship of data in multiple memory banks, comprising:

[0016] An overall data relationship matrix is ​​constructed based on the correspondence between the memory access request number, the memory bank number, and the memory access time. The memory access request number and the corresponding memory access time of the same memory bank number are used as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained.

[0017] Parallel determination of the memory access request numbers with the latest memory access times in the overall data relationship matrix and each group of data relationship matrices, as the first memory access request number, the second memory access request number, and the third memory access request number, respectively;

[0018] Using the first memory access request number as a first new memory access request number, and determining a first new data relationship according to the first new memory access request number and its corresponding memory bank number;

[0019] Based on the multiplexer, one of the second target memory bank number and the third target memory bank number is excluded according to the first memory access request number, and the second memory access request number or the third memory access request number obtained after exclusion is output as the second new memory access request number, and the second new memory access request number and its corresponding memory bank number are used as the second new data relationship.

[0020] In an optional embodiment of the present application, an overall data relationship matrix is ​​constructed based on the correspondence between the memory access request number, the memory bank number, and the memory access time, including:

[0021] The same memory access request number and its corresponding memory bank number and memory access time are taken as a row of the overall data relationship matrix, and all memory access request numbers and their corresponding memory bank numbers and memory access times constitute the overall data relationship matrix.

[0022] In an optional embodiment of the present application, the memory access request numbers of the same memory bank number and their corresponding memory access times are used as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained, including:

[0023] According to the type of memory bank number, the memory access request numbers with the same memory bank number in the overall data relationship matrix and their corresponding memory bank numbers and memory access times are taken as a set of data relationship matrices;

[0024] When the number of types of memory bank numbers is two, the overall data relationship matrix is ​​divided into two groups of data relationship matrices.

[0025] In an optional embodiment of the present application, the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices is determined in parallel as the first memory access request number, the second memory access request number, and the third memory access request number, respectively, including:

[0026] Input the overall data relationship matrix into the first processing module, and output the memory access request number with the latest memory access time in the overall data relationship matrix as the first memory access request number;

[0027] The two sets of data relationship matrices are input into the second processing module to the N+1th processing module, and the memory access request number with the latest memory access time in the first set of data relationship matrix and the second set of data relationship matrix is ​​output as the second memory access request number and the third memory access request number, respectively, wherein the second processing module to the N+1th processing module correspond to N memory access request numbers respectively.

[0028] In an optional embodiment of the present application, two sets of data relationship matrices are input into the second processing module to the N+1th processing module, and the memory access request number with the latest memory access time in the first set of data relationship matrix and the second set of data relationship matrix is ​​output as the second memory access request number and the third memory access request number, respectively, including:

[0029] The first memory access request number to the Nth memory access request number are stored correspondingly in the second processing module to the N+1th processing module respectively;

[0030] In each of the second processing module to the (N+1)th processing module, determining whether the data relationship matrix corresponding to the current memory access request number stored in the current processing module is the first group of data relationship matrices or the second group of data relationship matrices;

[0031] In a case where the data relation matrix corresponding to the current memory access request number is the first group of data relation matrices or the second group of data relation matrices, determining, according to the memory access time corresponding to the current memory access request number, whether the current memory access request number is the memory access request number with the latest memory access time in the first group of data relation matrices or the second group of data relation matrices;

[0032] When the current memory access request number is the memory access request number with the latest memory access time in the first group of data relationship matrix or the second group of data relationship matrix, the current memory access request number is used as the second memory access request number or the third memory access request number.

[0033] In an optional embodiment of the present application, excluding one of the second target memory bank number and the third target memory bank number according to the first memory access request number includes:

[0034] The target memory bank number that is the same as the first memory access request number is excluded from the second target memory bank number and the third target memory bank number.

[0035] In an optional embodiment of the present application, the second memory access request number or the third memory access request number obtained after the multiplexer output is excluded is used as the second new memory access request number, including:

[0036] In a case where the second target memory bank number is excluded, using the third memory access request number as the second new memory access request number;

[0037] When the third target memory bank number is excluded, the second memory access request number is used as the second new memory access request number.

[0038] A second aspect of an embodiment of the present application provides a device for quickly searching for new and old data relationships in multiple memory banks, comprising:

[0039] a construction module, configured to construct an overall data relationship matrix based on the correspondence between the memory access request number, the memory bank number, and the memory access time, and to use the memory access request number and the corresponding memory access time of the same memory bank number as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained;

[0040] A first determining module is used to concurrently determine the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices, respectively as the first memory access request number, the second memory access request number, and the third memory access request number;

[0041] a second determining module, configured to use the first memory access request number as a first new memory access request number, and determine a first new data relationship according to the first new memory access request number and its corresponding memory bank number;

[0042] A multiplexer is used to exclude one of the second target memory bank number and the third target memory bank number according to the first memory access request number, and output the second memory access request number or the third memory access request number obtained after exclusion as the second new memory access request number, and use the second new memory access request number and its corresponding memory bank number as the second new data relationship.

[0043] A third aspect of an embodiment of the present application provides a computer device comprising: a memory and a processor, the memory storing a computer program, and the processor implementing any of the steps of the above method for quickly finding the new and old relationships of data in multiple memory libraries when executing the computer program.

[0044] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the computer program implements the steps of any of the above methods for quickly finding the new and old relationships of data in multiple memory libraries.

[0045] The above technical solutions provided by the embodiments of the present application have at least some or all of the following advantages compared to the prior art:

[0046] The method for quickly finding the new and old relationships of data in multiple memory banks described in an embodiment of the present application constructs an overall data relationship matrix based on the correspondence between the memory access request number, the memory bank number and the memory access time, and takes the memory access request number of the same memory bank number and its corresponding memory access time as a group of data relationship matrices. When the number of types of memory bank numbers is two, two groups of data relationship matrices are obtained; the overall data relationship matrix and the memory access request number with the latest memory access time in each group of data relationship matrices are determined in parallel, and are respectively used as the first memory access request number, the second memory access request number and the third memory access request number; the first memory access request number is used as the The request number is used as the first new memory access request number, and the first new data relationship is determined according to the first new memory access request number and its corresponding memory bank number; based on the multiplexer, one of the second target memory bank number and the third target memory bank number is excluded according to the first memory access request number, and the second memory access request number or the third memory access request number obtained after exclusion is output as the second new memory access request number, and the second new memory access request number and its corresponding memory bank number are used as the second new data relationship. When finding the first new data relationship and the second new data relationship, only one age matrix algorithm is required. Compared with the related technology, the combination logic delay of an age matrix algorithm and a comparison logic is reduced, and the timing problem in the related technology is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0048] Figure 1 A flowchart of a method for quickly finding the new and old relationship of data in multiple memory banks provided by an embodiment of the related technology;

[0049] Figure 2 A flowchart of a method for quickly finding the new and old relationship of data in multiple memory banks provided by one embodiment of the present application;

[0050] Figure 3 A flowchart of a method for quickly finding the new and old relationship of data in multiple memory banks provided by another embodiment of the present application;

[0051] Figure 4 A schematic diagram of the structure of a device for quickly finding the new and old relationship of data in multiple memory banks provided by one embodiment of the present application;

[0052] Figure 5 A schematic diagram of the computer device structure provided for one embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

[0054] See Figure 2 The method for quickly searching for the new and old data relationship in multiple memory banks provided in the embodiment of the present application includes the following steps S100 to S400:

[0055] S100, constructing an overall data relationship matrix based on the correspondence between the memory access request number, the memory bank number, and the memory access time, taking the memory access request number of the same memory bank number and its corresponding memory access time as a set of data relationship matrices, and obtaining two sets of data relationship matrices when there are two types of memory bank numbers;

[0056] S200, determining in parallel the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices, and using them as the first memory access request number, the second memory access request number, and the third memory access request number respectively;

[0057] S300: Using the first memory access request number as a first new memory access request number, and determining a first new data relationship according to the first new memory access request number and its corresponding memory bank number;

[0058] S400. Based on the multiplexer, exclude one of the second target memory bank number and the third target memory bank number according to the first memory access request number, and output the second memory access request number or the third memory access request number obtained after exclusion as the second new memory access request number, and use the second new memory access request number and its corresponding memory bank number as the second new data relationship.

[0059] In an optional embodiment of the present application, in step S100, constructing an overall data relationship matrix based on the correspondence between the memory access request number, the memory bank number, and the memory access time includes:

[0060] The same memory access request number and its corresponding memory bank number and memory access time are taken as a row of the overall data relationship matrix. All memory access request numbers and their corresponding memory bank numbers and memory access times constitute the overall data relationship matrix. The overall data relationship matrix is ​​shown in Table 1 below, where entry1 to entryN represent the first to Nth memory access request numbers, bank0 and bank1 represent two memory bank numbers, and Time1 to TimeN represent memory access times.

[0061] Table 1

[0062]

[0063] In an optional embodiment of the present application, in step S100, the memory access request numbers of the same memory bank number and their corresponding memory access times are used as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained, including:

[0064] According to the type of memory bank number, the memory access request numbers with the same memory bank number in the overall data relationship matrix and their corresponding memory bank numbers and memory access times are taken as a set of data relationship matrices;

[0065] When there are two types of memory bank numbers, the overall data relationship matrix is ​​divided into two groups of data relationship matrices, where the two groups of data relationship matrices are shown in Table 2 and Table 3 below, respectively.

[0066] Table 2

[0067]

[0068] Table 3

[0069]

[0070] In an optional embodiment of the present application, in step S200, see Figure 3, and concurrently determining the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices as the first memory access request number, the second memory access request number, and the third memory access request number, respectively, including:

[0071] Input the overall data relationship matrix into the first processing module, and output the memory access request number with the latest memory access time in the overall data relationship matrix as the first memory access request number;

[0072] The two sets of data relationship matrices are input into the second processing module to the N+1th processing module, and the memory access request number with the latest memory access time in the first set of data relationship matrix and the second set of data relationship matrix is ​​output as the second memory access request number and the third memory access request number, respectively, wherein the second processing module to the N+1th processing module correspond to N memory access request numbers respectively.

[0073] In an optional embodiment of the present application, two sets of data relationship matrices are input into the second processing module to the N+1th processing module, and the memory access request number with the latest memory access time in the first set of data relationship matrix and the second set of data relationship matrix is ​​output as the second memory access request number and the third memory access request number, respectively, including:

[0074] The first memory access request number to the Nth memory access request number are stored correspondingly in the second processing module to the N+1th processing module respectively;

[0075] In each of the second processing module to the (N+1)th processing module, determining whether the data relationship matrix corresponding to the current memory access request number stored in the current processing module is the first group of data relationship matrices or the second group of data relationship matrices;

[0076] In a case where the data relation matrix corresponding to the current memory access request number is the first group of data relation matrices or the second group of data relation matrices, determining, according to the memory access time corresponding to the current memory access request number, whether the current memory access request number is the memory access request number with the latest memory access time in the first group of data relation matrices or the second group of data relation matrices;

[0077] When the current memory access request number is the memory access request number with the latest memory access time in the first group of data relationship matrix or the second group of data relationship matrix, the current memory access request number is used as the second memory access request number or the third memory access request number.

[0078] In an optional embodiment of the present application, when the current memory access request number is the memory access request number with the latest memory access time in the first group of data relationship matrix or the second group of data relationship matrix, the processing module corresponding to the current memory access request number outputs 1; when the current memory access request number is not the memory access request number with the latest memory access time in the first group of data relationship matrix or the second group of data relationship matrix, the processing module corresponding to the current memory access request number outputs 0, and the previous memory access request number output by the processing module as 1 is used as the second memory access request number or the third memory access request number.

[0079] In an optional embodiment of the present application, in step S400, excluding one of the second target memory bank number and the third target memory bank number according to the first memory access request number includes:

[0080] The target memory bank number that is the same as the first memory access request number is excluded from the second target memory bank number and the third target memory bank number.

[0081] In an optional embodiment of the present application, the second memory access request number or the third memory access request number obtained after the multiplexer output is excluded is used as the second new memory access request number, including:

[0082] In a case where the second target memory bank number is excluded, using the third memory access request number as the second new memory access request number;

[0083] When the third target memory bank number is excluded, the second memory access request number is used as the second new memory access request number.

[0084] See also Figure 3 For scenarios where a memory access module needs to maintain a new-old relationship when accessing multiple memory banks, the method of this application for quickly finding the new-old relationship of data in multiple memory banks has the following steps:

[0085] Input the overall data relationship matrix from N entries with Bank0 / Bank1 identifiers, and use the age matrix algorithm to find the first "youngest" data relationship in the overall data relationship matrix;

[0086] At the same time, when looking for the second "youngest" data relationship from N entries, both sets of data relationship matrices are input for each entry at the same time. Then, using the age matrix algorithm, we find out whether the current entry is the first "youngest" data relationship in the first or second set of data relationship matrices, and obtain the first "youngest" data relationship in the first and second sets of data relationship matrices.

[0087] The first "youngest" data relationship in the first and second groups of data relationship matrices is excluded from the first "youngest" data relationship in the overall data relationship matrix, and the second "youngest" entry can be directly selected through a multiplexer.

[0088] exist Figure 3 In the process of finding the first "young" data relationship and the second "young" data relationship, an age matrix algorithm is used at the same time. Compared with the related technology, the combination logic delay of an age matrix algorithm and a comparison logic is reduced.

[0089] It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0090] See Figure 4 One embodiment of the present application provides a device 400 for quickly searching for new and old data relationships in multiple memory banks, including:

[0091] A construction module 410 is configured to construct an overall data relationship matrix based on the correspondence between the memory access request numbers, the memory bank numbers, and the memory access times. The memory access request numbers and their corresponding memory access times for the same memory bank number are used as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained.

[0092] A first determining module 420 is configured to concurrently determine the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices, and use them as the first memory access request number, the second memory access request number, and the third memory access request number, respectively;

[0093] A second determining module 430 is configured to use the first memory access request number as a first new memory access request number, and determine a first new data relationship according to the first new memory access request number and its corresponding memory bank number;

[0094] Multiplexer 440 is used to exclude one of the second target memory bank number and the third target memory bank number according to the first memory access request number, and output the second memory access request number or the third memory access request number obtained after exclusion as the second new memory access request number, and use the second new memory access request number and its corresponding memory bank number as the second new data relationship.

[0095] The specific limitations of the apparatus 400 can be found in the above-mentioned limitations on the method for rapidly searching for the relationship between new and old data in multiple memory banks, and will not be further elaborated here. Each module in the apparatus 400 can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0096] In one embodiment, a computer device is provided. The internal structure diagram of the computer device can be as follows: Figure 5 As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a method for quickly finding the new and old relationship of data in multiple memory libraries as described above. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements any step of the method for quickly finding the new and old relationship of data in multiple memory libraries as described above.

[0097] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above method for quickly finding the new and old relationship of data in multiple memory banks can be implemented.

[0098] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0100] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0102] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0103] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for quickly finding the new and old relationship of data in multiple memory banks, characterized in that: include: An overall data relationship matrix is ​​constructed based on the correspondence between the memory access request number, the memory bank number, and the memory access time. The memory access request number and the corresponding memory access time of the same memory bank number are used as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained. Parallel determination of the memory access request numbers with the latest memory access times in the overall data relationship matrix and each group of data relationship matrices, as the first memory access request number, the second memory access request number, and the third memory access request number, respectively; Using the first memory access request number as a first new memory access request number, and determining a first new data relationship according to the first new memory access request number and its corresponding memory bank number; Based on the multiplexer, one of the second target memory bank number and the third target memory bank number is excluded according to the first memory access request number, and the second memory access request number or the third memory access request number obtained after exclusion is output as the second new memory access request number, and the second new memory access request number and its corresponding memory bank number are used as the second new data relationship.

2. The method according to claim 1, characterized in that The overall data relationship matrix is ​​constructed based on the correspondence between the memory access request number, the memory bank number, and the memory access time, including: The same memory access request number and its corresponding memory bank number and memory access time are taken as a row of the overall data relationship matrix, and all memory access request numbers and their corresponding memory bank numbers and memory access times constitute the overall data relationship matrix.

3. The method according to claim 1, characterized in that The memory access request number and the corresponding memory access time of the same memory bank number are used as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained, including: According to the type of memory bank number, the memory access request numbers with the same memory bank number in the overall data relationship matrix and their corresponding memory bank numbers and memory access times are taken as a set of data relationship matrices; When the number of types of memory bank numbers is two, the overall data relationship matrix is ​​divided into two groups of data relationship matrices.

4. The method according to claim 1, wherein Parallel determination of the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices as the first memory access request number, the second memory access request number, and the third memory access request number, respectively, including: Input the overall data relationship matrix into the first processing module, and output the memory access request number with the latest memory access time in the overall data relationship matrix as the first memory access request number; The two sets of data relationship matrices are input into the second processing module to the N+1th processing module, and the memory access request number with the latest memory access time in the first set of data relationship matrix and the second set of data relationship matrix is ​​output as the second memory access request number and the third memory access request number, respectively, wherein the second processing module to the N+1th processing module correspond to N memory access request numbers respectively.

5. The method according to claim 4, characterized in that Inputting the two sets of data relationship matrices into the second processing module to the N+1th processing module, outputting the memory access request number with the latest memory access time in the first set of data relationship matrix and the second set of data relationship matrix as the second memory access request number and the third memory access request number, respectively, including: The first memory access request number to the Nth memory access request number are stored correspondingly in the second processing module to the N+1th processing module respectively; In each of the second processing module to the (N+1)th processing module, determining whether the data relationship matrix corresponding to the current memory access request number stored in the current processing module is the first group of data relationship matrices or the second group of data relationship matrices; In a case where the data relation matrix corresponding to the current memory access request number is the first group of data relation matrices or the second group of data relation matrices, determining, according to the memory access time corresponding to the current memory access request number, whether the current memory access request number is the memory access request number with the latest memory access time in the first group of data relation matrices or the second group of data relation matrices; When the current memory access request number is the memory access request number with the latest memory access time in the first group of data relationship matrix or the second group of data relationship matrix, the current memory access request number is used as the second memory access request number or the third memory access request number.

6. The method according to claim 1, characterized in that Excluding one of the second target memory bank number and the third target memory bank number according to the first memory access request number comprises: The target memory bank number that is the same as the first memory access request number is excluded from the second target memory bank number and the third target memory bank number.

7. The method according to claim 6, characterized in that The second memory access request number or the third memory access request number obtained after the multiplexer output is excluded is used as the second new memory access request number, including: In a case where the second target memory bank number is excluded, using the third memory access request number as the second new memory access request number; When the third target memory bank number is excluded, the second memory access request number is used as the second new memory access request number.

8. A device for quickly finding the new and old relationship of data in multiple memory banks, characterized in that: include: a construction module, configured to construct an overall data relationship matrix based on the correspondence between the memory access request number, the memory bank number, and the memory access time, and to use the memory access request number and the corresponding memory access time of the same memory bank number as a set of data relationship matrices. When there are two types of memory bank numbers, two sets of data relationship matrices are obtained; A first determining module is used to concurrently determine the memory access request number with the latest memory access time in the overall data relationship matrix and each group of data relationship matrices, respectively as the first memory access request number, the second memory access request number, and the third memory access request number; a second determining module, configured to use the first memory access request number as a first new memory access request number, and determine a first new data relationship according to the first new memory access request number and its corresponding memory bank number; A multiplexer is used to exclude one of the second target memory bank number and the third target memory bank number according to the first memory access request number, and output the second memory access request number or the third memory access request number obtained after exclusion as the second new memory access request number, and use the second new memory access request number and its corresponding memory bank number as the second new data relationship.

9. A computer device comprising: The method comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the method implements the steps of the method for quickly finding the new and old relationships of data in multiple memory libraries as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for quickly finding the new and old relationships of data in multiple memory banks as described in any one of claims 1 to 7 are implemented.

Images