Method and device for loading page table items

Abstract

The invention discloses a method and device for loading page table items, and relates to the field of computers. The method comprises the following steps: acquiring a first request for indicating to access a first page of a program, and judging whether miss flow information comprises an identifier of the first page or not; when the miss flow information comprises the identification of the first page, a page table item of a second page is loaded, and the second page indicates a page which is in the miss flow information and is subjected to TLB miss after the first page. The miss flow information is used for indicating the identification of the page where the TLB miss has occurred and the sequence of the page where the TLB miss has occurred in the program execution process.

Description

[0001] This application claims the priority of a Chinese patent application with the application number 202410137727.8 and the application title "A Prefetching Method and Device" submitted to the National Intellectual Property Administration on January 31, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0002] This application relates to the field of computers, and particularly to a method and device for loading page table entries. Background Art

[0003] Paged virtual memory management is a basic attribute of today's computer systems. The paging translation function is described by a table resident in memory, which is called a page table and is stored in the physical address space.

[0004] Page tables are generally large and stored in memory. Therefore, after the processor introduces a memory management unit (MMU), reading instructions and data requires accessing memory twice: first, querying the page table in memory to obtain the physical address, and then accessing the physical address in memory to read the instructions and data.

[0005] To reduce the performance degradation of the processor caused by the MMU, translation lookaside buffers (TLBs) are introduced. TLBs are used to store the translations of virtual addresses to physical addresses that the processor has recently used to accelerate the speed of memory access. By caching the mapping from virtual addresses to physical addresses, TLBs only query the page table in memory when they are unable to complete the address translation task, avoiding a full address translation operation for each memory access, thereby improving the efficiency of memory access.

[0006] TLBs are finite caches, and current optimization techniques for TLBs are relatively mature. However, the rise of cloud computing has made the application programs in data centers not only have large data sets but also large code segments. The increasingly large binary files and the complex call relationships between cloud program instructions have led to a serious shortage of TLB page table entries during the address translation of cloud program instructions, increasing the probability of TLB misses during program instruction address translation, and thus increasing the overhead of program instruction address translation. Summary of the Invention

[0007] This application provides a method and device for loading page table entries to reduce the overhead of cloud program instruction address translation.

[0008] In a first aspect, a page prefetching method is provided, which is applied to a device for loading page table entries. Miss stream information is recorded in the device for loading page table entries, and the miss stream information is used to indicate the identifiers of the pages that have experienced TLB misses and the order in which the TLB misses of the pages occur during the execution of the program. The method includes: obtaining a first request indicating access to a first page of the program, and determining whether the identifier of the first page is included in the miss stream information; when the identifier of the first page is included in the miss stream information, loading the page table entry of a second page, where the second page is indicated in the miss stream information and is the page that experiences a TLB miss after the first page.

[0009] Through the solution provided by this application, since the miss stream information records the pages that have experienced TLB misses in the past, it can accurately describe the page call relationship of the program. When accessing the first page, the page table entry of the page (the second page) that may be accessed later and experiences a TLB miss in the miss stream information after the first page can be loaded in advance, achieving precise preloading, thereby reducing the number of instruction TLB misses, reducing the instruction address translation miss rate of the cloud program. In a cloud program with a large number of instructions, the hardware execution efficiency of the cloud program can be improved, and the overhead of cloud program instruction address translation can also be reduced.

[0010] A possible implementation is that the second page is indicated in the miss stream information and is the next page that experiences a TLB miss after the first page. By preloading in advance the page that may experience a miss next after the currently accessed first page, precise preloading can be achieved, and only a small number of pages are preloaded in advance, saving resources.

[0011] Another possible implementation is that the page table entry of the second page includes the mapping relationship between the identifier of the second page and the physical address of the second page. In the page table entry, the physical address of the page can be obtained by querying according to the page identifier indicated by the virtual address, completing the address translation.

[0012] Another possible implementation is that the above miss stream information further includes the miss stream history value of the page where a TLB miss has occurred, and the miss stream history value of the third page, which is used to indicate N pages where TLB misses have occurred in sequence before the TLB miss occurs on the third page in the miss stream information; N is greater than or equal to 2. The second page indicates that in the miss stream information, the fourth page is the successor page of the first page, and among the pages indicated by the miss stream history value of the fourth page, there are N - 1 pages where misses actually occurred before the first page. The successor page of the first page is used to indicate the next page where a TLB miss occurs after the first page in the miss stream information. The miss stream history value reflects the previous page of the page (i.e., the page where a miss occurred before this page), and the loading page determined by the previous page makes the accuracy of preloading higher.

[0013] Another possible implementation is that the above miss stream information is recorded in the form of a storage table, and the storage table includes M sub-tables. One sub-table is used to record the identifier of a page where a TLB miss has occurred and the identifier of its successor page; the number of successor page identifiers recorded in different sub-tables is different; M is greater than or equal to 2. By setting different sub-table capacities to record different numbers of successor pages, it also avoids occupying resources by reserving too much capacity.

[0014] Another possible implementation is that the method provided in this application further includes: when the number of successor pages of the fifth page increases and the first sub-table that stores the identifier of the fifth page and the identifier of the successor page of the fifth page is full, migrate the identifier of the fifth page and the identifier of the successor page of the fifth page to the second sub-table for storage, and the second sub-table stores a greater number of successor page identifiers than the first sub-table. In a storage table with different sub-table capacities set, when the successor pages increase, migrating the identifier of the page and the identifier of its successor page to a sub-table with a larger capacity improves the feasibility of the storage table.

[0015] Another possible implementation is that the method provided in this application further includes: when a TLB miss occurs on the sixth page, the identifier of the sixth page and the identifier of its successor page are not recorded in the miss stream information, and all sub-tables in the storage table are occupied, empty the third sub-table and store the sixth page and the successor page of the sixth page in the third sub-table. Among them, the third sub-table is the sub-table in the storage table that stores the smallest number of successor page identifiers; or the access frequency of the page where a TLB miss has occurred stored in the third sub-table is the smallest. By setting an upper limit for the storage table and dynamically adjusting the content in the storage table, it avoids the storage table occupying too much resources.

[0016] Another possible implementation is that frequency information of pages with TLB misses is also stored in the above-mentioned sub-tables. The frequency information is used to indicate the access frequency of the pages. The third sub-table stores the pages with the lowest access frequency among the pages with TLB misses, including: the access frequency indicated by the frequency information stored in the third sub-table is the lowest. This facilitates dynamically adjusting the content in the storage table according to the access frequency.

[0017] Another possible implementation is that the above-mentioned M can be 4, and the number of identifiers of successor pages recorded in each sub-table is 2, 4, 8, and 16 respectively.

[0018] Another possible implementation is that loading the page table entry of the second page includes: reading the page table entry where the second page is located from the page table in the memory and storing it in the prefetch queue. Wherein, the prefetch queue is the next-level buffer of the TLB, or the prefetch queue is the TLB.

[0019] In a second aspect, a device for loading page table entries is provided. Miss stream information is recorded in the device, and the miss stream information is used to indicate the identifiers of the pages with TLB misses and the sequence of TLB misses of the pages during the program execution. The device includes: an acquisition unit, a judgment unit, and a loading unit. Wherein:

[0020] The acquisition unit is used to acquire a first request, and the first request indicates accessing the first page of the program.

[0021] The judgment unit is used to judge whether the identifier of the first page is included in the miss stream information.

[0022] The loading unit is used to load the page table entry of the second page when the identifier of the first page is included in the miss stream information. Wherein, the second page indicates the page that has a TLB miss after the first page in the miss stream information.

[0023] In a possible implementation, the second page indicates the next page that has a TLB miss after the first page in the miss stream information. By preloading in advance the page that may have a miss next after the currently accessed first page, precise preloading can be achieved, and only a small number of pages are preloaded in advance, saving resources.

[0024] Another possible implementation is that the page table entry of the second page includes: the mapping relationship between the identifier of the second page and the physical address of the second page. In the page table entry, the physical address of the page can be queried according to the page identifier indicated by the virtual address, and the address translation is completed.

[0025] Another possible implementation is that the above miss stream information further includes the miss stream history value of the page where a TLB miss has occurred, the miss stream history value of the third page, which is used to indicate the N pages where TLB misses have occurred in sequence before the TLB miss occurs on the third page in the miss stream information; N is greater than or equal to 2. The second page indicates that in the miss stream information, the fourth page is the successor page of the first page, and among the pages indicated by the miss stream history value of the fourth page, there are N - 1 pages where misses actually occurred before the first page. The successor page of the first page is used to indicate the next page where a TLB miss occurs after the first page in the miss stream information. The miss stream history value reflects the previous page of the page (i.e., the page where a miss occurred before this page), and the loading page determined by the previous page makes the preloading accuracy higher.

[0026] Another possible implementation is that the above miss stream information is recorded in the form of a storage table. The storage table includes M sub-tables. One sub-table is used to record the identifier of a page where a TLB miss has occurred and the identifier of its successor page; the number of successor page identifiers recorded in different sub-tables is different; M is greater than or equal to 2. By setting different sub-table capacities to record different numbers of successor pages, it also avoids occupying resources by reserving too much capacity.

[0027] Another possible implementation is that the apparatus for page loading page table entries provided by this application further includes: a migration unit, which is used to, when the number of successor pages of the fifth page increases and the first sub-table storing the identifier of the fifth page and the identifier of its successor page is full, migrate the identifier of the fifth page and the identifier of its successor page to the second sub-table for storage. The second sub-table stores a greater number of successor page identifiers than the first sub-table. In the storage table with different sub-table capacities set, when the successor pages increase, migrating the identifier of the page and the identifier of its successor page to a sub-table with a larger capacity improves the feasibility of the storage table.

[0028] Another possible implementation is that the apparatus for page loading page table entries provided by this application further includes: a processing unit, which is used to, when a TLB miss occurs on the sixth page, the identifier of the sixth page and the identifier of its successor page are not recorded in the miss stream information, and all sub-tables in the storage table are occupied, empty the third sub-table and store the sixth page and its successor pages in the third sub-table. Among them, the third sub-table is the sub-table in the storage table that stores the least number of successor page identifiers; or the accessed frequency of the page where a TLB miss has occurred stored in the third sub-table is the smallest. By setting an upper limit for the storage table and dynamically adjusting the content in the storage table, it avoids the storage table occupying too much resources.

[0029] Another possible implementation is that frequency information of pages with TLB misses is also stored in the above sub-tables. The frequency information is used to indicate the access frequency of the pages. The third sub-table stores the pages with the lowest access frequency among the pages with TLB misses, including: the access frequency indicated by the frequency information stored in the third sub-table is the lowest. This facilitates dynamically adjusting the content in the storage table according to the access frequency.

[0030] Another possible implementation is that the above M can be 4, and the number of identifiers of successor pages recorded in each sub-table is 2, 4, 8, and 16 respectively.

[0031] Another possible implementation is that the above loading unit is specifically configured to: read the page table entry where the second page is located from the page table in the memory and store it in the prefetch queue. Wherein, the prefetch queue is the next-level buffer of the TLB, or the prefetch queue is the TLB.

[0032] In a third aspect, a computing device cluster is provided. The computing device cluster includes one or more computing devices. The computing device includes a processor. The processor is coupled to a memory. The memory is used to store instructions. When the instructions are executed by the processor, the computing device cluster is caused to execute the method described in the first aspect or any one of the possible implementation manners of the first aspect.

[0033] In a fourth aspect, a computer-readable storage medium is provided, including: computer software instructions; when the computer software instructions run in a computing device, the computing device is caused to execute the operation steps of the method described in the first aspect or any one of the possible implementation manners of the first aspect.

[0034] In a fifth aspect, a computer program product is provided. When the computer program product runs on a computing device, the computing device is caused to execute the operation steps of the method described in the first aspect or any one of the possible implementation manners of the first aspect.

[0035] For the technical effects brought by any one of the design manners in the second aspect to the fifth aspect, reference can be made to the technical effects brought by the first aspect or different design manners in the first aspect, which will not be elaborated here.

[0036] Based on the implementation manners provided in the above aspects of the present application, further combinations can be made to provide more implementation manners. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the architecture of a computer system provided by the present application;

[0038] Figure 2 It is a schematic flowchart of a method for loading page table entries provided by the present application;

[0039] Figure 3 Schematic diagram of the system framework of a solution for loading page table entries provided by this application;

[0040] Figure 4 Schematic diagram of a PFG provided by this application;

[0041] Figure 5 Schematic diagram of the processing flow of the prefetch logic unit provided by this application;

[0042] Figure 6 Schematic diagram of the sub - table logic of a PFG table provided by this application;

[0043] Figure 7 Schematic diagram of the structure of a device for loading page table entries provided by an embodiment of this application;

[0044] Figure 8 Schematic diagram of the structure of a computing device provided by an embodiment of this application;

[0045] Figure 9 Schematic diagram of the structure of a computing device cluster provided by an embodiment of this application;

[0046] Figure 10 Schematic diagram of the structure of another computing device cluster provided by an embodiment of this application. Detailed implementation manners

[0047] In the embodiments of this application, for the convenience of clearly describing the technical solutions of the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and roles. Those skilled in the art can understand that terms such as "first" and "second" do not limit the quantity and execution order, and "first" and "second" do not necessarily mean different. There is no sequential or size order between the technical features described by "first" and "second".

[0048] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner for easy understanding.

[0049] In the embodiments of this application, at least one can also be described as one or more. The plurality can be two, three, four or more, and this application does not make any restrictions.

[0050] In addition, the network architecture and scenarios described in the embodiments of this application are for more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those of ordinary skill in the art will know that with the evolution of the network architecture and the emergence of new service scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0051] For ease of understanding, first, the terms involved in the embodiments of this application are explained.

[0052] The physical address is the actual address of the memory unit in the memory, used for unit addressing at the memory chip level, opposite to the address bus connected to the processor and CPU.

[0053] The logical address is the offset address part related to the segment generated by the program. It can also be understood that in machine language instructions, it is used to specify the address of an operand or an instruction.

[0054] The virtual address, also known as the linear address, is the intermediate layer between the logical address and the physical address transformation, an abstract description of the memory, used to indicate the space in the virtual memory. The program code generates a logical address, and adding the base address of the corresponding segment generates a virtual address. If the paging mechanism is enabled, then the virtual address can be further transformed to generate a physical address. If the paging mechanism is not enabled, then the virtual address is directly the physical address. The virtual address is similar to the logical address and is also an untrue address. If the logical address is the address before the hardware platform segment management conversion, then the linear address corresponds to the address before the hardware page memory conversion. In the scenario where the segment base address is 0, the virtual address is the logical address.

[0055] A page is the unit for the operating system to manage the memory. In paged storage management, the memory space is divided into equal-sized partitions, and each partition is a page frame, also known as a page frame (or memory block, or physical block, or physical page). The logical address space of the process is also divided into parts of the same size as the page frame, and each part is called a page or a page. The operating system allocates memory space for each process in units of page frames, and each page of the process is placed in a page frame respectively, and there is a one-to-one correspondence between the pages of the process and the page frames of the memory.

[0056] The page table, also known as the page map table, is used to record the mapping relationship between the process pages (virtual addresses) and the actual memory blocks (physical addresses) where they are stored. Its purpose is to convert virtual addresses into physical addresses. A corresponding relationship (mapping relationship) in the page table, that is, an item where a page number corresponds to a physical block, is called a page table entry (PTE).

[0057] Prefetching refers to the operation of loading relevant content before accessing it. It can also be called prefetch, and the two concepts are the same and can be substituted for each other.

[0058] For the sake of clear and concise description of the following embodiments, the terms related to this application are briefly introduced first:

[0059] TLB is usually implemented inside the processor or in the MMU. It can store a certain number of mapping entries from virtual addresses to physical addresses, and one mapping entry is a page table entry. When the processor needs to access memory, it will first query the TLB to obtain the corresponding physical address. If the corresponding mapping exists in the TLB, the physical address can be directly obtained for use, thus avoiding the slower complete address conversion process, which is called a TLB hit. When the virtual address mapping accessed by the processor is not in the TLB, a TLB miss occurs. At this time, the processor needs to obtain the required physical address through a slower address conversion mechanism (such as page table lookup) and store the new mapping (the mapping between the page number and the physical address, that is, the page table entry) into the TLB. Frequent TLB misses will result in a longer miss penalty and affect the performance of memory access. Therefore, during the process of the CPU executing a program, the time overhead of address conversion when accessing instructions is determined by the TLB. This time overhead includes the time consumed for address conversion when accessing a single instruction, and from an overall perspective, the overall time overhead of address conversion for all instructions in the program.

[0060] Since the call relationship of instructions is not fixed during program execution, even if it is ensured that the TLB hits when accessing a certain instruction at a certain moment, due to the limited capacity of the TLB, before the next access to this instruction, the relevant page table entry of this instruction in the TLB has been replaced. Then, the next access to this instruction may result in a TLB miss.

[0061] The rise of cloud computing has led to data center applications requiring not only large data sets but also large code segments. This means massive amounts of instructions and data, and the complex call relationships between increasingly large binary files and numerous cloud program instructions. This leads to high contention for current processors' second-level translation lookaside buffers (STLBs, contained within the TLBs). This results in frequent replacement of page table entries in the TLBs during cloud program instruction address translation, exacerbating TLB misses of limited size and making TLB misses more likely to occur. Once an instruction TLB miss occurs, a multi-level page table access (page walk) through the MMU hardware is required, incurring significant latency and making address translation expensive. Currently, instruction address translation has become a major performance bottleneck for cloud programs. Eliminating instruction TLB misses and reducing the program's instruction translation overhead are key components in alleviating microarchitecture performance bottlenecks for cloud programs.

[0062] As one of the foundations of current computer systems, TLB-related optimization technologies have matured over the years. Currently, there are several solutions to reduce the instruction translation overhead of programs:

[0063] Solution 1: Increase TLB capacity. By increasing the physical capacity of the TLB, more TLB entries (PTEs) can be accommodated, thereby reducing the number of TLB misses. Alternatively, virtually and physically adjacent PTEs can be merged into a single TLB entry, indirectly increasing the effective TLB capacity.

[0064] However, due to limited hardware capacity, directly increasing the TLB capacity linearly will incur significant hardware overhead. Furthermore, as the cache becomes larger, its latency increases, reducing the cache's high-speed storage capabilities. Furthermore, because physical page contiguity cannot be guaranteed, there are limited opportunities to merge virtually and physically adjacent PTEs into a single TLB entry.

[0065] Solution 2: Speculative Address Translation. This method, based on speculation, predicts the address translation of non-TLB-resident pages. This method assumes that the processor will access instructions in the predicted order and prefetches pages into the TLB in that predicted order. The processor then continues speculatively executing instructions while initiating a page walk in the background to verify the predicted address translation. If the speculation is valid, the verification page walk can overlap with the current instruction execution, hiding its latency overhead.

[0066] The method of Solution 2 relies on explicit virtual and physical adjacencies to predict missing address translations, which is affected by the system state. However, this explicit relationship is not guaranteed in today's computing systems. The accuracy of the prediction in Solution 2 is difficult to guarantee, and it is difficult for this solution to guarantee the reduction of the program's instruction translation overhead.

[0067] Solution 3: Mitigate TLB miss latency. By improving the performance of MMU-Caches to reduce the latency penalty of frequent TLB misses, such as changing the access rules of the entire memory system, using a hash page table to solve TLB misses, which can solve TLB misses faster than the traditional radix-tree-based page table.

[0068] However, Solution 3 requires a revolutionary modification of the entire memory system, involving many aspects, such as modifying the operating system, compiler, etc. It is complex to implement, and its cost performance needs to be evaluated, and its compatibility is difficult to guarantee.

[0069] Solution 4: TLB management. As a cache, the replacement policy of the TLB (how to replace the entries when the TLB is full) has a great impact on its performance. The goal of the replacement policy is to retain the most useful PTEs in the TLB. Currently, the TLB basically adopts the least recently used (LRU) replacement policy.

[0070] After analysis, the temporal locality of cloud program instructions is poor (the time interval between two calls to a page will be very long), and the call relationship is complex. Therefore, the LRU replacement policy has limited improvement on the performance of cloud programs. Moreover, TLB management is one of the important means to improve TLB efficiency. Different programs have different characteristics, and it is difficult to achieve high performance for all cloud programs through a unified replacement policy.

[0071] Solution 5: Adopt large pages. Currently, the operating system uses a standard 4-kilobyte (KB) page size, and at the same time, it also supports multiple larger page sizes. By enabling large-page memory, the system only needs to process fewer page mapping tables, thereby reducing the access / maintenance overhead and significantly reducing TLB misses of cloud program instructions.

[0072] However, an overly large page capacity is likely to cause problems such as memory leaks, memory fragmentation, soaring CPU usage, and performance jitter, which poses a risk of reducing system performance.

[0073] As mentioned above, the current numerous solutions are ineffective in reducing the overhead of cloud program instruction address translation, or cannot be effectively applied to the scenario of cloud program instruction address translation. Therefore, reducing the overhead of cloud program instruction address translation needs to be urgently solved.

[0074] Based on this, the present application designs a method for loading page table entries. By recording the miss stream information during the program execution process, that is, the identifiers of the pages that have experienced TLB misses and the order in which the TLB misses occur for the pages, when the processor accesses a certain page during the execution of the program, if the identifier of the page is included in the miss stream information, the pages that experience TLB misses after this page in the miss stream information are pre-loaded.

[0075] Since the content recorded in the miss stream information reflects the logical order of the actual TLB misses of the pages during the program execution process, then, in the miss stream information, the pages that experience TLB misses after the currently accessed page are the pages that are most likely to be used in the future. By pre-loading them, when the processor accesses these pages, the instruction address translation can hit, without having to read from the memory, thereby reducing the instruction address translation miss rate of the cloud program, improving the hardware execution efficiency of the cloud program, and also reducing the overhead of the cloud program instruction address translation.

[0076] That is to say, by recording the logical relationship between the pages that experience TLB misses during the program running process, it is possible to determine the pages that may experience TLB misses in the future during the program running, and thus pre-load them in advance to reduce the performance loss caused by the instruction TLB miss.

[0077] Next, in conjunction with the accompanying drawings, the solution provided by the embodiments of the present application will be specifically described.

[0078] The solution provided by the present application can be applied to Figure 1 the computer system shown in the schematic. As Figure 1 shown, the computer system includes a processor 101 and a memory 102. Among them, a central processing unit 1011 and an MMU 1012 are deployed in the processor 101.

[0079] The central processing unit 1011 runs the program and accesses the instructions and data stored in the memory 102, enabling the computer system to provide corresponding functions externally.

[0080] The MMU 1012 is used to manage the memory 102. A TLB 10121 is deployed in the MMU 1012 for storing the recently used page table entries.

[0081] When the central processing unit 1011 needs to access the memory 102, it first queries the TLB 10121 to obtain the corresponding physical address. If there is a corresponding mapping (page table entry) in the TLB 10121, the physical address can be directly obtained for use. When the virtual address mapping accessed by the central processing unit 1011 is not in the TLB 10121, a TLB miss occurs. At this time, the central processing unit 1011 needs to search the page table in the memory 102 through the MMU 1012 to obtain the required physical address, and store the mapping of the new virtual address and the physical address in the TLB 10121.

[0082] Figure 1 The schematic computer system can be applied to the following scenarios: database programs, storage systems, service processing, etc. Figure 1 The schematic computer system can support cloud programs. Embodiments of the present application Figure 1 do not limit the application scenarios of the schematic computer system.

[0083] On the one hand, embodiments of the present application provide a method for loading page table entries, which is applied to a device for loading page table entries. The device for loading page table entries can be deployed in Figure 1 the MMU 1012 of the schematic computer system. The device for loading page table entries can be implemented in a hardware or software manner, and embodiments of the present application do not limit this.

[0084] The device for loading page table entries records miss stream information, which is used to indicate the identifiers of the pages that have experienced TLB misses and the order of occurrence of TLB misses for the pages during the program execution process. Specifically, the miss stream information is gradually recorded during the program execution process.

[0085] Such as Figure 2 shown, the method for loading page table entries provided by embodiments of the present application may include:

[0086] S201. The device for loading page table entries obtains a first request indicating the first page of the access program.

[0087] Among them, the first request may carry the identifier of the first page. The identifier of the first page is used to uniquely indicate the first page, and the present application does not limit the specific form and content of the page identifier. The first page can be any page in the program.

[0088] Exemplarily, the identifier of the first page may be the virtual address of the first page generated by the operating system, or the page number, or others.

[0089] Exemplarily, when the program called by the processor during the execution of the program is stored in the first page in the memory, the above-mentioned first request will be generated. Of course, the above-mentioned first request can also be generated by other means, and the embodiments of the present application do not limit this.

[0090] In a possible implementation manner, after S201, the device for loading page table entries executes S202.

[0091] In another possible implementation manner, after S201, if the first page is a page that misses in the TLB, that is, when address translation is performed on the first page and a TLB miss occurs, S202 is executed.

[0092] S202: The device for loading page table entries determines whether the miss stream information includes the identifier of the first page.

[0093] Specifically, when the device for loading page table entries records the program operation, each time it records the logical page number where the instruction STLB misses, it monitors the instruction page access stream of the central processing unit and determines whether the identifier of the currently accessed page exists in the miss stream information. If it exists, it means that the page has experienced a TLB miss before. In order to increase the overhead of program specified address translation and reduce the number of instruction TLB misses, S203 needs to be executed to preload the page table entries of the page that is most likely to be accessed in the future.

[0094] S203: When the miss stream information includes the identifier of the first page, the device for loading page table entries loads the page table entries of the second page, and the second page is indicated in the miss stream information and is the page that experiences a TLB miss after the first page.

[0095] Among them, the page that is considered to be most likely to be accessed in the future is the page recorded in the miss stream information that experiences a TLB miss after the first page.

[0096] In a possible implementation manner, the second page can be all the pages in the miss stream information that experience a TLB miss after the first page.

[0097] In another possible implementation manner, the second page can be the next page in the miss stream information that experiences a TLB miss after the first page.

[0098] In another possible implementation manner, the second page can be some of the pages in the miss stream information that experience a TLB miss after the first page, but the second page needs to include the page that experiences a TLB miss next after the first page, so as to ensure a higher accuracy of page table entry loading.

[0099] The embodiments of the present application do not limit the specific content of the second page.

[0100] Specifically, in S203, the device for loading page table entries can perform multi-level page walking access (pagetable walk, PTW) from the memory, access the page table in the memory, read the page table entries of the second page, and complete the loading of the page table entries of the second page.

[0101] Among them, the page table entries of the second page include: the mapping relationship between the identifier of the second page and the physical address of the second page.

[0102] In a possible implementation manner, the device for loading page table entries in S203 loads the page table entries of the second page and stores them in the TLB.

[0103] In another possible implementation manner, the device for loading page table entries in S203 loads the page table entries of the second page and stores them in the prefetch queue, and the prefetch queue can be used as the next-level buffer of the TLB.

[0104] In another possible implementation manner, the device for loading page table entries in S203 loads the page table entries of the second page and stores them in the prefetch queue, and the prefetch queue is deployed in the TLB.

[0105] The embodiments of the present application do not limit the storage location of the loaded page table entries of the second page.

[0106] Through the solution provided by the present application, since the miss stream information records the pages that have experienced TLB misses in the past, it can accurately describe the page call relationship of the program. When accessing the first page, the pages that experience TLB misses after the first page in the miss stream information can be pre-loaded in advance, and the page table entries of the pages (second pages) that the program may access subsequently and experience TLB misses can be loaded from the memory in advance, realizing precise pre-loading, thereby reducing the number of instruction TLB misses, reducing the instruction address translation miss rate of the cloud program. In a cloud program with a large number of instructions, the hardware execution efficiency of the cloud program can be improved, and the overhead of cloud program instruction address translation can also be reduced.

[0107] Exemplarily, the system framework diagram of the solution for loading page table entries provided by the present application can be as Figure 3As shown, in this system framework, the TLB is denoted as a two-level buffer, including a first-level translation lookaside buffer (L1I-TLB) and a second-level translation lookaside buffer (STLB). The prefetch logic unit (equivalent to the device for loading page table entries described above) is the core of this solution. It records the logical page numbers when a miss occurs in the STLB for each instruction during program execution, records this miss stream (i.e., the miss stream information described above), and simultaneously monitors the instruction page access stream of the central processing unit ( Figure 3 the logical address passed from the central processing unit to the prefetch logic unit in Figure 3 the logical address denoted as the first page in Figure 3 ). If it is found that the instruction page being accessed (the first page described above) ( Figure 3 the logical address denoted as the first page in Figure 3 ) appears in the recorded miss stream, then based on the recorded miss stream, predict the page on which a miss is about to occur (the logical page on which a miss occurs after the previously recorded instruction page being accessed), send an address translation prefetch request to the predicted page, and execute prefetch PTW. In this way, the instruction page table entries that may appear later in the program can be put into the prefetch queue in advance, realizing the replay of the recorded miss stream (replaying it back to the translation lookaside buffer), thereby reducing the number of instruction TLB misses.

[0108] In Figure 3 the system framework shown, when the central processing unit accesses a certain page, the following steps are included: 1. First, query the L1I-TLB according to the logical address; 2. If the L1I-TLB hits, obtain the physical address and return it to the central processing unit; 3. If the L1I-TLB misses, query the STLB according to the logical address; 4. If the STLB hits, obtain the physical address and return it to the central processing unit; 5. If the STLB misses, query the prefetch queue according to the logical address; at the same time, add the identifier of the currently accessed page to the miss stream information recorded in the prefetch logic unit, and the prefetch logic unit executes the solution of this application, predicts and determines the page that is expected to be preloaded in advance, and returns it to the prefetch queue as prefetch PTW; the prefetch queue determines the necessary PTW according to the already loaded pages and the prefetch PTW, executes the early loading, records the physical address obtained from the memory; 6. If the query of the prefetch queue in step 5 hits according to the logical address, obtain the physical address and return it to the central processing unit; 7. If the query of the prefetch queue in step 5 misses according to the logical address, execute the necessary PTW, obtain the physical address from the memory, and return it to the central processing unit. After that, the central processing unit accesses the memory according to the physical address.

[0109] Exemplarily, based on Figure 3 the system framework shown, the first page described above is the page currently accessed by the central processing unit and misses in both the TLB and the prefetch queue, that is, the page where a miss currently occurs.

[0110] When the solution provided by this application is applied to the cloud program scenario, the cloud program service can benefit from hardware preloading, and the degree of benefit depends on the complexity of function calls and the program scale in the cloud program. Typical scenarios include: database programs, storage systems, service processing, etc. Without modifying the program, the program performance can be transparently improved.

[0111] Exemplarily, in the miss stream information, the page that has the next TLB miss after the third page can be defined as the successor page of the third page. The above-mentioned second page may include: the successor page of the first page in the miss stream information.

[0112] Figure 4 It schematically shows a program page flow graph (PFG), which schematically shows the connection relationship graph of the pages where TLB misses have occurred during the program execution process, and it indicates the logical relationship of the pages where instructions have TLB misses in the STLB. Figure 4 The content shown can be constructed through the miss stream (the order of the pages where TLB misses occur) of the iSTLB. Figure 4 Each circle in it represents a miss page in the instruction STLB. For example, in the program execution history, after the 1st page has a miss, subsequent 2nd, 3rd, or 4th pages have TLB misses; when the 2nd page has a TLB miss, subsequent 5th or 6th pages have TLB misses. The successor page is defined as the page that immediately follows a given page in the iSTLB miss stream. For example, the 2nd, 3rd, and 4th pages are all successor pages of the 1st page, and the 5th and 6th pages are successor pages of the 2nd page.

[0113] According to Figure 4 The content shown, it can be determined which pages in the program may have misses in the future. Similarly, after the 1st page has a miss, one of the subsequent 2nd, 3rd, or 4th pages may have a miss, and the page table entry where it is located is preloaded in advance; when the 2nd page has a miss, the subsequent miss pages may be the 5th or 6th page. By determining which pages in the program may have misses in the future and preloading the page table entries, the performance loss caused by instruction TLB misses can be reduced.

[0114] More specifically, in the solution provided by this application, according to the STLB page miss stream information of the instructions recorded during program execution, a PFG table for prefetching can be constructed. When executing to a certain page, according to the page table entries existing in the PFG table, it is judged which pages in the program may have misses next, and more accurate page table entry loading is performed in this way to reduce the performance loss caused by TLB misses.

[0115] In a possible implementation, the above miss stream information may further include the miss stream history value of the page where a TLB miss has occurred, and the miss stream history value of the third page, which is used to indicate the N pages that have sequentially experienced TLB misses in the miss stream information before the TLB miss occurs on the third page; N is greater than or equal to 2.

[0116] It should be understood that the miss stream history value of a page is used to indicate the page history of TLB misses that occurred before this page during program execution, reflecting the source of the TLB miss on this page in the miss stream information, that is, the previous TLB miss page of this page.

[0117] Exemplarily, in Figure 4 In the schematic PFG shown, the successor pages of page 6 are page 7 and page 10. During program execution, the historical stream of TLB misses is as follows: page 2 experiences a miss first, then page 6 experiences a miss, and then page 10 experiences a miss; page 3 experiences a miss first, then page 6 experiences a miss, and then page 7 experiences a miss; then, the miss stream history value of page 10 includes page 2 - page 6; the miss stream history value of page 7 includes page 3 - page 6.

[0118] Exemplarily, the miss stream history value can be a hash value.

[0119] Correspondingly, the second page may include: the fourth page among the successor pages of the first page, and among the pages indicated by the miss stream history value of the fourth page, N - 1 pages that actually experienced misses before the first page are included.

[0120] Exemplarily, based on Figure 4 The miss stream information corresponding to the schematic PFG shown, assuming N is 2, and the currently accessed first page is page 6. Before the central processing unit accesses page 6 and experiences a miss, page 2 that was accessed experiences a miss. Then, since there are 2 successor pages of page 6 (page 7 and page 10), and the miss stream history value of page 10 includes page 2 - page 6, which includes page 2 that actually experienced a miss before page 6, page 10 can be determined as the second page, and the page table entry of page 10 can be pre-loaded.

[0121] Furthermore, a page and its successor pages in the miss stream information are defined as a stream information item, and a stream information item includes the page and the successor pages of the page. The number of stream information items stored in the miss stream information is limited. When a new stream information item needs to be added to the miss stream information, the original stream information item needs to be replaced.

[0122] In a possible implementation, frequency information indicating the access frequencies of the pages of each stream information item can be recorded in the miss stream information. The stream information item of the page with the least access frequency in the miss stream information can be removed, and the newly added stream information item can be added.

[0123] Exemplarily, the access frequency can be the number of times a page is accessed during program execution, and this number does not consider whether there is a TLB hit.

[0124] Exemplarily, the access frequency can be the number of times of TLB miss among the number of times a page is accessed during program execution.

[0125] In another possible implementation, the stream information item with the longest storage time in the miss stream information can be removed from the miss stream information, and the newly added stream information item can be added.

[0126] Exemplarily, the above miss stream information can be recorded in the form of a storage table. The storage table includes M sub-tables. One sub-table is used to record the identifier of a page that has had a TLB miss and the identifier of its successor page. M is greater than or equal to 2. The value of M can be configured according to actual requirements.

[0127] In a possible implementation, the number of identifiers of successor pages recorded in different sub-tables in the storage table can be different, which is used to save hardware storage space.

[0128] Further, on the premise that the number of identifiers of successor pages recorded in different sub-tables can be different, as the program executes, when the number of successor pages of a certain page gradually increases, the identifier of this page and the identifiers of its successor pages need to be migrated to other sub-tables for storage.

[0129] Exemplarily, the method for loading page table entries provided in this application can further include: when the number of successor pages of the fifth page increases and the first sub-table storing the identifier of the fifth page and the identifiers of the successor pages of the fifth page is full, migrating the identifier of the fifth page and the identifiers of the successor pages of the fifth page to the second sub-table for storage. The second sub-table stores a larger number of successor pages than the first sub-table.

[0130] Exemplarily, the second sub-table can be the next sub-table of the first sub-table in the order of storing an increasing number of successor pages in the storage table.

[0131] Further, in the solution where the miss stream information is implemented by a storage table and the number of identifiers of successor pages recorded in different sub-tables is different, the method for loading page table entries provided in this application may further include: when a TLB miss occurs on the sixth page, the identifier of the sixth page and the identifier of its successor page are not recorded in the miss stream information, and all sub-tables in the storage table are occupied, clear the third sub-table; store the identifier of the sixth page and the identifier of the successor page of the sixth page in the third sub-table.

[0132] In a possible implementation, the third sub-table is the sub-table in the storage table with the smallest number of identifiers of successor pages stored.

[0133] In another possible implementation, the access frequency of the page with a TLB miss stored in the third sub-table is the smallest.

[0134] Further, frequency information of the page with a TLB miss is also stored in the sub-table, and the frequency information is used to indicate the access frequency of the page. Exemplarily, assume that the third sub-table stores the identifier of the seventh page and the identifier of the successor page of the seventh page, and the frequency information of the seventh page is also stored in the third sub-table, and the frequency information of the seventh page is used to indicate the access frequency of the seventh page.

[0135] Correspondingly, the access frequency of the page with a TLB miss stored in the third sub-table being the smallest can be specifically understood as: the access frequency indicated by the frequency information stored in the third sub-table is the smallest.

[0136] Exemplarily, the above M can be 4, and the number of successor pages recorded in each sub-table is 2, 4, 8, and 16 respectively.

[0137] Exemplarily, the above storage table can be called a PFG table, and the PFG table is constructed according to the STLB page miss stream information of the instructions during program execution. When executing to a certain page, according to the table entries existing in the PFG table, judge the pages where misses may occur in the next program, and perform more accurate preloading in this way to reduce the performance loss caused by TLB miss.

[0138] Figure 5 Schematically shows the processing flow of the prefetch logic unit. As Figure 5 shown, the PFG table is stored in the prefetch logic unit. The PFG table is composed of multiple sub-tables. The structure of each sub-table is the same, but the number of identifiers of successor pages stored in each sub-table is different (the successor page is represented as N-VPN). In Figure 5 , the PFG table is composed of 4 sub-tables, and the number of identifiers of successor pages stored is 2, 4, 8, and 16 respectively.

[0139] As Figure 5As shown in the figure, when the central processing unit executes program instructions and an instruction miss page occurs in the STLB, the prefetch logic unit queries the PFG table according to the virtual address. If there is a VPN record in the PFG table that matches the current miss page (i.e., the VPN stored in the PFG table is the current miss page), it proves that this miss page has been recorded. Then, the page table entry of the successor page (N-VPN) of this logical page number (virtual page number, VPN) needs to be loaded from the memory and stored in the prefetch queue to issue the corresponding address translation page for early loading. If there is no VPN record in the PFG table that matches the current miss page, the prefetch logic unit needs to update the current miss page to the PFG table. The specific update process is not elaborated here.

[0140] It can be seen from this that the solution provided by this application constructs a PFG table by recording the miss page stream information of instructions on the STLB during the program execution process. The PFG table stores the logical relationship between the page miss stream predecessor and successor pages, so as to facilitate predicting the possible miss pages of the program in the future when the previous page of the current record appears, and then issuing a load request in advance to reduce the cost overhead caused by the miss. For the situation where the same page may access multiple different pages subsequently, a multi-level query history sub-table can be designed to save storage costs. It can reduce storage overhead, improve the expected accuracy, reduce invalid early loading, and reduce bandwidth contention.

[0141] Figure 6 It is a schematic diagram of the sub-table logic of a PFG table. Figure 6 The schematic PFG table can achieve the following functions: record the logical relationship between the pages in the PFG and the successor pages for issuing a load request during query; when a new miss page logical relationship appears, replace the sub-table therein. The following will be described separately.

[0142] 1. Recording: According to the page information accessed during program execution, record the information of the predecessor page (the page where a miss occurred before this page) and the successor page (the page where a miss occurred after this page) of the page where a miss occurred during the page access process, and at the same time update the counter field (counting field) and hash value of the page. Among them, the counter field is used to indicate the access frequency of the page; the hash value is used to indicate the miss stream history value of each successor page.

[0143] At the same time, a page access flow graph of the corresponding program can also be established according to the PFG table to more intuitively reflect the logical relationship of the pages where TLB misses occur during the program execution process.

[0144] 2. Query: When a STLB miss occurs during the access to a certain page, the VPN corresponding to this page can be obtained. Based on this VPN, continue to match with the VPNs recorded in the sub - tables of the PFG table; if there is an existing entry in the PFG table that contains this VPN ( Figure 6 the VPN hit branch shown in Figure 6 ), then load the page table entries of the pages that may be accessed subsequently.

[0145] To load the page table entries more precisely, the sub - table stores the hash value of the page miss stream history in each subsequent entry. By comparing the current page miss stream history with the stored page miss stream history, find the subsequent page whose miss stream history is the same as the current page. After taking it as the exact match item (P - VPN), then issue the corresponding load request. After completing the corresponding load item PTW, store the load result in the pre - fetch queue.

[0146] Among them, the miss stream history of the current page is used to indicate the page history where misses actually occurred before the current page, and the stored page miss stream history is used to indicate the page history where misses occurred in the past. The page table entry loading based on the previous page provided by the embodiments of the present application realizes more precise page table entry loading.

[0147] 3. Frequency - based replacement: When a new miss page appears, if no corresponding VPN match item is found in all sub - tables of the PFG table, it means that the PFG table needs to be updated. At this time, the replacement item needs to be found first. This solution can select the replacement item according to the counter field.

[0148] Exemplarily, select the smallest one in all counter fields, that is, the one with the lowest occurrence frequency is replaced, that is, removed from the PFG table, and the relevant content of the new miss page is added to the PFG table.

[0149] Furthermore, the replacement strategy based on call frequency provided by the embodiments of the present application is specifically implemented as follows: When there is a need to replace because the page table entry is full in the recorded page history access flow graph, according to the characteristics of the hot functions in the big - data program set, use the information of function call frequency for replacement, rather than the random replacement or LRU replacement strategy used in the previous methods, to further improve the storage efficiency of the PFG table.

[0150] The above has introduced the solution provided by the embodiments of the present invention from the perspective of the working principle of the device for loading page table entries. It can be understood that in order to implement the above functions, the device for loading page table entries, etc., includes the corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0151] The embodiments of the present invention can divide functional modules for the device for loading page table entries, etc. according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present invention is illustrative, only a logical functional division, and there can be other division methods in actual implementation.

[0152] This application also provides a device 70 for loading page table entries. The device records miss stream information, and the miss stream information is used to indicate the identifiers of the pages that have experienced TLB misses and the order of occurrence of TLB misses of the pages during the execution of the program, as Figure 7 shown. The device 70 for loading page table entries may include: an acquisition unit 701, a judgment unit 702, and a loading unit 703. Among them:

[0153] The acquisition unit 701 is configured to acquire a first request, and the first request indicates to access the first page of the program.

[0154] The judgment unit 702 is configured to judge whether the identifier of the first page is included in the miss stream information.

[0155] The loading unit 703 is configured to load the page table entry of the second page when the identifier of the first page is included in the miss stream information. Wherein, the second page indicates the page that experiences a TLB miss after the first page in the miss stream information.

[0156] Among them, the obtaining unit 701, the judging unit 702, and the loading unit 703 can all be implemented by software or by hardware. Exemplarily, next, taking the loading unit 703 as an example, the implementation manner of the loading unit 703 will be introduced. Similarly, the implementation manners of the obtaining unit 701 and the judging unit 702 can refer to the implementation manner of the loading unit 703.

[0157] As an example of a software functional unit, the loading unit 703 may include code running on a computing instance. Among them, the computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Further, the above computing instance may be one or more. For example, module A may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers for running this code may be distributed in the same region, or may be distributed in different regions. Further, the multiple hosts / virtual machines / containers for running this code may be distributed in the same availability zone (AZ), or may be distributed in different AZs, and each AZ includes one data center or multiple geographically proximate data centers. Among them, generally one region may include multiple AZs.

[0158] Similarly, the multiple hosts / virtual machines / containers for running this code may be distributed in the same virtual private cloud (VPC), or may be distributed in multiple VPCs. Among them, generally one VPC is set within one region. For cross-region communication between two VPCs within the same region and between VPCs in different regions, a communication gateway needs to be set in each VPC, and the interconnection between VPCs is realized through the communication gateway.

[0159] As an example of a hardware functional unit, module A may include at least one computing device, such as a server, etc. Alternatively, the determining unit 701 may also be a device implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). Among them, the above PLD may be implemented by a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0160] The multiple computing devices included in the loading unit 703 can be distributed in the same region or in different regions. The multiple computing devices included in the determination unit 701 can be distributed in the same availability zone (AZ) or in different AZs. Similarly, the multiple computing devices included in the loading unit 703 can be distributed in the same virtual private cloud (VPC) or in multiple VPCs. Among them, the multiple computing devices can be any combination of computing devices such as servers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), and generic array logic (GALs).

[0161] It should be noted that in other embodiments, the obtaining unit 701 is used to execute Figure 2 the process S201 in Figure 2 ; the judging unit 702 is used to execute Figure 2 the process S202 in Figure 2 ; the loading unit 703 is used to execute

[0162] the process S203 in Figure 2 . The steps to be implemented by the obtaining unit 701, the judging unit 702, and the loading unit 703 can be specified as needed, and all functions of the device 70 for loading page table entries are implemented by respectively implementing different steps in the method for loading page table entries provided by

[0163] This embodiment of the present application provides a schematic structural diagram of a computing device 800. Exemplarily, the computing device 800 can implement Figure 8 the functions of the device for loading page table entries illustrated in

[0164] As shown in Figure 8

[0165] Figure 8 shown, the computing device 800 may include a bus 802, a processor 804, a memory 806, and a communication interface 808. The processor 804, the memory 806, and the communication interface 808 communicate with each other through the bus 802. The computing device 800 can be a server or a terminal device. It should be understood that the present application does not limit the number of processors and memories in the computing device 800.

[0164] The bus 802 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, Figure 8 only one line is shown in

[0165] The processor 804 may include any one or more of processors such as a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0166] The memory 806 may include volatile memory, such as random access memory (RAM). The processor 804 may also include non-volatile memory, such as read-only memory (ROM), flash memory, a hard disk drive (HDD), or a solid state drive (SSD).

[0167] The communication interface 808 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 800 and other devices or communication networks.

[0168] On the other hand, provided by the present application Figure 8 Stored in the memory 806 of the computing device 800 shown is executable program code. The processor 804 executes the executable program code to respectively implement the functions of the aforementioned obtaining unit 701, determining unit 702, and loading unit 703, thereby implementing the above Figure 2 Schematic method for loading page table entries. That is, stored on the memory 806 are instructions for executing the above Figure 2 Schematic method for loading page table entries.

[0169] On yet another aspect, an embodiment of the present application further provides a computing device cluster as Figure 9 Shown. The computing device cluster includes at least one computing device. The computing device may be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device may also be a terminal device such as a desktop computer, a laptop computer, or a smart phone.

[0170] As Figure 9 Shown, the computing device cluster includes at least one computing device 800. In one or more of the computing devices 800 in the computing device cluster, the memory 806 may store the same instructions for executing the above Figure 2 Schematic method for loading page table entries.

[0171] In some possible implementations, the memories 806 of one or more computing devices 800 in the computing device cluster may also store, respectively, some instructions for executing the above-mentioned Figure 2 method for loading page table entries as illustrated. In other words, the combination of one or more computing devices 800 may jointly execute the instructions for executing the above-mentioned Figure 2 method for loading page table entries as illustrated.

[0172] It should be noted that the memories 806 in different computing devices 800 in the computing device cluster may store different instructions, respectively for executing some functions of the apparatus 70 for loading page table entries. That is to say, the instructions stored in the memories 806 of different computing devices 800 may implement the functions of one or more of the obtaining unit 701, the judging unit 702, and the loading unit 703.

[0173] In some possible implementations, one or more computing devices 800 in the computing device cluster may be connected through a network. Among them, the network may be a wide area network or a local area network, etc. Figure 10 A possible implementation is shown. As Figure 10 shown, two computing devices 800A and 800B are connected through a network. Specifically, they are connected to the network through the communication interfaces in each computing device. In this type of possible implementation, the memory 806 in the computing device 800A stores instructions for executing the functions of the obtaining unit 701 and the judging unit 702. At the same time, the memory 806 in the computing device 800B stores instructions for executing the function of the loading unit 703.

[0174] Figure 10 The connection method between the computing device clusters as shown may be considered because the method for loading page table entries provided in this application requires a large amount of data storage. Therefore, it is considered to hand over the function implemented by the loading unit

[0175] 703 to the computing device 800B for execution. Figure 10 It should be understood that the functions of the computing device 800A shown in

[0176] may also be completed by multiple computing devices 800. Similarly, the functions of the computing device 800B may also be completed by multiple computing devices 800. Figure 2 On the other hand, the embodiments of the present application also provide a computer program product containing instructions. The computer program product may be software or a program product containing instructions that can run on a computing device or be stored in any available medium. When the computer program product runs on at least one computing device, it causes at least one computing device to execute the above-mentioned

[0177] In another aspect, an embodiment of the present application further provides a computer-readable storage medium. The computer-readable storage medium may be any available medium that can be stored by a computing device or a data storage device such as a data center including one or more available media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive), etc. The computer-readable storage medium includes instructions that instruct the computing device to execute the above-mentioned Figure 2 method of loading a page table entry as illustrated, or instruct the computing device to execute the above-mentioned Figure 2 method of loading a page table entry as illustrated.

[0178] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for loading page table entries, characterized in that, A device for loading page table entries, where miss stream information is recorded in the device for loading page table entries, and the miss stream information is used to indicate the identifiers of the pages that have experienced translation lookaside buffer (TLB) misses and the sequence of TLB misses of the pages during program execution; the method includes: Obtain a first request, where the first request indicates accessing a first page of the program; Determine whether the identifier of the first page is included in the miss stream information; When the identifier of the first page is included in the miss stream information, load the page table entry of a second page, where the second page is indicated in the miss stream information and is the page that experienced a TLB miss after the first page.

2. The method according to claim 1, characterized in that The second page is the next page that is indicated in the miss stream information and experienced a TLB miss after the first page.

3. The method according to claim 1 or 2, characterized in that, The page table entry of the second page includes: The mapping relationship between the identifier of the second page and the physical address of the second page.

4. The method according to claim 1, characterized in that, The miss stream information further includes the miss stream history value of the page that has experienced a TLB miss; the miss stream history value of the third page is used to indicate N pages that sequentially experienced TLB misses in the miss stream information before the third page experienced a TLB miss, where N is greater than or equal to 2; The second page is the fourth page among the successor pages of the first page in the miss stream information, and the pages indicated by the miss stream history value of the fourth page include the N - 1 pages that actually experienced misses before the first page; the successor pages of the first page are used to indicate the next page that experienced a TLB miss after the first page in the miss stream information.

5. The method according to any one of claims 1 to 4, characterized in that The miss stream information is recorded in the form of a storage table, and the storage table includes M sub - tables. One sub - table is used to record the identifier of a page that has experienced a TLB miss and the identifier of its successor page; the number of successor page identifiers recorded in different sub - tables is different; M is greater than or equal to 2.

6. The method according to claim 5, characterized in that, The method further includes: When the number of successor pages of the fifth page increases and the first sub - table that stores the identifier of the fifth page and the identifier of its successor page is full, migrate the identifier of the fifth page and the identifier of its successor page to the second sub - table for storage, and the second sub - table stores a greater number of successor pages than the first sub - table.

7. The method according to claim 5 or 6, characterized in that, The method further includes: When the sixth page experiences a TLB miss, the identifier of the sixth page and the identifier of its successor page are not recorded in the miss stream information, and all sub - tables in the storage table are occupied, empty the third sub - table; the third sub - table is the sub - table in the storage table that stores the smallest number of successor page identifiers; or, the page that has experienced a TLB miss stored in the third sub - table has the smallest access frequency; Store the identifier of the sixth page and the identifier of its successor page in the third sub - table.

8. The method according to claim 7, characterized in that The sub - table also stores the frequency information of the pages that have experienced TLB misses. The frequency information is used to indicate the access frequency of the pages. The third sub - table stores the pages that have experienced TLB misses with the smallest access frequency, including: The access frequency indicated by the frequency information stored in the third sub - table is the smallest.

9. The method according to any one of claims 1-8, characterized in that, The loading of the page table entry of the second page includes: Reading the page table entry where the second page is located from the page table in the memory and storing it in the pre - fetch queue; where the pre - fetch queue is the next - level buffer of the TLB, or the pre - fetch queue is the TLB.

10. A device for loading page table entries, characterized in that The device records miss stream information, which is used to indicate the identifiers of the pages that have experienced translation look - aside buffer (TLB) misses and the sequence of TLB misses during the execution of the program; the device includes: An acquisition unit, configured to acquire a first request, where the first request indicates accessing a first page of the program. A judgment unit, configured to judge whether the identifier of the first page is included in the miss stream information. A loading unit, configured to load the page table entry of the second page when the identifier of the first page is included in the miss stream information, where the second page is indicated in the miss stream information and is the page that experiences a TLB miss after the first page.

11. The device according to claim 10, characterized in that, The second page is the next page that experiences a TLB miss after the first page and is indicated in the miss stream information.

12. The device according to claim 10 or 11, characterized in that, The page table entry of the second page includes: The mapping relationship between the identifier of the second page and the physical address of the second page.

13. The device according to claim 10, characterized in that, The miss stream information further includes the miss stream history value of the page that has experienced a TLB miss; the miss stream history value of the third page is used to indicate N pages that have sequentially experienced TLB misses before the third page experiences a TLB miss in the miss stream information, where N is greater than or equal to 2. The second page indicates the fourth page among the successor pages of the first page in the miss stream information. The pages indicated by the miss stream history value of the fourth page include the N - 1 pages that actually experienced misses before the first page; the successor pages of the first page are used to indicate the next page that experiences a TLB miss after the first page and is indicated in the miss stream information.

14. The device according to any one of claims 10-13, characterized in that, The miss stream information is recorded in the form of a storage table. The storage table includes M sub - tables. One sub - table is used to record the identifier of a page that has experienced a TLB miss and the identifier of its successor page; the number of successor pages recorded in different sub - tables is different; M is greater than or equal to 2.

15. The device according to claim 14, characterized in that, The device further includes: A migration unit, configured to, when the number of successor pages of the fifth page increases and the first sub - table storing the identifier of the fifth page and the identifier of its successor page is full, migrate the identifier of the fifth page and the identifier of its successor page to the second sub - table for storage, and the second sub - table stores a larger number of successor pages than the first sub - table.

16. The device according to claim 14 or 15, characterized in that, The device further includes: A storage unit, configured to clear the third sub-table when a TLB miss occurs in the sixth page, the identification of the sixth page and the identification of its successor page are not recorded in the miss stream information, and all sub-tables in the storage table are occupied; store the identification of the sixth page and the identification of its successor page in the third sub-table; the third sub-table is the sub-table in the storage table with the least number of stored successor pages; or, the access frequency of the pages that have had a TLB miss stored in the third sub-table is the smallest.

17. The device according to claim 16, wherein The miss stream information further includes the access frequency of the pages that have had a TLB miss. The access frequency of the pages that have had a TLB miss stored in the third sub-table being the smallest includes: The access frequency of the pages that have had a TLB miss stored in the third sub-table included in the miss stream information is the smallest.

18. The device according to any one of claims 10-17, characterized in that, The loading unit is specifically configured to: Read the page table entry where the second page is located from the page table in the memory and store it in the prefetch queue; wherein, the prefetch queue is the next-level buffer of the TLB, or the prefetch queue is the TLB.

19. A cluster of computing devices, characterized in that, Including at least one computing device, the computing device includes a processor, the processor is coupled to a memory, and the memory is used to store instructions. When the instructions are executed by the processor, the computing device cluster executes the operation steps of the method according to any one of claims 1-9.

20. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer instructions; when the computer instructions run in a computing device, the computing device executes the operation steps of the method according to any one of claims 1-9.

21. A computer program product, characterized in that, When the computer program product runs in a computing device, the computing device executes the operation steps of the method according to any one of claims 1-9.

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