Page table acquisition method, memory management unit, processor and computer equipment

Abstract

The invention provides a page table acquisition method, a memory management unit, a processor and computer equipment, the page table acquisition method is applied to the memory management unit, and the page table acquisition method comprises the following steps: after a first page table is extracted from a first cache data block, determining a virtual address of a second page table in the first cache data block based on a virtual address of the first page table; wherein the first cache data block is a cache data block obtained by the memory management unit from a second-level cache request based on a first page table request, and the cache data block comprises a plurality of page tables; generating a second page table request for requesting to acquire the second page table based on the virtual address of the second page table; and obtaining the second page table from the second-level cache request based on the second page table request. According to the scheme, the page table obtaining efficiency of the processor can be improved, and the performance of the processor can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a page table acquisition method, a memory management unit, a processor, and a computer device. Background Art

[0002] In the prior art, when a Memory Management Unit (MMU) obtains a target page table from a secondary cache, the secondary cache sends a cache data block storing the target page table to the MMU. Multiple page tables are included in the cache data block. After receiving the cache data block, the MMU selects the target page table from it and stores it in the L2 TLB (Translation Lookaside Buffer), and at the same time selectively retains other page tables in the cache data block.

[0003] Since other page tables are loaded into the L2 TLB in advance, when the MMU receives a request for other page tables, it can hit other page tables in the L2 TLB and will not send a request for other page tables to the secondary cache. This causes the cache data block storing these page tables to not be accessed for a long time, and after a period of time, the page tables stored in the cache data block will be replaced by other page tables. At the same time, the page table replacement in the L2 TLB is more frequent and will be replaced by other page tables earlier. In this case, when the MMU receives a request for the above page table again, the corresponding page table cannot be hit in both the L2 TLB and the secondary cache, resulting in a slow page table request and affecting the performance of the processor. Summary of the Invention

[0004] Based on the above technical status quo, this application proposes a page table acquisition method, a memory management unit, a processor, and a computer device, which can improve the page table acquisition efficiency of the processor and thus help improve the performance of the processor.

[0005] A first aspect of this application proposes a page table acquisition method applied to a memory management unit. The method includes:

[0006] After extracting a first page table from a first cache data block, determining the virtual address of a second page table in the first cache data block based on the virtual address of the first page table; wherein, the first cache data block is a cache data block that the memory management unit requests and obtains from the secondary cache based on a first page table request, and the cache data block includes multiple page tables;

[0007] Generating a second page table request for requesting and obtaining the second page table based on the virtual address of the second page table;

[0008] Requesting and obtaining the second page table from the secondary cache based on the second page table request.

[0009] In some implementations, a prefetch page table buffer is included in the memory management unit;

[0010] The requesting to obtain the second page table from the secondary cache based on the second page table request includes:

[0011] Requesting to obtain a second cache data block containing the second page table from the secondary cache based on the second page table request;

[0012] Extracting the second page table from the second cache data block and storing the second page table in the prefetch page table buffer.

[0013] In some implementations, a secondary translation table buffer is further included in the memory management unit, and the method further includes:

[0014] When a page table query request is received, performing a page table query operation in the secondary translation table buffer and the prefetch page table buffer respectively;

[0015] In the case of hitting the second page table in the prefetch page table buffer, storing the second page table in the secondary translation table buffer.

[0016] In some implementations, a secondary translation table buffer is included in the memory management unit. Before requesting to obtain the second page table from the secondary cache based on the second page table request, the method further includes:

[0017] Querying the second page table from the secondary translation table buffer based on the second page table request;

[0018] In the case of not querying the second page table from the secondary translation table buffer, requesting to obtain the second page table from the secondary cache based on the second page table request.

[0019] In some implementations, a page table prefetch unit is included in the memory management unit;

[0020] The determining the virtual address of the second page table in the first cache data block based on the virtual address of the first page table includes:

[0021] The page table prefetch unit determines the virtual addresses of other respective page tables in the first cache data block based on the virtual address of the first page table;

[0022] The page table prefetch unit selects a page table that meets the set prefetch requirements from the other respective page tables as the second page table and determines the virtual address of the second page table; wherein, the set prefetch requirements include at least one of the page table being valid and the page table passing the secondary cache parity check.

[0023] In some implementations, after extracting the first page table from the first cache data block, the method further includes:

[0024] Determining whether the first page table is successfully written into the second-level translation table cache area;

[0025] If the first page table is successfully written into the second-level translation table cache area, determining the virtual address of the second page table in the first cache data block based on the virtual address of the first page table.

[0026] In some implementations, generating a second page table request for requesting to obtain the second page table based on the virtual address of the second page table includes:

[0027] Extracting request element information from the first page table request, where the request element information includes a request privilege level and a conversion rule;

[0028] Using the virtual address of the second page table and the request element information to form a second page table request.

[0029] A second aspect of the present application provides a memory management unit, including:

[0030] A page table prefetch unit, configured to determine the virtual address of the second page table in the first cache data block based on the virtual address of the first page table after extracting the first page table from the first cache data block; where the first cache data block is a cache data block fed back by the second-level cache in response to a first page table request sent by the memory management unit, and the cache data block includes multiple page tables;

[0031] A request generation unit, configured to generate a second page table request for requesting to obtain the second page table based on the virtual address of the second page table;

[0032] A prefetch request unit, configured to request to obtain the second page table from the second-level cache based on the second page table request.

[0033] A third aspect of the present application provides a processor, including the above-mentioned memory management unit;

[0034] Alternatively, the processor is configured to implement the above-mentioned page table acquisition method.

[0035] A fourth aspect of the present application provides a computer device, including the above-mentioned processor.

[0036] In the page table acquisition method proposed in this application, after the memory management unit extracts the first page table from the first cache data block, it determines the virtual address of the second page table in the first cache data block based on the virtual address of the first page table; then, based on the virtual address of the second page table, it generates a second page table request for requesting the acquisition of the second page table; finally, it requests the acquisition of the second page table from the secondary cache based on the second page table request. The above solution enables the memory management unit to send a request for another page table in a certain cache data block in the secondary cache after requesting the first page table in the cache data block, so as to acquire other page tables in advance. On the one hand, this can make the request for accessing other page tables hit the target page table faster. On the other hand, the above processing increases the access frequency of this cache data block, thereby reducing the priority of the page table in this cache data block being replaced by other page tables, extending the residence time of the page table in this cache data block in the secondary cache, further ensuring the page table access timeliness, and facilitating the improvement of the processor performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0038] Figure 1 It is a schematic diagram of a partial structure inside the processor provided by an embodiment of the present application.

[0039] Figure 2 It is a schematic flowchart of the page table acquisition method provided by an embodiment of the present application.

[0040] Figure 3 It is a schematic diagram of the page table prefetch processing process provided by an embodiment of the present application.

[0041] Figure 4 It is a schematic diagram of the page table request processing process provided by an embodiment of the present application.

[0042] Figure 5 It is a schematic diagram of the structure of a memory management unit provided by an embodiment of the present application.

[0043] Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] The technical solution of the embodiment of the present application is applicable to the application scenario where the memory management unit in the processor prefetches the page table from the secondary cache. Adopting the technical solution of the embodiment of the present application can improve the page table prefetch efficiency and the page table reading performance of the processor.

[0045] Figure 1 A partial structural schematic diagram inside the processor is shown.

[0046] Refer to Figure 1 As shown, in the load store unit (LSU) inside the processor, a data prefetch module is provided. The data prefetch module is used to preload data so that when the processor core needs certain data, it can directly read it, thereby improving the running speed of the processor core.

[0047] An L1 TLB (Translation Lookaside Buffer) is provided inside the access unit, that is, the first-level translation table cache. The mapping relationship information between the virtual address and the physical address of the page table is stored in the L1 TLB. When the data prefetch module needs to prefetch a certain page table, it first queries from the L1 TLB using the page table prefetch request. If the corresponding page table is hit in the L1 TLB, the physical address of the page table is obtained from it. If the corresponding page table is not hit in the L1 TLB, the access unit sends the prefetch request to the MMU (Memory Management Unit).

[0048] An access unit request queue and an L2 TLB, that is, the second-level translation table cache, are provided in the MMU. The access unit request queue is used to receive requests from the LSU. The mapping relationship information between the virtual address and the physical address of the page table is also stored in the L2 TLB. In addition, a TBM (Table walk machine, a module responsible for translating the page table level by level) is also provided in the MMU. When the MMU receives a page table prefetch request from the LSU, it stores it in the access unit request queue. Then, the MMU processes the page table prefetch request in the access unit request queue. First, the MMU queries for the page table from the L2 TLB based on the page table prefetch request. If the corresponding target page table is found, it is fed back to the LSU. If the corresponding target page table is not found in the L2 TLB, the page table prefetch request is transferred to the TBM, and the TBM interacts with the L2 cache (that is, the secondary cache) to obtain the target page table from the L2 cache.

[0049] In the L2 cache, data is stored in units of data blocks, such as stored in cache lines. The length of a cache line is 512 bits, while the length of a page table is 64 bits. Therefore, 8 page tables can be stored in one cache data block.

[0050] When the MMU obtains the target page table from the L2 cache, the L2 cache sends a complete cache data block (cache line) where the target page table is located to the MMU. After receiving the cache data block, the MMU selects the target page table from it and stores it in the L2 TLB, and selectively retains other page tables in the cache data block at the same time.

[0051] Based on the above page table prefetch method, when prefetching the target page table, other page tables in the same cache data block as the target page table are loaded into the L2 TLB in advance. This enables the MMU to directly hit other page tables in the L2 TLB when receiving requests for other page tables, so that requests for other page tables are not sent to the L2 cache. As a result, the cache data block storing these page tables is not accessed for a long time, and the page tables stored in the cache data block will be replaced by other page tables after a period of time. At the same time, the page table replacement in the L2 TLB is more frequent and will be replaced by other page tables earlier. In this case, when the MMU receives a request for the page table in the above cache data block again, the corresponding page table cannot be hit in either the L2 TLB or the L2 cache, resulting in a slow page table request and affecting the processor performance.

[0052] To address the above technical problems, an embodiment of the present application proposes a page table acquisition method, which can avoid the page tables in the L2 cache from being replaced prematurely, thereby improving the speed at which the processor reads page tables and facilitating the improvement of processor performance.

[0053] Next, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0054] An embodiment of the present application proposes a page table acquisition method, which is applied to the MMU. Refer to Figure 2 As shown, the method includes:

[0055] S101. After extracting the first page table from the first cache data block, determine the virtual address of the second page table in the first cache data block based on the virtual address of the first page table.

[0056] Among them, the first cache data block is a cache data block fed back by the L2 cache in response to a first page table request sent by the MMU, and the cache data block includes multiple page tables.

[0057] Specifically, when the MMU requests a certain target page table from the L2 cache, it sends a first page table request containing the virtual address of the first page table to the L2 cache.

[0058] After receiving the first page table request, the L2 cache determines the cache line storing the first page table from each cache data block cache line, and sends the entire cache line as the first cache data block to the MMU. As introduced in the above embodiments, multiple page tables can be stored in one cache line in the L2 cache. For example, the length of one cache line in the L2 cache is 512bit, while the length of one page table is 64bit, and 8 page tables can be stored in one cache data block. In this case, the above first cache data block stores 8 page tables including the first page table.

[0059] In other embodiments, the length of one cache line in the L2 cache can be other length values. Correspondingly, the number of page tables included in the above first cache data block can be more than 8 or less than 8, which is not limited in the embodiments of the present application.

[0060] After the MMU receives the first cache data block fed back by the L2 cache in response to the above first page table request, the MMU first extracts the first page table from the first cache data block. For example, assuming the length of the first cache data block is 512bit and the length of one page table is 64bit, at this time, after receiving the first cache data block, the MMU divides the data in the first cache data block according to a 64bit bit width, so as to distinguish the 8 page tables in the first cache data block, and then further identifies the first page table from the 8 page tables according to the low bits of the virtual address of the first page table included in the first page table request.

[0061] Then, based on the virtual address of the first page table, the MMU further determines the virtual address of the second page table in the first cache data block. Among them, the above second page table can be one or more of the other page tables in the first cache data block except the first page table.

[0062] After the MMU identifies the first page table from the 8 page tables in the first cache data block according to the lower bits of the virtual address of the first page table, since the virtual addresses of adjacent page tables are also adjacent. For example, in a 4K page table, the virtual addresses of adjacent page tables are also adjacent in bits [14:12] of the address. Therefore, the virtual address corresponding to the nearby page table can be calculated by adding the offset of the nearby page table to the virtual address of the first page table.

[0063] S102. Generate a second page table request for requesting to obtain the second page table based on the virtual address of the second page table.

[0064] Specifically, after the MMU determines the virtual address of the second page table, it generates a second page table request that includes the virtual address of the second page table and is used to request to obtain the second page table.

[0065] When there are multiple second page tables, one second page table request that includes the virtual addresses of each of the multiple second page tables can be generated, or alternatively, for each second page table, a second page table request that includes its virtual address can be generated separately.

[0066] In some embodiments, after the MMU determines the virtual address of the second page table, it extracts request element information such as the request privilege level and conversion rules from the received first page table request. Then, the MMU uses the virtual address of the second page table and the above request element information to form a second page table request.

[0067] In other embodiments, a prefetch request queue is set inside the MMU. After the MMU generates the above second page table request, it stores it in the prefetch request queue and waits to be sent out.

[0068] S103. Request to obtain the second page table from the secondary cache based on the second page table request.

[0069] Specifically, the MMU sends the generated second page table request to the TBM, and the TBM requests the second page table from the L2 cache by interacting with the L2 cache.

[0070] Exemplarily, in response to the request of the TBM, the L2 cache feeds back the cache data block cacheline storing the second page table to the MMU, and the MMU then extracts the second page table from this cache database.

[0071] It can be understood that since the second page table and the first page table were originally stored in the page tables of the first cache data block, the cache data block fed back by the L2 cache in response to the request of the TBM is essentially still the first cache data block, thus achieving the effect of accessing the first cache data block again.

[0072] After obtaining the second page table, the MMU can store the TLB information of the second page table into the L2 TLB.

[0073] In addition, as disclosed in other embodiments, after the MMU extracts the first page table from the first cache data block, it can immediately perform the processing of steps S101 to S103 above to request the acquisition of the second page table, so that the cache lines storing the first page table and the second page table are accessed multiple times in a very short time, increasing their access frequency.

[0074] Alternatively, after extracting the first page table from the first cache data block, the processing of steps S101 to S103 above can be performed after a set duration. This method can also increase the access frequency of the cache line storing the first page table and the second page table within a period of time. Among them, the above set duration should be less than the cycle duration for the data in the cache line storing the first page table and the second page table to be replaced, that is, after the MMU requests the first page table from the L2 cache to access the cache line storing the first page table and the second page table, it should request the acquisition of the above second page table from the L2 cache again within no more than the cycle duration for the data in this cache line to be replaced.

[0075] As can be seen from the above introduction, in the page table acquisition method proposed in the embodiments of the present application, after the memory management unit extracts the first page table from the first cache data block, it determines the virtual address of the second page table in the first cache data block based on the virtual address of the first page table; then, based on the virtual address of the second page table, it generates a second page table request for requesting the acquisition of the second page table; finally, it requests the acquisition of the second page table from the secondary cache based on the second page table request. The above solution enables the memory management unit to send a request for another page table in the same cache data block in the secondary cache after requesting the first page table in a certain cache data block in the secondary cache, so as to acquire other page tables in advance. On the one hand, this can make the request for accessing other page tables hit the target page table faster. On the other hand, the above processing increases the access frequency of this cache data block, thereby reducing the priority of the page table in this cache data block being replaced by other page tables, extending the residence duration of the page table in this cache data block in the secondary cache, further ensuring the page table access timeliness, and being beneficial to improving the processor performance.

[0076] In some embodiments, refer to Figure 3As shown in the figure, a prefetch page table buffer is also provided inside the MMU. This prefetch page table buffer is a RAM structure different from the L2 TLB, and its size can be flexibly configured. It is specifically used to store the TLB information obtained again from the same cacheline of the target page table after the target page table is prefetched, and to record the offset of the stored page table relative to the target page table. For example, it stores the TLB information of the second page table obtained by the above-mentioned second page table request, and stores the offset of this second page table relative to the first page table. The prefetch page table buffer adopts a first-in-first-out storage mechanism. When the prefetch page table buffer is full, the TLB information of the page table that is newly to be stored in the prefetch page table buffer replaces the TLB information of the page table that entered the buffer earliest.

[0077] After the MMU generates the above-mentioned second page table request, it stores it in the prefetch request queue. Then, the MMU reads the page table prefetch request from the prefetch request queue at an appropriate time for processing.

[0078] When the MMU reads the second page table request from the prefetch request queue, it first queries the second page table from the L2 TLB based on this second page table request. If the TLB information of the second page table is hit in the L2 TLB, the MMU completes the response to this second page table request.

[0079] If the second page table is not queried from the L2 TLB, that is, the TLB information of the second page table is not hit in the L2 TLB, the MMU forwards this request to the TBM, and the TBM requests to obtain the second page table from the L2 cache based on the second page table request.

[0080] For example, the MMU sends the generated second page table request to the TBM, and the TBM requests the second page table from the L2 cache by interacting with the L2 cache.

[0081] During the interaction process, in response to the request from the TBM, the L2 cache feeds back the second cache data block cacheline storing the second page table to the MMU.

[0082] Then, the MMU extracts the second page table from this second cache data block. For example, assume that the length of the second cache data block is 512bit and the length of a page table is 64bit. At this time, after the MMU receives the second cache data block, it divides the data in the second cache data block according to a 64bit bit width, so as to distinguish 8 page tables in the second cache data block, and then further identifies the second page table from the 8 page tables according to the low bits of the virtual address of the second page table included in the second page table request.

[0083] After the second page table is recognized, the MMU stores the second page table in the prefetch page table buffer, that is, stores the TLB information of the second page table in the prefetch page table buffer, rather than directly storing it in the L2 TLB.

[0084] Since the above-mentioned first page table is the page table prefetched by a regular page table prefetch request, and the above-mentioned second page table request is a second page table request sent to the L2 cache to avoid the data in the cacheline storing the first page table and the second page table from being replaced due to long-term inaccessibility. The second page table is not the page table that really needs to be prefetched currently. If the TLB information of the second page table is also directly stored in the L2 TLB, it will cause unnecessary page table TLBs to be stored in the L2 TLB, which will contaminate the information in the L2 TLB and affect the reading efficiency of other necessary page table TLBs. At the same time, since the space of the L2 TLB is limited, too much TLB information that is not currently necessary for prefetching will cause the TLB information that really needs to be prefetched currently to be replaced, thus affecting the processor data reading performance.

[0085] In the embodiment of the present application, after the second page table is obtained by requesting from the L2 cache, it is not directly stored in the L2 TLB, but first stored in a separately set prefetch page table buffer, which can avoid contaminating the information in the L2 TLB by the obtained second page table and ensure the processor data reading performance.

[0086] In addition, before requesting to obtain the second page table from the L2 cache in this embodiment, the second page table is first queried in the L2 TLB. If the second page table is not found in the L2 TLB, then the second page table is requested to be obtained from the L2 cache. This can avoid repeatedly requesting the second page table and wasting computing resources.

[0087] Based on the above prefetch page table storage method, see Figure 4 As shown, when the MMU receives a storage unit request or an instruction fetch unit request, page table query operations are respectively performed in the L2 TLB and the prefetch page table buffer, that is, the page table TLB is respectively queried from the L2 TLB and the prefetch page table buffer. When the second page table is hit in the prefetch page table buffer for the request, the MMU migrates the TLB information of the second page table from the prefetch page table buffer to the L2 TLB. If the requested page table TLB is not hit in both the L2 TLB and the prefetch page table buffer, the requested page table is obtained by interacting with the L2 cache through the TBM.

[0088] In this embodiment, when the MMU receives a page table request, it performs a page table TLB query operation in the L2 TLB and the prefetch page table buffer respectively, which can improve the query hit rate. At the same time, in this embodiment, after the TLB information in the prefetch page table buffer is requested, it can be transferred to the L2 TLB, so as to realize the efficient update of the data in the L2 TLB, improve the probability that the MMU hits the page table from the L2 TLB, and improve the space utilization rate of the prefetch page table buffer.

[0089] In another embodiment, a page table prefetch unit is also separately provided in the MMU. The page table prefetch unit is specifically used to determine the virtual addresses of other page tables in the cache data block based on the virtual address of the target page table after the MMU receives the cache data block and extracts the target page table from the cache data block.

[0090] When the MMU obtains the first cache data block fed back by the L2 cache in response to the first page table request, when determining the virtual address of the second page table in the first cache data block based on the virtual address of the first page table, first, the page table prefetch unit determines the virtual addresses of other page tables in the first cache data block based on the virtual address of the first page table.

[0091] For example, assume that the length of the first cache data block is 512 bit and the length of a page table is 64 bit. At this time, after the MMU receives the first cache data block, the page table prefetch unit divides the data in the first cache data block according to a 64-bit width, so as to distinguish 8 page tables in the first cache data block, and then further identifies the first page table from the 8 page tables according to the low bits of the virtual address of the first page table included in the first page table request.

[0092] Then, the page table prefetch unit further determines the virtual addresses of other page tables in the first cache data block based on the virtual address of the first page table. Specifically, after the page table prefetch unit identifies the first page table from the 8 page tables in the first cache data block according to the low bits of the virtual address of the first page table, since the virtual addresses of adjacent page tables are also adjacent, for example, in a 4k page table, the virtual addresses corresponding to adjacent page tables are also adjacent in the [14:12] bits of the address. Therefore, the page table prefetch unit can calculate the virtual address corresponding to the nearby page table by adding the offset of the nearby page table to the virtual address of the first page table.

[0093] Then, the page table prefetch unit selects the page tables that meet the set prefetch requirements from other page tables as the second page table and determines the virtual address of the second page table.

[0094] Among them, the above set prefetch requirements include at least one of page table validity and page table passing the second-level cache parity check.

[0095] That is, the page table prefetch unit selects a page table that can be requested again from other page tables based on the validity and parity check results of each other page table parsed from the first cache data block as the second page table.

[0096] Specifically, when the L2 cache feeds back the cache data block to the MMU, it will also feed back whether the page table stored in the cache data block is valid, and will also feed back the parity check result of the L2 cache on the page table, such as whether it passes the parity check of the L2 cache. The page table prefetch unit can determine whether each page table is valid and whether it passes the parity check of the L2 cache based on the validity information and parity check information of each page table in the first cache data block. On this basis, the page table prefetch unit selects one or more page tables that are valid and pass the parity check of the L2 cache from each other page table as the second page table, and further determines the virtual address of the second page table based on the virtual addresses of each page table that have been determined in advance.

[0097] In another embodiment, before determining the virtual address of the second page table in the first cache data block based on the virtual address of the first page table, it is first determined whether the first page table is successfully written into the L2 TLB.

[0098] For example, before the page table prefetch unit calculates the virtual addresses of other page tables in the first cache data block based on the virtual address of the first page table, it first determines whether the first page table is successfully written into the L2 TLB. If the first page table is not successfully written into the L2 TLB, for example, an exception occurs when the first page table is finally converted into the TLB, it is considered that the first page table is not successfully written into the L2 TLB. At this time, the page table prefetch unit no longer calculates the virtual addresses of other page tables in the first cache data block, and thus no longer prefetches other page tables in the first cache data block. If the first page table is successfully written into the L2 TLB, it means that the prefetch of the first page table is successfully completed. In this case, the page table prefetch unit can determine the virtual address of the second page table in the first cache data block based on the virtual address of the first page table, that is, it can prefetch the second page table in the first cache data block.

[0099] This embodiment determines whether the first page table in the first cache data block is successfully prefetched before prefetching other page tables in the first cache data block, thereby avoiding invalid page table prefetch and wasting processor computing resources.

[0100] Corresponding to the above page table acquisition method, an embodiment of the present application also proposes a memory management unit. See Figure 5 As shown, the memory management unit includes:

[0101] The page table prefetch unit 100 is configured to, after extracting a first page table from a first cache data block, determine the virtual address of a second page table in the first cache data block based on the virtual address of the first page table; wherein, the first cache data block is a cache data block fed back by a secondary cache in response to a first page table request sent by the memory management unit, and the cache data block includes multiple page tables.

[0102] The request generation unit 110 is configured to generate a second page table request for requesting to obtain the second page table based on the virtual address of the second page table.

[0103] The prefetch request unit 120 is configured to request to obtain the second page table from the secondary cache based on the second page table request.

[0104] In some implementation manners, a prefetch page table buffer is included in the above-mentioned memory management unit.

[0105] The prefetch request unit 120 requests to obtain the second page table from the secondary cache based on the second page table request, including:

[0106] Requesting to obtain a second cache data block containing the second page table from the secondary cache based on the second page table request.

[0107] Extracting the second page table from the second cache data block and storing the second page table into the prefetch page table buffer.

[0108] In some implementation manners, a secondary translation table buffer is further included in the memory management unit, and the memory management unit further includes a page table query processing unit, which is configured to perform page table query operations in the secondary translation table buffer and the prefetch page table buffer respectively when receiving a page table query request; in the case of hitting the second page table in the prefetch page table buffer, storing the second page table into the secondary translation table buffer.

[0109] In some implementation manners, a secondary translation table buffer is included in the memory management unit. Before the prefetch request unit 120 requests to obtain the second page table from the secondary cache based on the second page table request, it further queries the second page table from the secondary translation table buffer based on the second page table request; in the case of not querying the second page table from the secondary translation table buffer, requesting to obtain the second page table from the secondary cache based on the second page table request.

[0110] In some implementation manners, the page table prefetch unit 100 determines the virtual address of the second page table in the first cache data block based on the virtual address of the first page table, including:

[0111] The page table prefetching unit determines the virtual addresses of other page tables in the first cache data block based on the virtual address of the first page table;

[0112] The page table prefetching unit selects a page table that meets the set prefetching requirements from the other page tables as the second page table, and determines the virtual address of the second page table; wherein, the set prefetching requirements include at least one of the page table being valid and the page table passing the secondary cache parity check.

[0113] In some implementation manners, after the page table prefetching unit 100 extracts the first page table from the first cache data block, it also determines whether the first page table is successfully written into the secondary translation table cache area; if the first page table is successfully written into the secondary translation table cache area, it determines the virtual address of the second page table in the first cache data block based on the virtual address of the first page table.

[0114] In some implementation manners, the request generation unit 110 generates a second page table request for requesting to obtain the second page table based on the virtual address of the second page table, including: extracting request element information from the first page table request, where the request element information includes a request privilege level and a conversion rule; using the virtual address of the second page table and the request element information to form the second page table request.

[0115] The memory management unit provided in this embodiment belongs to the same inventive concept as the page table acquisition method provided in the above embodiments of the present application, can execute the page table acquisition method provided in any of the above embodiments of the present application, and has the corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference may be made to the specific processing content of the page table acquisition method provided in the above embodiments of the present application, which will not be elaborated here.

[0116] The functions implemented by the above page table prefetching unit 100, request generation unit 110, and prefetch request unit 120 can be implemented by the same or different processors respectively, which is not limited in the embodiments of the present application.

[0117] It should be understood that the above units can be implemented in the form of software called by a processor. Alternatively, each unit in the memory management unit can be implemented in the form of a hardware circuit. By designing the hardware circuit, the functions of some or all of the units can be realized. This hardware circuit can be understood as one or more processors. For example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above units are realized by designing the logical relationships of the components in the circuit. Another example is that in another implementation, the hardware circuit can be implemented by a PLD. Taking an FPGA as an example, it can include a large number of logic gate circuits, and the connection relationships between the logic gate circuits are configured through a configuration file to realize the functions of some or all of the above units. All units of the memory management unit can be all implemented in the form of software called by a processor, or all implemented in the form of a hardware circuit, or some implemented in the form of software called by a processor and the remaining part implemented in the form of a hardware circuit.

[0118] In the embodiments of the present application, a processor is a circuit with the ability to process signals. In one implementation, the processor can be a circuit with the ability to read and execute instructions, such as a CPU, a microprocessor, a GPU, or a DSP, etc. In another implementation, the processor can realize certain functions through the logical relationships of a hardware circuit, and the logical relationships of this hardware circuit are fixed or can be reconfigured. For example, the processor is a hardware circuit implemented by an ASIC or a PLD, such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document to realize the configuration of the hardware circuit can be understood as the process of the processor loading instructions to realize the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as an NPU, a TPU, a DPU, etc.

[0119] It can be seen that each unit in the above memory management unit can be one or more processors (or processing circuits) configured to implement the above methods. For example: a CPU, a GPU, an NPU, a TPU, a DPU, a microprocessor, a DSP, an ASIC, an FPGA, or a combination of at least two of these processor forms.

[0120] Corresponding to the above page table prefetch processing method, other embodiments of the present application also propose a processor, which includes the memory management unit introduced in any of the above embodiments, or the processor is configured to implement the page table acquisition method introduced in any of the above embodiments.

[0121] In addition, another embodiment of the present application also proposes a computer device, which includes the above processor.

[0122] Exemplarily, the computer device can be a computer, a server, a smart terminal, a handheld terminal, a wearable terminal, etc.

[0123] Another embodiment of the present application further provides an electronic device. Refer to Figure 6 As shown, the device includes:

[0124] a memory 200 and a processor 210;

[0125] wherein, the memory 200 is connected to the processor 210 and is used for storing programs;

[0126] The processor 210 includes the memory management unit introduced in any of the above embodiments. Based on the structure and function of the memory management unit, the processor 210 realizes the page table acquisition method disclosed in any of the above embodiments by running the program stored in the memory 200.

[0127] Specifically, the above electronic device may further include: a bus, a communication interface 220, an input device 230, and an output device 240.

[0128] The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are interconnected through the bus. Among them:

[0129] The bus may include a path for transmitting information between various components of the computer system.

[0130] The processor 210 may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0131] The processor 210 may include a main processor and may also include a baseband chip, a modem, etc.

[0132] The memory 200 stores a program for implementing the technical solution of the present invention and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory 200 may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, etc.

[0133] The input device 230 may include devices for receiving user input data and information, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0134] The output device 240 may include devices for allowing information to be output to the user, such as a display screen, a printer, a speaker, etc.

[0135] The communication interface 220 may include devices of any transceiver type for communicating with other devices or communication networks, such as Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc.

[0136] The processor 210 executes the programs stored in the memory 200 and calls other devices, and can be used to implement the various steps of any one of the page table acquisition methods provided in the above embodiments of the present application.

[0137] An embodiment of the present application also proposes a chip, which includes a processor and a data interface. The processor includes the memory management unit introduced in any of the above embodiments. The processor reads and runs the programs stored on the memory through the data interface to implement the page table acquisition method introduced in any of the above embodiments. The specific processing process and its beneficial effects can be referred to the embodiment introduction of the above page table processing method.

[0138] For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0139] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0140] The steps in the methods of the embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The technical features recorded in each embodiment can be replaced or combined.

[0141] The modules and sub-modules in the devices and terminals in the embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0142] In several embodiments provided by this application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or modules, and can be in electrical, mechanical, or other forms.

[0143] The modules or sub-modules described as separate components may or may not be physically separated. The components as modules or sub-modules may or may not be physical modules or sub-modules, that is, they can be located in one place, or they can be distributed to multiple network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0144] In addition, in each embodiment of this application, each functional module or sub-module can be integrated in a processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The above-mentioned integrated modules or sub-modules can be implemented in the form of hardware or in the form of software functional modules or sub-modules.

[0145] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0146] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software units executed by a processor, or a combination of the two. The software units can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0147] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0148] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A page table acquisition method, characterized in that, Applied to a memory management unit, the method includes: After extracting a first page table from a first cache data block, determining the virtual address of a second page table in the first cache data block based on the virtual address of the first page table; wherein, the first cache data block is a cache data block obtained by the memory management unit requesting from a secondary cache based on the first page table request, and the cache data block includes multiple page tables; Generating a second page table request for requesting to obtain the second page table based on the virtual address of the second page table; Requesting to obtain the second page table from the secondary cache based on the second page table request.

2. The method according to claim 1, characterized in that, A prefetch page table buffer is included in the memory management unit; The requesting to obtain the second page table from the secondary cache based on the second page table request includes: Requesting to obtain a second cache data block containing the second page table from the secondary cache based on the second page table request; Extracting the second page table from the second cache data block and storing the second page table into the prefetch page table buffer.

3. The method according to claim 2, wherein A secondary translation table buffer is further included in the memory management unit, and the method further includes: When receiving a page table query request, performing page table query operations in the secondary translation table buffer and the prefetch page table buffer respectively; In the case of hitting the second page table in the prefetch page table buffer, storing the second page table into the secondary translation table buffer.

4. The method according to any one of claims 1 to 3, characterized in that A secondary translation table buffer is included in the memory management unit. Before requesting to obtain the second page table from the secondary cache based on the second page table request, the method further includes: Querying the second page table from the secondary translation table buffer based on the second page table request; In the case of not querying the second page table from the secondary translation table buffer, requesting to obtain the second page table from the secondary cache based on the second page table request.

5. The method according to any one of claims 1 to 3, characterized in that A page table prefetch unit is included in the memory management unit; The determining the virtual address of the second page table in the first cache data block based on the virtual address of the first page table includes: The page table prefetch unit determining the virtual addresses of other respective page tables in the first cache data block based on the virtual address of the first page table; The page table prefetch unit selecting a page table that meets the set prefetch requirements as the second page table from the other respective page tables and determining the virtual address of the second page table; wherein, the set prefetch requirements include at least one of page table validity and page table passing the secondary cache parity check.

6. The method according to any one of claims 1 to 3, characterized in that, After extracting the first page table from the first cache data block, the method further includes: Determining whether the first page table is successfully written into the secondary translation table buffer; If the first page table is successfully written into the secondary translation table buffer, determining the virtual address of the second page table in the first cache data block based on the virtual address of the first page table.

7. The method according to any one of claims 1 to 3, characterized in that, The generating a second page table request for requesting to obtain the second page table based on the virtual address of the second page table includes: Extracting request element information from the first page table request, and the request element information includes a request privilege level and a conversion rule; Compose a second page table request by using the virtual address of the second page table and the request element information.

8. A memory management unit, characterized in that, It includes: A page table prefetch unit, configured to, after extracting a first page table from a first cache data block, determine the virtual address of a second page table in the first cache data block based on the virtual address of the first page table; wherein, the first cache data block is a cache data block fed back by a secondary cache in response to a first page table request sent by the memory management unit, and the cache data block includes a plurality of page tables. A request generation unit, configured to generate a second page table request for requesting to obtain the second page table based on the virtual address of the second page table. A prefetch request unit, configured to request to obtain the second page table from the secondary cache based on the second page table request.

9. A processor, characterized in that, It includes the memory management unit as described in claim 8. Alternatively, the processor is configured to implement the page table acquisition method as described in any one of claims 1 to 7.

10. A computer device, characterized in that, It includes the processor as described in claim 9.

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