Multi-channel refresh control circuit, device, system and method

Abstract

The invention relates to a multi-channel refresh control circuit, device, system and method, and the circuit comprises a channel arbitration unit which is configured to be connected with a plurality of hosts, can receive a plurality of refresh commands of the hosts, and carries out the arbitration of the plurality of refresh commands, so as to judge the refresh command needing to be executed; the command decoding unit is connected with the channel arbitration unit and can decode the refreshing command needing to be executed; the address decoding unit is connected with the command decoding unit and can decode the address information of the refreshing command; and the refresh control signal generation unit is connected with the address decoding unit, is configured to be connected with a storage circuit, and can refresh the storage circuit based on the decoded refresh command and the address information. In this way, the efficiency of refreshing control over the storage device by multiple hosts can be improved through the embodiment.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to a multi-channel refresh control circuit, device, system and method. Background Art

[0002] Dynamic random access memories (DRAMs), such as DDR (Double Data Rate SDRAM), GDDR (Graphics Double Data Rate SDRAM), LPDDR (Low Power Double Data Rate SDRAM), and HBM (High Bandwidth Memory), etc., are volatile memories widely used in computer systems. The internal storage units thereof usually adopt a 1T1C (one transistor and one capacitor) structure to store each bit of data. This structure is simple and occupies less space. However, the charge in the capacitor will leak over time, resulting in data loss. Therefore, DRAMs need to be refreshed regularly through refresh operations to maintain data security and stability.

[0003] To implement these refresh operations, the main control circuit (Main Controller) of a DRAM chip will include a refresh-related control circuit (Refresh Controller). After receiving a refresh command from the interface, the DRAM generates a refresh control signal through this control circuit to refresh the DRAM. The refresh and other commands received by the DRAM interface are usually sent from the DRAM Controller and DDR PHY (Double Data Rate Physical Layer) of the main chip to the DRAM chip. In the prior art, in the case of multiple hosts sharing the DRAM memory, different hosts sharing the memory can only send refresh commands to the storage chip through the same DRAM Controller. Since these hosts need to send signals to the DRAM Controller integrated with multiple control functions through a bus, the response and processing of the refresh commands are slow. This also results in low access efficiency to the storage chip in this case.

[0004] Currently, for the problem of low access efficiency of multiple hosts to the storage memory in the prior art, no effective solution has been proposed. Summary of the Invention

[0005] In view of the above problems, the present invention provides a multi-channel refresh control circuit, device, and system, including: a channel arbitration unit configured to be connected to multiple hosts, capable of receiving multiple refresh commands from the multiple hosts, and arbitrating the multiple refresh commands to determine the refresh command to be executed;

[0006] A command decoding unit connected to the channel arbitration unit, capable of decoding the refresh command to be executed;

[0007] An address decoding unit connected to the command decoding unit, capable of decoding the address information of the refresh command; and

[0008] A refresh control signal generation unit connected to the address decoding unit and the command decoding unit respectively, and configured to be connected to a storage circuit, capable of generating a refresh control signal based on the decoded refresh command and address information, and refreshing the storage circuit according to the refresh control signal.

[0009] In summary, the present invention introduces a multi-channel refresh control circuit including a channel arbitration unit. The channel arbitration unit can receive multiple refresh commands from multiple hosts, and arbitrate the multiple refresh commands to determine the refresh command to be executed, so that when multiple refresh commands from multiple channels / hosts / processors are received, rapid response, arbitration, and refreshing can be achieved. Compared with the prior art's refresh control scheme through a storage control circuit, the refresh efficiency of the storage circuit can be effectively improved.

[0010] To solve the above technical problems, the present invention provides a storage device, including the multi-channel refresh control circuit described above, and further including:

[0011] A storage circuit configured to be connected to the multi-channel refresh control circuit, and the storage circuit includes multiple storage sub-circuits;

[0012] A storage sub-circuit capable of receiving a refresh command.

[0013] In summary, this embodiment provides a storage circuit connected to the multi-channel refresh control circuit. The storage circuit includes at least one storage sub-circuit. The storage sub-circuit can receive multiple refresh commands from multiple hosts / channels / processors through the channel arbitration unit included in the multi-channel refresh control circuit, and arbitrate the multiple refresh commands to determine the refresh command to be executed, so that the multi-channel refresh control circuit in the present application can receive refresh commands from multiple channels, and the refresh efficiency of the storage circuit can be effectively improved.

[0014] To solve the above technical problems, the present invention provides a storage device, including the multi-channel refresh control circuit described above, and further including:

[0015] A storage circuit, configured to be connected to a multi-channel refresh control circuit, and the storage circuit includes at least one storage module;

[0016] The storage module is capable of receiving a refresh command

[0017] In summary, the present embodiment provides the above storage module. In practical applications, a storage device may include multiple storage modules, and may perform corresponding refresh operations according to the received refresh command, and can complete the refresh of the storage device more flexibly.

[0018] To solve the above technical problems, the present invention provides a storage system, which is applied to the above multi-channel refresh control circuit or the above storage device, and further includes:

[0019] A storage control circuit, connected to the multi-channel refresh control circuit, and capable of controlling the operation of the storage device.

[0020] Optionally, the storage control circuit is configured to be connected to multiple hosts. Furthermore, it can receive refresh commands transmitted from multiple hosts simultaneously and determine the refresh commands that need to be executed among them.

[0021] Optionally, the multi-channel refresh control circuit is configured to be connected to multiple hosts.

[0022] Optionally, the storage system further includes a status monitoring module;

[0023] The status monitoring module is configured to be connected to the storage device and the multi-channel refresh control circuit respectively, and capable of monitoring the refresh result of the storage device;

[0024] The status monitoring module is further configured to generate an alarm signal when an abnormality is detected, and / or adjust the generation strategy of the refresh command of the multi-channel refresh control circuit.

[0025] Optionally, the storage device includes at least one of the following: Flash memory chip, DRAM memory chip, SRAM memory chip, MRAM memory chip, RRAM memory chip.

[0026] Optionally, the channel arbitration unit is connected to the host through at least one of the following connection methods: Wirebonding, Hybrid bonding, FlipChip, TSV, mini-TSV.

[0027] In summary, the multi-channel refresh control circuit provided by the present application can receive multiple host refresh control instructions simultaneously by introducing a channel arbitration unit and cooperating with a multi-channel design connected to multiple hosts, and arbitrate multiple refresh control instructions based on the channel arbitration unit to determine the refresh operation that needs to be executed, thereby effectively improving the refresh efficiency of the storage circuit in the shared storage memory scenario. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the multi-channel refresh control circuit structure in an embodiment;

[0029] Figure 2 It is a schematic diagram of the structure of a storage device in an embodiment;

[0030] Figure 3 It is a schematic diagram of the structure of a storage device in another embodiment;

[0031] Figure 4 It is a schematic diagram of the storage system structure in an embodiment;

[0032] Figure 5 It is a schematic diagram of the storage system structure in a preferred embodiment;

[0033] Figure 6 It is a schematic diagram of the control method flow in an embodiment. Detailed Embodiment

[0034] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0035] This embodiment provides a multi-channel refresh control circuit 10, as Figure 1 shown, including: an arbitration unit 11, configured to be connected to multiple hosts, capable of receiving multiple refresh commands from multiple hosts, and arbitrating the multiple refresh commands to determine the refresh command to be executed;

[0036] a command decoding unit 12, connected to the arbitration unit 11, capable of decoding the refresh command to be executed;

[0037] an address decoding unit 13, connected to the command decoding unit 12, capable of decoding the address information of the refresh command; and

[0038] a refresh control signal generation unit 14, respectively connected to the address decoding unit 13 and the command decoding unit 12, and configured to be connected to a storage circuit, capable of generating a refresh control signal based on the decoded refresh command and address information, and refreshing the storage circuit based on the refresh control signal.

[0039] Specifically, in this embodiment, the multi-channel refresh control circuit 10 is respectively connected to the storage circuit and multiple hosts, and is configured to receive multiple refresh commands sent by the multiple hosts, arbitrate the multiple refresh commands to determine the refresh commands that need to be executed, and send the refresh commands that need to be executed to the storage circuit, so that the storage circuit completes the corresponding refresh operation based on the refresh commands.

[0040] Further, according to Figure 1 It can be known that the multi-channel refresh control circuit 10 in this application includes a channel arbitration unit 11, a command decoding unit 12, an address decoding unit 13, and a refresh control signal generation unit 14, and the channel arbitration unit 11, the command decoding unit 12, the address decoding unit 13, and the refresh control signal generation unit 14 are connected in sequence. The channel arbitration unit 11 can be directly connected to multiple hosts to directly obtain the refresh commands sent by the multiple hosts, or can be connected to the hosts through the storage control circuit DRAM Controller. In some preferred embodiments, if the multi-channel refresh control circuit 10 and the host are based on the same channel protocol, the channel arbitration unit 11 in the multi-channel refresh control circuit 10 can be directly connected to the multiple hosts through the refresh channel, and if the multi-channel refresh control circuit 10 and the host are not based on the same channel protocol, signal interaction needs to be performed through the DRAM Controller. After the channel arbitration unit 11 obtains multiple refresh commands, it arbitrates the multiple refresh commands to determine the refresh commands that need to be executed. In some preferred embodiments, the refresh commands that need to be executed can be determined according to the priorities of the current tasks of each host, that is, the priorities, frequencies, and execution modes of the operations of the refresh control circuit can be dynamically adjusted according to the host (or processor) with the highest current task priority. Further, the refresh commands can include dynamic adjustments to the refresh period, refresh frequency, and refresh order.

[0041] Further, after the channel arbitration unit 11 determines the refresh command to be executed, it sends the refresh command to the command decoding unit 12. The command decoding unit 12 decodes the refresh command, and a series of digital signals or timing control signals can be obtained after decoding, which are used for refreshing control of the storage circuit, and the decoded refresh command is sent to the refresh control signal generation unit 14. Then, the address decoding unit 13 decodes the address information of the refresh command, and a pseudo-random sequence generator can be used to generate a refresh address, and the address is sent to the refresh control signal generation unit 14. Finally, through the refresh control signal generation unit 14, based on the decoded refresh command and its address information, refresh control signals are generated, and the storage circuit is refreshed based on the refresh control signals. Among them, the refresh control signal generation unit 14 can be directly connected to the storage circuit, and in this embodiment, the refresh control signal generation unit 14 can generate various refresh control signals according to the decoded command and address information, such as row address strobe signals, column address strobe signals, and segment signals, etc., to adapt to different DRAM chip types.

[0042] In summary, through the solution in this embodiment, refresh commands of multiple channels can be received, and according to the working conditions of each host or the arbitration rules preset in the channel arbitration unit 11, the refresh command to be executed is determined from multiple refresh commands, solving the problem in the prior art that in a shared memory scenario, multiple hosts can only perform refresh control on the memory through a single refresh channel, resulting in low refresh efficiency, and improving the efficiency of multiple hosts in refreshing and controlling the storage memory.

[0043] Further, the present application also provides a storage device 20, as Figure 2 shown. The storage device 20 includes the above multi-channel refresh control circuit 10, and further includes a storage circuit 22:

[0044] The storage circuit 22 is configured to be connected to the multi-channel refresh control circuit 10, and the storage circuit 22 includes at least one storage sub-circuit 21.

[0045] Specifically, the storage circuit 22 generally may include multiple storage sub-circuits 21. In some preferred embodiments, each storage sub-circuit 21 may also include multiple storage banks. When the storage circuit 22 obtains the refresh command to be executed transmitted by the multi-channel refresh control circuit 10, it can be refreshed through the storage sub-circuit 21 based on the refresh command.

[0046] Further, the present application also provides another storage device 30, as Figure 3 shown. The storage device 30 includes the above multi-channel refresh control circuit 10, and further includes a storage circuit 32:

[0047] A storage circuit 32, configured to be connected to a multi-channel refresh control circuit, and the storage circuit 32 includes at least one storage module 31;

[0048] The storage module 31 is capable of receiving a refresh command.

[0049] Specifically, in practical applications, the above storage module 31 can also be referred to as a storage bank; in some embodiments, the storage circuit 32 includes multiple storage modules 31. Further, the storage circuit 32 performs a refresh operation based on a refresh command that needs to be executed and transmitted through the multi-channel refresh control circuit 10, and the storage module 31 performs a refresh operation based on this refresh command. Further, in this embodiment, the refresh control circuit supports the multi-bank parallel refresh function, that is, it can perform refresh operations on multiple storage banks simultaneously; it also supports the single-bank sequential refresh function, that is, it can perform a refresh operation on only one corresponding storage bank each time. And, in this embodiment, the refresh control circuit also supports controlling multiple sub-storage circuits to perform refreshing simultaneously, where the sub-storage circuit 32 can be a storage circuit 32 including multiple storage banks. In summary, through this embodiment, the refresh control of the storage circuit 32 can be realized more flexibly.

[0050] Further, this application also provides a storage system, as Figure 4 shown, this storage system applies the multi-channel refresh control circuit 10 described above, or, the storage device described above, and this storage system further includes a storage control circuit 41, connected to the multi-channel refresh control circuit 10, and capable of controlling the operation of the storage device.

[0051] Specifically, in this embodiment, the storage control circuit 41 can be connected to the refresh channels corresponding to all hosts, or can also be connected to the refresh channels corresponding to some hosts. In some preferred embodiments, the storage control circuit 41 can be set as a DRAM Controller. In practical applications, if the multi-channel refresh control circuit 10 and the host are based on the same channel protocol, the multi-channel refresh control circuit 10 can be directly connected to the host through the refresh channel, and if the refresh control circuit and the host are not based on the same channel protocol, then it is necessary to connect to the host through the storage control circuit 41 DRAM Controller. Further, the storage control circuit 41 can also be used to control the operation of the storage device, such as coordinating data read / write access requests and refresh commands to ensure that the two do not conflict and maintain system efficiency, and can also be used to trigger the refresh request of the storage device at a preset time interval to realize the self-refresh of the storage device, etc.

[0052] Further, the storage control circuit is configured to be connected to multiple hosts.

[0053] Specifically, the storage control circuit DRAM Controller can be set to connect to multiple hosts to obtain refresh instructions from multiple hosts and further send them to the refresh control circuit. In practical applications, when it is detected that the host and the refresh control circuit do not comply with the same channel protocol, the host and the refresh control circuit can be connected through the storage control circuit to complete their signal interaction. Further, by connecting the refresh control circuit to the host through the storage control circuit, the host can directly monitor the behavior of the refresh circuit, and the refresh strategy can also be better optimized.

[0054] Further, the multi-channel refresh control circuit is configured to connect to multiple hosts.

[0055] Specifically, the refresh control circuit can be directly connected to the host without connecting to the host through the storage control circuit.

[0056] Further, the storage system further includes a status monitoring module;

[0057] The status monitoring module is configured to be connected to the storage device and the multi-channel refresh control circuit respectively, and can monitor the refresh result of the storage device;

[0058] The status monitoring module is also used to generate an alarm signal when an abnormality is detected, and / or adjust the generation strategy of the refresh command of the multi-channel refresh control circuit.

[0059] Specifically, the status monitoring module can be connected to the storage device to monitor the operating parameters of the storage device in real time, such as temperature, voltage, error rate, etc., and can analyze the storage device based on the collected data to determine whether the working state of the storage device is normal.

[0060] Further, on this basis, the status monitoring module is also connected to the multi-channel refresh control circuit, and can generate a corresponding alarm signal when an abnormality is detected in the storage device, and in some embodiments, the generation strategy of the refresh command of the multi-channel refresh control circuit can also be adjusted, such as adjusting parameters such as the refresh period and refresh frequency.

[0061] Further, the connection methods between the storage device and the host include but are not limited to Wire bonding, Hybridbonding, FlipChip, TSV, mini-TSV, etc.

[0062] Further, although DRAM storage chips / devices are used as examples in this embodiment, the storage devices mentioned in this embodiment include but are not limited to Flash storage chips, DRAM storage chips, SRAM storage chips, MRAM storage chips, RRAM storage chips, etc.

[0063] Furthermore, the present application also provides a preferred embodiment of a storage system. Figure 5 It is a schematic structural diagram of a storage system in a preferred embodiment.

[0064] As can be seen from Figure 5 , there are two hosts (host1, host2) connected to the storage device simultaneously, and both hosts can send refresh commands to the DRAM of the storage device. Among them, host1 is directly connected to the multi-channel refresh control circuit and directly sends refresh command 1 to refresh command channel 1 of the multi-channel refresh control circuit, while host2 is connected to the multi-channel refresh control circuit through the storage control circuit and sends refresh command 2 to refresh command channel 2 of the multi-channel refresh control circuit through the storage control circuit. Subsequently, the channel arbitration unit 11 in the multi-channel refresh control circuit screens refresh command 1 and refresh command 2, and finally determines that host1 takes over the refresh control of the storage device. Thus, the storage device shields the refresh command from host2 and performs operations such as command decoding, address decoding, and control signal generation on the refresh command from host1 based on the multi-channel refresh control circuit, and outputs a refresh operation signal corresponding to refresh command 1 from host1 to the storage device. Among them, the above refresh command 1 is preferably set as an all-bank refresh command. Through this embodiment, the efficiency of multi-host memory refresh control can be improved in the scenario of multi-host sharing a storage device.

[0065] So far, the technical solution of the present application has been described with reference to the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present application is obviously not limited to the above specific embodiments. Without departing from the principle of the present application, those skilled in the art can make equivalent changes or replacements to the relevant technical features, and the technical solutions after these changes or replacements will all fall within the protection scope of the present application.

Claims

1. A multi-channel refresh control circuit, characterized in that, Comprising: A channel arbitration unit, configured to be connected to multiple hosts, capable of receiving multiple refresh commands of the multiple hosts, and arbitrating the multiple refresh commands to determine the refresh command to be executed; A command decoding unit, connected to the channel arbitration unit, capable of decoding the refresh command to be executed; An address decoding unit, connected to the command decoding unit, capable of decoding the address information of the refresh command; And A refresh control signal generation unit, connected to the address decoding unit, and configured to be connected to a storage circuit, capable of refreshing the storage circuit based on the decoded refresh command and the address information.

2. A storage device, comprising the multi-channel refresh control circuit described in claim 1, characterized in that, Further comprising: A storage circuit, configured to be connected to the multi-channel refresh control circuit, and the storage circuit includes at least one storage sub-circuit; The storage sub-circuit, capable of receiving the refresh command.

3. A storage device, comprising the multi-channel refresh control circuit described in claim 1, characterized in that, Further comprising: A storage circuit, configured to be connected to the multi-channel refresh control circuit, and the storage circuit includes at least one storage module; The storage module, capable of receiving the refresh command.

4. A storage system, applying the multi-channel refresh control circuit according to claim 1, or the storage device according to claim 2, or the storage device according to claim 3, characterized in that, Further comprising: A storage control circuit, connected to the multi-channel refresh control circuit, and capable of controlling the operation of the storage device.

5. The storage system according to claim 4, wherein The storage control circuit is configured to be connected to the multiple hosts.

6. The storage system according to claim 4, wherein The multi-channel refresh control circuit is configured to be connected to the multiple hosts.

7. The storage system according to claim 4, wherein The storage system further includes an integrated verification module; The integrated verification module, configured to be connected to the storage device, and capable of performing verification processing on the refresh result of the storage device.

8. The storage system according to claim 4, wherein The storage system further includes a status monitoring module; The status monitoring module, configured to be respectively connected to the storage device and the multi-channel refresh control circuit, and capable of monitoring the refresh result of the storage device; The status monitoring module is further configured to generate an alarm signal when an abnormality is detected, and / or adjust the generation strategy of the refresh command of the multi-channel refresh control circuit.

9. A control method is applied to the multi-channel refresh control circuit as described in claim 1, characterized in that, The method includes: An arbitration step: obtaining multiple refresh commands of multiple hosts, and arbitrating the multiple refresh commands to determine the refresh command to be executed; A decoding step: decoding the refresh command to be executed; A decoding step: decoding the address information of the refresh command; and A refresh step: performing a refresh process on a corresponding storage circuit based on the decoded refresh command and the address information.

10. The control method according to claim 9, characterized in that, The arbitrating the multiple refresh commands to determine the refresh command to be executed includes: Controlling the channel arbitration unit to arbitrate the multiple refresh commands based on a preset arbitration rule, where the arbitration rule includes at least one of the following: a priority rule, a timestamp rule, a polling rule.

11. The control method according to claim 10, wherein The performing a refresh process on a corresponding storage circuit based on the decoded refresh command and the address information includes: Optimizing the refresh process based on a preset storage circuit refresh optimization strategy.

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