Data reading state updating method and data processing chip
By introducing initial pulse registers and cached data registers into the chip design, ensuring that the synchronization register is updated after RDMA data is read, the problem of high data read error rate is solved and the chip's performance and data processing efficiency are improved.
Patent Information
- Application Number
- CN202510584835.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-08-01
AI Technical Summary
In chip design, data dependence between computing units leads to limited OCM capacity, and the combination of task over-issuance and blocking instructions leads to conflicts between data integrity and storage multiplexing, increasing data read error rate and reducing chip performance.
By introducing the initial pulse register and the initial data register, the updated data is temporarily stored and updated to the cached data register until the data is read is completed, ensuring that the synchronization register is not updated before the RDMA completes the data reading, and non-blocking instructions are used to improve task execution efficiency.
Reduces the data read error rate, improves the chip's performance and the accuracy and consistency of data read status updates.
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Figure CN120407472A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the technical field of chip design, and in particular, to a method for updating data reading status and a data processing chip. Background Art
[0002] In chip design, multiple arithmetic units need to share on-chip memory (OCM) to reduce costs. However, there is data dependence between arithmetic units (for example, arithmetic unit A needs to perform data processing based on the output of arithmetic unit B). To improve the parallel efficiency, the data of arithmetic unit B can be temporarily stored in OCM and asynchronously read by arithmetic unit A to avoid the problem of low efficiency caused by direct bus transmission. However, the capacity of OCM is limited, and its utilization rate needs to be improved through dynamic multiplexing: after arithmetic unit A finishes reading data from OCM, the storage area needs to be quickly released for other arithmetic units to overwrite new data.
[0003] To achieve dynamic multiplexing of OCM, a synchronization module is required to manage the task status, and the completion status of the task is marked through synchronization registers. The specific method is as follows: after the read direct memory access (RDMA) and write direct memory access (WDMA) in the arithmetic unit complete the task, the task ID is written into the corresponding register, and other arithmetic units can judge whether the OCM area is reusable based on this. To shorten the latency, the task over-issuing mechanism is introduced in RDMA: when all read address requests are sent, but the data in OCM has not been completely received, a task end signal is sent in advance to trigger the update of the synchronization register and the start of the next task, and blocking instructions are used to ensure the serialization of operations.
[0004] However, the combination of task over-issuing and blocking instructions leads to a conflict between data integrity and storage multiplexing: RDMA updates the synchronization register before the data reading is completed, and other arithmetic units misjudge that the area storing the data required by this RDMA can be overwritten, resulting in the effective data being rewritten in advance. At the same time, the blocking instruction controls that the next task configuration can only start after the synchronization register is updated, making the next task configuration lag behind the actual data transmission, further exacerbating the risk that the data is overwritten before it is completely read, increasing the error rate of data reading, and reducing the performance of the chip. Summary of the Invention
[0005] To solve the above problems, the present application provides a method for updating data reading status and a data processing chip, which can avoid the risk that the RDMA data is overwritten before it is completely read, and solve the technical problems of increasing error rate of data reading and reducing chip performance.
[0006] To achieve the above object, in a first aspect, the present application provides a method for updating the data reading status, which is applied to a data processing chip. The data processing chip includes an arithmetic unit, a synchronization signal processing unit, an OCM, and a synchronization register. The arithmetic unit includes an RDMA, and the synchronization signal processing unit includes a cached data register. The method for updating the data reading status includes:
[0007] In response to an RDMA update instruction, update the initial pulse register and the initial data register. The initial pulse register is used to indicate that the channel controlling the RDMA starts to update the data reading status of the RDMA, and the initial data register is used to store the update data.
[0008] Send the update data in the initial data register to the cached data register; when the value of the data reading completion signal is 1, send the update data in the cached data register to the synchronization register to update the synchronization register. The data reading completion signal is issued by the RDMA and is used to indicate that the data reading in the RDMA OCM is completed.
[0009] After the method for updating the data reading status provided by the present application responds to the RDMA update instruction, it updates the initial pulse register to indicate that the channel controlling the RDMA starts to update the reading status of the RDMA, stores the update data in the initial data register, and then transfers the update data to the cached data register for temporarily storing the update data; when the previous round of data reading by the RDMA is completed, the update data is input to the synchronization register. Ensure that the synchronization register is not updated with data before the RDMA completes data reading, reduce the error rate of data reading, and at the same time do not affect the channel controlling the direct memory access to execute the next task, improving the chip performance.
[0010] In a realizable manner of the first aspect, the initial value of the initial pulse register is 0. Updating the initial pulse register and the initial data register includes:
[0011] Set the value of the initial pulse register to 1.
[0012] Store the update data in the initial data register.
[0013] In the above method, by setting the value of the initial pulse register to 1, it indicates that all read address requests of the RDMA at this time have been issued, and the data reading status of the RDMA needs to be updated, and the update data is stored in the initial data register, improving the real-time performance of the RDMA data reading status update.
[0014] In a realizable manner of the first aspect, the synchronization signal processing unit further includes a cached pulse register, and the initial value of the cached pulse register is 0; after updating the initial pulse register and the initial data register, the method for updating the data reading status further includes:
[0015] Set the value of the cache pulse register to 1.
[0016] In the above method, after the value of the initial pulse register is 1, setting the value of the cache pulse register to 1 indicates that the updated data can be stored in the synchronization signal processing unit, avoiding the loss of the original data in the synchronization register when the updated data is directly stored in the synchronization register, and improving the accuracy of the RDMA data reading status update process.
[0017] In an implementable manner of the first aspect, the data processing chip further includes a synchronization valid register, and the initial value of the synchronization valid register is 0; after sending the updated data in the cache data register to the synchronization register, the data reading status update method further includes:
[0018] When the values of both the cache pulse register and the data reading completion signal are 1, set the value of the synchronization valid register to 1, and set the value of the cache pulse register to 0.
[0019] In the above method, when the value of the reading completion signal is 1, it indicates that RDMA has completed the previous round of data reading, and the updated data can be passed into the synchronization register. Therefore, set the value of the synchronization valid register to 1 and reset the cache pulse register, so that the synchronization signal processing unit can continue to receive the next round of updated RDMA data reading status, improving the coherence of the RDMA data reading status update and reducing the error rate.
[0020] In an implementable manner of the first aspect, the data processing chip further includes a ready-to-update register, and the initial value of the ready-to-update register is 0; after setting the value of the synchronization valid register to 1, the data reading status update method further includes:
[0021] Set the value of the ready-to-update register to 1.
[0022] In the above method, setting the value of the ready-to-update register to 1 indicates that the update of the synchronization register data is completed, and the next round of updated RDMA data reading status can be started, improving the efficiency and coherence of the data reading status update method.
[0023] In an implementable manner of the first aspect, after setting the value of the ready-to-update register to 1, the data reading status update method further includes:
[0024] Set the value of the synchronization valid register to 0.
[0025] In the above method, after starting the update of the RDMA data reading state in the next round, the value of the synchronization valid register is modified to 0, indicating that the synchronization register is in a state where data update is not allowed at this time, avoiding the overwrite of the valid data in the OCM, reducing the error rate of data reading, and improving the accuracy of the data reading state update method.
[0026] In an implementable manner of the first aspect, the RDMA update instruction is a binary instruction, including a first preset bit, a second preset bit, a third preset bit, a fourth preset bit, a fifth preset bit, and a sixth preset bit;
[0027] The first preset bit is an instruction function bit, used to indicate that the function of the RDMA update instruction is to update the data in the synchronization register;
[0028] The second preset bit is an ID bit, representing the identifier of the RDMA;
[0029] The third preset bit is an update value bit, used to store the value of the update data;
[0030] The fourth preset bit is a general register judgment bit, used to judge whether to add a general register;
[0031] The fifth preset bit is a general register address bit, used to indicate the address of the general register;
[0032] The sixth preset bit is a general register area selection bit, used to select the high or low part of the general register.
[0033] In the above method, the first preset bit of the RDMA update instruction can specify the instruction function as data update to enhance the pertinence and accuracy of the synchronization register update; the second preset bit can determine the identifier of the RDMA to make the RDMA correspond to the synchronization register; the third preset bit is used to store the update data; the fourth, fifth, and sixth preset bits are used to introduce the general register, and by expanding the data volume of the update data, more RDMA data reading states can be processed, enhancing the universality of the application of the RDMA update instruction.
[0034] In an implementable manner of the first aspect, the general register is used to expand the data volume of the update data. After responding to the RDMA update instruction, the data reading state update method further includes:
[0035] Reading the fourth preset bit and the sixth preset bit;
[0036] When the value of the fourth preset bit is 0, the value of the update data is determined by the third preset bit;
[0037] When the value of the fourth preset bit is 1 and the value of the sixth preset bit is 0, the value of the update data is determined by the third preset bit and the lower area of the general register;
[0038] When the value of the fourth preset bit is 1 and the value of the sixth preset bit is 1, the value of the updated data is determined by the third preset bit and the high area of the general register.
[0039] In the above method, by reading the bit values of the fourth preset bit and the sixth preset bit, the specific usage method of the general register can be determined.
[0040] In one possible implementation of the first aspect, the RDMA update instruction is a non-blocking instruction;
[0041] When the data processing chip executes the RDMA update instruction, it continues to update the RDMA configuration.
[0042] In the above method, setting the RDMA update instruction as a non-blocking instruction does not require waiting for feedback to execute successfully when executing the instruction. RDMA can continue to execute the next update task, improving the task execution efficiency.
[0043] In a second aspect, the present application further provides a data processing chip, including an arithmetic unit, a synchronization signal processing unit, an OCM, and a synchronization register. The arithmetic unit includes an RDMA, and the synchronization signal processing unit includes a buffered data register;
[0044] The arithmetic unit is configured to: in response to the RDMA update instruction, update the initial pulse register and the initial data register. The initial pulse register is used to indicate that the channel controlling the RDMA starts to update the data reading state of the RDMA, and the initial data register is used to store the updated data;
[0045] The synchronization signal processing unit is configured to: send the updated data in the initial data register to the buffered data register; when the value of the data reading completion signal is 1, send the updated data in the buffered data register to the synchronization register to update the synchronization register; the data reading completion signal is issued by the RDMA and is used to indicate that the RDMA has completed reading data from the OCM.
[0046] It can be understood that the beneficial effects that can be achieved by the technical solution provided in the second aspect above can refer to the beneficial effects in the first aspect and any of its optional implementation manners, which will not be elaborated here.
[0047] As can be seen from the above technical solutions, the present application provides a method for updating a data reading status and a data processing chip. The data processing chip includes an arithmetic unit, a synchronization signal processing unit, an OCM, and a synchronization register. The arithmetic unit includes an RDMA, and the synchronization signal processing unit includes a buffer data register. The method for updating the data reading status includes: in response to an RDMA update instruction, updating an initial pulse register and an initial data register, where the initial pulse register is used to indicate that the channel controlling the RDMA starts to update the data reading status of the RDMA, and the initial data register is used to store updated data; sending the updated data in the initial data register to the buffer data register; when the value of the data reading completion signal is 1, sending the updated data in the buffer data register to the synchronization register to update the synchronization register; the data reading completion signal is sent by the RDMA and is used to indicate that the RDMA has completed reading data from the OCM.
[0048] After responding to the RDMA update instruction, the method for updating the data reading status provided by the present application starts to update the data reading status of the RDMA by updating the initial pulse register, stores the updated data in the initial data register, and then transfers the updated data to the buffer data register for temporarily storing the updated data; when the previous round of data reading by the RDMA is completed, the updated data is input to the synchronization register. It ensures that the OCM is not updated with data before the RDMA completes data reading, reduces the error rate of data reading, and improves the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0049] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.
[0050] Figure 1 Schematic diagram of a data processing chip architecture provided by an embodiment of the present application;
[0051] Figure 2 Schematic diagram of a method for updating a synchronization register provided by an embodiment of the present application;
[0052] Figure 3 Another schematic diagram of a data processing chip architecture provided by an embodiment of the present application;
[0053] Figure 4 Schematic diagram of a method for updating a data reading status provided by an embodiment of the present application;
[0054] Figure 5 Schematic diagram of a function of a synchronization signal processing unit provided by an embodiment of the present application;
[0055] Figure 6Another schematic diagram of the synchronous register update method provided by the embodiments of the present application. Detailed implementation manners
[0056] The embodiments will be described in detail below, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following embodiments do not represent all implementation manners consistent with the present application.
[0057] It should be noted that the brief description of the terms in the present application is only for facilitating the understanding of the following described implementation manners, rather than intending to limit the implementation manners of the present application. Unless otherwise specified, these terms should be understood in their ordinary and general meanings.
[0058] The terms "first", "second", "third", etc. in the specification and the above accompanying drawings of the present application are used to distinguish similar or the same kind of objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that such terms used can be interchanged under appropriate circumstances.
[0059] For the convenience of understanding the solution, the following explains the relevant terms:
[0060] On-Chip Memory (OCM): It is a storage unit integrated inside the processor chip, directly connected to the computing core, with low access latency and high bandwidth, which can improve the data processing efficiency.
[0061] Read Direct Memory Access (RDMA): It exists in the arithmetic unit and can directly obtain data from the memory, and is applied to scenarios that require high-speed and low-latency data transmission.
[0062] Synchronous register: It is a component in the chip that coordinates the cooperation of multiple arithmetic units, used to record the task status and achieve global synchronization. When updating the RDMA data reading status, the updated data will be stored in the synchronous register; when the RDMA completes the data transmission, the task ID will be written into the specified synchronous register through an instruction to mark that the task has been executed. It not only improves the parallel efficiency of multiple arithmetic units but also provides global status visibility for complex tasks.
[0063] Ready-to-update register: It has a single bit, used to indicate whether the data update task of the synchronous register for the current time is completed.
[0064] Synchronization valid register: It has a single bit, used to indicate whether the state of the synchronous register is that data can be updated or data cannot be updated.
[0065] Control Module: It exists in the arithmetic unit of the data processing chip and is responsible for fetching, decoding, and distributing instructions to ensure that instructions enter the execution stage sequentially or in parallel.
[0066] The data processing chip is used to perform data calculation, conversion, transmission, or storage tasks and includes multiple arithmetic units. Multiple arithmetic units can share the OCM. To achieve data interaction between multiple arithmetic units and improve parallel efficiency, the data of the first arithmetic unit can be temporarily stored in the OCM and asynchronously read by the second arithmetic unit A. However, the capacity of the OCM is limited, and its utilization rate needs to be improved through dynamic multiplexing: after the first arithmetic unit finishes reading data from the OCM, the storage area needs to be quickly released for other arithmetic units to overwrite new data.
[0067] To achieve the dynamic multiplexing of the OCM, a synchronization register in the synchronization module is required to manage the task status. It should be noted that there is a one-to-one correspondence between the RDMA and the synchronization register. After the task is completed, the RDMA in the arithmetic unit writes the task ID into the corresponding synchronization register, and other arithmetic units can judge whether the OCM area can be reused based on this.
[0068] Figure 1 This is a schematic diagram of a data processing chip architecture provided by an embodiment of the present application. As Figure 1 shown, the data processing chip includes a first arithmetic unit, a second arithmetic unit, and a synchronization module. Among them, the first arithmetic unit includes a first control module and a first RDMA, the second arithmetic unit includes a second control module and a second RDMA, and the synchronization module includes a first synchronization register and a second synchronization register.
[0069] It should be understood that the data processing chip may further include other arithmetic units, and the arithmetic unit may further include other RDMA, and the synchronization module may further include other synchronization registers, as long as the one-to-one correspondence between the RDMA and the synchronization register is ensured. Specific limitations are not made in the embodiments of the present application.
[0070] Based on the above data processing chip architecture, taking the first RDMA as an example, the process of updating the data reading status of the first RDMA includes: configuring and starting the first RDMA. After all the read address requests of the first RDMA are sent, the first control module obtains an instruction to update the data reading status of the first RDMA. The instruction is directly executed successfully, and the first RDMA is configured to start the next task; after the first RDMA finishes reading data, the first synchronization register corresponding to the first RDMA is updated. Among them, updating the first synchronization register corresponding to the first RDMA requires data transfer through the register. Figure 2 This is a schematic diagram of a synchronization register update method provided by an embodiment of the present application. As Figure 2As shown in the figure, the registers used to implement synchronous register updates include a valid register, a data register, and a ready-to-update register. First, the control module in the arithmetic unit sets the value of the valid register to 1, indicating that the synchronous register can be updated. Second, the update data is sent to the synchronous register through the data register. Finally, after the synchronous register receives the update data, it sets the value of the ready-to-update register to 1 and feeds it back to the arithmetic unit, indicating that the data update of the synchronous register is completed this time. Among them, the data register is the core device for updating data and includes 32 bits. Table 1 shows the data format of the data register.
[0071] Table 1
[0072] bit position [31:26] [25:20] [19:4] [3:0] description ID sync_reg_addr sync_reg_value mode
[0073] In the data register shown in Table 1, [3:0] represents the operation mode; [19:4] represents the data to be updated to the synchronous register; [25:20] represents the address of the synchronous register to be updated; [31:26] represents the ID of the RDMA. In the data processing chip, the RDMA has a unique ID to correspond to a specific synchronous register; [31:26] represents the ID of the RDMA that initiates the update operation.
[0074] Exemplarily, when the value of [3:0] in the data register is 2, it indicates that this is an update operation, and the data in the synchronous register with the value represented by [25:20] as the address is updated to the data represented by [19:4].
[0075] In some embodiments, to shorten the latency, the RDMA introduces a task over-issuance mechanism: when all the read address requests of the current task's RDMA are sent, but the data in the OCM has not been fully received, a task end signal is sent in advance to trigger the synchronous register update and the start of the next task, and blocking instructions are used to ensure the serialization of the operations.
[0076] However, the combination of task over-issuance and blocking instructions causes the RDMA to update the synchronous register before the data reading is completed. Other arithmetic units misjudge that the area storing the data required by the RDMA can be overwritten, resulting in the valid data being rewritten in advance and increasing the error rate of data reading. At the same time, the blocking instructions control that the next task configuration can only start after the synchronous register update is completed, resulting in the next task configuration having to wait until the synchronous register update is completed, reducing the performance of the chip.
[0077] To solve the above problems, the embodiments of the present application provide a method for updating the data reading state, which is applied to a data processing chip. Figure 3 Another schematic diagram of the data processing chip architecture provided by the embodiments of the present application. As Figure 3As shown in the figure, the data processing chip includes an arithmetic unit, a synchronization signal processing unit, an OCM, and a synchronization module. Among them, the arithmetic unit includes a control module and an RDMA, and the synchronization module includes a synchronization register. Compared with Figure 1 the data processing chip shown in the figure, another data processing chip provided by the embodiment of the present application adds a synchronization signal processing unit, and the synchronization signal processing unit includes a buffered data register.
[0078] Next, based on Figure 3 the data processing chip shown in the figure, the specific implementation manner of the data reading status update method will be introduced. It should be understood that, similar to Figure 1 the data processing chip shown in the figure, Figure 3 the data processing chip shown in the figure may also include other arithmetic units, other RDMA, and other synchronization registers, as long as it is ensured that there is a one-to-one correspondence between the RDMA and the synchronization register. In the embodiment of the present application, an arithmetic unit, an RDMA, and a synchronization register are taken as examples for introduction.
[0079] Figure 4 It is a schematic diagram of a data reading status update method provided by the embodiment of the present application. As Figure 4 shown in the figure, the data reading status update method includes steps S100 - S300.
[0080] S100: In response to the RDMA update instruction, update the initial pulse register and the initial data register.
[0081] In some embodiments, the control module updates the data in the synchronization register by obtaining and executing the RDMA update instruction. Specifically, the RDMA update instruction may be a 64-bit binary instruction, including a first preset bit, a second preset bit, a third preset bit, a fourth preset bit, a fifth preset bit, and a sixth preset bit. Among them, the first preset bit is an instruction function bit, which is used to indicate that the function of the RDMA update instruction is to update the data in the synchronization register. The second preset bit is an ID bit, which represents the identifier of the RDMA and is used to distinguish different RDMA, so that the RDMA can correspond to the synchronization register one by one. The third preset bit is an update value bit, which is used to store the value of the updated data. The fourth preset bit is a general register judgment bit, which is used to judge whether to add a general register. The fifth preset bit is a general register address bit, which is used to indicate the address of the general register. The sixth preset bit is a general register area selection bit, which is used to select the high or low bit of the general register.
[0082] In some embodiments, the RDMA update instruction is used to indicate that the third preset bit length of the updated data is limited, resulting in limited updated data. To increase the amount of updated data for each task and improve the generality of the application of the RDMA update instruction, other general-purpose registers can be introduced to expand the value of the updated data. Therefore, it is possible to determine whether to introduce a general-purpose register through a fourth preset bit, and specify the address of the introduced general-purpose register through a fifth preset bit. At the same time, to improve the utilization rate of the general-purpose register, when introducing a general-purpose register, the high area or the low area of the general-purpose register can be selected, so that the same general-purpose register can expand the amount of updated data for two different RDMA. Therefore, the high or low area can be selected through a sixth preset bit.
[0083] Exemplarily, Table 2 shows the instruction format of an RDMA update instruction.
[0084] Table 2
[0085]
[0086] In the RDMA update instruction shown in Table 2, bits 0 to 7 indicate that the instruction type is an RDMA update instruction; bits 8 to 12 are the CRC check value of the instruction, which is used to check whether an error occurs during the instruction reading process; bits 13 to 17 indicate reserved empty bits, which can be used to add other functions to the instruction later; bit 18 indicates whether the current work is a new work. For example, 0 indicates not a new work, and 1 indicates a new work; bit 19 indicates whether to print the time point when the instruction ends. For example, 0 indicates not to print, and 1 indicates to print; bit 20 is the sixth preset bit, which is used to indicate whether to select the high area or the low area of the general-purpose register; bits 21 to 25 are the fifth preset bits, which are used to indicate the address of the general-purpose register; bit 26 is the fourth preset bit, which indicates whether to introduce a general-purpose register when bit 26 is set; bits 27 to 31 are reserved empty bits, which can be used for the expansion of subsequent instruction functions; bits 32 to 35 are the first preset bits, and the value of the first preset bit is fixed to 0x2, indicating that the instruction is only used for data update to improve the update efficiency; bits 36 to 51 are the third preset bits, which are used to store the value of the updated data; bits 52 to 57 are the synchronous register address bits, which are used to represent the address of the synchronous register to be updated corresponding to the RDMA; bits 58 to 63 are the second preset bits, which are used to determine the unique identifier of the RDMA, so that the RDMA can correspond to the synchronous register one by one to improve the accuracy of data update.
[0087] In some embodiments, the specific method for updating the data volume through general register extension includes: reading the fourth preset bit and the sixth preset bit; when the value of the fourth preset bit is 0, the value of the updated data is determined by the third preset bit; when the value of the fourth preset bit is 1 and the value of the sixth preset bit is 0, the value of the updated data is determined by the third preset bit and the lower region of the general register; when the value of the fourth preset bit is 1 and the value of the sixth preset bit is 1, the value of the updated data is determined by the third preset bit and the upper region of the general register.
[0088] Exemplarily, the third preset bit in the RDMA update instruction is from bit 36 to bit 51, the fourth preset bit is bit 26, the fifth preset bit is from bit 21 to bit 25, and the sixth preset bit is bit 20. When bit 26 is 0, it means that the general register is not introduced, and the value of the updated data is only determined by bits 36 to 51 in the RDMA update instruction; when the value of bit 26 is 1, it means that the general register is introduced, and bits 21 to 25 are the addresses of the introduced general register. At this time, if the value of bit 20 is 0, it means that the lower region of the general register is used. Assuming that the general register includes 32-bit data, the value of the updated data is determined by bits 36 to 51 in the RDMA update instruction and bits 0 to 15 of the general register; when the value of bit 26 is 1, it means that the general register is introduced, and bits 21 to 25 are the addresses of the introduced general register. At this time, if the value of bit 20 is 1, it means that the upper region of the general register is used. Assuming that the general register includes 32-bit data, the value of the updated data is determined by bits 36 to 51 in the RDMA update instruction and bits 16 to 31 of the general register.
[0089] In some embodiments, to improve the efficiency of data update and chip performance, the RDMA update instruction can be a non-blocking instruction. When the RDMA update instruction is a non-blocking instruction, it is not necessary to wait for the value of the register to be updated to be 1 to execute successfully. Therefore, before the data update of the current task in the synchronization register ends, the control module can continue to configure the next RDMA data reading task.
[0090] In some embodiments, the initial pulse register is used to indicate the update status of the RDMA data reading, and the initial data register is used to store the updated data. After the control module executes the RDMA update instruction, the initial pulse register is updated first. The data stored in the initial pulse register is a pulse signal, and the data value is 0 or 1. When the control module does not execute the update instruction, the initial value of the initial pulse register is 0; when the control module executes the RDMA update instruction, the initial pulse register is updated, and the value of the initial pulse register is set to 1, indicating the start of updating the RDMA data reading status, and the updated data is stored in the initial data register.
[0091] It should be understood that the data in the initial data register is obtained by the control module executing the RDMA update instruction. Therefore, there is a corresponding relationship between the data in the initial data register and the RDMA update instruction. Taking the data format in the initial data register as the data format in Table 1 and the data format of the RDMA update instruction as the data format in Table 2 as an example, the corresponding relationship between the initial data register and the RDMA update instruction is shown in Table 3.
[0092] Table 3
[0093]
[0094]
[0095] In Table 3, mcode[] represents the address bits. For example, mcode[0:3] represents bits 0 to 3, and gprs[mcode[]] represents the general-purpose register address bits. For example, gprs[mcode[25:21]][15:0] represents bits 0 to 15 in the general-purpose register pointed to by bits 21 to 25 in the RDMA update instruction.
[0096] It should be noted that mcode[19:4] in the initial data register represents the value of the updated data. From the data format of the RDMA update instruction in Table 2, it can be seen that there are three types of address bits representing the value of the updated data in the RDMA update instruction: when the fourth preset bit, that is, the value of mcode
[26] is 0, the value bits of the updated data are mcode[51:36]; when the fourth preset bit, that is, the value of mcode
[26] is 1, and the sixth preset bit, that is, the value of mcode
[20] is 0, the value bits of the updated data are mcode[51:36]+gprs[mcode[25:21]][15:0]; when the fourth preset bit, that is, the value of mcode
[26] is 1, and the sixth preset bit, that is, the value of mcode
[20] is 1, the value bits of the updated data are mcode[51:36]+gprs[mcode[25:21]][31:16].
[0097] Based on the above content, after the control module executes the RDMA update instruction, it stores the updated data in the initial data register, that is, stores the data of mcode[51:36] in the RDMA update instruction, or the data of mcode[51:36]+gprs[mcode[25:21]][15:0], or the data of mcode[51:36]+gprs[mcode[25:21]][31:16] in mcode[19:4] of the initial data register.
[0098] In some embodiments, RDMA needs to read data from the OCM. After the initial data register obtains updated data, the updated data will be sent to the synchronization register to update the OCM. If the RDMA in the previous task has not completed data reading at this time, but the updated data has been received in the synchronization register, the data in the relevant area of the OCM can be overwritten, resulting in the valid data being rewritten in advance, increasing the error rate of data reading and reducing the performance of the chip.
[0099] To avoid the valid data in the OCM from being rewritten in advance, an embodiment of the present application adds a synchronization signal processing unit in the data processing chip. As Figure 4 shown, the synchronization signal processing unit includes a buffer pulse register and a buffer data register. Among them, the data stored in the buffer pulse register is a pulse signal, and the data value is 0 or 1. When the synchronization signal processing unit does not receive updated data, the initial value of the buffer pulse register is 0. When the control module executes the RDMA update instruction and updates the initial pulse register and the initial data register, the value of the buffer pulse register can be set to 1, indicating that the updated data can be sent to the buffer data register in the synchronization signal processing unit for temporarily storing the updated data.
[0100] S200: Send the updated data in the initial data register to the buffer data register.
[0101] In some embodiments, when the previous data reading of the RDMA is not completed, the updated data of the current task will be sent to the buffer data register for temporary storage to avoid the data in the synchronization register from being updated.
[0102] Figure 5 A functional schematic diagram of a synchronization signal processing unit provided by an embodiment of the present application. As Figure 5 shown, after the control module executes the RDMA update instruction, the value of the buffer pulse register in the synchronization signal processing unit is set to 1, and the updated data is input to the buffer data register. The data format of the buffer data register can be the same as that of the initial data register, which will not be elaborated here.
[0103] S300: When the value of the data reading completion signal is 1, send the updated data in the buffer data register to the synchronization register to update the synchronization register.
[0104] In some embodiments, since the updated data is temporarily stored in the buffer data register, the data in the synchronization register is not updated. To ensure the timeliness of the synchronization register update, the updated data needs to be sent to the synchronization register immediately after the previous data reading of the RDMA is completed. Therefore, it is necessary to receive the data reading completion signal sent by the RDMA, and the data reading completion signal is used to indicate that the RDMA has completed reading data from the OCM.
[0105] In some embodiments, to ensure both the accuracy of RDMA data reading and the efficiency of RDMA data updating, when the RDMA data reading is completed, the updated data can be sent to the synchronization register to indicate that the data in the relevant area of the OCM has been used up.
[0106] The value of the data read completion signal is 0 or 1, and when it is 1, it indicates that the data reading is completed. In step S100, the value of the buffer pulse register has been set to 1, indicating that the updated data has been stored in the buffer data register. Therefore, when the value of the data read completion signal issued by the RDMA is 1, the updated data in the buffer data register can be sent to the synchronization register.
[0107] Figure 6 It is a schematic diagram of another method for updating the synchronization register provided by the embodiment of the present application. As Figure 6 shown, when the data read completion signal issued by the RDMA is 1 and the value of the buffer pulse register is 1, the updated data in the buffer data register is sent to the synchronization register to achieve the update of the synchronization register. This update method can not only reduce the error rate of RDMA data reading, but also improve the data update efficiency and the performance of the data processing chip.
[0108] In some embodiments, to ensure that the buffer data register can store the updated data of the next task, when the buffer data register is idle, the value of the buffer pulse register needs to be set to 0 to indicate that the buffer data register can store the updated data of the next task, improving the logic and accuracy of data updating.
[0109] To achieve the above purpose, the data processing chip further includes a synchronization valid register, and the initial value of the synchronization valid register is 0. After the values of the buffer pulse register and the data read completion signal are both 1, the value of the synchronization valid register is set to 1, indicating that the synchronization register has received the updated data. When the value of the synchronization valid register is set to 1, the value of the buffer pulse register can be set to 0, and the buffer data register can store the updated data of the next task.
[0110] In some embodiments, the data processing chip further includes a ready-to-update register, and the initial value of the ready-to-update register is 0. After the synchronization register is updated, the value of the ready-to-update register is modified to 1 to indicate that the current data update is completed.
[0111] In some embodiments, after setting the value of the register to be updated to 1, it indicates that the synchronization register is ready for the next data update, and the next data update can be performed. To enhance the logic of the next data update, the value of the synchronization valid register is set to 0 until the synchronization register receives the next update data, and then the value of the synchronization valid register is set to 1.
[0112] Some embodiments of the present application further provide a data processing chip, including an arithmetic unit, a synchronization signal processing unit, an OCM, and a synchronization register. The arithmetic unit includes an RDMA, and the synchronization signal processing unit includes a buffer data register.
[0113] The arithmetic unit is configured to: in response to an RDMA update instruction, update an initial pulse register and an initial data register. The initial pulse register is used to indicate that the channel controlling the RDMA starts to update the data reading status of the RDMA, and the initial data register is used to store the update data.
[0114] The synchronization signal processing unit is configured to: send the update data in the initial data register to the buffer data register; when the value of the data reading completion signal is 1, send the update data in the buffer data register to the synchronization register; the data reading completion signal is issued by the RDMA and is used to indicate that the RDMA has completed reading data from the OCM.
[0115] As can be seen from the above technical solutions, the present application provides a method for updating the data reading status and a data processing chip. The data processing chip includes an arithmetic unit, a synchronization signal processing unit, an OCM, and a synchronization register. The arithmetic unit includes an RDMA, and the synchronization signal processing unit includes a buffer data register. The method for updating the data reading status includes: in response to an RDMA update instruction, updating an initial pulse register and an initial data register. The initial pulse register is used to indicate that the channel controlling the RDMA starts to update the data reading status of the RDMA, and the initial data register is used to store the update data; sending the update data in the initial data register to the buffer data register; when the value of the data reading completion signal is 1, sending the update data in the buffer data register to the synchronization register; the data reading completion signal is issued by the RDMA and is used to indicate that the RDMA has completed reading data from the OCM. After responding to the RDMA update instruction, the method for updating the data reading status provided by the present application indicates the start of updating the data reading status of the RDMA by updating the initial pulse register, stores the update data in the initial data register, and then transfers the update data to the buffer data register for temporarily storing the update data; when the previous round of data reading by the RDMA is completed, the update data is input to the synchronization register. It ensures that the synchronization register is not updated with data before the RDMA completes data reading, avoids overwriting the valid data in the OCM, reduces the error rate of data reading, and improves the chip performance.
[0116] For the similar parts between the embodiments provided in this application, reference can be made to each other. The specific embodiments provided above are only several examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other embodiments extended based on the solution of this application without creative efforts belong to the protection scope of this application.
Claims
1. A method for updating a data reading state, characterized in that, Applied to a data processing chip, the data processing chip includes an arithmetic unit, a synchronization signal processing unit, an on-chip memory, and a synchronization register. The arithmetic unit includes a read direct memory access. The synchronization signal processing unit includes a cache data register. The method includes: In response to a read direct memory access update instruction, update an initial pulse register and an initial data register. The initial pulse register is used to indicate that the channel controlling the read direct memory access starts to update the data reading status of the read direct memory access. The initial data register is used to store the updated data. Send the updated data in the initial data register to the cache data register; when the value of the data read completion signal is 1, send the updated data in the cache data register to the synchronization register to update the synchronization register. The data read completion signal is issued by the read direct memory access and is used to indicate that the read direct memory access has completed reading data from the on-chip memory.
2. The data reading status update method according to claim 1, wherein The initial value of the initial pulse register is 0. Updating the initial pulse register and the initial data register includes: Set the value of the initial pulse register to 1. Store the updated data in the initial data register.
3. The data reading status update method according to claim 1, wherein The synchronization signal processing unit further includes a cache pulse register, and the initial value of the cache pulse register is 0. After updating the initial pulse register and the initial data register, the method further includes: Set the value of the cache pulse register to 1.
4. The data reading status update method according to claim 3, characterized in that The data processing chip further includes a synchronization valid register, and the initial value of the synchronization valid register is 0. After sending the updated data in the cache data register to the synchronization register, the method further includes: When the values of the cache pulse register and the data read completion signal are both 1, set the value of the synchronization valid register to 1 and set the value of the cache pulse register to 0.
5. The data reading status update method according to claim 4, wherein The data processing chip further includes a ready-to-update register, and the initial value of the ready-to-update register is 0. After setting the value of the synchronization valid register to 1, the method further includes: Set the value of the ready-to-update register to 1.
6. The data reading status update method according to claim 5, wherein After setting the value of the ready-to-update register to 1, the method further includes: Set the value of the synchronization valid register to 0.
7. The data reading status update method according to claim 1, wherein The read direct memory access update instruction is a binary instruction with a length, including a first preset bit, a second preset bit, a third preset bit, a fourth preset bit, a fifth preset bit, and a sixth preset bit. The first preset bit is an instruction function bit, which is used to indicate that the function of the read direct memory access update instruction is to update the data in the synchronization register. The second preset bit is an ID bit, which represents the identifier of the read direct memory access. The third preset bit is an update value bit, which is used to store the value of the updated data. The fourth preset bit is a general register judgment bit, which is used to judge whether to add a general register. The fifth preset bit is a general register address bit, which is used to indicate the address of the general register. The sixth preset bit is a general register area selection bit for selecting the high or low bits of the general register.
8. The data reading status update method according to claim 7, wherein The general register is used to expand the data volume of the updated data. After the response to the read direct memory access update instruction, the method further includes: Reading the fourth preset bit and the sixth preset bit; When the value of the fourth preset bit is 0, the value of the updated data is determined by the third preset bit; When the value of the fourth preset bit is 1 and the value of the sixth preset bit is 0, the value of the updated data is determined by the third preset bit and the lower area of the general register; When the value of the fourth preset bit is 1 and the value of the sixth preset bit is 1, the value of the updated data is determined by the third preset bit and the upper area of the general register.
9. The data reading status update method according to claim 1, wherein The read direct memory access update instruction is a non-blocking instruction; When the data processing chip executes the read direct memory access update instruction, it continues to update the read direct memory access configuration.
10. A data processing chip, characterized in that, It includes an arithmetic unit, a synchronization signal processing unit, an on-chip memory, and a synchronization register. The arithmetic unit includes a read direct memory access, and the synchronization signal processing unit includes a cache data register; The arithmetic unit is configured to: in response to a read direct memory access update instruction, update an initial pulse register and an initial data register. The initial pulse register is used to indicate that the channel controlling the read direct memory access starts to update the data reading status of the read direct memory access, and the initial data register is used to store the updated data; The synchronization signal processing unit is configured to: send the updated data in the initial data register to the cache data register; When the value of the data read completion signal is 1, send the updated data in the cache data register to the synchronization register to update the synchronization register; the data read completion signal is issued by the read direct memory access and is used to indicate that the read direct memory access has completed reading data from the on-chip memory.