Model determination system, method, electronic device, storage medium and product

Abstract

The present application discloses a model determination system, method, electronic device, storage medium and product, relating to the technical field of server systems, comprising a first control module, a second control module, a first multiplexing module, a second multiplexing module and a plurality of serial communication devices deployed on a graphics processing module; the first control module and the second control module respectively output two buses, the buses being connected to the first multiplexing module and the second multiplexing module respectively, the second control module being used to obtain the address of the serial communication device and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus being connected to the plurality of serial communication devices on the graphics processing module, the device addresses being stored on the serial communication devices, solving the technical problem of requiring additional materials and production processes and increasing costs in related solutions, and achieving the technical effect of not requiring additional materials and production processes and avoiding cost increases.

Description

Technical Field

[0001] The present application relates to the technical field of server systems, and in particular to a model determination system, method, electronic device, storage medium, and product. Background Art

[0002] In the context of the rapid development of artificial intelligence servers, the graphics processing module, as an important expansion module that carries high-performance computing units, its model identification and management logic configuration have become key links in system design.

[0003] In related model determination schemes, the model of the graphics processing module is usually determined by deriving a hardware board or an external cable, which requires additional materials and production processes, resulting in increased costs. Summary of the Invention

[0004] The present application provides a model determination system, method, electronic device, storage medium and product to at least solve the problem in the related art that the model of the graphics processing module is determined by derivative hardware boards or external cables, which requires additional materials and production processes and leads to increased costs.

[0005] The present application provides a model determination system, comprising:

[0006] A first control module, a second control module, a first multiplexing module, a second multiplexing module, and a plurality of serial communication devices deployed on the graphics processing module;

[0007] The first control module and the second control module respectively output two buses, which are connected to the first multiplexing module and the second multiplexing module respectively. The first control module is used to control the power-on of the graphics processing module, and the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module;

[0008] The first multiplexing module and the second multiplexing module respectively output a bus line connected to multiple serial communication devices on the graphics processing module, the first multiplexing module is used to switch the connection line with the first serial communication device among the multiple serial communication devices, and the second multiplexing module is used to switch the connection line with the second serial communication device among the multiple serial communication devices;

[0009] The serial communication device has a device address stored on it.

[0010] This application provides a model determination method, including:

[0011] In response to the second control module completing loading, acquiring a control signal;

[0012] Using a control signal, controlling the first multiplexing module and the second multiplexing module to switch to a first target connection line, where the first target connection line is a connection line between the second control module and a plurality of serial communication devices;

[0013] determining an address of the serial communication device using the first target connection line;

[0014] The model of the graphics processing module is determined according to the mapping relationship between the address of the serial communication device and the model of the graphics processing module.

[0015] The present application also provides a model determination device, comprising:

[0016] an acquiring unit, configured to acquire a control signal in response to completion of loading of the second control module;

[0017] a control unit, configured to control the first multiplexing module and the second multiplexing module to switch to a first target connection line using a control signal, where the first target connection line is a connection line between the second control module and a plurality of serial communication devices;

[0018] a first determining unit, configured to determine an address of the serial communication device using the first target connection line;

[0019] The second determining unit is configured to determine the model of the graphics processing module according to a mapping relationship between the address of the serial communication device and the model of the graphics processing module.

[0020] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned model determination method when executing the computer program.

[0021] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned model determination method are implemented.

[0022] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned model determination method when executed by a processor.

[0023] The present application includes a first control module, a second control module, a first multiplexing module, a second multiplexing module and multiple serial communication devices deployed on a graphics processing module; the first control module and the second control module respectively output two buses, which are respectively connected to the first multiplexing module and the second multiplexing module; the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to connect to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem of requiring additional materials and production processes and increasing costs in related solutions, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic diagram of the structure of a model determination system provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of the structure of a model determination system provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of a flow chart of a model determination method provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a model matching process provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of a server power-on process flow provided in an embodiment of the present application;

[0030] Figure 6 A schematic diagram of the structure of a model determination device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0032] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0033] In order to facilitate those skilled in the art to better understand the technical solutions described in the embodiments of the present disclosure, the technical terms in the embodiments of the present disclosure are explained as follows before introducing the embodiments of the present disclosure.

[0034] The Baseboard Management Controller (BMC) is used to manage and monitor the hardware of servers or other electronic devices. Specifically, it can monitor the temperature of various components within the system in real time, including the Central Processing Unit (CPU), memory, storage devices, etc. It can also monitor and control the speed of fans to maintain proper cooling effect. It can also provide status monitoring of the power supply unit, including power input and output conditions, redundant power supply status, etc.

[0035] Complex Programmable Logic Device (CPLD): A CPLD is a programmable logic device that allows digital circuit functions to be implemented through software programming. It has a high level of integration and flexibility and is suitable for applications that require fast response times, such as signal processing and protocol conversion.

[0036] Basic Input Output System (BIOS): BIOS is the firmware in a computer that performs hardware initialization and provides runtime services for the operating system. It plays a vital role in the computer startup process, responsible for detecting and initializing hardware components (such as the hard drive, keyboard, mouse, etc.) and loading the operating system.

[0037] General-Purpose Input / Output (GPIO): GPIO is used for communication between integrated circuits (such as microcontrollers and CPUs) and external devices. Through the GPIO interface, the chip can configure pins as input or output mode to read or send data.

[0038] Graphics Processing Unit (GPU): A processor used to quickly process image and video data.

[0039] A graphics processing unit (GPU) box (GPU BOX) is a hardware unit that houses one or more GPUs, enhancing the computing power of servers or workstations. This module typically consists of eight GPUs deployed on a common baseboard. In this application, the GPU BOX is referred to as an image processing module.

[0040] With the rapid development of the information industry, the demand for servers is increasing. In particular, with the explosive growth of artificial intelligence (AI) in recent years, the demand for AI servers has also seen massive growth. AI servers used for large-model training require very high performance. Traditional high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) card electromechanical module (CEM) form factors are not optimized for AI workloads. These workloads require increasing bandwidth and interconnect flexibility for data / model parallelism. Therefore, the Open Accelerator Infrastructure (OAI) / Open Compute Project Accelerator Module (OAM) was born. Multiple OAM modules (typically eight) are paired with a universal baseboard (UBB) and other necessary modules to form an AI server, which plays a key role in machine learning, deep learning, and high-performance computing.

[0041] In 2023, the Open Platform Initiative (OCP) Open Access Initiative (OAI) released the UBB2.0 specification, adopting the uplink (HGX) interface definition to standardize GPU Box interfaces. This ensures that GPU Boxes built by different vendors according to the UBB2.0 standard can interoperate with each other, reducing the labor involved in developing and redesigning new boards during the R&D phase. While GPU Box interfaces are consistent, internal circuitry and functionality are not clearly defined in the specification, leading to significant design differences between different vendors. This also leads to differences in management schemes, power-on sequences, and power-on timeout alarm times across different GPU Box models. This presents significant challenges for host identification and power-on management of the GPU Boxes.

[0042] The following briefly introduces two methods for determining the GPU BOX model in related technologies:

[0043] Solution A: Solution A follows the UBB 2.0 specification. All UBBs are designed according to the HGX interface specification. The server distinguishes different GPU boxes primarily through the use of derivative hardware boards. By changing certain characteristic IDs of the boards and providing them to the BMC, BIOS, and CPLD, different GPU boxes can be identified and managed accordingly, such as power-on and power-off sequence control logic and power-on timeout timing logic.

[0044]

[0045] Table 1 Derivative hardware board model

[0046] Solution B: Solution B uses an additional plug-in cable to bind the cable to the GPU BOX's BOM. When using different GPU BOXes, you need to plug in the corresponding cable. The BMC, BIOS, and CPLD distinguish the GPU BOXes through the different cable connection relationships, thereby performing corresponding logical management.

[0047]

[0048] Table 2 Determine the model of external cable

[0049] The above scheme also has the following disadvantages:

[0050] A large number of board part numbers need to be developed to identify different types of GPU BOXes. The more compatible GPU BOXes are, the more board part numbers are generated, resulting in poor versatility. This poses a great challenge to production and subsequent board maintenance, and can easily cause material stagnation. Stagnant materials not only increase costs but also have a significant impact on warehousing.

[0051] Binding the GPU box with cables requires customizing multiple cables to suit different GPU boxes. The large number of cables not only increases the difficulty of material management but also increases production costs. Furthermore, an additional cable insertion process is required during production. As the number of cables increases, the probability of incorrect cable insertion increases, reducing the production qualification rate.

[0052] In summary, in related GPU BOX model determination solutions, derivative hardware boards or plug-in cables are usually used to determine the model of the graphics processing module, which requires additional materials and production processes, resulting in increased costs.

[0053] The present application includes a first control module, a second control module, a first multiplexing module, a second multiplexing module and multiple serial communication devices deployed on a graphics processing module; the first control module and the second control module respectively output two buses, which are respectively connected to the first multiplexing module and the second multiplexing module; the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to connect to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem of requiring additional materials and production processes and increasing costs in related solutions, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increases.

[0054] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0055] Figure 1 A schematic diagram of the structure of a model determination system provided by an embodiment of the present disclosure.

[0056] like Figure 1 As shown, the model determination system includes a first control module, a second control module, a first multiplexing module, a second multiplexing module, and a plurality of serial communication devices deployed on the graphics processing module;

[0057] The first control module and the second control module respectively output two buses, which are connected to the first multiplexing module and the second multiplexing module respectively. The first control module is used to control the power-on of the graphics processing module, and the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module;

[0058] The first multiplexing module and the second multiplexing module respectively output a bus line connected to multiple serial communication devices on the graphics processing module, the first multiplexing module is used to switch the connection line with the first serial communication device among the multiple serial communication devices, and the second multiplexing module is used to switch the connection line with the second serial communication device among the multiple serial communication devices;

[0059] The serial communication device has a device address stored on it.

[0060] In some embodiments, the first output end of the first control module is connected to the first input end of the first multiplexing module, and the second output end of the first control module is connected to the first input end of the second multiplexing module; the first output end of the second control module is connected to the second input end of the first multiplexing module, and the second output end of the second control module is connected to the second input end of the second multiplexing module. The second control module is used to perform an address scan on the serial communication device to obtain a target address. The second control module is also used to determine the model of the graphics processing module corresponding to the target address based on the mapping relationship between the address of the serial communication device and the model of the graphics processing module.

[0061] In some embodiments, the output end of the first multiplexing module is connected to the input end of a first serial communication device among the multiple serial communication devices, and the output end of the second multiplexing module is connected to the input end of a second serial communication device among the multiple serial communication devices.

[0062] In some embodiments, the first control module is typically a host-side BMC or CPU controller, which is used to manage the graphics processing module during normal system operation, such as powering on and off, and monitoring status.

[0063] In some embodiments, the second control module may include but is not limited to a CPLD, a Field-Programmable Gate Array (FPGA) or a Microcontroller Unit (MCU), and is used to perform address scanning of connected serial communication devices and identify the model of the graphics processing module during the system initialization phase.

[0064] In some embodiments, the first multiplexing module and the second multiplexing module refer to an Inter-Integrated Circuit (IIC) bus multiplexer chip (MUX), which is used to select different IIC channels according to a control signal, thereby switching the communication connection line.

[0065] In some embodiments, the graphics processing module (GPU BOX) is used to carry AI acceleration hardware such as the OAM module and UBB board. Different manufacturers may design different internal circuits, but they must be connected to the host through a unified interface; serial communication devices refer to slave devices that support serial communication protocols, which may include but are not limited to temperature sensors and electrically erasable programmable read-only memories (EEPROM).

[0066] In some embodiments, there may be multiple serial communication devices, but the first multiplexing module and the second multiplexing module are both connected to at least one serial communication device, and the device address of each serial communication device is unique.

[0067] The present application includes a first control module, a second control module, a first multiplexing module, a second multiplexing module and multiple serial communication devices deployed on a graphics processing module; the first control module and the second control module respectively output two buses, which are respectively connected to the first multiplexing module and the second multiplexing module; the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to connect to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem of requiring additional materials and production processes and increasing costs in related solutions, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increases.

[0068] In some embodiments, the model determination system further includes a basic input and output system, an output terminal of the basic input and output system is connected to the second input terminal of the second control module, and the basic input and output system is used to allocate resources to the graphics processing module.

[0069] In some embodiments, during the system startup phase, the BIOS identifies and allocates hardware resources of the GPU BOX, such as memory addresses, interrupt requests, PCIe resources, etc., to ensure that they can be correctly loaded and used by the operating system.

[0070] In some embodiments, the BIOS can load corresponding drivers and resource policies based on the identified GPU BOX model, thereby reducing manual configuration and improving system adaptability.

[0071] In some embodiments, the first multiplexing module and the second multiplexing module are connected to the plurality of serial communication devices via an uplink interface.

[0072] In some embodiments, the uplink interface refers to an HGX interface, and both the IIC MUX 1 and the IIC MUX 2 are connected to the serial communication device through the HGX interface.

[0073] In some embodiments, the first multiplexing module and the second multiplexing module are connected to multiple serial communication devices via an uplink interface, which can support multiple models of GPU BOXes to share a unified interface.

[0074] In some embodiments, the first multiplexing module and the second multiplexing module are used to switch the connection line with the serial communication device according to a control signal, and the control signal is determined by the universal input and output signal output by the second control module.

[0075] In some embodiments, the control signal is used to control the first multiplexing module and the second multiplexing module to select the electrical signal of which channel, which is usually determined by the state combination of several GPIO pins.

[0076] In some embodiments, the control signal is determined according to the general input and output signal. For example, when the GPIO is at a high level, the connection line with the serial communication device is switched to the second connection line. The second connection line refers to the line between the second control module and the serial communication device. Figure 1 As shown, connection line 2 connects the second control module to the first multiplexing module (IICMUX 1) and the second multiplexing module (IIC MUX 2). During power-on initialization, the CPLD can quickly access serial communication devices on the GPU Box. For example, the GPU Box deploys multiple IIC interface EEPROM chips. The host-side BMC and the motherboard CPLD each have a set of IIC control buses, requiring different controllers to access these IIC devices at different stages. Two IIC MUXs are used as connection line switching devices, and the CPLD outputs GPIO control signals for channel selection. The CPLD accesses multiple IIC devices on the GPU Box separately through the IIC MUXes (IIC MUX 1 and IIC MUX 2).

[0077] In some embodiments, the third output terminal of the first control module is connected to the first input terminal of the second control module, and the first control module is used to determine the power-on control logic corresponding to the model of the graphics processing module according to the model of the graphics processing module.

[0078] In some embodiments, after model identification is completed, the CPLD controls IIC MUX 1 and IIC MUX 2 to switch to connection line 1. The CPLD sends the identified GPU BOX model to the host-side BMC via a universal asynchronous receiver / transmitter (UART), GPIO, or synchronous serial communication interface (SPI). The host-side BMC controls subsequent communications, and the BMC loads the corresponding driver and power management policy based on the model.

[0079] In some embodiments, it refers to a specific power-on sequence designed for different models of GPU BOX, including power supply timing, delay control, status monitoring, timeout judgment, etc., to ensure safe startup of the device.

[0080] In some embodiments, as Figure 2 As shown, Figure 2 A structural diagram of a model determination system provided in an embodiment of the present application includes a host-side BMC, a mainboard CPLD, IIC MUX 1, IIC MUX 2, a GPU BOX, and several IIC devices. The host-side BMC and the mainboard CPLD are respectively connected to two IIC buses, wherein the IIC bus path connected to the host-side BMC is defined as line one, and the IIC bus line connected to the mainboard CPLD is defined as line two; the inputs of IIC MUX 1 and IIC MUX 2 are respectively connected to the IIC buses connected to the host-side BMC and the mainboard CPLD, and their output IIC buses are connected to the GPU BOX, and the two IIC buses connected to the GPU BOX are connected to at least one IIC device; the channel selection of IIC MUX 1 and IIC MUX 2 is controlled by the GPIO signal output by the mainboard CPLD.

[0081] The embodiment of the present disclosure also provides a model determination method.

[0082] In some embodiments, as Figure 3 As shown, Figure 3 A flow chart of a model determination method provided in an embodiment of the present application, the method comprising the following steps:

[0083] Step 301: In response to the second control module being loaded, obtaining a control signal;

[0084] In some embodiments, after the AC power supply of the server is connected, the second control module can quickly complete firmware loading and start working, and the CPLD begins to prepare to perform tasks in the initialization phase. The CPLD outputs a set of GPIO control signals, such as GPIO 1 is used to control IIC MUX 1 and IIC MUX 2 to select the connection line.

[0085] In some embodiments, the control signal refers to a signal determined by a general input / output pin of the second control module, and a high level and a low level respectively control different connection routes.

[0086] Step 302: Using a control signal, control the first multiplexing module and the second multiplexing module to switch to a first target connection line, where the first target connection line is a connection line between the second control module and a plurality of serial communication devices;

[0087] In some embodiments, the first target connection line, i.e., the line connecting the CPLD to the serial communication device on the GPU BOX via an IIC MUX, is used. Specifically, IIC MUX 1 selects the IIC2 bus controlled by the CPLD; IIC MUX 2 selects the IIC2 bus controlled by the CPLD. The CPLD can directly access all serial communication devices on the GPU BOX.

[0088] Step 303, determining the address of the serial communication device using the first target connection line;

[0089] In some embodiments, the CPLD uses the first target connection line to perform device scans on the two IIC buses of the GPU BOX respectively. For example, IIC1 scans device addresses 0x21 and 0x24, and IIC2 scans device addresses 0x50 and 0x70.

[0090] Step 304: Determine the model of the graphics processing module according to the mapping relationship between the address of the serial communication device and the model of the graphics processing module.

[0091] In some embodiments, the mapping relationship between the address of the serial communication device and the model of the graphics processing module can be embodied in the form of a mapping relationship table or in the form of a mapping relationship array. This is not limited in the present application. For example, as shown in Table 3, Table 3 is an IIC device table adapted to the GPU BOX given in an embodiment of the present application. The table shows the GPUBOX IIC device address, including the device addresses of IIC1 and IIC2, the model of the GPU BOX, the feature identifier (Identity Document, ID) corresponding to each model, the management logic corresponding to each GPU BOX model, and the power-on timeout period.

[0092]

[0093] Table 3 IIC device list compatible with GPU BOX

[0094] In some embodiments, the motherboard CPLD performs device scans on the two IIC buses of the GPU BOX respectively. After IIC1 scans the device addresses 0x21 and 0x24, and IIC2 scans the device addresses 0x50 and 0x70, according to the mapping relationship in Table 3, the motherboard CPLD matches this to a GPU BOX of model A, corresponding to feature ID 1, and uses management logic 1 for power-on sequence control, with a power-on timeout of 30 seconds.

[0095] In some embodiments, a control signal is obtained in response to completion of loading of the second control module; the control signal is used to control the first multiplexing module and the second multiplexing module to switch to the first target connection line, where the first target connection line is the connection line between the second control module and multiple serial communication devices; the address of the serial communication device is determined using the first target connection line; the model of the graphics processing module is determined based on the mapping relationship between the address of the serial communication device and the model of the graphics processing module. This allows model identification to be completed at the initial stage of system power-on, thereby improving startup efficiency, and only the mapping relationship between the address of the serial communication device and the model of the graphics processing module needs to be updated to adapt to the new GPU BOX type, thereby achieving multi-model adaptation.

[0096] In some embodiments, the address of the serial communication device includes an address of a first serial communication device and an address of a second serial communication device:

[0097] According to the mapping relationship between the address of the serial communication device and the model of the graphics processing module, determining the model of the graphics processing module includes:

[0098] The model of the graphics processing module is determined according to a mapping relationship between the address of the first serial communication device, the address of the second serial communication device, and the model of the graphics processing module.

[0099] In some embodiments, the address of the first serial communication device and the address of the second serial communication device need to be combined to determine the model of the graphics processing module. Taking the GPU BOX model A in Table 3 as an example, if IIC1 scans the device addresses 0x21 and 0x24, and IIC2 scans the device addresses 0x60 and 0x80, the match is unsuccessful. In short, the device address of each serial communication device needs to be successfully matched to determine the corresponding GPU BOX model.

[0100] In some embodiments, the mapping relationship between the address of the first serial communication device, the address of the second serial communication device and the graphics processing module model is improved to determine the graphics processing module model, and the address combination of multiple serial communication devices is used to avoid misjudgment caused by a single address conflict, thereby improving the recognition accuracy of the GPU BOX model.

[0101] In some embodiments, after determining the model of the graphics processing module according to the mapping relationship between the address of the serial communication device and the model of the graphics processing module, the model determination method further includes:

[0102] Determine the characteristic identifier, power-on timeout duration, and power-on control logic corresponding to the graphics processing module model.

[0103] In some embodiments, the feature identifier is used to identify different models of graphics processing modules. The feature identifier may be a manufacturer code, a device ID, an address combination, etc., to facilitate subsequent search for configuration parameters.

[0104] In some embodiments, the power-on timeout refers to the maximum waiting time (eg, 30 seconds) set by the system for the GPU BOX power-on process. If the power-on is not completed within this time, it is determined that the power-on has failed.

[0105] In some embodiments, the power-on control logic refers to the specific operation steps required for powering on the GPU BOX, such as power sequence, delay control, and reset signal triggering. For example, the power-on control logic can be to synchronously turn on all power domains, delay 100ms, and initiate a reset signal.

[0106] In some embodiments, the CPLD controls the power domains of the GPU BOX in sequence according to the matched power-on control logic. A watchdog timer (e.g., 30 seconds) may be used. If power-on is not completed within the specified time, a timeout alarm is triggered and an error log is recorded.

[0107] In some embodiments, by determining a power-on timeout duration corresponding to the graphics processing module model, it is possible to avoid wasting resources due to prolonged unresponsiveness.

[0108] In some embodiments, after matching the power-on timeout duration and the power-on control logic corresponding to the feature identifier, the model determination method includes:

[0109] The first multiplexing module and the second multiplexing module are controlled to switch to a second target connection line, where the second target connection line is a connection line between the first control module and a plurality of serial communication devices.

[0110] In some embodiments, after the model matching is completed, the CPLD changes the GPIO output state, such as GPIO is 0, so as to switch IICMUX 1 and IIC MUX 2 to the second target connection line (corresponding to Figure 1 Middle line 1) and wait for the power-on command.

[0111] In some embodiments, the second target connection line is a connection line for the first control module (host-side BMC) to control access to a serial communication device inside the GPUBOX.

[0112] In some embodiments, after receiving the power-on command, the host-side BMC can access the serial communication device on the GPU BOX through the IIC bus to perform operations such as reading firmware version information, obtaining device health status, executing remote diagnostic commands, and initiating power-on actions.

[0113] In some embodiments, by controlling the first multiplexing module and the second multiplexing module to switch to the second target connection line, the entire connection line switching process does not require manual intervention, which can improve the degree of system automation.

[0114] In some embodiments, after controlling the first multiplexing module and the second multiplexing module to switch to the second target connection line, the model determination method includes:

[0115] In response to receiving a power-on instruction, obtaining a first power-on timestamp;

[0116] In some embodiments, the boot instruction refers to a boot command from the host BMC or operating system, indicating that the GPU BOX or other graphics processing module needs to be powered on. The first power-on timestamp indicates the time point when the power-on action is started and is used to calculate the power-on time.

[0117] The second control module is powered on according to the power-on control logic;

[0118] In some embodiments, the power-on control logic refers to the aforementioned power-on control logic corresponding to the GPU BOX model.

[0119] Get the second power-on timestamp;

[0120] In some embodiments, the second power-on timestamp indicates the time point when the power-on action is completed, and is used to compare with the first timestamp to calculate the total time consumption.

[0121] Based on the second power-on timestamp, the first power-on timestamp and the power-on timeout duration, a power-on result of the electronic device is determined, where the power-on result includes power-on completion and power-on timeout.

[0122] In some embodiments, the electronic device may be a server, a mobile device, an industrial control device, etc. In this application, the electronic device takes a server as an example.

[0123] In some embodiments, power-on completion refers to the successful completion of all power-on actions within a specified time; power-on timeout refers to failure to complete the actions within the specified time.

[0124] In some embodiments, determining a power-on result of the electronic device based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration includes:

[0125] Determining a power-on duration of the electronic device based on the second power-on timestamp and the first power-on timestamp;

[0126] In response to a power-on duration of the electronic device being greater than a power-on timeout duration and the electronic device being in a powered-on state, determining that a power-on timeout has occurred for the electronic device;

[0127] In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a powered-on state, continuing to power on the electronic device according to the power-on control logic;

[0128] In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a power-on completion state, it is determined that the power-on of the electronic device is completed.

[0129] In some embodiments, the power-on duration of the electronic device refers to the time actually used to perform the power-on action, specifically the difference between the second timestamp and the first timestamp.

[0130] In some embodiments, the power-on state means that the power-on action has not been completed and is still being executed.

[0131] In some embodiments, when the electronic device is started, a first power-on timestamp is obtained, the power-on control logic is started to be executed, the current state is cyclically monitored and a second timestamp is obtained to determine whether it is completed or timed out.

[0132] In some embodiments, in response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in a powered-on state, after determining that the electronic device has timed out, the model determination method includes:

[0133] Obtain power-on timeout information of electronic devices;

[0134] In some embodiments, the power-on timeout information of the electronic device refers to information that the power-on action is not completed within a preset time, including the timeout duration, current status, etc.

[0135] An alarm message corresponding to the power-on timeout information of the electronic device is generated and sent to the controller, wherein the alarm message includes at least one of a graphics processing module model, a characteristic identifier of the graphics processing module, and an identifier of the power-on control logic.

[0136] In some embodiments, the alarm information is structured data used to locate faults, facilitating analysis and response by a remote management platform.

[0137] In some embodiments, by generating an alarm message corresponding to the power-on timeout information of the electronic device and sending it to the controller, which contains complete diagnostic information, it is convenient to quickly locate the root cause of the problem and support automatic reporting to the BMC without manual intervention, so that fault traceability and automatic alarm can be achieved.

[0138] In some embodiments, as Figure 4 As shown, Figure 4 A schematic diagram of a model matching process provided in an embodiment of the present application shows that after the server's AC power is connected, the mainboard CPLD quickly completes loading and starts working. At this time, the mainboard CPLD controls IIC MUX 1 and IIC MUX 2 to switch to connection line 2. The mainboard CPLD performs device scans on the two IIC buses of the GPU BOX respectively. IIC1 scans the device addresses 0x21 and 0x24, and IIC2 scans the device addresses 0x50 and 0x70. The mainboard CPLD matches this to a GPU BOX of model A through a table lookup, and the corresponding feature ID is ID 1. Management logic 1 is used for power-on timing control, and the power-on timeout is 30 seconds. After the matching is completed, the mainboard CPLD switches IIC MUX 1 and IIC MUX 2 to connection line 1 and waits for a power-on command.

[0139] In some embodiments, as Figure 5 As shown, Figure 5 A flow chart of a server power-on process is provided in an embodiment of the present application. After receiving the power-on command, the mainboard CPLD executes the power-on control logic and simultaneously starts the power-on timeout. The mainboard CPLD will monitor the server power-on status and power-on timeout at the same time. If the server power-on status is completed before the power-on timeout expires, the server successfully completes the power-on of the entire system; if the server power-on status is not completed when the power-on timeout expires, the mainboard records the power-on timeout.

[0140] The present application includes a first control module, a second control module, a first multiplexing module, a second multiplexing module and multiple serial communication devices deployed on a graphics processing module; the first control module and the second control module respectively output two buses, which are respectively connected to the first multiplexing module and the second multiplexing module; the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to connect to the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem of requiring additional materials and production processes and increasing costs in related solutions, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increases.

[0141] The embodiment of the present application further provides a model determination device 600, Figure 6A schematic diagram of a model determination device provided in an embodiment of the present disclosure is shown in FIG. Figure 6 Shown, including:

[0142] An acquiring unit 601 is configured to acquire a control signal in response to completion of loading of the second control module;

[0143] The control unit 602 is configured to control the first multiplexing module and the second multiplexing module to switch to a first target connection line using a control signal, where the first target connection line is a connection line between the second control module and the plurality of serial communication devices;

[0144] A first determining unit 603 is configured to determine an address of the serial communication device using the first target connection line;

[0145] The second determining unit 604 is configured to determine the model of the graphics processing module according to a mapping relationship between the address of the serial communication device and the model of the graphics processing module.

[0146] Furthermore, in a possible implementation of the embodiment of the present disclosure, the address of the serial communication device includes the address of the first serial communication device and the address of the second serial communication device:

[0147] Furthermore, in a possible implementation of the embodiment of the present disclosure, the second determining unit 604 is configured to:

[0148] The model of the graphics processing module is determined according to a mapping relationship between the address of the first serial communication device, the address of the second serial communication device, and the model of the graphics processing module.

[0149] Furthermore, in a possible implementation of the embodiment of the present disclosure, the model determination device 600 includes a matching unit, which is configured to:

[0150] Determine the characteristic identifier, power-on timeout duration, and power-on control logic corresponding to the graphics processing module model.

[0151] Furthermore, in a possible implementation of the embodiment of the present disclosure, the model determination device 600 includes a switching unit, which is configured to:

[0152] The first multiplexing module and the second multiplexing module are controlled to switch to a second target connection line, where the second target connection line is a connection line between the first control module and a plurality of serial communication devices.

[0153] Furthermore, in a possible implementation of the embodiment of the present disclosure, the model determination device 600 includes a power-on result determination unit, which is configured to:

[0154] In response to receiving a power-on instruction, obtaining a first power-on timestamp;

[0155] The second control module is powered on according to the power-on control logic;

[0156] Get the second power-on timestamp;

[0157] Based on the second power-on timestamp, the first power-on timestamp and the power-on timeout duration, a power-on result of the electronic device is determined, where the power-on result includes power-on completion and power-on timeout.

[0158] Furthermore, in a possible implementation of the embodiment of the present disclosure, the power-on result determination unit is further configured to:

[0159] Determining a power-on duration of the electronic device based on the second power-on timestamp and the first power-on timestamp;

[0160] In response to a power-on duration of the electronic device being greater than a power-on timeout duration and the electronic device being in a powered-on state, determining that a power-on timeout has occurred for the electronic device;

[0161] In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a powered-on state, continuing to power on the electronic device according to the power-on control logic;

[0162] In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a power-on completion state, it is determined that the power-on of the electronic device is completed.

[0163] Furthermore, in a possible implementation of the embodiment of the present disclosure, the model determination device 600 includes an alarm information generation unit, which is configured to:

[0164] Obtain power-on timeout information of electronic devices;

[0165] An alarm message corresponding to the power-on timeout information of the electronic device is generated and sent to the controller, wherein the alarm message includes at least one of a graphics processing module model, a characteristic identifier of the graphics processing module, and an identifier of the power-on control logic.

[0166] Through the present application, a first control module, a second control module, a first multiplexing module, a second multiplexing module and multiple serial communication devices deployed on the graphics processing module; the first control module and the second control module respectively output two buses, the buses are respectively connected to the first multiplexing module and the second multiplexing module, the second control module is used to obtain the address of the serial communication device and the model of the graphics processing module; the first multiplexing module and the second multiplexing module respectively output one bus to connect with the multiple serial communication devices on the graphics processing module, and the device addresses are stored on the serial communication devices, which solves the technical problem of requiring additional materials and production processes and increasing costs in related solutions, and achieves the technical effect of not requiring additional materials and production processes and avoiding cost increases.

[0167] For the description of the features in the embodiment corresponding to the model determination device, please refer to the relevant description of the embodiment corresponding to the model determination method, and will not be repeated here.

[0168] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned model determination method embodiments.

[0169] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned model determination method embodiments when running.

[0170] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0171] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned model determination method embodiments are implemented.

[0172] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned model determination method embodiments are implemented.

[0173] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0174] The above is a detailed introduction to a model determination system, method, electronic device, storage medium, and product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A model determination system, characterized in that: include: A first control module, a second control module, a first multiplexing module, a second multiplexing module, and a plurality of serial communication devices deployed on the graphics processing module; The first control module and the second control module respectively output two buses, each bus being connected to the first multiplexing module and the second multiplexing module. The first control module is used to control power-on of the graphics processing module, and the second control module is used to obtain the addresses of the multiple serial communication devices and the models of the graphics processing module. The second control module is further used to determine the model of the graphics processing module corresponding to a target address based on a mapping relationship between the addresses of the multiple serial communication devices and the models of the graphics processing module, where the target address is the address of the multiple serial communication devices. The first multiplexing module and the second multiplexing module each output a bus connected to multiple serial communication devices on the graphics processing module, the first multiplexing module is used to switch the connection line with a first serial communication device among the multiple serial communication devices, and the second multiplexing module is used to switch the connection line with a second serial communication device among the multiple serial communication devices; The serial communication device stores a device address; The first multiplexing module and the second multiplexing module are used to switch the connection line with the serial communication device according to a control signal, and the control signal is determined by the universal input and output signal output by the second control module.

2. The model determination system according to claim 1, characterized in that: The system further includes a basic input / output system, an output end of the basic input / output system is connected to the second input end of the second control module, and the basic input / output system is used to allocate resources to the graphics processing module.

3. The model determination system according to claim 1, characterized in that: The first multiplexing module and the second multiplexing module are connected to the multiple serial communication devices via an uplink interface.

4. The model determination system according to claim 1, characterized in that: The third output terminal of the first control module is connected to the first input terminal of the second control module. The first control module is used to determine the power-on control logic corresponding to the model of the graphics processing module according to the model of the graphics processing module.

5. A model determination method, characterized in that: The method is applied to the model determination system according to any one of claims 1 to 4, and the method includes: In response to the second control module completing loading, acquiring a control signal; Using the control signal, control the first multiplexing module and the second multiplexing module to switch to a first target connection line, where the first target connection line is a connection line between the second control module and a plurality of serial communication devices; determining addresses of the plurality of serial communication devices using the first target connection line; The graphics processing module model is determined according to a mapping relationship between the address of the serial communication device and the graphics processing module model.

6. The model determination method according to claim 5, characterized in that: The addresses of the serial communication devices include the addresses of the first serial communication device and the second serial communication device: Determining the model of the graphics processing module according to a mapping relationship between an address of the serial communication device and a model of the graphics processing module includes: The graphics processing module model is determined according to a mapping relationship between the address of the first serial communication device, the address of the second serial communication device, and the graphics processing module model.

7. The model determination method according to claim 5, characterized in that: After determining the model of the graphics processing module according to the mapping relationship between the address of the serial communication device and the model of the graphics processing module, the method further includes: Determine a characteristic identifier, a power-on timeout duration, and a power-on control logic corresponding to the graphics processing module model.

8. The model determination method according to claim 7, characterized in that: After matching the power-on timeout duration and the power-on control logic corresponding to the feature identifier, the method includes: The first multiplexing module and the second multiplexing module are controlled to switch to a second target connection line, where the second target connection line is a connection line between the first control module and the plurality of serial communication devices.

9. The model determination method according to claim 8, characterized in that: After controlling the first multiplexing module and the second multiplexing module to switch to the second target connection line, the method includes: In response to receiving a power-on instruction, obtaining a first power-on timestamp; The second control module is powered on according to the power-on control logic; Get the second power-on timestamp; Based on the second power-on timestamp, the first power-on timestamp and the power-on timeout duration, a power-on result of the electronic device is determined, where the power-on result includes power-on completion and power-on timeout.

10. The model determination method according to claim 9, characterized in that: The determining a power-on result of the electronic device based on the second power-on timestamp, the first power-on timestamp, and the power-on timeout duration includes: determining a power-on duration of the electronic device based on the second power-on timestamp and the first power-on timestamp; In response to a power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in a powered-on state, determining that the electronic device has timed out from power-on; In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a powered-on state, continuing to power on according to the power-on control logic; In response to the power-on duration of the electronic device being less than the power-on timeout duration and the electronic device being in a power-on completion state, it is determined that the power-on of the electronic device is completed.

11. The model determination method according to claim 10, characterized in that: In response to the power-on duration of the electronic device being greater than the power-on timeout duration and the electronic device being in a powered-on state, after determining that the electronic device has timed out, the method includes: Obtaining power-on timeout information of the electronic device; An alarm message corresponding to the power-on timeout information of the electronic device is generated and sent to a controller, wherein the alarm message includes at least one of the model of the graphics processing module, the characteristic identifier of the graphics processing module, and the identifier of the power-on control logic.

12. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the model determination method according to any one of claims 5 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the model determination method according to any one of claims 5 to 11 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the model determination method according to any one of claims 5 to 11 are implemented.

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