Hardware Trojan trigger circuit based on aging effect and control method

Abstract

The invention discloses a hardware Trojan trigger circuit based on an aging effect and a control method, which are used for solving the technical problem that the reliability of the hardware Trojan trigger circuit is poor due to the fact that the existing hardware Trojan trigger circuit mainly adopts a design scheme based on a charge sharing principle. The circuit comprises an annular oscillator circuit, a duty ratio adjusting circuit, a delay selection circuit, an NBTI aging circuit and a D flip-flop circuit. The ring oscillator circuit is respectively connected with the duty ratio adjusting circuit and the delay selection circuit; the duty ratio adjusting circuit is connected with the delay selection circuit; the NBTI aging circuit is connected with the duty ratio adjusting circuit and the D flip-flop circuit. The D flip-flop circuit is connected with the ring oscillator circuit; a target control signal, a square wave signal and a second delay square wave signal are generated through an annular oscillator circuit, and the signals are transmitted and processed by combining a duty ratio adjusting circuit, a delay selection circuit, an NBTI aging circuit and a D flip-flop circuit to generate a target trigger signal.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware security, and in particular, to a hardware Trojan trigger circuit and a control method based on the aging effect. Background Art

[0002] A hardware Trojan is a special circuit module deliberately implanted or modified during the integrated circuit design or manufacturing process, or a design defect inadvertently left by the designer. When it is activated in a certain way, it may change the function or specification of the integrated circuit, leak sensitive information, cause the performance of the integrated circuit to decline, lose control, or even cause irreversible damage.

[0003] The application of the hardware Trojan trigger circuit is mainly reflected in the fields of security testing, hardware authentication, and fault-tolerant design. In security testing, researchers use a controllable hardware Trojan trigger mechanism to evaluate the vulnerability of the chip, so as to improve the defense strategy. For example, in high-security chips in the military and financial fields, actively implanting a monitorable hardware Trojan module can be used to simulate attack scenarios and verify the effectiveness of the hardware security protection mechanism. In terms of hardware authentication, a specific trigger circuit can be used as an auxiliary module of the physical unclonable function (PUF), generating keys or identity identifiers through unique hardware characteristics to enhance the anti-counterfeiting ability of the device. In addition, in fault-tolerant design, a programmable hardware Trojan trigger mechanism can be reconfigured as part of a redundant circuit to activate a standby module when a system anomaly is detected, improving the reliability of the system. These applications show that if the hardware Trojan trigger technology is reasonably utilized, it can bring innovative solutions to the field of hardware security.

[0004] The existing hardware Trojan trigger circuits mainly adopt a design scheme based on the charge sharing principle. Its working principle requires an external signal to continuously switch between high and low levels, and realizes charge accumulation by controlling the periodic charging and discharging process of a capacitor. When the accumulated charge reaches a preset threshold, the subsequent load circuit is triggered. However, this trigger circuit is overly dependent on the external signal, which not only increases the risk of being detected by side-channel analysis, but more critically, it will cause the trigger to fail in application scenarios lacking a stable external signal, resulting in poor reliability of the hardware Trojan trigger circuit. Summary of the Invention

[0005] The present invention provides a hardware Trojan trigger circuit and a control method based on the aging effect, which are used to solve the technical problem that the existing hardware Trojan trigger circuits mainly adopt a design scheme based on the charge sharing principle, resulting in poor reliability of the hardware Trojan trigger circuit.

[0006] A hardware Trojan trigger circuit based on aging effect provided by the first aspect of the present invention, the circuit includes a ring oscillator circuit, a duty cycle adjustment circuit, a delay selection circuit, an NBTI aging circuit, and a D flip-flop circuit;

[0007] The ring oscillator circuit is respectively connected to the duty cycle adjustment circuit and the delay selection circuit;

[0008] The duty cycle adjustment circuit is connected to the delay selection circuit;

[0009] The NBTI aging circuit is respectively connected to the duty cycle adjustment circuit and the D flip-flop circuit;

[0010] The D flip-flop circuit is connected to the ring oscillator circuit;

[0011] The ring oscillator circuit is used to generate a target control signal, a square wave signal, and a second delayed square wave signal;

[0012] The delay selection circuit is used to generate a first delayed square wave signal based on the target control signal or the square wave signal transmitted by the ring oscillator circuit;

[0013] The duty cycle adjustment circuit is used to perform a logical operation on the square wave signal transmitted by the ring oscillator circuit, the second delayed square wave signal, and the first delayed square wave signal transmitted by the delay selection circuit, output a target composite square wave signal and transmit it to the NBTI aging circuit;

[0014] The NBTI aging circuit is used to generate a voltage signal according to the target composite square wave signal;

[0015] The D flip-flop circuit is used to generate a target trigger signal according to the square wave signal transmitted by the ring oscillator circuit and the voltage signal transmitted by the NBTI aging circuit.

[0016] Optionally, the ring oscillator circuit includes an odd number of cascaded inverters.

[0017] Optionally, the target composite square wave signal includes a first composite square wave signal and a second composite square wave signal; the duty cycle adjustment circuit includes an AND gate and an OR gate;

[0018] The first input terminal of the AND gate is connected to the first output terminal of the ring oscillator circuit, and the second input terminal of the AND gate is connected to the signal output terminal of the delay selection circuit;

[0019] The first input terminal of the OR gate is connected to the first output terminal of the ring oscillator circuit, and the second input terminal of the OR gate is connected to the second output terminal of the ring oscillator circuit;

[0020] The output terminal of the AND gate and the output terminal of the OR gate are both connected to the NBTI aging circuit;

[0021] The AND gate is configured to perform an AND operation on the square wave signal transmitted by the ring oscillator circuit and the first delayed square wave signal transmitted by the delay selection circuit, and output a first synthesized square wave signal;

[0022] The OR gate is configured to perform an OR operation on the square wave signal transmitted by the ring oscillator circuit and the second delayed square wave signal, and output a second synthesized square wave signal.

[0023] Optionally, the delay selection circuit includes three switches, and all three switches are composed of a transmission gate and an inverter connected in series;

[0024] The signal input terminal of the transmission gate of the first switch is connected to the third output terminal of the ring oscillator circuit, and the signal output terminal of the transmission gate of the first switch is connected to the second input terminal of the AND gate;

[0025] The signal input terminal of the transmission gate of the second switch is connected to the fourth output terminal of the ring oscillator circuit, and the signal output terminal of the transmission gate of the second switch is connected to the second input terminal of the AND gate;

[0026] The signal input terminal of the transmission gate of the third switch is connected to the first output terminal of the ring oscillator circuit, and the signal output terminal of the transmission gate of the third switch is connected to the second input terminal of the AND gate.

[0027] Optionally, the target control signal includes a first control signal and a second control signal;

[0028] The first switch is configured to generate a first delayed square wave signal according to the first control signal transmitted by the ring oscillator circuit when the control input terminal of the transmission gate of the first switch is at a high level, and the control input terminals of the transmission gates of the second switch and the third switch are at a low level;

[0029] The second switch is configured to generate a first delayed square wave signal according to the second control signal transmitted by the ring oscillator circuit when the control input terminal of the transmission gate of the second switch is at a high level, and the control input terminals of the transmission gates of the first switch and the third switch are at a low level;

[0030] The third switch is configured to generate a first delayed square wave signal according to the square wave signal transmitted by the ring oscillator circuit when the control input terminal of the transmission gate of the third switch is at a high level, and the control input terminals of the transmission gates of the first switch and the second switch are at a low level.

[0031] Optionally, the NBTI aging circuit includes a power supply terminal, a ground terminal, two P-channel metal-oxide-semiconductor field-effect transistors, and two N-channel metal-oxide-semiconductor field-effect transistors;

[0032] The power supply terminal is connected to the source of the first P-channel metal-oxide-semiconductor field-effect transistor;

[0033] The output terminals of the AND gate are respectively connected to the gate of the first P-channel metal-oxide-semiconductor field-effect transistor and the gate of the second P-channel metal-oxide-semiconductor field-effect transistor;

[0034] The drain of the first P-channel metal-oxide-semiconductor field-effect transistor is connected to the source of the second P-channel metal-oxide-semiconductor field-effect transistor;

[0035] The drain of the second P-channel metal-oxide-semiconductor field-effect transistor is connected to the drain of the first N-channel metal-oxide-semiconductor field-effect transistor;

[0036] The output terminals of the OR gate are respectively connected to the gate of the first N-channel metal-oxide-semiconductor field-effect transistor and the gate of the second N-channel metal-oxide-semiconductor field-effect transistor;

[0037] The source of the first N-channel metal-oxide-semiconductor field-effect transistor is connected to the drain of the second N-channel metal-oxide-semiconductor field-effect transistor;

[0038] The source of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to the ground terminal;

[0039] The input terminal of the D flip-flop circuit is connected between the drain of the second P-channel metal-oxide-semiconductor field-effect transistor and the drain of the first N-channel metal-oxide-semiconductor field-effect transistor.

[0040] A second aspect of the present invention provides a control method for a hardware Trojan trigger circuit based on aging effect, which is applied to the above-mentioned hardware Trojan trigger circuit based on aging effect, and includes:

[0041] When the ring oscillator circuit in the hardware Trojan trigger circuit based on aging effect generates a target control signal, a square wave signal, and a second delayed square wave signal, a first delayed square wave signal is generated based on the target control signal or the square wave signal;

[0042] Perform a logical operation on the square wave signal, the second delayed square wave signal, and the first delayed square wave signal, and output a target composite square wave signal;

[0043] Generate a voltage signal based on the target synthesized square wave signal;

[0044] Generate a target trigger signal according to the square wave signal and the voltage signal.

[0045] A computer device provided by the third aspect of the present invention includes a memory and a processor. A computer program is stored in the memory. When the computer program is executed by the processor, the processor executes the steps of the control method of the hardware Trojan trigger circuit based on the aging effect as described above.

[0046] A computer-readable storage medium provided by the fourth aspect of the present invention stores a computer program thereon. When the computer program is executed, the steps of the control method of the hardware Trojan trigger circuit based on the aging effect as described above are implemented.

[0047] A computer program product provided by the fifth aspect of the present invention includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the steps of the control method of the hardware Trojan trigger circuit based on the aging effect as described above.

[0048] It can be seen from the above technical solutions that the present invention has the following advantages:

[0049] In the first aspect of the above technical solution of the present invention, a hardware Trojan trigger circuit based on aging effect is provided. The circuit includes a ring oscillator circuit, a duty cycle adjustment circuit, a delay selection circuit, an NBTI aging circuit, and a D flip-flop circuit. Among them, the ring oscillator circuit is respectively connected to the duty cycle adjustment circuit and the delay selection circuit; the duty cycle adjustment circuit is connected to the delay selection circuit; the NBTI aging circuit is respectively connected to the duty cycle adjustment circuit and the D flip-flop circuit; the D flip-flop circuit is connected to the ring oscillator circuit. The ring oscillator circuit is used to generate a target control signal, a square wave signal, and a second delayed square wave signal. The delay selection circuit is used to generate a first delayed square wave signal based on the target control signal or the square wave signal transmitted by the ring oscillator circuit. The duty cycle adjustment circuit is used to perform a logical operation on the square wave signal, the second delayed square wave signal, and the first delayed square wave signal transmitted by the delay selection circuit, output a target composite square wave signal, and transmit it to the NBTI aging circuit. The NBTI aging circuit is used to generate a voltage signal according to the target composite square wave signal. The D flip-flop circuit is used to generate a target trigger signal according to the square wave signal transmitted by the ring oscillator circuit and the voltage signal transmitted by the NBTI aging circuit. Based on the above solution, by generating a target control signal, a square wave signal, and a second delayed square wave signal through the ring oscillator circuit, and combining the duty cycle adjustment circuit, the delay selection circuit, the NBTI aging circuit, and the D flip-flop circuit to process the signals, a target trigger signal is generated. The present invention uses the ring oscillator as the internal drive signal of the hardware Trojan trigger circuit, does not need to rely on external drive signals, can be directly implanted into any type of normal circuit without modifying the internal signals of the normal circuit, and improves the reliability of the hardware Trojan trigger circuit.

[0050] In the second aspect of the above technical solution of the present invention, a control method for a hardware Trojan trigger circuit based on aging effect is provided. When the ring oscillator circuit in the hardware Trojan trigger circuit based on aging effect generates a target control signal, a square wave signal, and a second delayed square wave signal, a first delayed square wave signal is generated based on the target control signal or the square wave signal; a logical operation is performed on the square wave signal, the second delayed square wave signal, and the first delayed square wave signal, and a target composite square wave signal is output; a voltage signal is generated based on the target composite square wave signal; a target trigger signal is generated according to the square wave signal and the voltage signal. Based on the above solution, in the process of generating a target control signal, a square wave signal, and a second delayed square wave signal through the ring oscillator circuit and processing the generated signals to output a target trigger signal, the present invention uses the ring oscillator as the internal drive signal of the hardware Trojan trigger circuit, does not need to rely on external drive signals, can be directly implanted into any type of normal circuit without modifying the internal signals of the normal circuit, and improves the reliability of the hardware Trojan trigger circuit. Description of the Drawings

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0052] Figure 1 Schematic diagram of the structure of a hardware Trojan trigger circuit based on aging effect provided in Embodiment 1 of the present application;

[0053] Figure 2 Schematic diagram of the waveform signal output by the ring oscillator provided in Embodiment 1 of the present application;

[0054] Figure 3 Schematic diagram of the output signal of the AND gate provided in Embodiment 1 of the present application;

[0055] Figure 4 Schematic diagram of the output signal of the OR gate provided in Embodiment 1 of the present application;

[0056] Figure 5 Schematic diagram of the structure of the NBTI aging circuit provided in Embodiment 1 of the present application;

[0057] Figure 6 Schematic diagram of the input and output signals of the NBTI aging circuit provided in Embodiment 1 of the present application;

[0058] Figure 7 Schematic diagram of the signals RO, TJ, and QN before triggering provided in Embodiment 1 of the present application;

[0059] Figure 8 Schematic diagram of the signals RO, TJ, and QN after triggering provided in Embodiment 1 of the present application;

[0060] Figure 9 Schematic diagram of the structure of the trigger circuit based on charge sharing provided in Embodiment 1 of the present application;

[0061] Figure 10 Schematic diagram of the relationship curve between the trigger time and the width of the M2 transistor provided in Embodiment 1 of the present application;

[0062] Figure 11 Schematic diagram of the relationship curve between the trigger time and the duty cycle of the gate of the M2 transistor provided in Embodiment 1 of the present application;

[0063] Figure 12 Flowchart of the steps of a control method for a hardware Trojan trigger circuit based on aging effect provided in Embodiment 2 of the present application;

[0064] Among them, the reference numerals are as follows:

[0065] 1. Ring oscillator circuit; 2. Duty cycle adjustment circuit; 3. Delay selection circuit; 4. NBTI aging circuit; 5. D flip - flop circuit. Specific implementation manners

[0066] An embodiment of the present invention provides a hardware trojan trigger circuit and a control method based on aging effect, which are used to solve the technical problem that the existing hardware trojan trigger circuits mainly adopt design schemes based on the charge sharing principle, resulting in poor reliability of the hardware trojan trigger circuits.

[0067] Term explanations:

[0068] 1. Hardware trojan: It refers to a special circuit module deliberately implanted or modified during the integrated circuit design or manufacturing process, or a design defect inadvertently left by the designer. When it is activated in a certain way, it may change the function or specifications of the integrated circuit, leak sensitive information, cause a decline in the performance of the integrated circuit, loss of control, or even irreversible damage.

[0069] 2. Trigger circuit: A hardware trojan can be composed of a trigger circuit and a load circuit. The trigger circuit is mainly used to monitor specific signals or a series of target events in the circuit. When specific conditions are met, the load circuit is activated.

[0070] 3. Load circuit: A hardware trojan can be composed of a trigger circuit and a load circuit. When the load circuit is activated, it will perform an attack behavior.

[0071] 4. PMOS (P - type Metal - Oxide - Semiconductor Field - Effect Transistor): P - channel metal - oxide - semiconductor field - effect transistor. Its basic structure includes a source electrode, a gate electrode, a drain electrode, and a substrate, and it is an important device in integrated circuits.

[0072] 5. NMOS (N - type Metal - Oxide - Semiconductor Field - Effect Transistor): N - channel metal - oxide - semiconductor field - effect transistor. Its basic structure includes a source electrode, a gate electrode, a drain electrode, and a substrate, and it is an important device in integrated circuits.

[0073] 6. NBTI (Negative Bias Temperature Instability): Negative bias temperature instability. An aging effect of integrated circuits, which refers to the phenomenon that the resistance and threshold voltage of PMOS gradually drift over time under negative gate bias and high - temperature conditions. This drift will cause device performance degradation and affect the long - term reliability of the circuit.

[0074] 7. RTL (Register - Transfer - Level): Register Transfer Level. It is an abstraction level in digital circuit design, used to describe the flow and processing method of data between registers.

[0075] In order to make the invention purpose, features, and advantages of the present invention more obvious and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0076] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a hardware Trojan trigger circuit based on aging effect provided in Embodiment 1 of this application.

[0077] A hardware Trojan trigger circuit based on aging effect provided by the present invention, the circuit includes a ring oscillator circuit 1, a duty cycle adjustment circuit 2, a delay selection circuit 3, an NBTI aging circuit 4, and a D - flip - flop circuit 5; the ring oscillator circuit 1 is respectively connected to the duty cycle adjustment circuit 2 and the delay selection circuit 3; the duty cycle adjustment circuit 2 is connected to the delay selection circuit 3; the NBTI aging circuit 4 is respectively connected to the duty cycle adjustment circuit 2 and the D - flip - flop circuit 5; the D - flip - flop circuit 5 is connected to the ring oscillator circuit 1;

[0078] The ring oscillator circuit 1 is used to generate a target control signal, a square wave signal, and a second delayed square wave signal;

[0079] The delay selection circuit 2 is used to generate a first delayed square wave signal based on the target control signal or the square wave signal transmitted by the ring oscillator circuit;

[0080] The duty cycle adjustment circuit 3 is used to perform a logical operation on the square wave signal transmitted by the ring oscillator circuit, the second delayed square wave signal, and the first delayed square wave signal transmitted by the delay selection circuit, and output a target composite square wave signal and transmit it to the NBTI aging circuit 4;

[0081] The NBTI aging circuit 4 is used to generate a voltage signal according to the target composite square wave signal;

[0082] The D - flip - flop circuit 5 is used to generate a target trigger signal according to the square wave signal transmitted by the ring oscillator circuit and the voltage signal transmitted by the NBTI aging circuit.

[0083] It should be noted that the trigger circuit proposed by the present invention is implemented based on the NBTI aging effect of PMOS. Under the conditions of negative gate bias and high temperature, the resistance and threshold voltage of PMOS gradually increase with time, so that the output of the trigger circuit changes from low level to high level, activating the subsequent load circuit. Moreover, the trigger time of the trigger circuit can be controlled by adjusting the width of the PMOS transistor during design. The complete circuit diagram of the trigger circuit is as shown in Figure 1 shown, which has five parts, namely a ring oscillator circuit 1 (red box), a duty cycle adjustment circuit 2 (yellow box), a delay selection circuit 3 (purple box), an NBTI aging circuit 4 (blue box), and a D flip-flop circuit 5 (green box). The square wave signal RO output by the ring oscillator circuit 1 serves as the clock signal of the D flip-flop circuit 5. At the same time, the square wave signal RO also serves as an input to the duty cycle adjustment circuit 2. The signal output by the delay selection circuit 3 serves as another input to the duty cycle adjustment circuit 2. The longer the PMOS is subjected to the negative gate bias, the more severe its NBTI aging effect. Therefore, the signals with different duty cycles output by the duty cycle adjustment circuit 2 can control the aging rate of the NBTI aging circuit 4. In addition, adjusting the width of the PMOS in the NBTI aging circuit 4 can also control the aging rate. As time goes by, the output voltage TJ (i.e., the voltage signal) of the NBTI aging circuit 4 increases, and the voltage signal TJ serves as the input of the D flip-flop circuit 5, which will cause the signal at the QN terminal (i.e., the target trigger signal) to flip from low level to high level, thus realizing the trigger.

[0084] It is worth mentioning that the first output terminal of the ring oscillator circuit 1 is used to output the square wave signal RO, the second output terminal of the ring oscillator circuit 1 is used to output the second delayed square wave signal a2, the third output terminal of the ring oscillator circuit 1 is used to output the first control signal p1, and the fourth output terminal of the ring oscillator circuit 1 is used to output the second control signal p2.

[0085] As a further improvement, the ring oscillator circuit 1 includes an odd number of cascaded inverters.

[0086] It should be noted that the ring oscillator circuit 1 is formed by connecting an odd number of inverters end to end to form a closed loop, using gate delay to generate a periodic oscillation signal. The fewer the number of stages, the higher the frequency, but the worse the stability. However, if the number of stages is too large, the area of the ring oscillator will also be too large. Therefore, the present invention selects a 25-stage ring oscillator, and its output waveform is as shown in Figure 2 shown, and the frequency of this square wave is about 1.77 GHz. The output of the ring oscillator circuit 1 serves as the input of the duty cycle adjustment circuit 2 and the D flip-flop circuit 5, so that the trigger circuit does not require an external drive signal and can be directly implanted into any type of normal circuit without modifying the internal signals of the normal circuit.

[0087] As a further improvement, the target synthesized square wave signal includes a first synthesized square wave signal and a second synthesized square wave signal; the duty cycle adjustment circuit 2 includes an AND gate and an OR gate;

[0088] The first input terminal of the AND gate is connected to the first output terminal of the ring oscillator circuit 1, and the second input terminal of the AND gate is connected to the signal output terminal of the delay selection circuit 3;

[0089] The first input terminal of the OR gate is connected to the first output terminal of the ring oscillator circuit 1, and the second input terminal of the OR gate is connected to the second output terminal of the ring oscillator circuit 1;

[0090] The output terminals of the AND gate and the OR gate are both connected to the NBTI aging circuit 4;

[0091] The AND gate is used to perform an AND operation on the square wave signal transmitted by the ring oscillator circuit 1 and the first delayed square wave signal transmitted by the delay selection circuit 3, and output the first synthesized square wave signal;

[0092] The OR gate is used to perform an OR operation on the square wave signal transmitted by the ring oscillator circuit 1 and the second delayed square wave signal, and output the second synthesized square wave signal.

[0093] It should be noted that the NBTI aging effect of PMOS is related to the length of time that PMOS is in the negative gate bias state. Therefore, the aging rate of the NBTI aging circuit can be controlled by adjusting the duty cycle of the PMOS gate voltage signal. The smaller the duty cycle, the longer the low-level time in one cycle, so that the time that PMOS is in the negative gate bias state is longer and the aging rate is faster. The duty cycle adjustment circuit 2 consists of two devices, namely an AND gate and an OR gate. The input of the AND gate is the square wave signal RO and the first delayed square wave signal a1 after the square wave signal RO passes through a period of delay. The output is connected to the gates of the two PMOSs in the NBTI aging circuit 4, which is used to reduce the duty cycle and accelerate aging. The input of the OR gate is the square wave signal RO and the second delayed square wave signal a2 after RO passes through another period of delay. The output is connected to the gates of the two NMOSs in the NBTI aging circuit, which is used to increase the duty cycle and shorten the time when the 4 MOSs in the NBTI aging circuit 4 are conducting simultaneously, thereby reducing power consumption. The output signal of the AND gate is as Figure 3 shown, and the output signal of the OR gate is as Figure 4 shown.

[0094] As a further improvement, the delay selection circuit 3 includes three switches, and all three switches are composed of a series-connected transmission gate and an inverter;

[0095] The signal input terminal of the transmission gate of the first switch is connected to the third output terminal of the ring oscillator circuit 1, and the signal output terminal of the transmission gate of the first switch is connected to the second input terminal of the AND gate;

[0096] The signal input terminal of the transmission gate of the second switch is connected to the fourth output terminal of the ring oscillator circuit 1, and the signal output terminal of the transmission gate of the second switch is connected to the second input terminal of the AND gate;

[0097] The signal input terminal of the transmission gate of the third switch is connected to the first output terminal of the ring oscillator circuit 1, and the signal output terminal of the transmission gate of the third switch is connected to the second input terminal of the AND gate.

[0098] As a further improvement, the target control signal includes a first control signal and a second control signal;

[0099] The first switch is configured to generate a first delayed square wave signal according to the first control signal transmitted by the ring oscillator circuit 1 when the control input terminal of the transmission gate of the first switch is at a high level, and the control input terminals of the transmission gates of the second switch and the third switch are at low levels;

[0100] The second switch is configured to generate a first delayed square wave signal according to the second control signal transmitted by the ring oscillator circuit 1 when the control input terminal of the transmission gate of the second switch is at a high level, and the control input terminals of the transmission gates of the first switch and the third switch are at low levels;

[0101] The third switch is configured to generate a first delayed square wave signal according to the square wave signal transmitted by the ring oscillator circuit 1 when the control input terminal of the transmission gate of the third switch is at a high level, and the control input terminals of the transmission gates of the first switch and the second switch are at low levels.

[0102] It should be noted that the delay selection circuit 3 is essentially composed of three switches (i.e., the first switch K1, the second switch K2, and the third switch K3) formed by transmission gates and inverters, which are used to select signals with different delays and input them into the duty cycle adjustment circuit 2, so as to realize the output of different duty cycles. In the delay selection circuit 3, when the control input terminal S25 of the transmission gate of the first switch K1 is at a high level, and the control input terminals S9 of the transmission gates of the second switch K2 and S45 of the transmission gate of the third switch K3 are at low levels, the transmission gate of the first switch K1 is turned on to transmit the first control signal p1, thereby outputting the first delayed square wave signal a1; when the control input terminal S9 of the transmission gate of the second switch K2 is at a high level, and the control input terminals S25 of the transmission gate of the first switch K1 and S45 of the transmission gate of the third switch K3 are at low levels, the transmission gate of the second switch K2 is turned on to transmit the second control signal p2, thereby outputting the first delayed square wave signal a1; when the control input terminal S45 of the transmission gate of the third switch K3 is at a high level, and the control input terminals S9 of the transmission gate of the first switch K1 and S25 of the transmission gate of the second switch K2 are at low levels, the transmission gate of the third switch K3 is turned on to transmit the square wave signal RO, thereby outputting the first delayed square wave signal a1.

[0103] As a further improvement, the NBTI aging circuit 4 includes a power supply terminal, a ground terminal, two P-channel metal oxide semiconductor field effect transistors, and two N-channel metal oxide semiconductor field effect transistors;

[0104] The power supply terminal is connected to the source electrode of the first P-channel metal oxide semiconductor field effect transistor;

[0105] The output terminals of the AND gate are respectively connected to the gate electrodes of the first P-channel metal oxide semiconductor field effect transistor and the second P-channel metal oxide semiconductor field effect transistor;

[0106] The drain electrode of the first P-channel metal oxide semiconductor field effect transistor is connected to the source electrode of the second P-channel metal oxide semiconductor field effect transistor;

[0107] The drain electrode of the second P-channel metal oxide semiconductor field effect transistor is connected to the drain electrode of the first N-channel metal oxide semiconductor field effect transistor;

[0108] The output terminals of the OR gate are respectively connected to the gate electrodes of the first N-channel metal oxide semiconductor field effect transistor and the second N-channel metal oxide semiconductor field effect transistor;

[0109] The source electrode of the first N-channel metal oxide semiconductor field effect transistor is connected to the drain electrode of the second N-channel metal oxide semiconductor field effect transistor;

[0110] The source of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to the ground terminal;

[0111] The input terminal of the D flip-flop circuit is connected between the drain of the second P-channel metal-oxide-semiconductor field-effect transistor and the drain of the first N-channel metal-oxide-semiconductor field-effect transistor.

[0112] It should be noted that the NBTI aging circuit 4, as Figure 5 shown, is composed of two PMOSs (the first P-channel metal-oxide-semiconductor field-effect transistor M1, the second P-channel metal-oxide-semiconductor field-effect transistor M2) and two NMOSs (the first N-channel metal-oxide-semiconductor field-effect transistor M3, the second N-channel metal-oxide-semiconductor field-effect transistor M4) connected in series. The gates of M1 and M2 are connected to the AND gate in the duty cycle adjustment circuit 2, as Figure 6 the blue signal in; the gates of M3 and M4 are connected to the OR gate in the duty cycle adjustment circuit 2, as Figure 6 the green signal in. The output voltage signal TJ is like Figure 6 the red signal in. When the blue signal is at a high level, M1 and M2 are turned off. When the blue signal is at a low level, M1 and M2 are turned on. When the green signal is at a high level, M3 and M4 are turned on. When the green signal is at a low level, M3 and M4 are turned off. Therefore, when both the blue signal and the green signal are at a high level, the TJ signal outputs a low level; when both the blue signal and the green signal are at a low level, the TJ signal outputs a high level; when the blue signal is at a low level and the green signal is at a high level, the signal TJ outputs the voltage division of the PMOS and NMOS for the power supply. As time goes by, the NBTI aging effect will increase the resistance of M1 and M2, thereby reducing the voltage of TJ.

[0113] Furthermore, for the D flip-flop circuit 5, the D flip-flop 5 used in the present invention is a rising-edge triggered D flip-flop 5. The input terminal of the D flip-flop 5 includes a first input terminal (for inputting TJ) and a second input terminal (for inputting RO). When the square wave signal RO jumps from a low level to a high level, the voltage signal TJ is sampled, and the output target trigger signal QN has a level opposite to that of the voltage signal TJ. When the trigger circuit is not triggered, the TJ voltage is relatively high and is sampled into a high level by the D flip-flop circuit, so that QN outputs a low level, as Figure 7 shown, the blue is the signal RO, the green is the signal TJ, and the red is the signal QN; as time goes by, due to the NBTI aging effect, the voltage of TJ gradually decreases and is sampled into a low level by the D flip-flop circuit, so that QN outputs a high level, as Figure 8 shown, the blue is the signal RO, the green is the signal TJ, and the red is the signal QN. Taking QN as the output of the trigger circuit can achieve the trigger from a low level to a high level.

[0114] As a comparison of technical effects, it can be referenced in combination with the existing technology. Currently, hardware Trojans cover digital and analog circuit types, and their attack carriers include processor cores, memories, power management units, etc., penetrating the entire life cycle of chip design, manufacturing, packaging, and the supply chain. From the perspective of technical implementation, a typical hardware Trojan can be composed of a trigger circuit and a load circuit. The trigger circuit, as the central decision-making module of the hardware Trojan, its core function is to activate the load circuit through multi-modal condition perception. The main technical paths include: ① Timing trigger: For example, realizing delayed activation based on a counter or a timer to avoid early functional testing; ② Protocol trigger: For example, parsing the bus communication content to achieve protocol-level context awareness; ③ Physical environment trigger: Using an integrated micro-sensor to monitor physical characteristics such as temperature, voltage, and electromagnetic radiation; ④ Combinational logic trigger: For example, using a specific combinational logic signal as a trigger condition. The design of the trigger circuit directly affects the concealment, reliability, and attack effect of the hardware Trojan. The load circuit covers functions such as functional change or damage, information leakage, and denial of service. Despite the variety of disguises and techniques, the identification of hardware Trojans still mainly relies on the identification of the functions of the trigger circuit and the load circuit. If the two screening limitations can be effectively broken through, new types of hardware Trojans with high survivability can be explored and designed. In addition, in order to reduce the potential risk of hardware Trojans being identified, hardware Trojans that meet a series of requirements such as low overhead cost, high success rate, flexible deployment, and strong latency are also key indicators to focus on during design.

[0115] For the trigger circuit, it should be integrated with the normal circuit as much as possible to increase concealment and avoid being discovered during routine tests. At the same time, it should also meet the characteristics of controllable trigger time and a large trigger time range. Currently, a relatively mature solution is the trigger circuit based on charge sharing, as Figure 9 shown. This solution requires an external signal Clk. When Clk is at a low level, the capacitor Cunit starts to charge, and the charge of the capacitor Cmain remains unchanged. When Clk is at a high level, the capacitor Cunit and the capacitor Cmain are connected for charge sharing, that is, the charge of Cunit decreases and the charge of Cmain increases until the charges of the two are equal. Therefore, as Clk continuously changes between low and high levels, the charge of Cmain gradually increases. When it increases to a certain value, the subsequent load circuit can be triggered. This solution has a small trigger circuit area, a simple structure, can be directly inserted into the normal circuit without modifying the RTL (Register Transfer Level) code of the normal circuit, has high concealment, and is difficult to detect. However, this solution relies on an external signal, and due to the principle of charge sharing, the trigger time range of this trigger circuit is very short.

[0116] Furthermore, the disadvantages of existing hardware Trojan trigger circuits are as follows: ① They require external signal drive; ② The trigger time range is small; ③ The trigger time is difficult to control. In view of these disadvantages, the object of the present invention is to implement a hardware Trojan trigger circuit with high concealment, difficult to detect, without external signal drive, a wide trigger time range, and controllable trigger time.

[0117] Therefore, the technical problems to be solved by the present invention are: ① Implement a trigger circuit without external signals; ② Increase the trigger time range of the trigger circuit; ③ Be able to accurately control the trigger circuit to trigger within a specified time by adjusting circuit parameters. Specifically, the present invention proposes a hardware Trojan trigger circuit based on the aging effect, which uses a ring oscillator as the internal drive signal of the hardware Trojan trigger circuit, without the need for an external drive signal, and can be directly implanted into any type of normal circuit without modifying the internal signals of the normal circuit. At the same time, an NBTI aging circuit with a series structure is used to achieve a wider trigger time range by adjusting the width of the transistor during the circuit design stage. In addition, during the circuit operation stage, the trigger time is extended or shortened by adjusting the duty cycle, enhancing the controllability of the hardware Trojan trigger circuit.

[0118] In summary, the hardware Trojan trigger circuit based on the aging effect proposed by the present invention realizes the functions of without external signal drive, a wide trigger time range, and controllable trigger time. Specifically, in the hardware Trojan trigger circuit based on the aging effect, a ring oscillator is used as the input of the duty cycle adjustment circuit and the D flip-flop circuit, without the signal of an external circuit. Therefore, for any type of normal circuit, this trigger circuit can be implanted without changing the internal signals of the normal circuit. At the same time, the voltage magnitude of signal TJ is related to the voltage division of the power supply by PMOS and NMOS. The voltage division of the power supply by PMOS and NMOS depends on their resistances, and the resistance is related to the width of the transistor. Therefore, during the circuit design process, the voltage magnitude of TJ can be controlled by adjusting the width of transistor M2. The smaller the width of M2, the larger the resistance, the smaller the voltage of TJ, and the shorter the trigger time. The relationship between the trigger time and the width of transistor M2 is as Figure 10 shown. Under the conditions of a temperature of 27 degrees and a duty cycle of 45%, by setting the width of transistor M2 between 400nm - 650nm, the achievable trigger time range is 0 - 30 years, which is wider than the trigger time range of currently advanced hardware Trojan trigger circuits.

[0119] Furthermore, when designing the hardware Trojan trigger circuit, the designer can select the width of transistor M2 according to the required trigger time. However, when the trigger circuit is running, the width of the transistor cannot be changed. Therefore, during the circuit operation, the trigger time can be controlled by adjusting the duty cycle of the gate signal of transistor M2. The relationship between the trigger time and the duty cycle of the gate signal of transistor M2 is as Figure 11As shown, under the conditions of a temperature of 27 degrees and an M2 transistor width of 600 nm, the trigger time and the duty cycle are approximately linearly related. This trigger circuit uses a delay selection circuit and a duty cycle adjustment circuit to control the duty cycle. The delay selection circuit provides three ports: S9, S25, and S45, corresponding to duty cycles of 9%, 25%, and 45% respectively.

[0120] In the circuit design stage, the transistor width can be set according to the required trigger time under the condition of a 25% duty cycle; in the circuit operation stage, the trigger time can be extended or shortened by setting the values of S9, S25, and S45. When S9 is set to a high level and S25 and S45 are set to low levels, the duty cycle becomes 9%, accelerating the NBTI aging effect and thus shortening the trigger time; when S45 is set to a high level and S9 and S25 are set to low levels, the duty cycle becomes 45%, slowing down the NBTI aging effect and thus extending the trigger time.

[0121] In summary, the trigger time of this hardware Trojan trigger circuit can be adjusted in both the design stage and the operation stage, greatly increasing the controllability of the trigger time. Compared with the existing technology, although the existing optimal solution has a small area, a simple structure, can be directly inserted into the normal circuit without modifying the RTL code of the normal circuit, and has high concealment and is difficult to detect. However, this solution relies on external signals, and due to the fact that this solution is based on the charge sharing principle, the trigger time range of this trigger circuit is very short. And the present invention uses a ring oscillator as the internal drive signal of the hardware Trojan trigger circuit, without relying on external signals; uses a series-structured NBTI aging circuit, sets the trigger time by adjusting the transistor width, and has a wider trigger time range than the current optimal solution; uses a duty cycle adjustment circuit to extend or shorten the trigger time, and is more controllable than the current optimal solution.

[0122] In practical applications, the hardware Trojan trigger circuit based on the aging effect proposed by the present invention has the following application values in the field of hardware security: First, in chip security testing, the built-in ring oscillator driving mechanism can simulate a hardware Trojan attack scenario with extremely strong concealment. Through the NBTI aging effect, it can achieve a delay trigger characteristic, which can effectively verify the chip's defense ability against long-term latent threats. Second, in the authentication of military-grade encryption devices, this circuit can be combined with the PUF module to construct a dual security mechanism. By using the unique threshold voltage drift characteristics generated by aging to generate unclonable physical keys, it can significantly improve the anti-reverse engineering ability. In addition, in high-reliability systems such as aerospace, this circuit can be reconfigured as an aging monitoring module. When it detects that the PMOS transistor degrades in performance due to radiation or long-term use, it can automatically activate the redundant circuit to replace the failed unit, realizing the chip-level autonomous fault tolerance function. These applications fully reflect the innovative value of this technology in enhancing the depth of hardware security testing, strengthening the anti-counterfeiting ability, and extending the lifespan of key devices through internal signal driving and a controllable aging mechanism.

[0123] In an embodiment of the present invention, the present invention provides a hardware Trojan trigger circuit based on the aging effect. The circuit includes a ring oscillator circuit, a duty cycle adjustment circuit, a delay selection circuit, an NBTI aging circuit, and a D flip-flop circuit. Among them, the ring oscillator circuit is respectively connected to the duty cycle adjustment circuit and the delay selection circuit; the duty cycle adjustment circuit is connected to the delay selection circuit; the NBTI aging circuit is respectively connected to the duty cycle adjustment circuit and the D flip-flop circuit; the D flip-flop circuit is connected to the ring oscillator circuit. The ring oscillator circuit is used to generate a target control signal, a square wave signal, and a second delayed square wave signal. The delay selection circuit is used to generate a first delayed square wave signal based on the target control signal or the square wave signal transmitted by the ring oscillator circuit. The duty cycle adjustment circuit is used to perform a logical operation on the square wave signal transmitted by the ring oscillator circuit, the second delayed square wave signal, and the first delayed square wave signal transmitted by the delay selection circuit, and output a target composite square wave signal and transmit it to the NBTI aging circuit. The NBTI aging circuit is used to generate a voltage signal according to the target composite square wave signal. The D flip-flop circuit is used to generate a target trigger signal according to the square wave signal transmitted by the ring oscillator circuit and the voltage signal transmitted by the NBTI aging circuit. Based on the above solution, by generating a target control signal, a square wave signal, and a second delayed square wave signal through the ring oscillator circuit, and combining the duty cycle adjustment circuit, the delay selection circuit, the NBTI aging circuit, and the D flip-flop circuit to process the signals to generate a target trigger signal, the present invention uses the ring oscillator as the internal driving signal of the hardware Trojan trigger circuit, does not need to rely on external driving signals, and can be directly implanted into any type of normal circuit without modifying the internal signals of the normal circuit, improving the reliability of the hardware Trojan trigger circuit.

[0124] Please refer toFigure 12 , Figure 12 This is a flowchart of the steps of a control method for a hardware Trojan trigger circuit based on aging effects provided in the second embodiment of the present application.

[0125] A control method for a hardware Trojan trigger circuit based on aging effects provided by the present invention is applied to the above-mentioned hardware Trojan trigger circuit based on aging effects, and includes:

[0126] Step 1201: When the ring oscillator circuit in the hardware Trojan trigger circuit based on aging effects generates a target control signal, a square wave signal, and a second delayed square wave signal, generate a first delayed square wave signal based on the target control signal or the square wave signal.

[0127] Step 1202: Perform a logical operation on the square wave signal, the second delayed square wave signal, and the first delayed square wave signal, and output a target composite square wave signal.

[0128] Step 1203: Generate a voltage signal based on the target composite square wave signal.

[0129] Step 1204: Generate a target trigger signal according to the square wave signal and the voltage signal.

[0130] In the embodiment of the present invention, the present invention provides a control method for a hardware Trojan trigger circuit based on aging effects. When the ring oscillator circuit in the hardware Trojan trigger circuit based on aging effects generates a target control signal, a square wave signal, and a second delayed square wave signal, a first delayed square wave signal is generated based on the target control signal or the square wave signal; a logical operation is performed on the square wave signal, the second delayed square wave signal, and the first delayed square wave signal, and a target composite square wave signal is output; a voltage signal is generated based on the target composite square wave signal; a target trigger signal is generated according to the square wave signal and the voltage signal; based on the above solution, in the process of generating a target control signal, a square wave signal, and a second delayed square wave signal by the ring oscillator circuit and processing the generated signals to output a target trigger signal, the present invention uses the ring oscillator as the internal drive signal of the hardware Trojan trigger circuit, does not need to rely on an external drive signal, can be directly implanted into any type of normal circuit without modifying the internal signals of the normal circuit, and improves the reliability of the hardware Trojan trigger circuit.

[0131] The embodiment of the present invention also provides a computer device, including a memory and a processor, and a computer program is stored in the memory; when the computer program is executed by the processor, the processor executes the steps of the control method for the hardware Trojan trigger circuit based on aging effects in the second embodiment as described above.

[0132] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program / instructions are stored. When the computer program / instructions are executed by a processor, the steps of the control method of the hardware Trojan trigger circuit based on the aging effect in the above-mentioned Embodiment 2 are implemented.

[0133] An embodiment of the present invention further provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the control method of the hardware Trojan trigger circuit based on the aging effect in the above-mentioned Embodiment 2 are implemented.

[0134] As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hardware Trojan trigger circuit based on the aging effect, characterized in that The circuit includes a ring oscillator circuit, a duty cycle adjustment circuit, a delay selection circuit, an NBTI aging circuit, and a D flip-flop circuit; The ring oscillator circuit is respectively connected to the duty cycle adjustment circuit and the delay selection circuit; The duty cycle adjustment circuit is connected to the delay selection circuit; The NBTI aging circuit is respectively connected to the duty cycle adjustment circuit and the D flip-flop circuit; The D flip-flop circuit is connected to the ring oscillator circuit; The ring oscillator circuit is used to generate a target control signal, a square wave signal, and a second delayed square wave signal; The delay selection circuit is used to generate a first delayed square wave signal based on the target control signal or the square wave signal transmitted by the ring oscillator circuit; The duty cycle adjustment circuit is used to perform a logical operation on the square wave signal transmitted by the ring oscillator circuit, the second delayed square wave signal, and the first delayed square wave signal transmitted by the delay selection circuit, output a target composite square wave signal, and transmit it to the NBTI aging circuit; The NBTI aging circuit is used to generate a voltage signal according to the target composite square wave signal; The D flip-flop circuit is used to generate a target trigger signal according to the square wave signal transmitted by the ring oscillator circuit and the voltage signal transmitted by the NBTI aging circuit.

2. The hardware Trojan trigger circuit based on the aging effect according to claim 1, wherein The ring oscillator circuit includes an odd number of cascaded inverters.

3. The hardware Trojan trigger circuit based on the aging effect according to claim 1, wherein The target composite square wave signal includes a first composite square wave signal and a second composite square wave signal; the duty cycle adjustment circuit includes an AND gate and an OR gate; The first input terminal of the AND gate is connected to the first output terminal of the ring oscillator circuit, and the second input terminal of the AND gate is connected to the signal output terminal of the delay selection circuit; The first input terminal of the OR gate is connected to the first output terminal of the ring oscillator circuit, and the second input terminal of the OR gate is connected to the second output terminal of the ring oscillator circuit; The output terminals of the AND gate and the OR gate are both connected to the NBTI aging circuit; The AND gate is used to perform an AND operation on the square wave signal transmitted by the ring oscillator circuit and the first delayed square wave signal transmitted by the delay selection circuit, and output a first composite square wave signal; The OR gate is used to perform an OR operation on the square wave signal and the second delayed square wave signal transmitted by the ring oscillator circuit, and output a second composite square wave signal.

4. The hardware Trojan trigger circuit based on the aging effect according to claim 1, wherein, The delay selection circuit includes three switches, and all three switches are composed of a series-connected transmission gate and an inverter; The signal input terminal of the transmission gate of the first switch is connected to the third output terminal of the ring oscillator circuit, and the signal output terminal of the transmission gate of the first switch is connected to the second input terminal of the AND gate; The signal input terminal of the transmission gate of the second switch is connected to the fourth output terminal of the ring oscillator circuit, and the signal output terminal of the transmission gate of the second switch is connected to the second input terminal of the AND gate; The signal input terminal of the transmission gate of the third switch is connected to the first output terminal of the ring oscillator circuit, and the signal output terminal of the transmission gate of the third switch is connected to the second input terminal of the AND gate.

5. The hardware Trojan trigger circuit based on the aging effect according to claim 4, characterized in that, The target control signal includes a first control signal and a second control signal; The first switch is configured to generate a first delayed square wave signal according to a first control signal transmitted by the ring oscillator circuit when the control input terminal of the transmission gate of the first switch is at a high level, and the control input terminals of the transmission gates of the second switch and the third switch are at low levels; The second switch is configured to generate a first delayed square wave signal according to a second control signal transmitted by the ring oscillator circuit when the control input terminal of the transmission gate of the second switch is at a high level, and the control input terminals of the transmission gates of the first switch and the third switch are at low levels; The third switch is configured to generate a first delayed square wave signal according to a square wave signal transmitted by the ring oscillator circuit when the control input terminal of the transmission gate of the third switch is at a high level, and the control input terminals of the transmission gates of the first switch and the second switch are at low levels.

6. The hardware Trojan trigger circuit based on the aging effect according to claim 3, wherein The NBTI aging circuit includes a power supply terminal, a ground terminal, two P-channel metal-oxide-semiconductor field-effect transistors, and two N-channel metal-oxide-semiconductor field-effect transistors; The power supply terminal is connected to the source electrode of the first P-channel metal-oxide-semiconductor field-effect transistor; The output terminal of the AND gate is respectively connected to the gate electrode of the first P-channel metal-oxide-semiconductor field-effect transistor and the gate electrode of the second P-channel metal-oxide-semiconductor field-effect transistor; The drain electrode of the first P-channel metal-oxide-semiconductor field-effect transistor is connected to the source electrode of the second P-channel metal-oxide-semiconductor field-effect transistor; The drain electrode of the second P-channel metal-oxide-semiconductor field-effect transistor is connected to the drain electrode of the first N-channel metal-oxide-semiconductor field-effect transistor; The output terminal of the OR gate is respectively connected to the gate electrode of the first N-channel metal-oxide-semiconductor field-effect transistor and the gate electrode of the second N-channel metal-oxide-semiconductor field-effect transistor; The source electrode of the first N-channel metal-oxide-semiconductor field-effect transistor is connected to the drain electrode of the second N-channel metal-oxide-semiconductor field-effect transistor; The source electrode of the second N-channel metal-oxide-semiconductor field-effect transistor is connected to the ground terminal; The input terminal of the D flip-flop circuit is connected between the drain electrode of the second P-channel metal-oxide-semiconductor field-effect transistor and the drain electrode of the first N-channel metal-oxide-semiconductor field-effect transistor.

7. A control method for a hardware Trojan trigger circuit based on aging effect, characterized in that, Applied to the hardware Trojan trigger circuit based on the aging effect according to any one of claims 1 to 9, the method includes: When the ring oscillator circuit in the hardware Trojan trigger circuit based on the aging effect generates a target control signal, a square wave signal, and a second delayed square wave signal, generating a first delayed square wave signal based on the target control signal or the square wave signal; Performing a logical operation on the square wave signal, the second delayed square wave signal, and the first delayed square wave signal, and outputting a target synthesized square wave signal; Generating a voltage signal based on the target synthesized square wave signal; Generating a target trigger signal according to the square wave signal and the voltage signal.

8. A computer device, characterized in that, It includes a memory and a processor. A computer program is stored in the memory. When the computer program is executed by the processor, the processor is caused to execute the steps of the control method of the hardware Trojan trigger circuit based on the aging effect according to any one of claim 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the control method of the hardware Trojan trigger circuit based on the aging effect according to any one of claim 7.

10. A computer program product, characterized in that, The computer program product includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. Wherein, when the program instructions are executed by a computer, the computer is caused to execute the control method of the hardware Trojan trigger circuit based on the aging effect according to any one of claim 7.

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