Clock tree generation and optimization method for quickly realizing time sequence convergence

Abstract

The invention belongs to the field of digital integrated chips, particularly relates to a clock tree generation and optimization method for quickly realizing time sequence convergence, and aims to solve the problems that an existing clock tree does not completely optimize a time sequence violation path and is difficult to realize quick time sequence convergence. The method comprises the following steps: carrying out logic synthesis on RTL codes to obtain a time sequence convergence netlist after logic synthesis; performing chip layout planning and hardware unit placement based on the time sequence convergence netlist; performing clock tree generation and clock tree comprehensive optimization on the chip with the hardware unit to obtain to-be-wired chip data with time sequence convergence; and based on the to-be-wired chip data, wiring of the to-be-wired chip is carried out according to preset parameters, and static time sequence analysis is carried out. According to the method, the frequency index of the chip is effectively optimized by combining an EDA tool, manually adjusting the clock tree structure and guiding the file, the number of iterations in the clock tree generation process and the time sequence optimization process after the clock tree generation process can be reduced, and the method is effective, reliable, convenient and practical.

Description

Technical Field

[0001] The present invention belongs to the field of digital integrated chips, and in particular relates to a clock tree generation and optimization method for rapidly achieving timing closure. Background Art

[0002] With the continuous advancement of integrated circuit technology, the continuous reduction of chip feature sizes and the continuous improvement of integration, the physical design of integrated circuits has become increasingly complex, and higher requirements have been placed on design methods. Traditional clock tree synthesis (CTS) solutions are increasingly unable to meet the chip's requirements for clock signals.

[0003] While current mainstream automatic place-and-route tools all feature clock skew optimization, they still have drawbacks in practical applications. This is primarily due to the fact that after timing optimization, significant timing margins remain unused in the preceding or subsequent stages of the critical path. Timing optimization can be achieved by manually obtaining and properly allocating timing margins. This essentially involves taking some excess time from non-critical paths and assigning it to the critical path to resolve timing violations. Therefore, effectively leveraging external methods to achieve rapid timing closure, based on traditional clock tree synthesis solutions, is a crucial issue that needs to be addressed in engineering practice. Summary of the Invention

[0004] To address the aforementioned problem in the prior art, namely, the problem that existing clock tree generation and optimization methods do not fully optimize the timing violation paths to achieve rapid timing closure, the present invention provides a clock tree generation and optimization method for rapidly achieving timing closure, specifically comprising:

[0005] Step S1, performing logic synthesis on the RTL code to obtain a timing-closed netlist after logic synthesis;

[0006] Step S2, performing chip layout planning and hardware unit placement based on the timing-closed netlist after logic synthesis;

[0007] Step S3, performing clock tree generation and clock tree comprehensive optimization on the chip where the hardware unit is placed, and obtaining chip data to be routed that meets timing requirements after clock tree comprehensive optimization is completed;

[0008] Step S4: Based on the chip data to be routed, routing is performed according to preset parameters, and static timing analysis is performed iteratively on the routed chip until timing convergence.

[0009] Furthermore, the method for obtaining the timing-closed netlist after logic synthesis includes:

[0010] Perform timing analysis on the netlist after logic synthesis to determine whether there are timing violations or insufficient margins;

[0011] If there is a timing violation or insufficient margin, logical synthesis is performed again through logic restructuring or module regrouping until there is no timing violation or insufficient margin during the next timing analysis.

[0012] Furthermore, step S2 specifically includes:

[0013] Place a Clock Anchor unit at the physical center position of the chip;

[0014] Reserve placement space for Std cells after placing Macro cells;

[0015] Place timing units, power consumption optimization units, and driver units;

[0016] Furthermore, after performing clock tree synthesis optimization, it also includes performing timing convergence verification on the netlist after clock tree synthesis optimization. The method is as follows:

[0017] Perform timing analysis to determine whether the netlist after clock tree synthesis optimization meets the preset timing constraint requirements;

[0018] If it does not meet the preset timing constraint requirements, perform timing repair through manual clock skew optimization measures.

[0019] Furthermore, performing timing optimization on the netlist after clock tree synthesis optimization includes:

[0020] According to the timing information of the critical path, search for the timing margin of the pre-stage path or the post-stage path of the critical path, and by adjusting the path delay of the critical path Lanuch Path or Capture Path, call the timing margin of the non-critical timing path to the critical timing path.

[0021] Furthermore, the static timing analysis includes signal integrity analysis and violation path analysis.

[0022] Furthermore, if the result of the static timing analysis is abnormal, perform repair by adjusting the wiring layer, wiring layer spacing, or adjusting the type and size of the driver unit.

[0023] Furthermore, after the static timing analysis, it includes physical verification and Signoff process.

[0024] Furthermore, the clock tree synthesis optimization optimizes the timing through the EDA tool using Useful Skew.

[0025] Furthermore, the clock tree generation is executed through a CTS engine.

[0026] Advantages of the present invention:

[0027] (1) Based on the traditional clock tree generation method, the present invention realizes rapid timing convergence, further explores the potential of the tool in timing convergence, provides a practical solution for shortening the development cycle and improving chip performance, and has important application value in engineering practice;

[0028] (2) The present invention effectively optimizes the frequency index of the chip by combining EDA tools, manual adjustment of the clock tree structure, and the clock tree synthesis guidance file, solves the timing violation paths that are not fully optimized by the tool, achieves the purpose of rapid timing convergence, and can reduce the number of iterations in the clock tree generation and subsequent timing optimization processes. It is an effective, reliable, convenient, and practical design method.

[0029] (3) This method intervenes starting from the logic synthesis stage. By pre-placing ClockAnchor units in the Floorplan stage, based on the traditional clock tree design process, it reasonably utilizes the self-optimization ability of EDA tools, and through manual adjustment of the clock tree structure and the clock tree synthesis guidance file, solves the violation paths that are not fully optimized by the EDA tool, achieving the purpose of rapid timing convergence. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objectives, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings:

[0031] Figure 1 is a flow schematic diagram of a clock tree generation and optimization method for rapidly achieving timing convergence according to the present invention;

[0032] Figure 2 is a digital backend design flow chart of a clock tree generation and optimization method for rapidly achieving timing convergence according to the present invention;

[0033] Figure 3 is a schematic diagram of logic reconstruction in a clock tree generation and optimization method for rapidly achieving timing convergence according to the present invention;

[0034] Figure 4 is a schematic diagram of pre-placing ClockAnchor units in a clock tree generation and optimization method for rapidly achieving timing convergence according to the present invention;

[0035] Figure 5 is a schematic diagram of reducing the impact of OCV in a clock tree generation and optimization method for rapidly achieving timing convergence according to the present invention;

[0036] Figure 6 is a schematic diagram of optimizing timing using clock useful skew in a clock tree generation and optimization method for rapidly achieving timing convergence according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. Additionally, it should be noted that for ease of description, only parts related to the relevant invention are shown in the drawings.

[0038] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0039] For a clearer description of a method for generating and optimizing a clock tree for quickly achieving timing convergence in the present invention, the following combines Figure 1 and Figure 2 to elaborate on each step in the embodiments of the present invention.

[0040] Step S1: Perform logic synthesis on the RTL code to obtain a timing convergence netlist after logic synthesis.

[0041] In this embodiment, the method for obtaining the timing convergence netlist after logic synthesis includes:

[0042] Perform timing analysis on the netlist after logic synthesis to determine whether there are timing violations or insufficient margins.

[0043] If there are timing violations or insufficient margins, re - perform logic synthesis through logic restructuring or module regrouping until there are no timing violations or insufficient margins during the next timing analysis.

[0044] Maximize the optimization of timing through measures such as logic restructuring or module regrouping, increase the timing margin at this stage, and perform placement and planning after meeting the timing requirements. The process of performing logic restructuring is as Figure 3 shown.

[0045] Since the timing violations of Setup deteriorate more and more as the placement and routing stage progresses, the netlist can be optimized through methods such as logic restructuring or module regrouping during the logic synthesis stage to maximize the Setup margin at this stage. Logic restructuring can be performed through methods such as Retiming, Pipeline, or module regrouping, or incremental compilation can be performed using DCT (combined with MCMM). The DEF file of the Floorplan is exported by the automatic placement and routing tool to DCT, and then compile_ultra is used for re - synthesis. If the problem of timing violations still cannot be solved, optimize the circuit structure or algorithm.

[0046] Step S2: Based on the timing convergence netlist after logic synthesis, perform placement and planning of the chip and place hardware units.

[0047] In this embodiment, step S2 specifically includes:

[0048] As Figure 4 shown, place the Clock Anchor unit at the physical center position of the chip;

[0049] Arranging the Clock Anchor unit includes placing independent Clock Anchor units for each Module in the clock domain;

[0050] In the layout planning stage, the rationality of the Floorplan directly affects whether the timing can converge or converge quickly. The schematic diagram of the principle affected by OCV is as Figure 5 shown. Therefore, in this stage, it is planned strictly according to the data flow and combined with the shape characteristics of the chip.

[0051] Reserve the placement space for Std cells after placing the Macro cells;

[0052] Place timing units, power consumption optimization units, and driver units;

[0053] Place the Macro and registers with signal interaction close to each other within the range where the signals do not interfere, and reserve space in the Macro area for subsequent timing optimization and repair. The placement of the Macro will affect the placement position of the Std Cell, thus affecting the length of the Common Path in the clock path. Therefore, when placing the Macro, the interaction problem with the relevant Stdcell should be fully considered, and a certain space should be left for Std cell placement and subsequent timing optimization.

[0054] When selecting the clock Clock Anchor unit, preferably select the dedicated clock tree inverter unit CKIN with a larger driving ability.

[0055] Step S3: Generate a clock tree and perform comprehensive optimization of the clock tree for the chip with the hardware units placed, to obtain the data of the to-be-routed chip that meets the timing requirements after the comprehensive optimization of the clock tree.

[0056] In this embodiment, for the comprehensive optimization of the clock tree, the timing is optimized by using the useful clock skew UsefulSkew through an EDA tool. The clock tree synthesis is executed by a CTS engine. In the placement of standard cells, clock tree synthesis, routing, and optimization at each stage, the tool can be enabled to use the useful clock skew UsefulSkew for timing optimization according to the timing results. After the comprehensive optimization of the clock tree, it is decided whether to use manual clock skew optimization measures according to the optimized timing analysis results. The principle of optimizing the timing by using the useful clock skew is as Figure 6 shown.

[0057] In this embodiment, after clock tree synthesis optimization, it further includes performing timing convergence verification on the netlist after clock tree synthesis optimization. The method is as follows:

[0058] Perform timing analysis to determine whether the netlist after clock tree synthesis optimization meets the preset timing constraint requirements;

[0059] If it does not meet the preset timing constraint requirements, perform timing repair through manual clock skew optimization measures.

[0060] In this embodiment, performing timing optimization on the netlist after clock tree synthesis optimization includes:

[0061] According to the timing information of the critical path, search for the timing slack of the previous path or the subsequent path of the critical path, and by adjusting the path delay of the critical path Lanuch Path or Capture Path, call the timing slack of the non-critical timing path to the critical timing path.

[0062] As Figure 6 shown, the setup time timing slack of the DFF3 register is -1ns. It can be seen that the skew related to this path is t3 - t2 = -1ns. At this time, the clock delay of the clock port of the DFF2 register can be adjusted, and 1ns of time can be borrowed from the path with a relatively abundant Slack in front (such as the Slack of the DFF2 register = 2ns) using the effective clock skew, so that the timing of both paths meets the requirements.

[0063] Step S4: Perform routing based on the data of the to-be-routed chip according to the preset parameters, and iteratively perform static timing analysis on the routed chip until timing convergence.

[0064] After clock tree generation, synthesis optimization, and timing repair are completed, detailed routing is performed. Relevant parameter settings need to be performed before routing, including multi-via holes, routing layers, and units specifying antenna effect repair, etc. After parameter settings are completed, detailed routing is performed. After routing is completed, measures such as adding Metal Fill also need to be completed according to manufacturability requirements.

[0065] In this embodiment, the static timing analysis includes signal integrity analysis and violation path analysis.

[0066] In this embodiment, if the result of the static timing analysis is abnormal, repair is performed by adjusting the routing layer, routing layer spacing, or adjusting the type and size of the driving unit.

[0067] In this embodiment, after the static timing analysis, it includes physical verification and Signoff process.

[0068] In the above embodiments, although the various steps are described in the above order, those skilled in the art can understand that, in order to achieve the effects of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reversed order, and these simple changes are all within the protection scope of the present invention.

[0069] The terms "first", "second", etc. are used to distinguish similar objects, rather than to describe or represent a specific order or sequence.

[0070] The term "comprising" or any other similar term is intended to cover non-exclusive inclusion, so that a process, method, article, or apparatus / device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent in these processes, methods, articles, or apparatus / device.

[0071] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, those skilled in the art can easily understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of the present invention.

Claims

1. A clock tree generation and optimization method for quickly achieving timing convergence, characterized in that The method includes: Step S1: Perform logic synthesis on the RTL code to obtain a timing - convergent netlist after logic synthesis; Step S2: Based on the timing - convergent netlist after logic synthesis, perform layout planning and hardware unit placement of the chip; Step S3: Generate a clock tree and perform clock tree synthesis optimization on the chip with hardware units placed, to obtain the data of the chip to be routed that meets the timing requirements after completing clock tree synthesis optimization; Step S4: Based on the data of the chip to be routed, perform routing according to pre - set parameters, and iteratively perform static timing analysis on the routed chip until timing convergence.

2. The clock tree generation and optimization method for quickly achieving timing convergence according to claim 1, wherein, The method for obtaining the timing - convergent netlist after logic synthesis includes: Perform timing analysis on the netlist after logic synthesis to determine whether there are timing violations or insufficient margins; If there are timing violations or insufficient margins, re - perform logic synthesis through logic restructuring or module regrouping until there are no timing violations or insufficient margins during the next timing analysis.

3. The clock tree generation and optimization method for quickly achieving timing convergence according to claim 1, characterized in that The specific content of step S2 includes: Place the Clock Anchor unit at the physical center position of the chip; Reserve the placement space for Std cells after placing Macro units; Place timing units, power - consumption optimization units, and driver units.

4. The method for generating and optimizing a clock tree for quickly achieving timing convergence according to claim 1, wherein After performing clock tree synthesis optimization, it also includes performing timing convergence verification on the netlist after clock tree synthesis optimization. The method is: Perform timing analysis to determine whether the netlist after clock tree synthesis optimization meets the pre - set timing constraint requirements; If it does not meet the pre - set timing constraint requirements, perform timing repair through manual clock skew optimization measures.

5. The clock tree generation and optimization method for quickly achieving timing convergence according to claim 4, characterized in that, The timing optimization for the netlist after clock tree synthesis optimization includes: According to the timing information of the critical path, search for the timing margin of the pre - stage path or the timing margin of the post - stage path of the critical path, and by adjusting the path delay of the critical path Lanuch Path or Capture Path, transfer the timing margin of the non - critical timing path to the critical timing path.

6. The clock tree generation and optimization method for quickly achieving timing convergence according to claim 1, characterized in that, The static timing analysis includes signal integrity analysis and violation path analysis.

7. The method for generating and optimizing a clock tree for quickly achieving timing convergence according to claim 6, characterized in that, If the result of the static timing analysis is abnormal, perform repair by adjusting the routing layer, routing layer spacing, or adjusting the type and size of the driver unit.

8. The method for generating and optimizing a clock tree for quickly achieving timing convergence according to claim 1, wherein, After the static timing analysis, it includes physical verification and Signoff process.

9. The clock tree generation and optimization method for quickly achieving timing convergence according to claim 1, characterized in that The clock tree synthesis optimization uses Useful Skew in the EDA tool to optimize the timing.

10. The clock tree generation and optimization method for quickly achieving timing convergence according to claim 1, characterized in that The clock tree generation is executed by the CTS engine.

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