System-on-chip address allocation verification method and device, equipment and medium

Abstract

The invention discloses a system-on-chip address allocation verification method, device and equipment and a medium, and relates to the technical field of chip design, and the method comprises the steps: reading address allocation summary information of a system-on-chip; generating an address macro definition file, an address access case and a function coverage rate according to the read address allocation summary information; and integrating the address macro definition file, the address access case and the function coverage rate into a preset verification environment to complete verification of address allocation of the system on chip. Therefore, automatic verification of address allocation of the system on chip can be realized, and the verification efficiency and verification accuracy of address access are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a method, device, equipment and medium for verifying on-chip system address allocation. Background Art

[0002] Integrated circuits are developing rapidly. Since the proposal of Moore's Law, the number of transistors that can be accommodated on an integrated circuit has continued to increase in iterations. With the improvement of manufacturing technology and the diversification of market demands, the scale and complexity of integrated circuit design have become increasingly complex, and the cost of tape-out has been rising steadily, making design and verification work increasingly important. The verification of SOC (System on Chip) chips needs to take into account the following aspects: ensuring functional correctness, improving product quality, reducing risks, optimizing performance, security checks, compatibility tests, meeting industry standards, accelerating time to market, reducing development costs, supporting complex designs, promoting continuous improvement, etc. In the initial stage of chip R & D, digital verification accounts for up to 60% - 70% of the entire project's design phase.

[0003] With the continuous increase in the scale of integrated circuits, the requirements and challenges for verification are also continuously increasing. While improving the quality of product verification, it is also necessary to shorten the verification cycle as much as possible. Even with great effort, things like verification loopholes or errors leading to the loss of integrated circuit functions still occur from time to time. How to ensure the completeness, efficiency and reusability of digital verification has become a key point in current chip verification. The solutions to this key point include two aspects of improvement. On the one hand, the improvement of verification tools can increase verification detection means and adapt to higher integration levels. On the other hand, continuous progress has been made in verification methods and strategies to adapt to more complex and high-performance design requirements.

[0004] The address allocation of SOC chips has the characteristics of a large number, simple structure, strong repeatability and iteration in the chip design process. The repeatability mainly refers to the simple structure. For example, the address repeatability of a single domain segment is strong; as the chip design gradually matures, the repeated iteration of address allocation is inevitable. The verification of SOC chip address allocation is a key process. For the key points and characteristics of address allocation, the verification must ensure that each module or peripheral in the system is correctly mapped to memory and there are no address conflicts.

[0005] Obviously, how to verify the address allocation of SOC chips is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of the embodiments of the present invention is to provide a method, device, equipment and medium for verifying the address allocation of a system-on-chip, which can realize the automatic verification of the address allocation of the system-on-chip and significantly improve the verification efficiency and accuracy of address access. The specific scheme is as follows:

[0007] In the first aspect, the present invention provides a method for verifying the address allocation of a system-on-chip, including:

[0008] Reading the address allocation summary information of the system-on-chip;

[0009] Generating an address macro definition file, address access test cases and functional coverage according to the read address allocation summary information;

[0010] Integrating the address macro definition file, address access test cases and functional coverage into a preset verification environment to complete the verification of the address allocation of the system-on-chip.

[0011] Optionally, before reading the address allocation summary information of the system-on-chip, it further includes:

[0012] Determining a summary standard based on the subsystem name of the system-on-chip, the address space module name of the subsystem, the start address of the address space module, the end address of the address space module, the address space size and the address type;

[0013] Summarizing the address allocation access information of the system-on-chip according to the summary standard to obtain the address allocation summary information.

[0014] Optionally, generating an address macro definition file, address access test cases and functional coverage according to the read address allocation summary information includes:

[0015] Judging whether the current verification is for the address allocation verification of the overall system-on-chip components, and obtaining the corresponding judgment result;

[0016] Generating an address macro definition file, address access test cases and functional coverage according to the judgment result and the read address allocation summary information.

[0017] Optionally, generating an address macro definition file, address access test cases and functional coverage according to the judgment result and the read address allocation summary information includes:

[0018] If the current verification is for the address allocation verification of the overall system-on-chip components, then generating C code-based address access test cases for the system-on-chip components, a C code-based address macro definition file for the system-on-chip components and the functional coverage of the system-on-chip according to the read address allocation summary information;

[0019] If the current verification is not a verification of the address assignment for the overall system-on-chip components, then determine whether the current verification is a verification of the address assignment for a single subsystem component of the system-on-chip;

[0020] If the current verification is a verification of the address assignment for a single subsystem component of the system-on-chip, then generate an address access test case based on SV code, an address macro definition file based on SV code, and the functional coverage rate of the target subsystem according to the read address assignment summary information; the target subsystem is any subsystem of the system-on-chip;

[0021] If the current verification is not a verification of the address assignment for a single subsystem component of the system-on-chip, then generate an address access test case based on SV code, an address macro definition file based on SV code, and the functional coverage rate for all subsystems of the system-on-chip.

[0022] Optionally, the process of generating an address macro definition file according to the read address assignment summary information includes:

[0023] Generate an address macro definition file based on C code according to the start address of the address space module, the end address of the address space module, and the address space size in the read address assignment summary information;

[0024] Generate an address macro definition file based on SV code according to the start address of the address space module, the end address of the address space module, the address space size, and the address type in the read address assignment summary information.

[0025] Optionally, the process of generating an address access test case according to the read address assignment summary information includes:

[0026] Judge the type of the address access test case;

[0027] If the address access test case is an address access test case based on C code, then generate an address access test case based on C code according to the start address of the address space module and the end address of the address space module in the read address assignment summary information;

[0028] If the address access test case is an address access test case based on SV code, then generate an address access test case based on SV code according to the name of the address space module of the subsystem, the start address of the address space module, the end address of the address space module, the address space size, and the address type in the read address assignment summary information.

[0029] Optionally, the process of generating the functional coverage rate according to the read address assignment summary information includes:

[0030] Determine the cover group, cover point and bin of each address space module according to the start address and end address of the address space module in the read address allocation summary information;

[0031] Instantiate the cover groups of all address space modules to obtain instantiated cover groups;

[0032] Several instantiated covergroups are sampled in parallel based on coverpoints and bins to generate functional coverage.

[0033] In a second aspect, the present invention provides a system on chip address allocation verification device, comprising:

[0034] A summary information reading module is used to read the address allocation summary information of the system on chip;

[0035] A generation module is used to generate an address macro definition file, address access use cases, and function coverage based on the read address allocation summary information;

[0036] An integration module for integrating address macro definition files, address access use cases, and functional coverage into a preset verification environment to complete the verification of address allocation for the system-on-chip.

[0037] In a third aspect, the present invention provides an electronic device, comprising:

[0038] memory for storing computer programs;

[0039] The processor is configured to execute a computer program to implement the above-mentioned system-on-chip address allocation verification method.

[0040] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the aforementioned system-on-chip address allocation verification method when executed by a processor.

[0041] In the present invention, the address allocation summary information of the on-chip system is first read; then the address macro definition file, address access use case and function coverage are generated according to the read address allocation summary information; finally, the address macro definition file, address access use case and function coverage are integrated into a preset verification environment to complete the verification of the address allocation of the on-chip system.

[0042] Beneficial effects: The present invention first summarizes the address allocation of the system-on-chip, and then reads the summarized information of the address allocation to automatically generate verification components such as address macro definition files, address access test cases, and functional coverage. In this way, the automatically generated verification components can cover all application scenarios, eliminate errors or omissions caused by manual writing, and improve the accuracy rate. At the same time, it can greatly reduce the waiting time cost of project verification nodes. And because the time cost of manually writing verification components is greatly reduced, it also eliminates human errors in manual writing and reduces the time for repeated simulations; it significantly improves the work efficiency and accuracy of verification. Description of the Drawings

[0043] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0044] Figure 1 Flowchart of a method for verifying system-on-chip address allocation provided by an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of an address allocation provided by an embodiment of the present invention;

[0046] Figure 3 Schematic diagram of the implementation principle of a method for verifying system-on-chip address allocation provided by an embodiment of the present invention;

[0047] Figure 4 Schematic diagram of a macro definition pseudocode provided by an embodiment of the present invention;

[0048] Figure 5 Schematic diagram of the C code structure of an address access test case provided by an embodiment of the present invention;

[0049] Figure 6 Schematic diagram of the C code structure of an address access test case provided by an embodiment of the present invention;

[0050] Figure 7 Schematic diagram of generating functional coverage code provided by an embodiment of the present invention;

[0051] Figure 8 Schematic diagram of generating functional coverage code provided by an embodiment of the present invention;

[0052] Figure 9 Schematic diagram of the structure of a device for verifying system-on-chip address allocation provided by an embodiment of the present invention;

[0053] Figure 10A structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0054] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0055] The terms "include" and "have" in the specification of the present invention and the accompanying drawings above, as well as any variations related to "include" and "have", are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0056] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0057] The traditional method for verifying the address allocation of an SOC chip is to manually write test components. If there are handwritten errors, simulation debugging and modification are required. And during the development iteration and modification process, for the iteration modification of fixed addresses without accurate boundary access, the meaning of verifying the addresses is lost. To solve the defects of the above technical problems, the present invention discloses a method, device, equipment and medium for verifying the address allocation of a system on a chip, which can realize the automatic verification of the address allocation of the system on a chip, and significantly improve the verification efficiency and verification accuracy of address access.

[0058] See Figure 1 As shown, an embodiment of the present invention provides a method for verifying the address allocation of a system on a chip, including:

[0059] Step S11, reading the summary information of the address allocation of the system on a chip.

[0060] In the embodiment of the present invention, before reading the address allocation summary information of the system-on-chip, first determine the summary criteria based on the subsystem name of the system-on-chip, the address space module name of the subsystem, the start address of the address space module, the end address of the address space module, the address space size, and the address type; summarize the address allocation access information of the system-on-chip according to the summary criteria to obtain the address allocation summary information. In a specific embodiment, based on the traditional verification method, and aiming at the digital verification characteristics of the address allocation of the above SOC chip, combined with the general content of the address allocation table, it can be summarized into a table with a fixed format of address allocation, which includes addresses in units of 32 bits and the address types are classified and labeled. Specifically, it is necessary to input the address allocation access information of the SOC into a table with a fixed format, such as Figure 2 shown. The naming is divided into two levels. The first level is the subsystem level, and the second level is the first-level sub-module. Its space size, start address, and end address are all in hexadecimal for the convenience of calculation and code reading and writing configuration. Since the CPU (Central Processing Unit) access address is limited, this table only requires 64-bit addresses. The type includes ROM (Read-Only Memory), RAM (Random Access Memory), FLASH, peripheral addresses, configuration space (CFG, Configuration), reserved addresses, and virtual address mapping, etc. For different address types, the access prerequisites, access methods, and inspection methods are also different. In this way, the present invention only requires the verification personnel to summarize a table of address allocation summary in a fixed format according to the standard file given by the architecture, and does not need to care much about whether the test code is implemented and released, and can generate the verification component code required for verification within a few minutes. And taking into account the iterative modification of the architecture, the verification personnel only need to iteratively refresh the summary table, reducing the workload of iterative modification of use cases and repeated modification due to address boundary offset.

[0061] Step S12: Generate an address macro definition file, an address access use case, and a functional coverage rate according to the read address allocation summary information.

[0062] In the embodiment of the present invention, after reading the address allocation summary information, or after grabbing the table content, as Figure 3 shown, first determine whether the current verification is for the address allocation verification of the overall system-on-chip components, and obtain the corresponding judgment result; generate an address macro definition file, an address access use case, and a functional coverage rate according to the judgment result and the read address allocation summary information. Different verifications generate different types of code. Before verification, it can be determined whether to verify the SOC components according to the selection of the verification personnel.

[0063] In the embodiments of the present invention, in the process of generating the address macro definition file, the address access use case, and the functional coverage rate, if the current verification is for the verification of the address allocation of the overall on-chip system components, then based on the read address allocation summary information, generate the address access use case based on C code, the address macro definition file based on C code, and the functional coverage rate of the on-chip system for the on-chip system components; if the current verification is not for the verification of the address allocation of the overall on-chip system components, then determine whether the current verification is for the verification of the address allocation of a single subsystem component of the on-chip system; if the current verification is for the verification of the address allocation of a single subsystem component of the on-chip system, then based on the read address allocation summary information, generate the address access use case based on SV (SystemVerilog) code, the address macro definition file based on SV code, and the functional coverage rate of the target subsystem; the target subsystem is any subsystem of the on-chip system; if the current verification is not for the verification of the address allocation of a single subsystem component of the on-chip system, then generate the address access use case based on SV code, the address macro definition file based on SV code, and the functional coverage rate for all subsystems of the on-chip system.

[0064] Specifically, in the process of generating the address macro definition file based on the read address allocation summary information, the present invention generates the address macro definition file based on C code according to the start address, end address, and address space size of the address space module in the read address allocation summary information; generates the address macro definition file based on SV code according to the start address, end address, address space size, and address type of the address space module in the read address allocation summary information. The present invention automatically generates the address macro definition files of C code and SV code. Here, the content of the address macro definition file of C code is mainly described. The main content is as Figure 4 shown. Since the address macro definition file of SV code is similar to this basic principle, it will not be described in detail here. Figure 4 mainly describes the memory address space division scheme of the hardware system, which mainly includes three parts: the start address, middle address, and end address of the LMU0_ROM storage area; the start address, middle address, and end address of the LMU0_RSD storage area, and the start address, middle address, and end address of the PCIE (peripheral component interconnect express) prefetch space.

[0065] In addition, traditional test cases are written manually. During the regular writing process, it is necessary to manually search for and add the address access boundary addresses of each address space module, including the start address and end address of the address space module. After the address configuration is determined, it is necessary to configure the access data required for verification according to different address space modules. However, the present invention will automatically capture the start address and end address of each address space module according to the content of the summarized address allocation table. The representative data for the access data used are 0x00000000, 0x5A5A5A5A, and 0xFFFFFFFF. Data flipping is performed on each bit of the access address to achieve the purpose of 32-bit address allocation testing. Therefore, during the process of generating address access test cases based on the read address allocation summary information, the present invention determines the type of the address access test case. If the address access test case is a C-code-based address access test case, a C-code-based address access test case is generated according to the start address of the address space module and the end address of the address space module in the read address allocation summary information. Since the verification process of SOC address access mainly verifies that its access path is not hung up and there are no error reports, before the start code of a single address space access, the corresponding module and address size are commented. After the access operation is completed, the completion status flag is printed. This is beneficial for both test case inspection and locating inaccessible address boundaries during the simulation process. At the same time, the present invention generates SV-language address access test cases mainly according to the content of the summarized address allocation table. The main table information captured includes: the name of the corresponding address space module, the start address of the module, the end address of the module, the address space size, and the address type. That is to say, if the address access test case is an SV-code-based address access test case, an SV-code-based address access test case is generated according to the name of the address space module of the subsystem, the start address of the address space module, the end address of the address space module, the address space size, and the address type in the read address allocation summary information. The present invention can automatically generate C-code address access test case programs and SV-code address access test cases. The test cases for C-code address access are as shown in Figure 5 and Figure 6 Shown, the principle of the SV-code address access test case is similar to this, and it will not be described in detail here. Figure 5 and Figure 6This mainly describes a test framework for the memory address access characteristics of an embedded system, including read-write consistency checking (Addr_check), read-only type checking (Addr_no_check), and reserved bit checking (Rsd_Addr_check). And it uses ROM test functions (mem_addr_no_check), reserved area tests (Rsd_mem_addr_check), and RAM test functions (mem_addr_check) to perform address range tests. Generally speaking, its display code includes address space name annotations, configuring address read-write operations, status printing, and status data comparison, etc. Since the subsystem needs to be independently verified, the generated test cases mainly target the sub-modules corresponding to a certain subsystem, and the generated case names are system names such as LMU0_test, RAM_test, PCIe_test, etc. The case annotation and the completion status printing code are generated through the module name and the address space size information; the access address information of the case is generated through the start address, end address, and address space size, and the unique randomization mechanism of SV is used to randomly access the address; whether to perform read-write consistency checking is determined by the address type information.

[0066] In the embodiment of the present invention, in the process of generating the functional coverage rate according to the read address allocation summary information, the present invention determines the cover group, cover point, and bin of each address space module according to the start address of the address space module and the end address of the address space module in the read address allocation summary information; instantiates the cover groups of all address space modules to obtain instantiated cover groups; and performs parallel sampling on several instantiated cover groups based on the cover point and the bin to generate the functional coverage rate. The present invention automatically generates a functional coverage rate file for the UVM (Universal Verification Methodology) platform, which can be applied to both SOC and subsystem verification environments at the same time. The main code is as Figure 7 and Figure 8 shown, and the functional coverage rate file can be added in the top layer of the verification environment. It should be noted that three parts of the functional coverage rate content are automatically added. The first part is to input the covergroup, coverpoint, and bin descriptions of each address space module one by one, including the range constraints of the address boundary and the random address; the second part is to instantiate the cover groups of all address space modules; the third part is to use parallel conditions to formulate sampling conditions, and then sample the instantiations of each address space module. To achieve a closed loop where the incentive trigger is the coverage rate that can be collected.

[0067] Step S13: Integrate the address macro definition file, the address access cases, and the functional coverage into a preset verification environment to complete the verification of the address allocation of the system on a chip.

[0068] In the embodiment of the present invention, after generating the address macro definition file, the address access cases, and the functional coverage according to the above method, integrating the generated address macro definition file, the address access cases, and the functional coverage into a preset verification environment can automatically complete the verification of the address allocation of the system on a chip. Among them, the present invention ensures the completeness of the address allocation verification work by analyzing the functional coverage results.

[0069] In the embodiment of the present invention, for the configured address space, it can also be subdivided into the domains and bit positions of the registers. And because the registers are divided into different types, the processing methods are also different, which can also be integrated into this invention. Secondly, in some special SOC chips, not only the CPU has the function of accessing addresses, but other address access methods can also be integrated, such as the bus access of PCIe, etc. Specifically, when subdividing the configured address space into the domains and bit positions of the registers, first determine the system requirements, that is, clarify the configured hardware modules (such as interrupt controllers, clock generators, input / output ports, etc.), and list the parameters that each module needs to configure (such as enable bits, clock division values, data formats, etc.) to define the parameters. Then allocate the address space: determine the starting address and size of the configured address space; allocate register addresses according to the bus width (such as 32 bits), usually aligned by 4 bytes (for example, 0x0000, 0x0004, 0x0008). Then define the register functions, such as the register type and register attributes (determine the read / write permissions and reset values of each register). Design the domain attributes and constraints: Bit width: Ensure that the number of bits of the domain is sufficient to represent all possible values (such as a 3-bit domain can represent 8 states). Access attributes: Define the read / write permissions of the domain (such as some bits are read-only or need to be written 1 to clear). Default value: Specify the initial value after reset (such as the enable bit defaults to 0, and the division value defaults to the system clock). Finally, document and code generation: Register mapping table: Write a document to record the address, bit field definition, and function of each register. In this way, the configured address space is systematically subdivided into registers and their bit fields to ensure the coordinated work of hardware and software.

[0070] Beneficial effects: The present invention first summarizes the address allocation of the system-on-chip, and then reads the summary information of the address allocation to automatically generate verification components such as address macro definition files, address access test cases, and functional coverage. In this way, the automatically generated verification components can cover all application scenarios, eliminate errors or omissions caused by manual writing, and improve accuracy. At the same time, it can greatly reduce the waiting time cost of project verification nodes. And because the time cost of manually writing verification components is greatly reduced, and the human errors in manual writing are also eliminated, the time for repeated simulations is reduced; moreover, the work efficiency and accuracy of verification are significantly improved.

[0071] Based on the previous embodiment, in a specific embodiment, the technical key points of the present invention include two points. The first point is to summarize through the architecture and design documents, add verification methodologies and verification mode thinking, and summarize them into a fixed-format table for convenient sampling; the second point is to generate address macro definition files, C code address access test cases, SV code address access test cases, and functional coverage. Next, the specific verification process will be described in detail.

[0072] Based on the traditional verification method, and aiming at the digital verification characteristics of the address allocation of the above SOC chip, combined with the general content of the address allocation table, it can be summarized into a table with a fixed format for address allocation, which includes addresses in 32-bit units and classification markings for address types. First, based on a specific address allocation table, sample the content of the address allocation table. Such as Figure 3As shown in the figure, after scraping the table content, it is determined whether this verification is for the SOC component. If it is for the SOC component, it enters the process branch of generating the C code component. In this branch, code cases for accessing the central processing unit, a macro definition file for the C code, and the SOC functional coverage will be further generated. The code cases for accessing the central processing unit are used to construct the basic verification layer for the hardware trustworthiness, ensure the correctness of the current behavior, and also provide a stable hardware foundation for the subsequent system-level function development. The macro definition file for the C code provides unified macro definitions such as constants and addresses for the subsequent code writing, improving the readability and maintainability of the code. If it is not a verification for the SOC component, it is further determined whether it is a verification for a single subsystem component. If not, the process of generating the SV code components for all subsystems will be generated, where a series of codes and files related to all subsystems can be generated. If so, according to the pre-input subsystem name, the SV code components for this subsystem will be specifically generated. In this branch, code address access cases for the subsystem, a macro definition file for the subsystem, and the functional coverage of the subsystem will be generated. The code address access cases for the subsystem are used to detect the functional correctness of the subsystem in different scenarios; the macro definition file for the SV code provides macro definitions for the code written in the SV language. The functional coverage is used to verify the integrity and efficiency optimization of the subsystem, guide the test direction to avoid verification blind spots, and also provide quantitative evidence to support the tape-out decision.

[0073] After generating the address macro definition file, address access cases, and functional coverage, the address macro definition file, address access cases, and functional coverage can be integrated into the preset verification environment to complete the verification of the address allocation of the system-on-chip.

[0074] Beneficial effects: The present invention can greatly reduce the waiting time cost of the project verification nodes, and since the time cost of manually writing verification components is greatly reduced, at the same time, the human errors in manual writing are eliminated, and the repeated simulation time is reduced. It also meets the requirements of verification process automation, verification test case automation, and reusability. It significantly improves the verification efficiency and verification accuracy of address access.

[0075] See Figure 9 As shown in the figure, an embodiment of the present invention provides a system-on-chip address allocation verification device, including:

[0076] A summary information reading module 11, configured to read the address allocation summary information of the system-on-chip;

[0077] A generating module 12, configured to generate an address macro definition file, address access cases, and functional coverage according to the read address allocation summary information;

[0078] An integrated module 13 is used to integrate an address macro definition file, an address access use case, and functional coverage into a preset verification environment to complete the verification of the address allocation of the system on a chip.

[0079] Since the embodiments of the device part correspond to the above embodiments, the embodiments of the device part are described with reference to the embodiments of the above method part and will not be repeated here.

[0080] Beneficial effects: The present invention first summarizes the address allocation of the system on a chip, and then reads the summary information of the address allocation to automatically generate verification components such as an address macro definition file, an address access use case, and functional coverage. In this way, the automatically generated verification components can cover all application scenarios, eliminate errors or omissions caused by manual writing, and improve the accuracy. At the same time, it can greatly reduce the waiting time cost of project verification nodes. And because the time cost of manually writing verification components is greatly reduced, and the human errors in manual writing are also eliminated, the time for repeated simulations is reduced; moreover, the verification work efficiency and accuracy are significantly improved.

[0081] Furthermore, an embodiment of the present application also discloses an electronic device. Figure 10 It is a structural diagram of an electronic device shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation to the scope of use of the present application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the method for verifying the address allocation of the system on a chip disclosed in any of the foregoing embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0082] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is made here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0083] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0084] Among them, the operating system 221 is used to manage and control each hardware device and computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the on-chip system address allocation verification method executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks.

[0085] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the on-chip system address allocation verification method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0086] Furthermore, the present application also discloses a computer program product, including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the on-chip system address allocation verification method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0087] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts between the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0088] Those skilled in the art can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0089] The steps of the method or algorithm described in combination with the embodiments disclosed herein can be directly implemented by hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0090] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0091] The technical solutions provided in this application have been introduced in detail above. Specific examples are used in this text to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A method for verifying on-chip system address allocation, characterized in that, Including: Reading the address allocation summary information of the system-on-chip; Generating an address macro definition file, an address access case, and a functional coverage based on the read address allocation summary information; Integrating the address macro definition file, the address access case, and the functional coverage into a preset verification environment to complete the verification of the address allocation of the system-on-chip.

2. The on-chip system address allocation verification method according to claim 1, wherein Before reading the address allocation summary information of the system-on-chip, it further includes: Determining a summary criterion based on the subsystem name of the system-on-chip, the address space module name of the subsystem, the start address of the address space module, the end address of the address space module, the address space size, and the address type; Summarizing the address allocation access information of the system-on-chip according to the summary criterion to obtain the address allocation summary information.

3. The on-chip system address allocation verification method according to claim 2, wherein The generating of an address macro definition file, an address access case, and a functional coverage based on the read address allocation summary information includes: Judging whether the current verification is for the address allocation verification of the overall system-on-chip components, and obtaining the corresponding judgment result; Generating an address macro definition file, an address access case, and a functional coverage according to the judgment result and the read address allocation summary information.

4. The method for verifying on-chip system address allocation according to claim 3, wherein The generating of an address macro definition file, an address access case, and a functional coverage according to the judgment result and the read address allocation summary information includes: If the current verification is for the address allocation verification of the overall system-on-chip components, then generating a C-code-based address access case for the system-on-chip components, a C-code-based address macro definition file for the system-on-chip components, and the functional coverage of the system-on-chip based on the read address allocation summary information; If the current verification is not for the address allocation verification of the overall system-on-chip components, then judging whether the current verification is for the address allocation verification of a single subsystem component of the system-on-chip; If the current verification is for the address allocation verification of a single subsystem component of the system-on-chip, then generating an SV-code-based address access case for the target subsystem, an SV-code-based address macro definition file for the target subsystem, and the functional coverage of the target subsystem based on the read address allocation summary information; the target subsystem is any subsystem of the system-on-chip; If the current verification is not for the address allocation verification of a single subsystem component of the system-on-chip, then generating an SV-code-based address access case for all subsystems of the system-on-chip, an SV-code-based address macro definition file, and a functional coverage.

5. The on-chip system address allocation verification method according to claim 4, wherein The process of generating an address macro definition file based on the read address allocation summary information includes: Generating a C-code-based address macro definition file according to the start address of the address space module, the end address of the address space module, and the address space size in the read address allocation summary information; Generating an SV-code-based address macro definition file according to the start address of the address space module, the end address of the address space module, the address space size, and the address type in the read address allocation summary information.

6. The method for verifying on-chip system address allocation according to claim 4, wherein The process of generating an address access case based on the read address allocation summary information includes: Determine the type of the address access use case; If the address access use case is an address access use case based on C code, generate an address access use case based on C code according to the start address and the end address of the address space module in the read address allocation summary information; If the address access use case is an address access use case based on SV code, generate an address access use case based on SV code according to the name of the address space module of the subsystem, the start address of the address space module, the end address of the address space module, the address space size, and the address type in the read address allocation summary information.

7. The method for verifying on-chip system address allocation according to claim 4, wherein The process of generating the functional coverage according to the read address allocation summary information includes: Determine the cover group, cover point, and bin of each address space module according to the start address and the end address of the address space module in the read address allocation summary information; Instantiate the cover groups of all the address space modules to obtain instantiated cover groups; Perform parallel sampling on several of the instantiated cover groups based on the cover point and the bin to generate the functional coverage.

8. An on-chip system address allocation verification device, characterized in that, Include: A summary information reading module, configured to read the address allocation summary information of the system on chip; A generation module, configured to generate an address macro definition file, an address access use case, and a functional coverage according to the read address allocation summary information; An integration module, configured to integrate the address macro definition file, the address access use case, and the functional coverage into a preset verification environment to complete the verification of the address allocation of the system on chip.

9. An electronic device, characterized in that, Include: A memory, configured to store a computer program; A processor, configured to execute the computer program to implement the steps of the method for verifying the address allocation of the system on chip according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method for verifying the address allocation of the system on chip according to any one of claims 1 to 7 are implemented.

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