BFM random response method, electronic equipment and storage medium

Abstract

The invention relates to the field of chip design, in particular to a BFM random response method, electronic equipment and a storage medium, and the method comprises the steps: configuring a quick response time period and a quick response probability for each bus function model, and calculating the response probability of the current bus function model in each quick response time period; the step that each bus function model carries out random response according to the response probability comprises the steps that a random number is generated, the random number and each response probability are sequentially compared, and when the random number is smaller than or equal to the jth response probability, the current bus function model makes a response within the jth quick response time period; according to the method, random response probabilities of RTi in different times of time periods are calculated through random numbers, and the purpose of considering the simulation speed and a real scene is achieved.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and particularly to a BFM random response method, an electronic device, and a storage medium. Background Art

[0002] The RTL (Register Transfer Level) interface is responsible for external data reading and writing operations. In digital verification (DV), a Bus Functional Model (BFM) is configured to respond to these read and write requests. For example, when the RTL interface reads data externally, the BFM needs to return the data to the interface, and each interface must have a corresponding BFM for response. The response time of the BFM in the simulation phase is not the actual response time of the entire chip. For example, in the simulation phase, the BFM will return the data to the RTL interface after 5 - 10 clock cycles; while in the real scenario, it may take 5000 or even 10000 clock cycles to return the data to the corresponding interface. During IP verification, due to intensive communication traffic, it is different from the real chip situation. For example, a real chip may continuously send 1000 to 10000 data items to test whether the interface behavior is correct; but if each data item requires 5000 or even 10000 clock cycles to respond, the simulation time will become very long, and the simulation efficiency will be greatly reduced, which poses a great challenge to chip verification.

[0003] For example, in the simulation phase, the data is returned in 10 clock cycles; while in the real scenario, the data is returned in 1000 clock cycles; in this case, the simulation phase fails to truly simulate the real scenario. If the current design can only correctly respond within 100 clock cycles and cannot correctly respond beyond 100 clock cycles. Then in the simulation phase, since the situation of responding in 1000 clock cycles in the real scenario is not simulated and verified, there may be a problem that the real scenario cannot correctly respond, ultimately resulting in incorrect results.

[0004] Therefore, there is an urgent need for a return method that can balance the simulation speed and the real scenario. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is: a BFM random response method, the method comprising the following steps: S100, obtaining N interfaces INTER in the chip to be verified and the bus function model BFM of each interface in the verification system, where INTER = {inter1, inter2, …, inter , i , , i ,

[0005] , N ,

[0004] , , , …, inter N}, inter iFor the i-th interface inter i , the value range of i is from 1 to N; BFM = {BFM1, BFM2, …, BFM i , …, BFM N}, where BFM i is the bus function model BFM i of inter i .

[0006] S200, configure a fast response time period and a fast response probability for each bus function model. Among them, for BFM i , configure the fast response time period RT i and the fast response probability a i .

[0007] S300, according to the fast response time period and the fast response probability, obtain the response probability of each bus function model within each fast response time period; among them, the response probability of BFM i within K RT i is P i ={P i1 , P i2 , …, P ij , …, P iK}, where P ij is the response probability of BFM i within the j-th RT i , and the value range of j is from 1 to K; among them, P ij satisfies: P ij =(1 - a i ) j-1 ×a i .

[0008] S400, each bus function model makes a random response according to the response probability. Among them, each random response step of BFM i includes: S410, generate a random number r i for BFM i , and the value range of r i is from 0 to 1.

[0009] S420, compare the r i with each response probability in P i in turn. When the r i is less than or equal to the P ij , then BFM i makes a response within the j-th RT i .

[0010] In addition, the present invention also provides a non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, which is loaded and executed by a processor to implement the above method.

[0011] In addition, the present invention also provides an electronic device, including a processor and the above non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects: The present invention provides a BFM random response method, an electronic device and a storage medium. By configuring a quick response time period and a quick response probability for each bus function model, and calculating the response probability of the current bus function model within each quick response time period; generating a random number, comparing the random number with the response probability of the current bus function model within each quick response time period, and then determining the quick response time period of the random response; calculating the random response probability within different multiple time periods through the random number, so as to achieve the purpose of balancing the simulation speed and the real scenario. i The random response probabilities within different multiple time periods are calculated to achieve the purpose of balancing the simulation speed and the real scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0014] Figure 1 It is a flowchart of a BFM random response method provided by an embodiment of the present invention; Figure 2 It is BFM provided by an embodiment of the present invention i The flowchart of the random response step each time. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0016] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meaning as commonly understood by those of ordinary skill in the art.

[0017] Please refer to Figure 1, which shows a BFM random response method, and the method includes the following steps: S100, obtain N interfaces INTER in the chip to be verified and the bus function model BFM of each interface in the verification system, where INTER = {inter1, inter2, …, inter i , …, inter N}, inter i is the i-th interface inter i , and the value range of i is from 1 to N; BFM = {BFM1, BFM2, …, BFM i , …, BFM N}, BFM i is the bus function model BFM of inter i . i .

[0018] Among them, the bus function model (Bus Functional Model, BFM) is mainly used to define how data is transmitted and interacted between various components within the system through the bus; it describes how signals and messages are exchanged between various modules under different conditions to achieve specific functions. During the verification process, BFM can abstract the bus interconnection and provide high-level interfaces to implement a test platform for stimulating RTL modules.

[0019] As an example, inter i is used to implement direct data transfer between the hard disk and the system memory. BFM i is used to simulate various functions of inter i during the data transfer process, such as the initiation of DMA requests, the timing of data transfer, the response after transfer completion, etc.

[0020] S200, configure a fast response time period and a fast response probability for each bus function model, where a fast response time period RT i and a fast response probability a i are configured for BFM i .

[0021] Among them, the fast response time period is the time period during which it is expected that the bus function model can give a quick response. This time period is a time length, rather than a specific time point range. Among them, RT i is [t0 i , t1 i . As an example, RT i is [100, 200], and the time unit is milliseconds.

[0022] Among them, t0 iThe value is the shortest time consumption to complete an event, which is a fixed lower limit value determined based on the basic characteristics of the event itself. t1 i is determined according to the simulation time of each bus function model; when each bus function model executes a single test case, there is a preset upper limit value for its simulation duration. t1 i It is dynamically adjusted within the limit of the preset upper limit value. That is, t1 i The value is greater than the value of t0 i and less than or equal to the upper limit value of the simulation duration.

[0023] Among them, the quick response probability is the likelihood of making a response within the current quick response time period.

[0024] In order to accurately and reasonably configure the quick response time period and quick response probability for each bus function model, two key factors, namely the protocol characteristics and workload of the interface itself, need to be comprehensively considered.

[0025] In one implementation, according to the protocol followed by inter i the type of event generated is determined; based on the priority of the event types of different interfaces, the quick response probability is determined, providing a stable and reliable basis for the subsequent simulation process. Among them, the priority of the event type is relative to the event types of different interfaces. The event types corresponding to different interfaces are different. When configuring the quick response probability, it is configured according to the priority of the event type. The quick response probability of the interface with a relatively higher priority event type is configured to be higher, and the quick response probability of the interface with a relatively lower priority event type is configured to be lower. It should be noted that when it comes to the interface of a certain specific protocol bus, this interface strictly executes various operations according to the corresponding protocol; this means that the events generated during its operation are completely defined by this protocol, so the event type is determined; taking the SPI (Serial Peripheral Interface) protocol bus interface as an example, its main operation event types include the generation of clock signals initiated by the host, the switching of slave selection signals, and the sending and receiving of data, etc.; these event types are stipulated by the SPI protocol, and as long as it is an interface based on the SPI protocol, its event type follows this standard.

[0026] In one implementation, the load size of inter i is negatively correlated with the size of RT i The greater the load, the smaller the value of RT i ; the smaller the load, the larger the value of RT i . Among them, the load of inter i is determined by the product of the event and the number of transactions.

[0027] S300, obtain the response probability of each bus function model within each fast response time period according to the fast response time period and the fast response probability; where, BFM i The response probability within K of the RT i is P i ={P i1 , P i2 , …, P ij , …, P iK}, P ij is the response probability of BFM i within the j-th RT i , and the value range of j is from 1 to K; where P ij satisfies: P ij =(1 - a i ) j-1 ×a i .

[0028] In one implementation, S300 further includes initializing a counter for BFM i , and the value j of the counter is the response probability P i of the currently calculated j-th RT ij ; after calculating P ij , update the value of the counter to j + 1, and calculate the response probability again according to S300 until j = K, and stop when calculating P iK . Where, K×RT i is the longest response time of BFM i during the simulation process, and the value of K can be configured according to experience. It should be noted that when the interface function is simple, since the system behavior is relatively easy to predict and simulate, there is no need to simulate a too long response time, and at this time, K can be set to a smaller value. And when there may be various complex interactions and delays in the interface, in order to more comprehensively simulate the possible long response time in the real scenario, at this time, the value of K can be set to a larger value.

[0029] It should be noted that each bus function model corresponds to a counter.

[0030] In one implementation, the management step of the counter is further included in S310: S311, define a data container with the same size as the number N of bus function models for storing counters.

[0031] In one implementation, the data container is an array or a hash table (such as a Python dictionary). If a hash table is used, its key is the index of BFM, and the value is initialized to 1. Other types of data containers also fall within the protection scope of the present invention.

[0032] S312, initialize the values corresponding to each element in the data container to 1, indicating starting from the 1st RT i to start the calculation.

[0033] S313, when calculating the response probability of each BFM at different RTs i obtain the value of the corresponding counter from the data container.

[0034] S314, after calculating the response probability, increment the value of the corresponding counter in the data container by 1.

[0035] S315, after each update, check whether the value of the counter has reached K. If it has reached, stop calculating the response probability of this BFM.

[0036] The management steps of S311 - S315 can reduce the complexity of resource management, simplify the code structure, and improve the readability and maintainability of the code.

[0037] S400, each bus function model makes a random response according to the response probability.

[0038] Among them, please refer to Figure 2 , BFM i each random response step includes: S410, generate a random number r i for BFM i , r i ranges from 0 to 1.

[0039] In one implementation, the random number in S410 is generated by a random number generator each time the simulation response time is calculated and is uniformly distributed within the range of 0 to 1. The uniform distribution of the random number can ensure the accuracy of probability calculation.

[0040] In one implementation, the random number generation algorithm is a lagged Fibonacci generator, a pseudo-random number generation algorithm based on Mersenne primes, or an Xorshift algorithm. Other algorithms for generating random numbers also fall within the protection scope of the present invention.

[0041] S420, compare the r i with each response probability in P i in sequence. When the r i is less than or equal to the P ij , then BFM i makes a response within the jth RT i .

[0042] In one implementation, the comparison step includes: starting from j = 1, compare the magnitudes between r i and P ij in sequence. If ri Greater than the said P ij , then the BFM i does not respond, updates j to j + 1, and continues to compare r i with P ij for their magnitudes; if r i is less than or equal to the said P ij , then the BFM i responds within the j-th RT i and stops the comparison.

[0043] After determining the value of j, the response time is randomly determined within the j-th RT i . As an example, when j = 3 and RT i is [100, 200] with the unit of ms, that is, the response time randomly selects a value between the 3rd [100, 200] milliseconds, that is, randomly selects a value between 300 - 400 milliseconds. After determining the response time, the bus function model performs corresponding operations at this response time point. For example, the bus function model processes the received data and sends it back to the requester at the determined response time point.

[0044] Since a i is usually configured as a relatively large probability value, in most cases the bus function model responds quickly within the first RT i , which can accelerate the overall speed of the simulation and meet the requirements of the debugging simulation time. At the same time, by calculating the random response probability within different multiples of RT i through random numbers, it is possible to simulate the longer response time situation of a similar real full chip with a low probability, making the simulation closer to the real scenario without overly affecting the simulation speed; achieving the purpose of balancing the simulation speed and the real scenario. In addition, the method provided by the present invention can also flexibly focus on different time weights by adjusting the length of RT i and the magnitude of a i to adapt to different verification requirements.

[0045] In summary, the present invention provides a BFM random response method, which configures a fast response time period and a fast response probability for each bus function model, and calculates the response probability of the current bus function model within each fast response time period; generates a random number, compares the random number with the response probability of the current bus function model within each fast response time period, and then determines the fast response time period for random response; it calculates the random response probability within different multiples of RT i through random numbers, achieving the purpose of balancing the simulation speed and the real scenario.

[0046] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be disposed in an electronic device to store at least one instruction or at least one program segment related to a method for implementing a method in the method embodiment. The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method provided in the above embodiment.

[0047] An embodiment of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0048] An embodiment of the present invention also provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps in the method according to various exemplary embodiments of the present invention described above in this specification.

[0049] Those skilled in the art can clearly understand that for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is used as an example. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0050] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention disclosed is defined by the appended claims.

Claims

1. A BFM random response method, characterized in that, The method includes the following steps: S100, obtaining N interfaces INTER in the chip to be tested and the bus function model BFM of each interface in the verification system, where INTER={inter1,inter2,…,inter i ,…,inter N },inter i For the i-th interface inter i , the value range of i is 1 to N; BFM={BFM1,BFM2,…,BFM i ,…,BFM N }, BFM i For inter i Bus Functional Model BFM i ; S200, configure a fast response time period and a fast response probability for each bus function model, where it is for the BFM i Configure the fast response time period RT i And the fast response probability a i ; S300. Obtain the response probability of each bus function model within each fast response time period according to the fast response time period and the fast response probability; where, BFM i The response probability within K of the RT i is P i ={P i1 , P i2 , …, P ij , …, P iK}, P ij is the response probability of BFM i within the j-th RT i , and the value range of j is from 1 to K; where P ij satisfies: P ij =(1 - a i ) j-1 ×a i ; S400, each bus function model makes a random response according to the response probability, where BFM i Each random response step includes: S410, generate BFM i random number r i , r i has a value range from 0 to 1; S420, compare the r i with each response probability in P i in sequence. When the r i is less than or equal to the P ij , then BFM i makes a response within the j-th RT i .

2. The method according to claim 1, wherein S300 also includes BFM i Initialize a counter, where the value j of the counter represents that the j-th RT is currently being calculated i of the response probability P ij ; after calculating P ij , update the value of the counter to j + 1, and calculate the response probability again according to S300 until j = K and stop after calculating P iK .

3. The method according to claim 2, wherein The management step of the counter is further included in S310: S311, define a data container with the same size as the number N of bus function models for storing the counter; S312, initialize the values corresponding to each element in the data container to 1, indicating the calculation starts from the 1st RT i Start the calculation; S313. When calculating the response probability of each BFM at different RTs i obtain the value of the corresponding counter from the data container; S314, after calculating the response probability, increment the value of the corresponding counter in the data container by 1; S315, after each update, check whether the value of the counter reaches K, and if so, stop calculating the response probability for this BFM.

4. The method according to claim 3, characterized in that, The data container is an array or a hash table.

5. The method according to claim 1, wherein The generation algorithm of the random number is a lagged Fibonacci generator, a pseudo-random number generation algorithm based on Mersenne primes, or an Xorshift algorithm.

6. The method according to claim 1, wherein In S400, the comparison steps include: starting from j = 1, successively compare r i with P ij for their magnitudes. If r i is greater than the said P ij , then BFM i does not make a response, update j to j + 1, and continue to compare r i with P ij for their magnitudes; if r i is less than or equal to the said P ij , then BFM i makes a response within the j-th RT i and stops the comparison.

7. The method according to claim 1, wherein Determine the type of event generated according to the protocol followed by inter i Determine the type of event generated; determine the fast response probability based on the priority of the event types of different interfaces.

8. The method according to claim 1, characterized in that, inter i The load magnitude of i is negatively correlated with the magnitude of RT.

9. A non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by a processor to implement the method according to any one of claims 1-8.

10. An electronic device, characterized in that, It includes a processor and the non-transitory computer-readable storage medium described in claim 9.

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