Circuit analysis searching method and device with gated clock

Abstract

The invention discloses a circuit analysis searching method and device with a gated clock. The method comprises the following steps: S1, distinguishing a time sequence relationship of triggers according to clock gating, and re-screening and grouping the triggers based on a time sequence to obtain a grouping result of the triggers; s2, according to a bidirectional data flow relationship between the adder and the trigger, dynamically searching, positioning and capturing a related logic gate circuit, and combining and grouping with a corresponding trigger circuit to obtain a preliminary grouping result of the counter and the accumulator; s3, verifying whether boundaries of a counter and an accumulator in the preliminary grouping result are complete or not to obtain a verified grouping result; and S4, reordering and classifying the counters and the accumulators in the verified grouping results according to the sequence of the adders to obtain final classification results of the counters and the accumulators. According to the method, the search efficiency and accuracy of the counter and the accumulator with time sequence correlation are improved, the manual analysis time of the digital integrated circuit is shortened, and the cost is reduced.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of circuit analysis, and in particular, to a circuit analysis and search method and device with gated clocks. Background Art

[0002] In the reverse analysis of digital integrated circuits, counters and accumulators, as the core modules for implementing arithmetic operations and state control, the accurate identification of their functional characteristics is one of the core challenges in reverse engineering.

[0003] Taking the counter as an example, it can be implemented through synchronous, asynchronous, ripple-carry, etc., and has functions such as variable modulus value and gated clock. Its diverse implementation methods and dynamic reconfiguration functions require collaborative analysis of multi-dimensional characteristics such as timing, data path, and control grid. And due to the involvement of multi-level data dependencies and feedback paths, the accumulator faces the risk of logical connection breakage in scenarios such as bus multiplexing and multi-clock domain crossing.

[0004] See Figure 1 , the existing technology can only identify counters with specific structures, and cannot identify the parts with simplified logic therein, and there is a high misjudgment rate in general identification, such as misidentifying the accumulator as a general register, incomplete path, and low efficiency, etc., which seriously restricts the chip analysis efficiency and the reliability of intellectual property analysis. Summary of the Invention

[0005] The present invention provides a circuit analysis and search method and device with gated clocks, which solves the problems of fuzzy counter paths and broken accumulator data chains in the reverse analysis of integrated circuits by introducing clock gating signal tracking, two-way data flow search mechanism for data streams, and cross-level verification strategy.

[0006] In a first aspect, embodiments of the present invention provide a circuit analysis and search method with gated clocks, including: S1. In a scattered data netlist with connection relationships, distinguish the timing relationships of flip-flops according to the clock gating circuit, and re-screen and group the flip-flops based on the timing to obtain the grouping result of the flip-flops; S2. According to the two-way data flow relationship between the adder and the flip-flop, dynamically search and locate relevant logic gate circuits, and merge and group the captured logic gate circuits with the corresponding flip-flop circuits to obtain the preliminary grouping results of the counter and the accumulator; S3. Verify whether the boundaries of the counter and the accumulator in the preliminary grouping results are complete to obtain the verified grouping results; S4. Reorder and classify the counters and accumulators in the verified grouping results according to the adder order to obtain the final classification results of the counters and the accumulators.

[0007] Optionally, the S1 specifically includes: Classify the clock gating circuit according to the number of positive gate-level circuits and the number of negative gate-level circuits that the clock gating reaches the clock input source through. Group the flip-flops according to the connection relationship between the post-timing of the same type of clock gating circuit and the flip-flops. Verify the classification correctness of the flip-flops and the clock gating circuit, and arrange the flip-flops and the clock gating circuit.

[0008] Optionally, the grouping the flip-flops according to the connection relationship between the post-timing of the same type of clock gating circuit and the flip-flops includes: If the post-timing of the same type of clock gating circuit is connected to the flip-flop through a positive logic gate circuit, consider the corresponding flip-flop and the clock gating as the same logic. If the post-timing of the same type of clock gating circuit is connected to the flip-flop through a negative logic gate circuit, consider the corresponding flip-flop and the clock gating as the opposite logic.

[0009] Optionally, the S2 specifically includes: S21. Grab the adder and related logic gate circuits from the scattered netlist according to the bidirectional data flow relationship between the adder and the flip-flop, and add them to the corresponding flip-flop group to obtain an adder-flip-flop group. S22. Grab the simplified logic circuit of the adder from the scattered netlist, and add the simplified logic circuit to the corresponding adder-flip-flop group.

[0010] Optionally, the S21 includes: Look forward a preset number of gate-level circuits from the input D terminal of the grouped flip-flops, and grab the adder and related logic gate circuits in the search path. Look backward a preset number of gate circuits from the carry output port of the grabbed adder. If it passes through an adder, continue to look backward a preset number of gate circuits. If a closed loop can be formed, incorporate the adder and logic gate circuits in the path into the group; otherwise, reserve a search vacancy at the corresponding port.

[0011] Optionally, the S22 includes: Look forward a preset number of gate circuits from the D terminal of the flip-flop in the group that is not matched with the adder. After finding an exclusive OR gate or an equivalence gate, continue to look forward a preset number of gate circuits. If it can be connected to the carry output port in the group, grab all the found gate circuits into the group and fill them into the reserved search vacancy. Look backward a preset number of gate circuits from the output port of the flip-flop. If it passes through other groups, terminate the search and keep the port; if it can return to the group, grab the found gate circuits into the corresponding group.

[0012] Optionally, S3 specifically includes: Check whether the output port of the grouped external connection is only the output port Q or the inverted output port QN of the flip-flop. If not, return to execute S2; If so, check the input port of the grouped external connection. If there is a structure where the adder input is connected to the SUM output of another adder, it is classified as a multiplier or other group.

[0013] Optionally, S4 specifically includes: Sort the adders from low to high according to the carry output port of the adder composition circuit, connect the ports of the adder to the corresponding ports of the flip-flop and retain all the output port short lines; According to the type of adder and the type of logic gate circuit in the group, set the corresponding group as a counter or an accumulator to obtain the final classification result of the counter and the accumulator.

[0014] Optionally, setting the corresponding group as a counter or an accumulator according to the type of adder and the type of logic gate circuit in the group includes: If there is a full adder or a three-input exclusive OR gate / equivalence gate in the group, set the corresponding group as an accumulator; If there is only a half adder or a two-input exclusive OR gate / equivalence gate in the group, set the corresponding group as a counter.

[0015] In a second aspect, an embodiment of the present invention further provides a circuit analysis and search device with a gated clock, including: A flip-flop grouping module, configured to distinguish the timing relationship of flip-flops according to a clock gating circuit in a scattered data netlist with connection relationships, and re-screen and group the flip-flops based on the timing to obtain a grouping result of the flip-flops; A preliminary grouping module, configured to dynamically search for and locate relevant logic gate circuits according to the two-way data flow relationship between the adder and the flip-flop, merge and group the captured logic gate circuits with the corresponding flip-flop circuits to obtain a preliminary grouping result of the counter and the accumulator; A verification module, configured to verify whether the boundaries of the counter and the accumulator in the preliminary grouping result are complete to obtain a verified grouping result; A classification and sorting module, configured to re-sort and classify the counter and the accumulator in the verified grouping result according to the adder order to obtain the final classification result of the counter and the accumulator.

[0016] The present invention solves the problems of counter path ambiguity and accumulator data chain breakage in integrated circuit reverse analysis by introducing clock gating signal tracking, data stream bidirectional search mechanism, and cross-level verification strategy. In addition, the technical solution of the present invention can search for special counters and accumulators including logic simplified circuits, improve the search efficiency and accuracy of counters and accumulators related to timing, reduce the time of manual analysis of digital integrated circuits, and reduce costs. Description of the Drawings

[0017] Figure 1 It is a structural diagram of a conventional counter in the prior art; Figure 2 It is a flowchart of a circuit analysis and search method with a gated clock provided by an embodiment of the present invention; Figure 3 It is a gated clock circuit diagram provided by an embodiment of the present invention; Figure 4 It is a flip-flop circuit diagram provided by an embodiment of the present invention; Figure 5 It is a diagram of a fragmented data netlist provided by an embodiment of the present invention; Figure 6 It is a diagram of a flip-flop grouping provided by an embodiment of the present invention; Figure 7 It is a half adder structural diagram provided by an embodiment of the present invention; Figure 8 It is a full adder structural diagram provided by an embodiment of the present invention; Figure 9 It is a preliminary capture result diagram provided by an embodiment of the present invention; Figure 10 It is an exclusive OR gate structural diagram provided by an embodiment of the present invention; Figure 11 It is an exclusive NOR gate structural diagram provided by an embodiment of the present invention; Figure 12 It is a further capture result diagram provided by an embodiment of the present invention; Figure 13 It is a verification and sorting completed result diagram provided by an embodiment of the present invention. Detailed Embodiment

[0018] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the present invention, rather than limiting the present invention. In addition, it should be noted that only parts related to the present invention rather than all structures are shown in the drawings for the convenience of description. Embodiment

[0019] Figure 2The following is a flowchart of a circuit analysis and search method with gated clock provided by an embodiment of the present invention, which specifically includes the following steps: S1. In a scattered data netlist with connection relationships, distinguish the timing relationships of flip-flops according to the clock gating circuit, and re-screen and group the flip-flops based on the timing to obtain the grouping result of the flip-flops.

[0020] See Figure 3 and Figure 4 , in this embodiment, the timing relationships of the flip-flops in Figure 3 are distinguished according to the clock gating circuit in Figure 4 , and the flip-flops are re-screened and grouped based on the timing.

[0021] Figure 5 is a diagram of a scattered data netlist with connection relationships. This step mainly preprocesses the functional elements in the data netlist based on logic such as timing, and specifically includes the following steps: 1. Screen the clock gating circuit based on the clock tree Specifically, according to the number m of forward gate-level circuits and the number n of reverse gate-level circuits passed from the clock gating to the clock input source, classify the clock gating circuits, which can be correspondingly classified into categories A, B, C, etc.

[0022] Among them, the gated clocks with the same m and n can be regarded as one category and executed according to the same category in the subsequent steps. If there are still other clock gating circuits connected after the clock gating, it is further classified into A1, A2, etc.

[0023] 2. Screen the flip-flops based on the classified clock gating circuits Grab the flip-flops whose timing is directly connected to the clock gating circuit from the flip-flop stack according to the connection relationship after the same-category clock gating circuits. Specifically, group the flip-flops according to the connection relationship between the timing and the flip-flops after the same-category clock gating circuits. If the timing after the same-category clock gating circuit is connected to the flip-flop through a forward logic gate circuit, regard the corresponding flip-flop and the clock gating circuit as the same logic; if the timing after the same-category clock gating circuit is connected to the flip-flop through a reverse logic gate circuit, regard the corresponding flip-flop and the clock gating circuit as the opposite logic and classify them into different categories from the previous group of flip-flops, such as A1 and A1N.

[0024] 3. Verify the classified flip-flops and clock gating circuits Specifically, based on the scan control terminal and reset terminal of the classified flip-flops, as well as the control terminal of the clock gating circuit, check the classification correctness of the flip-flops and the clock gating circuit. For example, for the flip-flops and gated clock circuits distributed in the same group, their control terminals and reset terminals should be connected to the same wire. If not, they will be removed from the group. Further, arrange the flip-flops and clock gating columns according to the magnitudes of m and n. For example, the groups of flip-flops can be sorted in ascending order of m and n. The grouped flip-flops after preprocessing are shown in Figure 6 。

[0025] S2. According to the two-way data flow relationship between the adder and the flip-flop, dynamically search for and locate the relevant logic gate circuits, and merge and group the captured logic gate circuits with the corresponding flip-flop circuits to obtain the preliminary grouping results of the counter and accumulator.

[0026] Both the counter and the accumulator are composed of adders. Among them, the counter has various types such as adder, subtractor, and reversible counter, and the adder also has various compositional forms with simplified logic. In this embodiment, according to the two-way data flow relationship between the adder and the flip-flop, locate and capture the relevant logic gate circuits, and merge and group them with the corresponding flip-flop circuits.

[0027] Specifically, the S2 includes: S21. According to the two-way data flow relationship between the adder and the flip-flop, capture the adder and relevant logic gate circuits from the scattered netlist and add them to the corresponding flip-flop groups to obtain adder-flip-flop groups; S22. Capture the simplified logic circuit of the adder from the scattered netlist and add the simplified logic circuit to the corresponding adder-flip-flop groups. The detailed steps are as follows: 1. Forward search a preset number of gate-level circuits from the input D terminal of the grouped flip-flops. The preset number can be adjusted according to the circuit process node and complexity, so as to more accurately find the key circuits of the counter or accumulator. Here, the default setting is 3. If there is a Figure 7 half adder in <XXX>or a Figure 8 full adder in <XXX> among the three gate-level circuits, then incorporate all the passed logic gate circuits into the flip-flop group together. This operation is applied to all flip-flops within the group. If no adder is found by searching forward for the flip-flop group, set this flip-flop group as a pending group, which can expand the search level in the future according to the needs of the engineer or be regarded as a non-counter and non-accumulator unit. If it passes through other groups, terminate and retain the ports.

[0028] 2. Among the searched adder-trigger groups, look backward for three logic gate circuits from the carry CO data port of the captured adder. If passing through other groups, terminate and retain the port; if passing through an adder, continue to look backward for three logic gate circuits from the sum output port SUM of the adder. If it can return to the D input of the trigger within this group, incorporate the adder along with the passed logic gate circuits into the group; otherwise, draw a frame at this port to reserve a search space. See the preliminary capture result diagram in Figure 9 。

[0029] 3. Based on the sum output SUM of the adder to the D input of the trigger in the previous step, match the corresponding adder-trigger. Then look forward for three gate circuits from the D input of the unmatched trigger. If the exclusive OR gate in Figure 10 or the equivalence gate in Figure 11 is found, capture it into the group, and further look forward for three gate circuits from the exclusive OR gate and the equivalence gate. If it can be connected to the carry output port CO within the group, capture all the gate circuits found in this sub-step into the group and fill them into the corresponding reserved search space in the previous step.

[0030] 4. Continue to look backward for three gate circuits from the output port Q and the inverted output port QN of the trigger. If passing through other groups, terminate and retain the port. If it can return to the group, capture the found gate circuits into the group. See the further capture result diagram in Figure 12 。

[0031] S3. Verify whether the boundaries of the counters and accumulators in the preliminary grouping result are complete to obtain the verified grouping result.

[0032] After performing S1 and S2, the functions within the group are basically complete, but there may still be some individual scattered gate circuits that have not been captured, or the multiplier has been mis-captured. This needs to be improved in this step. The specific method is as follows: 1. Check the output ports connected outward from the group. Except for the output port Q and the inverted output port QN of the trigger, whether there are other output ports. If so, return to S2 for re-capture; if not, proceed to the next step.

[0033] 2. Check the input ports connected outward from the group. Excluding the gated clock input CP, the trigger reset CDN / set input SDN, the test chain select input SE, and the serial data input SI, whether there is an input of the same adder connected to the sum SUM output of another adder. If so, classify it as a multiplier or other group, distinguishing it from the counter and accumulator groups in this embodiment; if not, proceed to the next step.

[0034] S4. Reorder and classify the counters and accumulators in the verified grouped results according to the adder sequence to obtain the final classification results of the counters and accumulators.

[0035] After the above steps are completed, the regional division of the counters and accumulators is basically completed. This step mainly differentiates the functions of the two based on the structure, and performs optimization and sorting. First, sort the adders from low to high according to the carry output port of the adder composition circuit, connect the ports of the adder to the corresponding ports of the flip-flops, and retain all the short output ports; then, according to the types of adders and logic gate circuits within the group, set the corresponding group as a counter or an accumulator to obtain the final classification results of the counters and accumulators.

[0036] The specific method is as follows: 1. Based on the adder and the carry output port CO of the adder composition circuit that is outlined, sort the adders from low to high, connect the output port SUM of the adder to the input D terminal of the flip-flop correspondingly, connect the output Q or the inverted input terminal QN of the flip-flop to the corresponding input port of the adder, and retain all the short output ports.

[0037] 2. Check the grouped results that have been screened and sorted. If there is a full adder or a three-input exclusive OR gate / equivalence gate within the group, set the corresponding group as an accumulator; if there is only a half adder or a two-input exclusive OR gate / equivalence gate within the group, set the corresponding group as a counter. The result diagram after verification and sorting is shown in Figure 13 .

[0038] The present invention provides a new type of circuit analysis and search method, which can search for special counters and accumulators including logic simplified circuits, improves the search efficiency and accuracy of counters and accumulators related to timing, reduces the time of manual analysis of digital integrated circuits, and reduces costs.

[0039] The present invention also provides a circuit analysis and search device with a gated clock, including: A flip-flop grouping module, which is used to distinguish the timing relationship of flip-flops according to the clock gating circuit in a scattered data netlist with connection relationships, and re-screen and group the flip-flops based on the timing to obtain the grouped results of the flip-flops; A preliminary grouping module, which is used to dynamically search for and locate relevant logic gate circuits according to the two-way data flow relationship between the adder and the flip-flop, and merge and group the captured logic gate circuits with the corresponding flip-flop circuits to obtain the preliminary grouped results of the counters and accumulators; A verification module, which is used to verify whether the boundaries of the counters and accumulators in the preliminary grouped results are complete to obtain the verified grouped results; The classification and sorting module is used to re - sort and classify the counters and accumulators in the verified grouped results according to the adder order, so as to obtain the final classification results of the counters and accumulators.

[0040] Among them, the preliminary grouped results are specifically used for: Classify the clock gating circuits according to the number of forward gate - level circuits and reverse gate - level circuits passed from the clock gating to the clock input source; Group the flip - flops according to the connection relationship between the post - timing of the same - type clock gating circuits and the flip - flops; Verify the classification correctness of the flip - flops and the clock gating circuits, and arrange the flip - flops and the clock gating circuits.

[0041] Specifically, grouping the flip - flops according to the connection relationship between the post - timing of the same - type clock gating circuits and the flip - flops includes: If the post - timing of the same - type clock gating circuit is connected to the flip - flop through a forward logic gate circuit, consider the corresponding flip - flop and clock gating as the same logic; If the post - timing of the same - type clock gating circuit is connected to the flip - flop through a reverse logic gate circuit, consider the corresponding flip - flop and clock gating as the opposite logic.

[0042] Optionally, the above - mentioned preliminary grouped results specifically include: S21. Grab the adder and related logic gate circuits from the scattered netlist according to the two - way data flow relationship between the adder and the flip - flop, and add them to the corresponding flip - flop group to obtain the adder - flip - flop group; S22. Grab the simplified logic circuit of the adder from the scattered netlist, and add the simplified logic circuit to the corresponding adder - flip - flop group.

[0043] Specifically, the above S21 includes: Search forward a preset number of gate - level circuits from the input D - terminal of the grouped flip - flops, and grab the adder and related logic gate circuits in the search path; Search backward a preset number of gate circuits from the carry - output port of the grabbed adder. If passing through an adder, continue to search backward a preset number of gate circuits. If a closed loop can be formed, incorporate the adder and logic gate circuits in the path into the group. Otherwise, reserve a search vacancy at the corresponding port.

[0044] The above S22 includes: Search forward a preset number of gate circuits from the D - terminal of the flip - flops in the group that are not matched with the adder. After finding an exclusive - OR gate or an equivalence gate, continue to search forward a preset number of gate circuits. If it can be connected to the carry - output port in the group, grab all the found gate circuits and fill them into the reserved search vacancy; Search backward from the output port of the flip-flop for a preset number of logic gates. If other groups are passed through, terminate the search and retain the port. If it can return within the group, grab the found logic gates into the corresponding group.

[0045] Specifically, S3 includes: Check whether the output port connected outward from the group is only the output port Q or the inverted output port QN of the flip-flop. If not, return to execute the preliminary grouping module. If so, check the input port connected outward from the group. If there is a structure where the input of an adder is connected to the SUM output of another adder, divide it into a multiplier or other groups.

[0046] Furthermore, the above classification and sorting module specifically includes: Sort the adders from low to high according to the carry output port of the circuit composed of adders, connect the ports of the adders to the corresponding ports of the flip-flops, and retain all the short lines of the output ports. According to the type of adder and the type of logic gate circuit within the group, set the corresponding group as a counter or an accumulator to obtain the final classification results of the counter and the accumulator.

[0047] Specifically, setting the corresponding group as a counter or an accumulator according to the type of adder and the type of logic gate circuit within the group includes: If there is a full adder or a three-input exclusive OR gate / equivalence gate within the group, set the corresponding group as an accumulator. If there is only a half adder or a two-input exclusive OR gate / equivalence gate within the group, set the corresponding group as a counter.

[0048] A circuit analysis and search device with a gated clock provided by an embodiment of the present invention can execute a circuit analysis and search method with a gated clock provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method.

[0049] Note that the above is only a preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A circuit analysis and search method with gated clock, characterized in that Including: S1. In the scattered data netlist with connection relationships, distinguish the timing relationships of flip-flops according to the clock gating circuit, and re-screen and group the flip-flops based on the timing to obtain the grouping result of the flip-flops; S2. According to the bidirectional data flow relationship between the adder and the flip-flop, dynamically search for and locate the relevant logic gate circuits, and merge and group the captured logic gate circuits with the corresponding flip-flop circuits to obtain the preliminary grouping results of the counter and accumulator; S3. Verify whether the boundaries of the counter and accumulator in the preliminary grouping result are complete to obtain the verified grouping result; S4. Reorder and classify the counter and accumulator in the verified grouping result according to the adder order to obtain the final classification result of the counter and accumulator.

2. The method according to claim 1, wherein The specific steps of S1 include: Classify the clock gating circuit according to the number of forward gate-level circuits and reverse gate-level circuits passed from the clock gating to the clock input source; Group the flip-flops according to the connection relationship between the subsequent timing of the same type of clock gating circuit and the flip-flops; Verify the classification correctness of the flip-flops and the clock gating circuit, and arrange the flip-flops and the clock gating circuit.

3. The method according to claim 2, wherein Grouping the flip-flops according to the connection relationship between the subsequent timing of the same type of clock gating circuit and the flip-flops includes: If the subsequent timing of the same type of clock gating circuit is connected to the flip-flop through a forward logic gate circuit, regard the corresponding flip-flop and clock gating as the same logic; If the subsequent timing of the same type of clock gating circuit is connected to the flip-flop through a reverse logic gate circuit, regard the corresponding flip-flop and clock gating as the opposite logic.

4. The method according to claim 1, characterized in that The specific steps of S2 include: S21. According to the bidirectional data flow relationship between the adder and the flip-flop, capture the adder and relevant logic gate circuits from the scattered data netlist and add them to the corresponding flip-flop group to obtain the adder-flip-flop group; S22. Capture the simplified logic circuit of the adder from the scattered data netlist, and add the simplified logic circuit to the corresponding adder-flip-flop group.

5. The method according to claim 4, wherein The steps of S21 include: Search forward a preset number of gate-level circuits from the input D terminal of the grouped flip-flops, and capture the adder and relevant logic gate circuits in the search path; Search backward a preset number of gate circuits from the carry output port of the captured adder. If it passes through the adder, continue to search backward a preset number of gate circuits. If a closed loop can be formed, incorporate the adder and logic gate circuits in the path into the group. Otherwise, reserve a search vacancy at the corresponding port.

6. The method according to claim 5, characterized in that, The steps of S22 include: Search forward a preset number of gate circuits from the D terminal of the flip-flop that is not matched with the adder in the group. After finding an exclusive OR gate or an equivalence gate, continue to search forward a preset number of gate circuits. If it can be connected to the carry output port in the group, capture all the found gate circuits into the group and fill them into the reserved search vacancy; Search backward a preset number of gate circuits from the output port of the flip-flop. If it passes through other groups, terminate the search and retain the port; if it can return to the group, capture the found gate circuits into the corresponding group.

7. The method according to claim 1, characterized in that The specific steps of S3 include: Check whether the output port of the check group connected externally is only the output port Q or the inverted output port QN of the flip-flop. If not, return to execute S2; If so, check the input port of the check group connected externally. If there is a structure where the SUM output of one adder is connected to the input of another adder, it is classified as a multiplier or other group.

8. The method according to claim 1, characterized in that, The specific content of S4 includes: Sort the adders from low to high according to the carry output port of the adder circuit composed of adders, connect the ports of the adders to the corresponding ports of the flip-flops, and retain all the short lines of the output ports; According to the type of adder and the type of logic gate circuit in the group, set the corresponding group as a counter or an accumulator to obtain the final classification result of the counter and the accumulator.

9. The method according to claim 8, wherein According to the type of adder and the type of logic gate circuit in the group, setting the corresponding group as a counter or an accumulator includes: If there is a full adder or a three-input exclusive-OR gate / equivalence gate in the group, set the corresponding group as an accumulator; If there is only a half adder or a two-input exclusive-OR gate / equivalence gate in the group, set the corresponding group as a counter.

10. A circuit analysis and search device with gated clock, characterized in that, It includes: A flip-flop grouping module, which is used to distinguish the timing relationship of flip-flops according to the clock gating circuit in the scattered data netlist with connection relationships, and re-screen and group the flip-flops based on the timing to obtain the grouping result of the flip-flops; A preliminary grouping module, which is used to dynamically search for and locate relevant logic gate circuits according to the two-way data flow relationship between adders and flip-flops, and merge and group the captured logic gate circuits with the corresponding flip-flop circuits to obtain the preliminary grouping result of the counter and the accumulator; A verification module, which is used to verify whether the boundaries of the counter and the accumulator in the preliminary grouping result are complete to obtain the verified grouping result; A classification and sorting module, which is used to re-sort and classify the counters and accumulators in the verified grouping result according to the adder order to obtain the final classification result of the counters and accumulators.

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