Method and device for inserting test circuit into integrated circuit and integrated circuit
By establishing a digital virtual pad inside the top-level analog circuit of the integrated circuit and inserting the test module, the problem that the electronic design automation software cannot be recognized is solved, and the chip test coverage and performance quality is improved.
Patent Information
- Application Number
- CN202510359981.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-08-01
AI Technical Summary
Existing electronic design automation software cannot insert test circuits into all types of chip circuits, resulting in the inability to complete the pad function and connection relationship test, affecting the quality of chip products.
A virtual pad in digital form is established inside the top-level analog circuit of the integrated circuit, and a test module is inserted to conduct circuit testing through the connection relationship between the virtual pad and the test module.
The test coverage of integrated circuits is improved, the performance quality of the chip is ensured, and the problem that electronic design automation software cannot identify virtual pads in top-level analog circuits is overcome.
Smart Images
Figure CN120409384A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of chip design, and in particular, to a method, apparatus, and integrated circuit for inserting a test circuit into an integrated circuit. Background Art
[0002] Currently, in the field of chip design technology, it is usually necessary to perform functional tests on the pad functions existing inside the chip and the connections between the pads and external pins. To complete the test work, it is usually necessary to use, for example, Electronics Design Automation (EDA) tools to insert test circuits into the chip circuit.
[0003] However, with the rapid development of circuit technology, correspondingly, there are more and more different types of chip circuits. Therefore, since EDA tools are not compatible with any type of chip circuit, not all chip circuits can successfully insert test circuits. If a test circuit cannot be inserted into the chip circuit, then the test of the pad functions and their connection relationships inside the chip cannot be successfully completed, which will lead to the inability to guarantee the quality of chip products. Summary of the Invention
[0004] Based on this, in view of the above technical problems, it is necessary to provide a method, apparatus, computer device, computer-readable storage medium, computer program product, integrated circuit, and chip for inserting a test circuit into an integrated circuit that can improve the test coverage rate of the integrated circuit.
[0005] In a first aspect, this application provides a method for inserting a test circuit into an integrated circuit. The integrated circuit is configured with a first input pin to be tested and a first output pin to be tested. The method includes:
[0006] Based on the testable design library files of the first input pin to be tested and the first output pin to be tested, establish digital virtual pads inside the top-level simulation circuit of the integrated circuit. The virtual pads are configured with a second input pin to be tested corresponding to the first input pin to be tested, and test input pins and test output pins for connecting test signals;
[0007] Insert a test module connected to the virtual pads;
[0008] Based on the connection relationships of the virtual pads and the test module, connect the first input pin to be tested to the input pin of the test module, and connect the first output pin to be tested to the output pin of the test module, so that the test module performs circuit tests on the first input pin to be tested based on the signals input by the first input pin to be tested;
[0009] Among them, the test input pins are respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module.
[0010] In a second aspect, the present application further provides a device for inserting a test circuit into an integrated circuit. The integrated circuit is configured with a first input pin to be tested and a first output pin to be tested. The device includes:
[0011] A building module, configured to build digital virtual pads inside the top-level analog circuit of the integrated circuit based on the testable design library files of the first input pin to be tested and the first output pin to be tested. The virtual pads are configured with second input pins to be tested corresponding to the first input pins to be tested, and test input pins and test output pins for connecting test signals;
[0012] An inserting module, configured to insert a test module connected to the virtual pads;
[0013] A connecting module, configured to connect the first input pin to be tested to the input pin of the test module and connect the first output pin to be tested to the output pin of the test module based on the connection relationship between the virtual pads and the test module, so that the test module performs circuit testing on the first input pin to be tested based on the signal input by the first input pin to be tested;
[0014] Among them, the test input pins are respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module.
[0015] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements some or all of the steps described in any method of the first aspect of the embodiments of the present application.
[0016] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements some or all of the steps described in any method of the first aspect of the embodiments of the present application.
[0017] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, it implements some or all of the steps described in any method of the first aspect of the embodiments of the present application.
[0018] In a sixth aspect, the present application further provides an integrated circuit. The integrated circuit includes a test module inserted by any method of the first aspect of the embodiments of the present application.
[0019] In a seventh aspect, the present application also provides a chip. The chip is obtained by testing through any method of the first aspect of the embodiments of the present application.
[0020] The above method, device, computer device, computer-readable storage medium, computer program product, integrated circuit, and chip for inserting a test circuit into an integrated circuit are based on a testable design library file of a first input pin to be tested and a first output pin to be tested. A digital virtual pad is established inside the top-level analog circuit of the integrated circuit. The virtual pad is configured with a second input pin to be tested corresponding to the first input pin to be tested, and a test input pin and a test output pin for connecting test signals. A test module connected to the virtual pad is inserted. Based on the connection relationship between the virtual pad and the test module, the first input pin to be tested is connected to the input pin of the test module, and the first output pin to be tested is connected to the output pin of the test module, so that the test module can perform a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested. Among them, the test input pin is respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module. By using the method provided by the present application, a digital virtual pad is established inside the top-level analog circuit of the integrated circuit, and a test module is inserted inside the top-level analog circuit of the integrated circuit. Thus, based on the connection relationship between the virtual pad and the test module, the test module can perform a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested, overcoming the technical defect that the electronic design automation software cannot recognize the virtual pad in the top-level analog circuit and cannot insert the test module. By improving the testability of the integrated circuit, the test coverage rate of the integrated circuit is improved. Thus, the performance quality of the integrated circuit can be ensured. Description of the Drawings
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.
[0022] Figure 1 It is an application environment diagram of the method for inserting a test circuit into an integrated circuit in an embodiment;
[0023] Figure 2 It is a flowchart of the method for inserting a test circuit into an integrated circuit in an embodiment;
[0024] Figure 3A It is a corresponding circuit structure diagram of the content of the initial netlist file of the top-level analog circuit in an embodiment;
[0025] Figure 3B Schematic diagram of the corresponding circuit structure of the netlist file content after establishing virtual pads in digital form inside the top-level analog circuit in one embodiment;
[0026] Figure 3C Schematic diagram of the corresponding circuit structure of the netlist file content after inserting a test module inside the top-level analog circuit in one embodiment;
[0027] Figure 3D Schematic diagram of the corresponding circuit structure of the final netlist file content of the top-level analog circuit in one embodiment;
[0028] Figure 4A For Figure 3C Refined schematic diagram of the corresponding circuit structure of the netlist file content after inserting a test module inside the top-level analog circuit corresponding to;
[0029] Figure 4B For Figure 3D Refined schematic diagram of the corresponding circuit structure of the netlist file content after inserting a test module inside the top-level analog circuit corresponding to;
[0030] Figure 5 Block diagram of the structure of the device for inserting a test circuit into an integrated circuit in one embodiment;
[0031] Figure 6 Internal structure diagram of a computer device in one embodiment;
[0032] Figure 7 Internal structure diagram of a computer device in another embodiment. Specific implementation manners
[0033] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0034] The method for inserting a test circuit into an integrated circuit provided by the embodiments of the present application can be applied to, for example, Figure 1In the application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed in the cloud or on other network servers. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The head-mounted device can be a virtual reality (VR) device, an augmented reality (AR) device, smart glasses, etc. The server 104 can be an independent physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.
[0035] In an exemplary embodiment, as Figure 2 shown, a method for inserting a test circuit into an integrated circuit is provided. Taking the method applied to the Figure 1 terminal in as an example for description, the integrated circuit is configured with a first input pin to be tested and a first output pin to be tested. The method includes the following steps 202 to step 206. Among them:
[0036] Step 202, based on the testable design library files of the first input pin to be tested and the first output pin to be tested, establish digital virtual pads inside the top-level simulation circuit of the integrated circuit. The virtual pads are configured with a second input pin to be tested corresponding to the first input pin to be tested, and a test input pin and a test output pin for connecting test signals.
[0037] Among them, the first input pin to be tested refers to the input pin to be tested of the actual pad corresponding to the virtual pad. The first output pin to be tested refers to the output pin to be tested of the actual pad corresponding to the virtual pad. Since the first input pin to be tested and the first output pin to be tested correspond to the same virtual pad, the first input pin to be tested and the first output pin to be tested correspond to each other.
[0038] Specifically, in this embodiment, the digital virtual pads are established inside the top-level simulation circuit of the integrated circuit through electronic design automation software.
[0039] A testable design library file refers to a library file used for performing Design for Testability (DFT) on a first input pin under test and a first output pin under test. The testable design library file includes various types of pad information, pin connection relationship information of each type of pad, or other pad-related information, etc., which is used to guide Electronic Design Automation (EDA) software to correctly establish and configure virtual pads in digital form inside the top-level analog circuit of an integrated circuit, so as to improve the testability of the integrated circuit.
[0040] An integrated circuit refers to a circuit with a specific function formed by integrating a large number of microelectronic components (exemplarily, transistors, resistors, capacitors, etc.) and their connection lines on a small semiconductor chip. In this embodiment, the integrated circuit may be a circuit including a top-level analog circuit, input pins under test with multiple actual pads, and output pins under test with multiple actual pads.
[0041] The top-level analog circuit refers to the analog circuit at the highest design level in the integrated circuit.
[0042] A virtual pad refers to a virtual pad module corresponding to an actual pad established inside the top-level analog circuit for testing the actual pad. The virtual pad does not physically exist, but is represented in digital form inside the top-level analog circuit and is used to simulate the performance of the real actual pad. The virtual pad can be used to verify the function and connection relationship of the corresponding actual pad. Through the virtual pad in digital form, the relevant circuit of the actual pad can be tested and verified without actually manufacturing an integrated circuit or chip including the actual pad, so as to improve the design reliability and testability of the integrated circuit.
[0043] Since the integrated circuit corresponds to the top-level analog circuit, and the current testability process of Electronic Design Automation (EDA) software can usually only recognize virtual pads in digital circuits and cannot recognize virtual pads in analog circuits. Therefore, the EDA software cannot insert a test module into the top-level analog circuit. Thus, in order to enable the EDA software to recognize the virtual pad and successfully insert the test module, the virtual pad in this embodiment is in digital form, and the virtual pad in digital form can be successfully recognized by the EDA software. Furthermore, the test module can be successfully inserted into the integrated circuit in subsequent steps.
[0044] The second input pin under test refers to the input pin to be tested configured on the virtual pad for testing the first input pin under test. The second input pin under test corresponds to the first input pin under test, which means that the configuration information and pin function of the second input pin under test are the same as those of the first input pin under test, respectively.
[0045] Step 204, insert a test module connected to the virtual pad.
[0046] The test module is a module used for circuit testing of the first input pin to be tested. Specifically, the test module connected to the virtual pad is inserted through electronic design automation software. The test module is configured with an input pin connected to the test input pin of the virtual pad and an output pin connected to the test output pin of the virtual pad.
[0047] In an exemplary embodiment, the circuit type of the above test module is a boundary scan circuit.
[0048] In this embodiment, the circuit type of the test module is a boundary scan circuit. Thus, based on the boundary scan circuit, the functions and connection relationships of the virtual pads can be comprehensively tested, improving the test coverage rate of the integrated circuit. Furthermore, the performance quality of the subsequent actually fabricated integrated circuit can be ensured.
[0049] Step 206, based on the connection relationship between the virtual pad and the test module, connect the first input pin to be tested to the input pin of the test module, and connect the first output pin to be tested to the output pin of the test module, so that the test module performs circuit testing on the first input pin to be tested based on the signal input by the first input pin to be tested;
[0050] The test input pin is respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module.
[0051] Specifically, the connection relationship between the virtual pad and the test module is located in the testable design library file. That is to say, based on the testable design library file, the connection relationship between the virtual pad and the test module can be determined.
[0052] In an exemplary embodiment, the above connecting the first input pin to be tested to the input pin of the test module and connecting the first output pin to be tested to the output pin of the test module based on the connection relationship between the virtual pad and the test module includes: disconnecting the connection relationship between the test input pin of the virtual pad and the input pin of the test module, and connecting the first input pin to be tested to the input pin of the test module; disconnecting the connection relationship between the test output pin of the virtual pad and the output pin of the test module, and connecting the first output pin to be tested to the output pin of the test module.
[0053] In the method for inserting the above test circuit into an integrated circuit, based on the testable design library file of the first input pin to be tested and the first output pin to be tested, a virtual pad in digital form is established inside the top-level analog circuit of the integrated circuit. The virtual pad is configured with a second input pin to be tested corresponding to the first input pin to be tested, and a test input pin and a test output pin for connecting test signals. A test module connected to the virtual pad is inserted. Based on the connection relationship between the virtual pad and the test module, the first input pin to be tested is connected to the input pin of the test module, and the first output pin to be tested is connected to the output pin of the test module, so that the test module can perform a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested. Among them, the test input pin is respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module. By using the method provided in this application, a virtual pad in digital form is established inside the top-level analog circuit of the integrated circuit, and a test module is inserted inside the top-level analog circuit of the integrated circuit. Thus, based on the connection relationship between the virtual pad and the test module, the test module can perform a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested, overcoming the technical defect that the electronic design automation software cannot recognize the virtual pad in the top-level analog circuit and cannot insert the test module, improving the test coverage rate of the integrated circuit by improving the testability of the integrated circuit. Thus, the performance quality of the integrated circuit can be ensured.
[0054] In an exemplary embodiment, the above method for establishing a virtual pad in digital form inside the top-level analog circuit of the integrated circuit based on the testable design library file of the first input pin to be tested and the first output pin to be tested includes:
[0055] Based on the testable design library file of the first input pin to be tested and the first output pin to be tested, configuration information of the virtual pad is added to the netlist file of the top-level analog circuit to establish a virtual pad in digital form inside the top-level analog circuit.
[0056] Among them, the configuration information of the virtual pad is used to represent the second input pin to be tested corresponding to the first input pin to be tested, and the test input pin and the test output pin for connecting test signals.
[0057] Among them, the configuration information of the virtual pad is located in the testable design library file. The configuration information of the virtual pad may include pad information and pin connection relationship information of the virtual pad. Therefore, the configuration information of the virtual pad can be used to represent the second input pin to be tested corresponding to the first input pin to be tested, and the test input pin and the test output pin for connecting test signals. Thus, based on the configuration information of the virtual pad, the electronic design automation software can configure the functions and connection relationships of the virtual pad.
[0058] The netlist file of the top-level analog circuit, including a list of electronic components recording the names, types, and electrical parameters of the electronic components in the top-level analog circuit, and also including the connection relationships of the various electronic components. Based on this, the netlist file of the top-level analog circuit can be used to ensure the accuracy of the integrated circuit in circuit design, so as to ensure that the test results of the test module for circuit testing of the first input pin to be tested based on the signal input through the first input pin to be tested are accurate and consistent with the test results of the actual circuit.
[0059] In this embodiment, configuration information of virtual pads is added to the netlist file of the top-level analog circuit to establish digital virtual pads inside the top-level analog circuit. Thus, it can be ensured that the test module covers each pin of the virtual pad to comprehensively test the functions and connection relationships of the virtual pad. At the same time, since the configuration information of the virtual pad can be manually modified and configured, the configuration information of the virtual pad can be flexibly adjusted according to different test requirements to support various test modes and test strategies, improving the test flexibility and pertinence for the actual pads corresponding to the virtual pads.
[0060] In an exemplary embodiment, the above-mentioned inserting a test module connected to the virtual pad includes:
[0061] Based on the configuration information of the virtual pad, insert a test module connected to the virtual pad.
[0062] Based on the connection relationship between the virtual pad and the test module, add the configuration information of the test module to the netlist file of the top-level analog circuit.
[0063] Among them, the configuration information of the test module includes the pin types of the input pins and output pins of the test module, and the connection relationship information between the input pins, output pins and the virtual pad respectively.
[0064] In this embodiment, by adding the configuration information of the test module to the netlist file of the top-level analog circuit, the test module can be inserted into the integrated circuit and accurately connected to the virtual pad. Thus, the test module can be inserted into the integrated circuit and identify the digital virtual pad, and finally the first input pin to be tested can be circuit-tested based on the test module, improving the test coverage rate of the integrated circuit.
[0065] In an exemplary embodiment, the above-mentioned connecting the first input pin to be tested to the input pin of the test module and connecting the first output pin to be tested to the output pin of the test module includes:
[0066] Delete the connection relationship information of the virtual pad and the test module in the netlist file of the top-level analog circuit.
[0067] Based on the configuration information of the test module, connection relationship information between the integrated circuit and the test module is added to the netlist file of the top-level analog circuit, so as to connect the first input pin to be tested with the input pin of the test module and connect the first output pin to be tested with the output pin of the test module based on the connection relationship information between the integrated circuit and the test module.
[0068] In this embodiment, on the one hand, deleting the connection relationship information of the virtual pads and the test module in the netlist file of the top-level analog circuit can reduce the redundant information in the netlist file, avoid occupying resources by the redundant information, and also avoid the confusion or errors that the redundant information may cause in the subsequent integrated circuit manufacturing process, improving the reliability of the integrated circuit; on the other hand, adding the connection relationship information between the integrated circuit and the test module to the netlist file of the top-level analog circuit to realize the connection between the integrated circuit and the test module can improve the accuracy and reliability of the circuit connection by inserting the test module into the integrated circuit.
[0069] In an exemplary embodiment, the integrated circuit is configured with a plurality of first input pins to be tested and a plurality of first output pins to be tested; each of the first input pins to be tested corresponds to one of the first output pins to be tested, and each of the first input pins to be tested corresponds to a different virtual pad.
[0070] Among them, each of the first input pins to be tested corresponds to a different virtual pad, and thus, each of the first input pins to be tested corresponds to a different actual pad. Correspondingly, each of the first output pins to be tested also corresponds to a different virtual pad, and thus, each of the first output pins to be tested corresponds to a different actual pad.
[0071] In this embodiment, since the integrated circuit is configured with a plurality of first input pins to be tested and a plurality of first output pins to be tested, the test module can perform circuit tests on each of the first input pins to be tested based on the signals input by each of the first input pins to be tested. That is to say, the test module can perform circuit tests on the first input pins to be tested of multiple different types of virtual pads to indirectly perform circuit tests on multiple actual pads, improving the test coverage rate of the integrated circuit and also improving the flexibility of circuit testing.
[0072] In an exemplary embodiment, for the above-mentioned testable design library file based on the first input pin to be tested and the first output pin to be tested, digital virtual pads are established inside the top-level analog circuit of the integrated circuit, including:
[0073] Based on the target pad, determine the temporary design library file of the virtual pad corresponding to the target pad in the testable design library file of the plurality of first input pins to be tested and the plurality of first output pins to be tested.
[0074] Based on a temporary design library file, digital virtual pads are established inside the top-level analog circuit of the integrated circuit.
[0075] Among them, the target pad refers to the actual pad to be tested corresponding to the virtual pad. In other words, it is the actual pad for which the corresponding first input pin to be tested needs to be tested.
[0076] In an exemplary embodiment, the above-mentioned temporary design library file for determining the virtual pad corresponding to the target pad in the testable design library file of multiple first input pins to be tested and multiple first output pins to be tested includes: determining the first input pin to be tested of the target pad and the first output pin to be tested of the target pad in the testable design library file of multiple first input pins to be tested and multiple first output pins to be tested; based on the first input pin to be tested of the target pad and the first output pin to be tested of the target pad, determining the temporary design library file of the virtual pad corresponding to the target pad.
[0077] Specifically, since the testable design library file includes various types of pad information, pin connection relationship information of each type of pad, or other pad-related information, etc., thus, the temporary design library file obtained based on the testable design library file includes the pad information and pin connection relationship information of the target pad. Therefore, based on the temporary design library file, digital virtual pads can be established inside the top-level analog circuit of the integrated circuit, and the connection between the virtual pads and the test module can be realized in subsequent steps.
[0078] In an exemplary embodiment, after the test module performs a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested, the above method further includes: deleting the temporary design library file from inside the top-level analog circuit of the integrated circuit.
[0079] In this embodiment, based on the temporary design library file of the virtual pad corresponding to the target pad, digital virtual pads are established inside the top-level analog circuit of the integrated circuit. Thus, the pad information and pin connection relationship information of the target pad corresponding to the virtual pad can be provided for the electronic design automation software, enabling the electronic design automation software to recognize the digital virtual pads, ensuring that the test module can be smoothly inserted into the integrated circuit, and improving the test coverage rate of the integrated circuit.
[0080] In an exemplary embodiment, after the test module performs a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested, the above method further includes:
[0081] Deleting the virtual pads, the second pins to be tested, the test input pins, and the test output pins from inside the top-level analog circuit of the integrated circuit.
[0082] In this embodiment, since the virtual pad is temporarily established to solve the technical defect that the electronic design automation software cannot recognize the virtual pad in digital form in the top-layer analog circuit, after the test module is successfully inserted into the integrated circuit, the virtual pad becomes redundant information inside the top-layer analog circuit. By deleting the virtual pad, the second pins to be tested of the virtual pad, the test input pins, and the test output pins from inside the top-layer analog circuit of the integrated circuit, the redundant information in the integrated circuit can be eliminated, avoiding the occupation of resources by the redundant information, making the finally obtained integrated circuit more concise. At the same time, it can also avoid the confusion or errors that may be caused by the redundant information in the subsequent integrated circuit manufacturing process, improving the reliability of the integrated circuit.
[0083] The application process of the method for inserting the above test circuit into an integrated circuit is described below in combination with a detailed embodiment, as follows:
[0084] (1) Initial netlist file of the top-layer analog circuit
[0085] If the actual pads are pad A, pad B, and pad C, the integrated circuit is configured with multiple first pins to be tested for input corresponding to different actual pads and multiple first pins to be tested for output. Exemplarily, the multiple first pins to be tested for input are respectively the first pin to be tested for input of pad A, the first pin to be tested for input of pad B, and the first pin to be tested for input of pad C, and the multiple first pins to be tested for output are respectively the first pin to be tested for output of pad A, the first pin to be tested for output of pad B, and the first pin to be tested for output of pad C. The first pin to be tested for input of pad A corresponds to the first pin to be tested for output of pad A, the first pin to be tested for input of pad B corresponds to the first pin to be tested for output of pad B, and the first pin to be tested for input of pad C corresponds to the first pin to be tested for output of pad C. So far, the netlist file of the top-layer analog circuit of the integrated circuit is as Figure 3A shown.
[0086] (2) Netlist file after establishing a virtual pad in digital form inside the top-layer analog circuit
[0087] A testable design library file based on multiple first pins to be tested and multiple first output pins to be tested adds the configuration information of virtual pad A, virtual pad B, and virtual pad C to the netlist file of the top-level simulation circuit respectively, so as to establish virtual pad A, virtual pad B, and virtual pad C in digital form inside the top-level simulation circuit; the configuration information of each virtual pad is used to represent the second input pins to be tested corresponding to the first input pins to be tested, and the test input pins and test output pins for connecting test signals. Thus, virtual pad A is configured with the second input pins to be tested of virtual pad A, the test input pins of virtual pad A for connecting test signals, and the test output pins of virtual pad A. The configuration information of virtual pad B and virtual pad C is the same, so it will not be elaborated here. So far, the netlist file of the top-level simulation circuit of the integrated circuit is as Figure 3B shown.
[0088] (3) The netlist file after inserting the test module inside the top-level simulation circuit
[0089] Based on the configuration information of virtual pad A, insert a test module connected to virtual pad A; based on the connection relationship between virtual pad A and the test module, add the configuration information of the test module to the netlist file of the top-level simulation circuit; among them, the configuration information of the test module includes the pin types of the input pins and output pins of the test module, and the connection relationship information between the input pins, output pins and virtual pads respectively. The connection configuration of virtual pad B and virtual pad C is the same, so it will not be elaborated here. So far, the netlist file of the top-level simulation circuit of the integrated circuit is as Figure 3C shown.
[0090] (4) The final netlist file of the top-level simulation circuit
[0091] Delete the connection relationship information between virtual pad A and the test module in the netlist file of the top-level simulation circuit, and delete each virtual pad (virtual pad A, virtual pad B, virtual pad C) and the second input pins to be tested, test input pins, and test output pins of each virtual pad from inside the top-level simulation circuit of the integrated circuit; based on the configuration information of the test module, add the connection relationship information between the integrated circuit and the test module to the netlist file of the top-level simulation circuit, so as to connect the first input pins to be tested with the input pins of the test module and connect the first output pins to be tested with the output pins of the test module based on the connection relationship information between the integrated circuit and the test module, so that the test module can perform circuit testing on the first input pins to be tested based on the signals input by the first input pins to be tested. So far, the netlist file of the top-level simulation circuit of the integrated circuit is as Figure 3D shown.
[0092] In this embodiment, by adding configuration information of virtual pads to the initial netlist file of the top-layer analog circuit in the integrated circuit, digital-form virtual pads are established inside the top-layer analog circuit, and by adding configuration information of the test module to the netlist file of the top-layer analog circuit, the electronic design automation software can successfully identify the digital-form virtual pads and insert the test module into the top-layer analog circuit. Finally, by disconnecting the test module from the virtual pad and connecting the input pin of the test module to the first input pin to be tested of the integrated circuit and connecting the output pin of the test module to the first output pin to be tested of the integrated circuit, the test module can be inserted into the integrated circuit, and the test coverage rate of the integrated circuit is improved by improving the testability of the integrated circuit, so that the performance quality of the integrated circuit can be ensured.
[0093] It should be noted that the first output pin to be tested, the test input pin of the virtual pad, and the output pin of the test module in this embodiment can be a group of pins rather than a single pin respectively. Exemplarily, the first input pins to be tested of pad A, pad B, and pad C are respectively represented as A_pin, B_pin, and C_pin; the first output pin to be tested of pad A includes three pins: A_pout, A_in_enb, and A_out_en, the first output pin to be tested of pad B includes three pins: B_pout, B_in_enb, and B_out_en, and the first output pin to be tested of pad C includes three pins: C_pout, C_in_enb, and C_out_en; the input pin of the test module having a connection relationship with virtual pad A is represented as PAD_in_A, and the output pins of the test module include three pins: BSD_merged_in_enb_A, BSD_merged_out_enb_A, and BSD_merged_out_A; the second input pins to be tested of virtual pad A, virtual pad B, and pad C are respectively represented as A’, B’, and C’; the test output pins of virtual pad A each include three pins: P_A_in_enb, P_A_out_en, and P_A_out, the test output pins of virtual pad B each include three pins: P_B_in_enb, P_B_out_en, and P_B_out, and the test output pins of virtual pad C each include three pins: P_C_in_enb, P_C_out_en, and P_C_out; the test input pins of virtual pad A, virtual pad B, and virtual pad C are respectively represented as P_A_in, P_B_in, and P_C_in.
[0094] As Figure 4A shown in connection withFigure 3C Schematic diagram of the corresponding circuit structure refinement of the netlist file content after inserting a test module inside the corresponding top-level analog circuit. Based on the connection relationship between the virtual pad A and the test module, connect the test input pin P_A_in of the virtual pad A to the input pin PAD_in_A of the test module, connect P_A_in_enb among the test output pins of the virtual pad A to BSD_merged_in_enb_A among the output pins of the test module, connect P_A_out_en among the test output pins of the virtual pad A to BSD_merged_out_enb_A among the output pins of the test module, and connect P_A_out among the test output pins of the virtual pad A to BSD_merged_out_A among the output pins of the test module. Thus, the test input pin of the virtual pad A is connected to the input pin of the test module, and the pin groups of the test output pins are connected to the pin groups of the output pins of the test module.
[0095] Similarly, as Figure 4B shown for Figure 3D Schematic diagram of the corresponding circuit structure refinement of the netlist file content after inserting a test module inside the corresponding top-level analog circuit. Based on the connection relationship between the virtual pad and the test module, connect the first input pin to be measured A_pin of the pad A to the input pin PAD_in_A of the test module, connect A_pout among the first output pins to be measured to BSD_merged_in_enb_A among the output pins of the test module, connect A_in_enb among the first output pins to be measured to BSD_merged_out_enb_A among the output pins of the test module, and connect A_out_en among the first output pins to be measured to BSD_merged_out_A among the output pins of the test module. Thus, the input pin of the test module is connected to the first input pin to be measured, and the pin groups of the output pins are connected to the pin groups of the first output pins to be measured, so that the test module can perform circuit testing on the first input pin to be measured based on the signal input from the first input pin to be measured.
[0096] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless clearly stated herein, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.
[0097] Based on the same inventive concept, an embodiment of the present application further provides an apparatus for inserting a test circuit into an integrated circuit for implementing the method for inserting a test circuit into an integrated circuit as described above. The solution provided by this apparatus for solving problems is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the apparatus for inserting a test circuit into an integrated circuit provided below can refer to the limitations on the method for inserting a test circuit into an integrated circuit in the above text, and will not be elaborated here.
[0098] In an exemplary embodiment, as Figure 5 shown, an apparatus for inserting a test circuit into an integrated circuit is provided. The integrated circuit is configured with a first input pin to be tested and a first output pin to be tested. The apparatus includes: a building module 502, an inserting module 504, and a connecting module 506, where:
[0099] The building module 502 is configured to establish digital virtual pads inside the top-level analog circuit of the integrated circuit based on the testable design library files of the first input pin to be tested and the first output pin to be tested. The virtual pads are configured with a second input pin to be tested corresponding to the first input pin to be tested, and a test input pin and a test output pin for connecting test signals.
[0100] The inserting module 504 is configured to insert a test module connected to the virtual pads.
[0101] The connecting module 506 is configured to connect the first input pin to be tested to the input pin of the test module and connect the first output pin to be tested to the output pin of the test module based on the connection relationship between the virtual pads and the test module, so that the test module performs circuit testing on the first input pin to be tested based on the signal input from the first input pin to be tested.
[0102] Among them, the test input pin is respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module.
[0103] In an exemplary embodiment, the establishing module 502 is further configured to add configuration information of virtual pads to the netlist file of the top-level simulation circuit based on the testable design library files of the first input pin to be tested and the first output pin to be tested, so as to establish virtual pads in digital form inside the top-level simulation circuit; wherein, the configuration information of the virtual pads is used to represent the second input pin to be tested corresponding to the first input pin to be tested, and the test input pin and test output pin for connecting test signals.
[0104] In an exemplary embodiment, the inserting module 504 is further configured to insert a test module connected to the virtual pad based on the configuration information of the virtual pad; add configuration information of the test module to the netlist file of the top-level simulation circuit based on the connection relationship between the virtual pad and the test module; wherein, the configuration information of the test module includes the pin types of the input pin and output pin of the test module, and the connection relationship information between the input pin and output pin and the virtual pad respectively.
[0105] In an exemplary embodiment, the connecting module 506 is further configured to delete the connection relationship information between the virtual pad and the test module in the netlist file of the top-level simulation circuit; add the connection relationship information between the integrated circuit and the test module to the netlist file of the top-level simulation circuit based on the configuration information of the test module, so as to connect the first input pin to be tested with the input pin of the test module and connect the first output pin to be tested with the output pin of the test module based on the connection relationship information between the integrated circuit and the test module.
[0106] In an exemplary embodiment, the establishing module 502 is further configured to determine a temporary design library file of the virtual pad corresponding to the target pad in the testable design library files of multiple first input pins to be tested and multiple first output pins to be tested based on the target pad; establish virtual pads in digital form inside the top-level simulation circuit of the integrated circuit based on the temporary design library file.
[0107] In an exemplary embodiment, the connecting module 506 is further configured to delete the virtual pad, the second pin to be tested, the test input pin, and the test output pin from inside the top-level simulation circuit of the integrated circuit.
[0108] Each module in the above device for inserting a test circuit into an integrated circuit can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or be independent of the processor, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above respective modules.
[0109] In an exemplary embodiment, a computer device is provided. The computer device can be a server, and its internal structure diagram can be asFigure 6 As shown in the figure. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O), and a communication interface. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store testable design library files. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, it implements a method for inserting a test circuit into an integrated circuit.
[0110] In an exemplary embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 7 As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, a mobile cellular network, near field communication (Near Field Communication, NFC), or other technologies. When the computer program is executed by the processor, it implements a method for inserting a test circuit into an integrated circuit. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the computer device housing, or an external keyboard, touchpad, or mouse, etc.
[0111] Those skilled in the art can understand that Figure 7The structure shown is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device to which the solution of this application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.
[0112] In an exemplary embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.
[0113] In an exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.
[0114] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.
[0115] In an exemplary embodiment, an integrated circuit is provided, including a test module inserted by any one of the above method embodiments.
[0116] In an exemplary embodiment, a chip is provided, and the chip is obtained by testing through any one of the above method embodiments.
[0117] It should be noted that the data involved in this application (including but not limited to data for analysis, stored data, displayed data, etc.) are all information and data authorized by users or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with relevant regulations.
[0118] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.
[0119] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this application.
[0120] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims
1. A method for inserting a test circuit into an integrated circuit, characterized in that, The integrated circuit is configured with a first input pin to be tested and a first output pin to be tested. The method includes: Based on the testable design library files of the first input pin to be tested and the first output pin to be tested, digital virtual pads are established inside the top-level simulation circuit of the integrated circuit. The virtual pads are configured with a second input pin to be tested corresponding to the first input pin to be tested, and a test input pin and a test output pin for connecting test signals. Insert a test module connected to the virtual pads. Based on the connection relationship between the virtual pads and the test module, connect the first input pin to be tested to the input pin of the test module, and connect the first output pin to be tested to the output pin of the test module, so that the test module conducts a circuit test on the first input pin to be tested based on the signal input by the first input pin to be tested. Among them, the test input pin is respectively connected to the second input pin to be tested and the input pin of the test module, and the test output pin is connected to the output pin of the test module.
2. The method according to claim 1, wherein The step of establishing digital virtual pads inside the top-level simulation circuit of the integrated circuit based on the testable design library files of the first input pin to be tested and the first output pin to be tested includes: Based on the testable design library files of the first input pin to be tested and the first output pin to be tested, add the configuration information of the virtual pads to the netlist file of the top-level simulation circuit to establish digital virtual pads inside the top-level simulation circuit. Among them, the configuration information of the virtual pads is used to characterize the second input pin to be tested corresponding to the first input pin to be tested, and the test input pin and the test output pin for connecting test signals.
3. The method according to claim 2, wherein The step of inserting a test module connected to the virtual pads includes: Based on the configuration information of the virtual pads, insert a test module connected to the virtual pads. Based on the connection relationship between the virtual pads and the test module, add the configuration information of the test module to the netlist file of the top-level simulation circuit. Among them, the configuration information of the test module includes the pin types of the input pin and the output pin of the test module, and the connection relationship information between the input pin, the output pin and the virtual pads respectively.
4. The method according to claim 3, wherein The step of connecting the first input pin to be tested to the input pin of the test module and connecting the first output pin to be tested to the output pin of the test module based on the connection relationship between the virtual pads and the test module includes: Delete the connection relationship information between the virtual pads and the test module in the netlist file of the top-level simulation circuit. Based on the configuration information of the test module, add the connection relationship information between the integrated circuit and the test module to the netlist file of the top-level simulation circuit, so as to connect the first input pin to be tested to the input pin of the test module and connect the first output pin to be tested to the output pin of the test module based on the connection relationship information between the integrated circuit and the test module.
5. The method according to claim 1, wherein The integrated circuit is configured with a plurality of the first input pins to be tested and a plurality of the first output pins to be tested; each of the first input pins to be tested corresponds to one of the first output pins to be tested, and each of the first input pins to be tested corresponds to a different virtual pad.
6. The method according to claim 5, characterized in that, The testable design library file based on the first input pins to be tested and the first output pins to be tested, and establishing digital virtual pads inside the top-level analog circuit of the integrated circuit, includes: Based on the target pad, determining a temporary design library file of the virtual pad corresponding to the target pad in the testable design library files of the plurality of the first input pins to be tested and the plurality of the first output pins to be tested; Based on the temporary design library file, establishing digital virtual pads inside the top-level analog circuit of the integrated circuit.
7. The method according to any one of claims 1-6, characterized in that, After enabling the test module to perform a circuit test on the first input pins to be tested based on the signals input by the first input pins to be tested, the method further includes: Deleting the virtual pads, the second pins to be tested, the test input pins, and the test output pins from inside the top-level analog circuit of the integrated circuit.
8. The method according to any one of claims 1 to 6, characterized in that, The circuit type of the test module is a boundary scan circuit.
9. A device for inserting a test circuit into an integrated circuit, characterized in that, The integrated circuit is configured with a first input pin to be tested and a first output pin to be tested, and the device includes: A establishing module, configured to establish digital virtual pads inside the top-level analog circuit of the integrated circuit based on the testable design library file of the first input pins to be tested and the first output pins to be tested, the virtual pads being configured with second input pins to be tested corresponding to the first input pins to be tested, and test input pins and test output pins for connecting test signals; An inserting module, configured to insert a test module connected to the virtual pads; A connecting module, configured to connect the first input pins to be tested to the input pins of the test module and connect the first output pins to be tested to the output pins of the test module based on the connection relationship between the virtual pads and the test module, so that the test module performs a circuit test on the first input pins to be tested based on the signals input by the first input pins to be tested; Wherein, the test input pins are respectively connected to the second input pins to be tested and the input pins of the test module, and the test output pins are connected to the output pins of the test module.
10. An integrated circuit, characterized in that, The integrated circuit includes a test module inserted by the method according to any one of claims 1 to 8.