Cross-level gating conversion method and device, equipment and storage medium

Abstract

The embodiment of the invention discloses a cross-level gating conversion method and device, equipment and a storage medium, and the method comprises the steps: obtaining a target gating circuit diagram; identifying a connection relationship between devices in the target gating circuit diagram, and determining at least one clock path according to the connection relationship; wherein the clock path is used for representing a signal transmission path from the register to the top port; compiling a device in the clock path into a corresponding integrated unit so as to complete a conversion process of the target gating circuit diagram; wherein the integrated unit represents a device set composed of at least one register. According to the technical scheme, the clock paths in the circuit diagram can be automatically recognized, the devices in the clock paths are compiled into the corresponding integrated units, a large number of fan-out devices do not need to be processed in the conversion process, the logic copy amount is reduced, system resource consumption is reduced, and the device compiling efficiency is improved by conducting device compiling based on the clock paths. Original hierarchical structures between devices can be retained.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of data processing, and in particular, to a cross-hierarchy gating conversion method, apparatus, device, and storage medium. Background Art

[0002] In FPGA (Field-Programmable Gate Array) and ASIC (Application Specific Integrated Circuit) designs, clock signals are usually signals with very high inversion frequencies. The inversion of a circuit is essentially the charging and discharging of a capacitor, which is the circuit power consumption brought by the clock signal. In low-power designs, gated clock is a common method to reduce system power consumption. It controls the clock signal to be disabled when it is unnecessary by using an enable signal, thereby reducing system power consumption.

[0003] Gated clock adds additional logic units to the circuit. This method is sometimes not very good on FPGAs because FPGAs themselves have advanced dedicated clock resources, which are designed to optimize the setting of the clock structure to avoid clock skew. Placing a gating circuit in the middle of this structure may interfere with these resources. In addition, these clock resources are limited, and having many different gated clocks may cause problems in FPGA designs.

[0004] Existing gating conversion methods are based on flattening the design, which is relatively simple to implement but requires a large amount of uniquification processing. Especially for ultra-large-scale designs, flattening will cause memory resource consumption, a significant increase in processing time, and the original hierarchical structure of the design cannot be maintained. Summary of the Invention

[0005] The embodiments of the present invention provide a cross-hierarchy gating conversion method, apparatus, device, and storage medium. The technical solutions of the embodiments of the present invention can reduce the amount of logic replication during the conversion process, reduce system resource consumption, and enable the original hierarchical structure to be retained between the converted devices.

[0006] In a first aspect, the embodiments of the present invention provide a cross-hierarchy gating conversion method, which includes:

[0007] Obtain a target gating circuit diagram; identify the connection relationships between components in the target gating circuit diagram, and determine at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; compile the components in the clock path into corresponding synthesis units to complete the transformation process of the target gating circuit diagram, where the synthesis unit represents a set of components composed of at least one register.

[0008] In a second aspect, an embodiment of the present invention provides a cross-hierarchical gating conversion device, which includes:

[0009] A gating circuit diagram acquisition module, configured to obtain a target gating circuit diagram; a clock path identification module, configured to identify the connection relationships between components in the target gating circuit diagram and determine at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; a component compilation module, configured to compile the components in the clock path into corresponding synthesis units to complete the transformation process of the target gating circuit diagram, where the synthesis unit represents a set of components composed of at least one register.

[0010] In a third aspect, an embodiment of the present invention provides a computer device, which includes:

[0011] One or more processors;

[0012] A memory, configured to store one or more programs;

[0013] When the one or more programs are executed by the one or more processors, the one or more processors implement the cross-hierarchical gating conversion method described in any embodiment.

[0014] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, the cross-hierarchical gating conversion method described in any embodiment is implemented.

[0015] The technical solution provided by the embodiments of the present invention includes obtaining a target gating circuit diagram; identifying the connection relationships between components in the target gating circuit diagram, and determining at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; compiling the components in the clock path into corresponding synthesis units to complete the conversion process of the target gating circuit diagram, where the synthesis unit represents a set of components composed of at least one register. The technical solution of the embodiments of the present invention solves the problems in the existing gating conversion technology that affect clock resources and consume excessive system resources. It can automatically identify the clock paths in the circuit diagram, compile the components in the clock path into corresponding synthesis units, so that the conversion process does not need to process a large number of fan-out components, reduces the amount of logic replication, and thus reduces system resource consumption. By compiling components based on the clock path, the original hierarchical structure between components can be retained. Description of the Drawings

[0016] Figure 1 is a flowchart of a cross-hierarchical gating conversion method provided by an embodiment of the present invention;

[0017] Figure 2 is another flowchart of a cross-hierarchical gating conversion method provided by an embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a processed gating circuit diagram provided by an embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of a compiled gating circuit diagram provided by an embodiment of the present invention;

[0020] Figure 5 is a schematic structural diagram of a cross-hierarchical gating conversion device provided by an embodiment of the present invention;

[0021] Figure 6 is a schematic structural diagram of a computer device provided by an embodiment of the present invention. Detailed Embodiments

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0023] Figure 1It is a flowchart of a cross - level gating conversion method provided by an embodiment of the present invention. The embodiment of the present invention is applicable to the scenario of converting a gating circuit diagram. This method can be executed by a cross - level gating conversion device, and the device can be implemented in a software and / or hardware manner.

[0024] As Figure 1 shown, the cross - level gating conversion method includes the following steps:

[0025] S110. Obtain a target gating circuit diagram.

[0026] Among them, the target gating circuit diagram can be a circuit diagram that needs to perform gating conversion. Specifically, the target gating circuit diagram can be a digital circuit diagram, and the target gating circuit diagram can be composed of at least one register and at least one fan - out device connected. Further, the target gating circuit diagram can be input manually or obtained from a specified storage path. The technical solution of the embodiment of the present invention needs to adjust the clock tree in the target gating circuit diagram to optimize the circuit diagram logic design.

[0027] S120. Identify the connection relationship between devices in the target gating circuit diagram, and determine at least one clock path according to the connection relationship.

[0028] Among them, the clock path is used to represent the signal transmission path from the register to the circuit diagram input port. Therefore, the connection relationship between devices in the target gating circuit diagram can be identified first. For each register, search for the signal transmission path from the register to the circuit diagram input port in the target gating circuit diagram to obtain the clock path corresponding to the register.

[0029] S130. Compile the devices in the clock path into the corresponding synthesis unit to complete the conversion process of the target gating circuit diagram.

[0030] Among them, the synthesis unit represents a device set composed of at least one register. After determining the clock path corresponding to each register as above, the synthesis unit corresponding to each register can be determined according to the hierarchical relationship between devices in the clock path. Further, all devices in the clock path can be copied to the synthesis unit, and the copied devices can be connected according to the original connection manner of the clock path. By copying the devices in the clock path to the synthesis unit according to the original connection manner, the original design hierarchy of the devices in the target gating circuit diagram can be retained.

[0031] The technical solution provided by the embodiments of the present invention includes: obtaining a target gating circuit diagram; identifying the connection relationships between devices in the target gating circuit diagram, and determining at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; compiling the devices in the clock path into corresponding synthesis units to complete the conversion process of the target gating circuit diagram, where the synthesis unit represents a set of devices composed of at least one register. The technical solution of the embodiments of the present invention solves the problems existing in the existing gating conversion technology, such as affecting clock resources and consuming too much system resources. It can automatically identify the clock paths in the circuit diagram and compile the devices in the clock path into corresponding synthesis units, so that the conversion process does not need to process a large number of fan-out devices, reducing the amount of logic replication, and thus reducing the consumption of system resources. By compiling devices based on the clock path, the original hierarchical structure between devices can be retained.

[0032] Figure 2 FIG. 4 is a flowchart of another cross-hierarchical gating conversion method provided by the embodiments of the present invention. The embodiments of the present invention are applicable to the scenario of converting a gating circuit diagram. On the basis of the above embodiments, this embodiment further illustrates how to identify the connection relationships between devices in the target gating circuit diagram, determine at least one clock path according to the connection relationships, and how to compile the devices in the clock path into corresponding synthesis units. This device can be implemented in software and / or hardware and integrated in a computer device with application development functions.

[0033] As Figure 2 shown, the cross-hierarchical gating conversion method includes the following steps:

[0034] S210. Obtain a target gating circuit diagram.

[0035] Among them, the target gating circuit diagram may be a circuit diagram that needs to be gated-converted. Specifically, the target gating circuit diagram may be a digital circuit diagram, and the target gating circuit diagram may be formed by connecting at least one register and at least one fan-out device. Further, the target gating circuit diagram may be input manually or obtained from a specified storage path. The technical solution of the embodiments of the present invention needs to adjust the clock tree in the target gating circuit diagram to optimize the logic design of the circuit diagram.

[0036] S220. For each register in the target gating circuit diagram, search for the signal transmission path from the register to the top port to obtain the clock path corresponding to the register.

[0037] Among them, the top port can be the port with the highest hierarchical relationship in the target gated circuit diagram. Optionally, the external port in the target gated circuit diagram can be used as the top port. The top port can be specified by the user or determined after analyzing the circuit diagram. Further, the clock path is used to represent the signal transmission path from the register to the top port. Therefore, for each register, the signal transmission path from the register to the top port can be searched in the target gated circuit diagram to obtain the clock path corresponding to the register.

[0038] S230. For each clock path, identify the hierarchical relationship between the device ports in the clock path, and determine multiple synthesis units according to the hierarchical relationship.

[0039] Among them, the device ports can include the input ports and output ports of the device. The hierarchical relationship can be information representing the rank and hierarchical structure between the device ports. Specifically, the hierarchical relationship between the device ports can be determined according to the distance from the top port. Exemplarily, the device ports on the clock path can be numbered in sequence according to the order from the top port of the clock path to the output port of the register, and then the hierarchical relationship between the device ports can be determined according to the port numbers. For example, the device ports on the clock path can be numbered incrementally in sequence according to the order from the top port of the clock path to the output port of the register, so as to determine the port number of each device port. The smaller the port number, the higher the hierarchical rank of the device port.

[0040] Optionally, the port numbers on multiple clock paths can adopt the same numbering system. That is, the port numbers of the repeated device ports on multiple clock paths can remain unchanged, and only the non-repeated device ports need to be numbered additionally. For example, if the device port in the main path appears in multiple clock paths and the port number of this device port is set to 1, then in multiple clock paths, the port number of this device port is 1. By using the same numbering system to number the device ports, it is convenient to divide the synthesis units in the target gated circuit diagram based on the device numbers later and reduce the interference of complicated numbering methods.

[0041] Optionally, when there is a direct connection between two device ports, the port numbers of the two device ports are set to the same number. For example, if the input port of device A and the output port of device B are directly connected, the port numbers of the input port of device A and the output port of device B can be both set to 3. In actual design, there may be a lot of gated clock logic, and the output clock of the same gated logic may fan out to a large number of sequential devices at different levels or modules. By uniformly numbering the interconnected ports, cross-level connections are supported, and different port information corresponding to each number is collected. The clock ports of all sequential devices fanned out by the same gated logic have the same number. In this way, when searching for the clock path, the path of the same clock logic only needs to be searched once, and there is no need to search for each fan-out, avoiding a large number of repeated clock path searches.

[0042] Furthermore, the synthesis unit represents a set of devices composed of at least one register. Specifically, starting from the top port, all devices with port numbers greater than or equal to the port number of the top port form the synthesis unit with the highest hierarchical relationship; then find the device port a at the next level below the top port with the port number only greater than the top port, and all devices with port numbers greater than or equal to the port number of device port a form the synthesis unit with the second highest hierarchical relationship; and so on, until all devices with port numbers greater than or equal to the port number of the register port form the synthesis unit with the lowest hierarchical relationship.

[0043] Exemplarily, Figure 3 is a schematic diagram of a processed gated clock circuit diagram provided by an embodiment of the present invention. As Figure 3 shown, there are two registers in the figure, so there are a total of two corresponding clock path rules. The device ports are numbered on the clock path, and the number values range from 0 to 6, where the port numbers of two directly connected device ports are the same. The output of the AND gate serves as the clock input of the two lower-level registers, so the output port of the AND gate and the clock ports of the registers are set to the same number. The box composed of solid lines can be understood as a synthesis unit. Among them, starting from the top port (the top port numbered 0), all devices with port numbers greater than or equal to 0 form the synthesis unit with the highest hierarchical relationship; then all devices with port numbers greater than or equal to 1 form the synthesis unit with the second highest hierarchical relationship; and then all devices with port numbers greater than or equal to 2 form the synthesis unit with the lowest hierarchical relationship. There are two basic synthesis units in the figure, that is, each clock path has a corresponding basic synthesis unit.

[0044] S240. Compile the devices in the clock path into the basic synthesis unit corresponding to the clock path.

[0045] Among them, the basic integrated unit is the integrated unit with the lowest hierarchical relationship. As can be seen from the above, the basic integrated unit is an integrated unit composed of devices with port numbers greater than or equal to the port number of the register port. Further, all the devices in the clock path can be copied into the basic integrated unit, and the copied devices are connected according to the original connection mode of the clock path. By copying the devices in the clock path into the basic integrated unit according to the original connection mode, the original design hierarchy of the devices in the target gating circuit diagram can be retained.

[0046] Optionally, the clock signal ports of the newly copied registers can be respectively connected to the clock input ports of all the fan-out devices in the original clock path, and the enable signal ports of the newly copied registers can be respectively connected to the enable input ports of all the fan-out devices in the original enable path.

[0047] To avoid logic replication and uniquification to the greatest extent, the present invention only copies the devices and connections on the clock path into the same integrated unit, and then the new clock logic is fan-out to a newly added register, and a special attribute is added to the register. It is not necessary to copy all the fan-outs of the original clock logic into this integrated unit (especially when there are many sequential devices with gated logic fan-outs, copying or re-wiring them will cause hierarchical changes and a large amount of uniquification processing, resulting in resource inflation). After synthesis, find the newly added register in the synthesized netlist, and then connect the clock and enable of the register to all the fan-out sequential devices of the original clock logic.

[0048] Exemplarily, to better understand the technical solution provided by the present invention, the following is an introduction to specific embodiments: Figure 4 It is a schematic diagram of a gated circuit diagram after compilation provided by an embodiment of the present invention. As Figure 4 shown, for each basic integrated unit, all the devices in the clock path can be copied into the basic integrated unit, and the copied devices are connected according to the original connection mode of the clock path. In addition, the default register of each clock path and each recorded fan-out device can be found, pull out the clock signal and enable signal of the default register, disconnect the clock input of the fan-out device, and directly or hierarchically connect the clock signal of the default register to the clock port of the fan-out device. At the same time, if the fan-out device itself has an enable input, first disconnect the enable input, and then AND the enable signal pulled from the default register with the enable of the fan-out device itself as the enable of the fan-out device. If the fan-out device itself has no enable input, the enable signal of the default register can be directly or hierarchically connected to the enable port of the fan-out device.

[0049] The technical solution provided by the embodiments of the present invention obtains a target gating circuit diagram; for each register in the target gating circuit diagram, searches for the signal transmission path from the register to the top interface to obtain the clock path corresponding to the register; for each clock path, identifies the hierarchical relationship between the device ports in the clock path, and determines a plurality of hierarchical synthesis units according to the hierarchical relationship; and compiles the devices in the clock path into the basic synthesis unit corresponding to the clock path. The technical solution of the embodiments of the present invention solves the problems existing in the existing gating conversion technology that affect the clock resources and consume too much system resources. It can automatically identify the clock paths in the circuit diagram and compile the devices in the clock paths into the corresponding synthesis units, so that the conversion process does not have to process a large number of fan-out devices, reduces the amount of logic replication, and thus reduces the consumption of system resources. By compiling devices based on the clock path, the original hierarchical structure between devices can be retained.

[0050] Figure 5 FIG. is a schematic structural diagram of a cross-hierarchical gating conversion device provided by an embodiment of the present invention. The embodiments of the present invention are applicable to the scenario of converting a gating circuit diagram. The device can be implemented in a software and / or hardware manner and integrated into a computer device with application development functions.

[0051] As Figure 5 shown, the cross-hierarchical gating conversion device includes: a gating circuit diagram acquisition module 310, a clock path identification module 320, and a device compilation module 330.

[0052] Among them, the gating circuit diagram acquisition module 310 is configured to acquire a target gating circuit diagram; the clock path identification module 320 is configured to identify the connection relationship between devices in the target gating circuit diagram and determine at least one clock path according to the connection relationship, where the clock path is used to represent the signal transmission path from the register to the top port; the device compilation module 330 is configured to compile the devices in the clock path into the corresponding synthesis unit to complete the conversion process of the target gating circuit diagram, where the synthesis unit represents a device set composed of at least one register.

[0053] The technical solution provided by the embodiments of the present invention includes: obtaining a target gating circuit diagram; identifying the connection relationships between devices in the target gating circuit diagram, and determining at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; compiling the devices in the clock path into corresponding synthesis units to complete the conversion process of the target gating circuit diagram, where the synthesis unit represents a set of devices composed of at least one register. The technical solution of the embodiments of the present invention solves the problems existing in the existing gating conversion technology, such as affecting clock resources and consuming excessive system resources. It can automatically identify the clock paths in the circuit diagram, compile the devices in the clock path into corresponding synthesis units, so that the conversion process does not need to process a large number of fan-out devices, reduces the amount of logic replication, and further reduces the consumption of system resources. By compiling devices based on the clock path, the original hierarchical structure between devices can be retained.

[0054] In an alternative embodiment, the clock path identification module 320 is specifically configured to: for each register in the target gating circuit diagram, search for the signal transmission path from the register to the top interface to obtain the clock path corresponding to the register.

[0055] In an alternative embodiment, the device compilation module 330 is specifically configured to: for each clock path, identify the hierarchical relationship between the device ports in the clock path, and determine a plurality of hierarchical synthesis units according to the hierarchical relationship; compile the devices in the clock path into the basic synthesis unit corresponding to the clock path, where the basic synthesis unit is the synthesis unit with the lowest hierarchical relationship.

[0056] In an alternative embodiment, the device compilation module 330 includes: a hierarchical relationship determination unit, configured to: number the device ports on the clock path in sequence according to the order from the top interface of the clock path to the output port of the register, and determine the hierarchical relationship between the device ports according to the port numbers.

[0057] In an alternative embodiment, the hierarchical relationship determination unit includes: a device port numbering subunit, configured to: when there is a direct connection relationship between two device ports, set the port numbers of the two device ports to the same number.

[0058] In an alternative embodiment, the device compilation module 330 further includes: a device replication unit, configured to: replicate all the devices in the clock path to the basic synthesis unit, and connect the replicated devices in the original connection manner of the clock path.

[0059] In an alternative embodiment, the device replication unit includes: a signal port connection sub-unit, configured to: connect the clock signal ports of the newly replicated registers to the clock input ports of all the fan-out devices in the original clock path respectively, and connect the enable signal ports of the newly replicated registers to the enable input ports of all the fan-out devices in the original enable path respectively.

[0060] The cross-hierarchical gating conversion device provided by the embodiments of the present invention can execute the cross-hierarchical gating conversion method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.

[0061] Figure 6 It is a schematic structural diagram of a computer device provided by an embodiment of the present invention. Figure 6 It shows a block diagram of an exemplary computer device 12 suitable for implementing the embodiments of the present invention. Figure 6 The shown computer device 12 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention. The computer device 12 can be any terminal device with computing capabilities and can be configured in a cross-hierarchical gating conversion device.

[0062] As Figure 6 shown, the computer device 12 is presented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0063] The bus 18 can be one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any bus structure in a variety of bus structures. For example, these architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0064] The computer device 12 typically includes a variety of computer system-readable media. These media can be any available media accessible by the computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0065] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache 32. The computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used for reading and writing on non-removable, non-volatile magnetic media ( Figure 6 not shown, typically referred to as a "hard disk drive"). Although Figure 6 not shown in, a disk drive for reading and writing on removable non-volatile disks (such as a "floppy disk"), and an optical disk drive for reading and writing on removable non-volatile optical disks (such as CD-ROM, DVD-ROM or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 through one or more data media ports. The system memory 28 may include at least one program product having a set (such as at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0066] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the system memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods in the embodiments described in the present invention.

[0067] The computer device 12 may also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and may also communicate with one or more devices that enable a user to interact with the computer device 12, and / or communicate with any device that enables the computer device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication may be carried out through the input / output (I / O) port 22. And, the computer device 12 may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 20. As Figure 6 shown, the network adapter 20 communicates with other modules of the computer device 12 through the bus 18. It should be understood that although Figure 6 not shown in, other hardware and / or software modules may be used in conjunction with the computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0068] The processing unit 16 executes various functional applications and data processing by running the programs stored in the system memory 28, such as implementing the cross-level gating conversion method provided by the embodiments of the present invention. The method includes:

[0069] Obtain a target gating circuit diagram; identify the connection relationships between the devices in the target gating circuit diagram, and determine at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; compile the devices in the clock path into corresponding synthesis units to complete the conversion process of the target gating circuit diagram, where the synthesis unit represents a set of devices composed of at least one register.

[0070] This embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the cross-level gating conversion method provided by any embodiment of the present invention, including:

[0071] Obtain a target gating circuit diagram; identify the connection relationships between the devices in the target gating circuit diagram, and determine at least one clock path according to the connection relationships, where the clock path is used to represent the signal transmission path from a register to a top port; compile the devices in the clock path into corresponding synthesis units to complete the conversion process of the target gating circuit diagram, where the synthesis unit represents a set of devices composed of at least one register.

[0072] The computer storage medium of the embodiments of the present invention may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to: an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the computer-readable storage medium include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device.

[0073] A computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0074] The program code contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0075] The computer program code for performing the operations of the present invention may be written in one or more programming languages or combinations thereof. The programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0076] Those of ordinary skill in the art should understand that the various modules or steps of the present invention described above may be implemented using a general-purpose computing device. They may be centralized on a single computing device or distributed across a network composed of multiple computing devices. Optionally, they may be implemented using program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them may be fabricated into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0077] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A cross - level gating conversion method, characterized in that, Including: Obtain the target gated circuit diagram; Identify the connection relationships between devices in the target gated circuit diagram, and determine at least one clock path according to the connection relationships; wherein, the clock path is used to represent the signal transmission path from the register to the top port; Compile the devices in the clock path into corresponding synthesis units to complete the transformation process of the target gated circuit diagram; wherein, the synthesis unit represents a set of devices composed of at least one register.

2. The method according to claim 1, characterized in that, The identifying the connection relationships between devices in the target gated circuit diagram and determining at least one clock path according to the connection relationships includes: For each register in the target gated circuit diagram, search for the signal transmission path from the register to the top port to obtain the clock path corresponding to the register.

3. The method according to claim 1, wherein The compiling the devices in the clock path into corresponding synthesis units includes: For each clock path, identify the hierarchical relationships between device ports in the clock path, and determine multiple synthesis units according to the hierarchical relationships; Compile the devices in the clock path into the basic synthesis unit corresponding to the clock path; wherein, the basic synthesis unit is the synthesis unit with the lowest hierarchical relationship.

4. The method according to claim 3, wherein The identifying the hierarchical relationships between device ports in the clock path includes: Number the device ports on the clock path in sequence according to the order from the top port of the clock path to the output port of the register, and determine the hierarchical relationships between the device ports according to the port numbers.

5. The method according to claim 4, wherein The sequentially numbering the device ports on the clock path includes: In the case where there is a direct connection relationship between two device ports, set the port numbers of the two device ports to the same number.

6. The method according to claim 3, wherein The compiling the devices in the clock path into the basic synthesis unit corresponding to the clock path includes: Copy all the devices in the clock path into the basic synthesis unit, and connect the copied devices according to the original connection manner of the clock path.

7. The method according to claim 6, wherein The method further includes: Connect the clock signal ports of the newly copied registers to the clock input ports of all the fan-out devices in the original clock path respectively, and connect the enable signal ports of the newly copied registers to the enable input ports of all the fan-out devices in the original enable path respectively.

8. A cross-level gating conversion device, characterized in that The device includes: A gated circuit diagram acquisition module, configured to obtain a target gated circuit diagram; A clock path identification module, configured to identify the connection relationships between devices in the target gated circuit diagram, and determine at least one clock path according to the connection relationships; wherein, the clock path is used to represent the signal transmission path from the register to the top port; A device compilation module, configured to compile the devices in the clock path into corresponding synthesis units to complete the transformation process of the target gated circuit diagram; wherein, the synthesis unit represents a set of devices composed of at least one register.

9. A computer device, characterized in that, The computer device includes: One or more processors; A memory, configured to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the cross-level gating conversion method according to any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, the cross-level gating conversion method according to any one of claims 1-7 is implemented.

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