Chip initial layout method and device and terminal equipment

Abstract

The invention discloses a chip initial layout method and device and terminal equipment, and the method comprises the steps: traversing a specified parent module of a chip hierarchical structure and sub-modules included in the specified parent module, and expanding the area of a layout region; performing hierarchical clustering on the sub-modules to generate corresponding clustering modules; traversing the pin of each sub-module in each clustering module, and mapping the pin of each sub-module to the central position of the clustering module; establishing a network connection relationship between the clustering modules according to a network connected with the pins of the sub-modules; and constructing a quadratic programming model based on the line network connection weight and the module overlapping repulsive force between the clustering modules, and iteratively optimizing to generate a two-dimensional layout area. According to the method, the cross-layer module can be rapidly divided and arranged in a more reasonable mode, unnecessary cross-layer connection lines are reduced, and a more stable initial solution is provided for the subsequent 3D-EFS layout optimization process.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit layout, and particularly to a method, device and terminal device for initial chip layout. Background Art

[0002] With the continuous expansion of the scale of integrated circuit (IC) design, three-dimensional integrated circuit (3D-IC) has gradually become an important development direction in the chip industry due to its higher integration density, shorter interconnect length, and lower power consumption. Currently, mainstream 3D-IC design research mainly focuses on the hybrid layout of macro cells and standard cells. In the actual layout process, the common practice is to reasonably allocate macro cells and standard cells to the top die and bottom die based on comprehensive consideration of the wire length and the number of vias (such as vertical interconnect channels). For this purpose, various three-dimensional layout algorithms have been proposed in the prior art, such as the layout method based on temperature perception, the optimization method based on genetic ideas, and the physical model based on electric field force. Most of these methods take the hybrid layout of macro cells and standard cells as the main goal, and improve the performance and integration density of 3D-IC through various optimization strategies.

[0003] The existing three-dimensional layout planning methods have certain limitations in the 3D-EFS (3D Early Floorplan Synthesis) scenario. First, 3D-EFS requires hierarchical clustering and packing of modules, and reasonably dividing these packed modules into different chip layers to further shorten the wire length between modules, accelerate data transmission speed, and improve the overall chip performance.

[0004] However, the existing layout algorithms fail to effectively handle this special requirement of "module packing layout" and cannot quickly output a high-quality initial layout suitable for this scenario. Secondly, in the two-dimensional layout stage, traditional secondary layout algorithms need to repeatedly calculate the wire attraction force and the unit overlap repulsion force, and generate a layout solution through multiple iterations of optimization. In the complex wire structure of 3D-EFS, directly applying these algorithms not only has low efficiency, but also because of unnecessary attention to all unit connection and overlap relationships, the layout result is difficult to meet the requirements of 3D-EFS.

[0005] Based on this, a new technical solution is needed. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a method, device and terminal device for initial chip layout to at least solve the problems existing in the existing three-dimensional layout planning methods.

[0007] Embodiments of the present invention provide the following technical solutions:

[0008] An embodiment of the present invention provides a method for initial chip layout, including:

[0009] Traverse the specified parent module of the chip hierarchical structure and the sub-modules included in the specified parent module, and expand the area of the layout region;

[0010] Hierarchically cluster the sub-modules to generate corresponding clustering modules, and each clustering module inherits the total area, network connection relationship, and pin information of the corresponding sub-module;

[0011] Traverse the pins of each sub-module in each clustering module, and map the pins of each sub-module to the central position of the clustering module;

[0012] Establish a netlist connection relationship between the clustering modules according to the network connected by the pins of the sub-modules, where the repeated network connections between the sub-modules can increase the netlist connection weight between the corresponding clustering modules;

[0013] Based on the netlist connection weight and module overlapping repulsion between the clustering modules, construct a quadratic programming model and iteratively optimize to generate a two-dimensional layout region;

[0014] Divide the clustering modules in the two-dimensional layout region into the top-layer chip and the bottom-layer chip;

[0015] Shrink the area of the layout region, and in the top-layer chip and the bottom-layer chip, iteratively generate a three-dimensional initial layout according to the netlist connection weight and module overlapping repulsion between the clustering modules.

[0016] Further, the dividing the clustering modules in the two-dimensional layout region into the top-layer chip and the bottom-layer chip includes:

[0017] Divide the two-dimensional layout region into N*N panes, and divide the clustering modules into the top-layer chip and the bottom-layer chip according to the pane position where the center point of the clustering module is located and the area utilization rate of the top-layer chip and the bottom-layer chip.

[0018] Further, when dividing the clustering modules into the top-layer chip and the bottom-layer chip, if the area utilization rate of the top-layer chip or the bottom-layer chip exceeds a preset threshold, the clustering module is preferentially allocated to the chip with a smaller area utilization rate.

[0019] Further, the shrinking the area of the layout region includes:

[0020] Shrink the area of the layout region according to a preset ratio;

[0021] In the top - layer chip and the bottom - layer chip, based on the wire - net connection weights and the module overlap repulsion, iteratively optimize the positions of their respective clustering modules to generate the three - dimensional initial layout.

[0022] Further, the clustering modules include designated clustering modules and non - designated clustering modules;

[0023] The designated clustering modules include designated sub - modules in the designated parent module, and the non - designated clustering modules include non - designated sub - modules in the designated parent module.

[0024] Further, the clustering modules are distributed at intervals on the enlarged layout area.

[0025] Further, establishing the wire - net connection relationship between the clustering modules according to the network connected by the sub - module pins includes:

[0026] Obtain the network information connected by the pins of each sub - module, and determine all the clustering modules connected by the pins in the network information;

[0027] Traverse all the network information, and record the wire - net connection relationship between the mutually connected clustering modules into the netlist.

[0028] Further, based on the wire - net connection weights and module overlap repulsion between the clustering modules, constructing a quadratic programming model and iteratively optimizing to generate a two - dimensional layout area includes:

[0029] Perform wire - net modeling based on the clustering modules and a preset wire - net model, establish the wire - net connection relationship between the clustering modules, and obtain the wire - net connection weights;

[0030] Based on the wire - net connection weights and module overlap repulsion between the clustering modules, construct the coefficient matrix and the target vector required for quadratic programming solution, and use the quadratic programming algorithm to iteratively generate a two - dimensional layout area.

[0031] The present invention also provides a chip initial layout device, including:

[0032] A traversal module, which is used to traverse the designated parent module of the chip hierarchical structure and the sub - modules included in the designated parent module, expand the area of the layout area, and traverse the pins of the sub - modules;

[0033] A clustering module, which is used to hierarchically cluster the sub - modules to generate corresponding clustering modules, and each clustering module inherits the total area, network connection relationship, and pin information of the corresponding sub - module;

[0034] A mapping module, which is used to map the pins of the sub - modules to the central positions of the clustering modules;

[0035] A building module, which is used to establish a netlist connection relationship between the clustering modules according to the network connected to the pins of the sub-modules, wherein the repeated network connections between the sub-modules can increase the netlist connection weight between the corresponding clustering modules;

[0036] An iterative generation module, which is used to construct a quadratic programming model based on the netlist connection weight and module overlap repulsion between the clustering modules, and iteratively optimize to generate a two-dimensional layout area, and divide the clustering modules in the two-dimensional layout area into the top chip and the bottom chip; shrink the area of the layout area, and in the top chip and the bottom chip, iteratively generate a three-dimensional initial layout according to the netlist connection weight and module overlap repulsion between the clustering modules.

[0037] An embodiment of the present invention further provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the chip initial layout method described in any one of the above are implemented.

[0038] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve at least the following beneficial effects:

[0039] A chip initial layout method of the present invention can quickly obtain a reasonable three-dimensional chip initial layout through a complete process from hierarchical structure analysis, clustering to two-dimensional optimization, and then to three-dimensional hierarchical legalization. The present invention fully considers the hierarchical relationship of modules and can use the hierarchical structure specified by the user to guide clustering, so that cross-layer modules can be quickly divided and laid out in a more reasonable manner; and by maintaining the logical integrity of the clustering modules during the layout stage, unnecessary cross-layer connections are reduced, providing a more stable initial solution for the subsequent 3D-EFS layout optimization process. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0041] Figure 1 It is a flowchart of a chip initial layout method according to an embodiment of the present invention;

[0042] Figure 2 It is a schematic diagram of a user-specified hierarchical module according to an embodiment of the present invention;

[0043] Figure 3 It is the overall flowchart of the implementation of a chip initial layout method according to an embodiment of the present invention;

[0044] Figure 4 It is a schematic flowchart of a chip initial layout method according to an embodiment of the present invention;

[0045] Figure 5 It is a window division diagram of a chip initial layout method according to an embodiment of the present invention. Specific embodiments

[0046] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0047] The following illustrates the embodiments of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The present application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0048] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0049] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. The diagrams only show the components related to the present application, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be an arbitrary change, and the component layout type may also be more complex.

[0050] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0051] Based on the deficiencies of existing three-dimensional layout methods, the inventors conducted in-depth research and improvement exploration on hierarchical clustering and window partitioning, and found that: by clustering the modules below a specified level according to the modules at the level specified by the user, and based on the clustering modules formed by this clustering method, using a quadratic programming layout algorithm to generate a two-dimensional initial layout, and finally using a window-based partitioning method to iterate the two-dimensional initial layout into a three-dimensional chip initial layout to legally obtain a high-quality initial solution that meets the requirements of the composite 3D-EFS scenario.

[0052] Based on this, an embodiment of this specification proposes a processing solution: as Figures 1 to 5 shown, a three-dimensional chip initial layout method based on hierarchical clustering and window partitioning of the present invention clusters the specified modules hierarchically, inherits the area, utilization rate, and network information of the sub-modules, uses an improved quadratic programming layout algorithm to place the clustering modules in two-dimensional positions, and finally uses a window-based partitioning method to obtain a three-dimensional legalized layout, thereby being able to provide an efficient and stable initial solution for subsequent three-dimensional integrated circuit layout;

[0053] Specifically, the present invention expands the layout area, clusters the hierarchical modules according to the user settings, and generates a two-dimensional layout solution based on the attraction generated by the nets between the clustering modules and the repulsion generated by module overlaps. Subsequently, a window partitioning method is adopted, such as dividing the two-dimensional layout solution into 4*4 panes, and dividing the clustering modules into two chips according to the positions of the clustering modules in the panes and the area occupancy rate in the chip; finally, the position coordinates of the clustering modules are shrunk, and the final three-dimensional initial layout is obtained iteratively based on the attraction generated by the nets and the repulsion generated by module overlaps in the two-layer chips.

[0054] More specifically, by specifying the parent module and its sub-modules in the chip hierarchical structure, clustering these sub-modules, and uniformly inheriting the area, network connection relationship, and pin information. Subsequently, by performing central mapping on the sub-module pins of each clustering module and establishing the net weights between modules based on the network relationship, the complex unit-level network connections in the original design are effectively simplified, the scale and complexity of the local optimization target are significantly reduced, and the problem that existing algorithms are difficult to handle large-scale "module packing layout" scenarios is solved, providing a feasible and efficient initial layout strategy for new three-dimensional integrated circuits such as 3D-EFS.

[0055] Furthermore, in the two-dimensional layout stage, by constructing a quadratic programming model only for the net connection weights and module overlap repulsion between clustering modules, the number of objects participating in iterative calculations is significantly reduced. Combining the pane division and area utilization balance mechanism, the clustering modules are reasonably allocated to the top and bottom chips, and hierarchical optimization continues after shrinking the layout area, finally efficiently outputting a three-dimensional initial layout that meets the special requirements of 3D-EFS. Compared with the traditional quadratic layout algorithm that directly acts on all units, the present invention effectively avoids inefficient and irrelevant iterations, significantly improves the layout efficiency and quality, and better adapts to the actual application requirements under the complex net structure of three-dimensional chips.

[0056] The following describes the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.

[0057] As Figures 1 to 5 shown, a method for initial chip layout of the present invention includes:

[0058] Step S102, traverse the specified parent module of the chip hierarchical structure and the sub-modules included in the specified parent module, and expand the layout area.

[0059] Among them, traversing the specified parent module of the chip hierarchical structure means traversing all parent modules at the user-specified levels, and then traversing all sub-modules included in the parent module. By analyzing and traversing the user-specified parent module and all its sub-modules in the chip design, the orderly screening and information collection of layout objects are realized.

[0060] Among them, expanding the layout area is used to reserve physical space for the subsequent clustering and optimization stages, preventing initial congestion and overlap from affecting the optimization effect.

[0061] Among them, the layout area can be expanded proportionally or appropriately according to the number of modules. The purpose is to enable the subsequent clustering modules to be distributed on the layout area without overlap.

[0062] Step S102 is used to lay a data foundation for the packaged layout of modules, enabling the entire process to focus on the designer's structural units, providing a good initial distribution environment for large-scale modules, and improving the feasibility of the initial solution.

[0063] Step S104, hierarchically cluster the sub-modules to generate corresponding clustering modules, and each clustering module inherits the total area, network connection relationship, and pin information of the corresponding sub-module.

[0064] Among them, the clustering modules include specified clustering modules and non-specified clustering modules; the specified clustering modules include the specified sub-modules in the specified parent module, and the non-specified clustering modules include the non-specified sub-modules in the specified parent module.

[0065] Among them, the specified clustering module is a clustering module formed by sub - modules specified by the user; the non - specified clustering module is a clustering module automatically clustered by sub - modules not specified by the user.

[0066] Among them, by classifying the clustering modules into two categories: specified and non - specified, the layout process can be processed separately as needed, achieving precise control of key modules, so as to overcome the problem that existing methods cannot flexibly meet diverse requirements; and the non - specified clustering modules participate in automatic packaging and optimization as ordinary background structures, which also effectively reduces the overall complexity.

[0067] Among them, the total area of the clustering module can be obtained according to the total area of the sub - modules and the specified area utilization rate. For example, the total area of the clustering module is obtained by dividing the total area of the sub - modules by the specified area utilization rate, so as to distribute the clustering modules on the enlarged layout area according to the total area.

[0068] For example, as Figure 2 shown, all the modules shown in the figure are hierarchical modules. There are three modules A, B, and C under the top module. Module A has three modules D, E, and F. Module B has two modules G and H. The user specifies that module A and module G are clustered respectively. The obtained results are three clustering modules I, J, and K (the K clustering module is automatically clustered by the sub - modules not specified). Module I contains all the modules in module A, that is, the three modules D, E, and F; module J only contains module G; module K contains module C and module H in module B.

[0069] Furthermore, the clustering modules are distributed at intervals on the enlarged layout area, so that when initially placing each clustering module, each clustering module can be evenly distributed in the expanded layout space without significant accumulation, avoiding serious overlap and density caused by the concentration of clustering modules in a local area at the initial stage, providing a good starting point for secondary layout optimization, and improving the convergence speed of the optimization algorithm and the final layout quality.

[0070] Step S104 uses the hierarchical clustering method to merge the sub - modules specified by the user into a clustering module and completely inherit the key attributes, thus eliminating the redundant connection operations in the original netlist and raising the optimization focus from numerous tiny units to a more representative module set.

[0071] Through step S104, the amount of calculation and the complexity of network relationships can be greatly reduced, which can provide a concise but information - complete input for subsequent secondary layout optimization, while retaining the functional boundaries of each module, and solving the problem that existing algorithms are difficult to adapt to module - level layout.

[0072] Step S106 traverses the pins of each sub - module in each of the clustering modules and maps the pins of each sub - module to the center position of the clustering module.

[0073] In step S106, by physically converging the pins of the sub-modules of the same clustering module to the center of the clustering module, the reference coordinates for subsequent grid modeling are unified, thereby avoiding the overestimation or error of the wire length caused by the scattered spatial distribution of the sub-modules and ensuring the accuracy of network modeling.

[0074] For example, after the user specifies the modules to be clustered, all clustering modules will inherit the wire network information of the sub-modules, build the network connection relationship between the clustering modules, and place the pins at the center position of the clustering module.

[0075] Through step S106, an accurate physical basis can be provided for the establishment of wire network relationships, making the layout optimization objective function more intuitive and reasonable, so as to further reduce the complexity of subsequent wire length estimation and improve the overall layout quality.

[0076] Step S108: Establish the wire network connection relationship between the clustering modules according to the network connected by the pins of the sub-modules. Among them, the repeated network connections between the sub-modules can increase the wire network connection weight corresponding to the clustering modules.

[0077] In step S108, by counting the number of all interconnected networks between the clustering modules, a weighted inter-module network relationship graph is established, and the weight setting also reflects the strength of the actual electrical connection between different clustering modules (i.e., the gravitational force between the clustering modules), which is beneficial to correctly measuring the driving force of approaching or moving away during the optimization process.

[0078] Among them, the greater the weight between the clustering modules, the stronger the connection gravitational force between them.

[0079] Specifically, step S108 includes:

[0080] Step S108a: Obtain the network information connected by the pins of each sub-module and determine all the clustering modules connected by the pins in the network information;

[0081] Step S108b: Traverse all the network information and record the wire network connection relationship between the interconnected clustering modules in the netlist.

[0082] Steps S108a and S108b systematically obtain the actual network connection conditions of each sub-module pin, trace to the affiliated clustering module through the mapping relationship, then traverse all the network information, summarize the clustering modules involved in each network, abstract these interconnected clustering modules into an effective edge in the network diagram, clearly record it in the netlist, and automatically accumulate the weight of the repeatedly occurring network to reflect the true signal interaction strength between the modules.

[0083] Steps S108a and S108b greatly simplify the scale of network modeling, and can provide highly relevant and non-redundant inputs for subsequent layout objective function modeling and physical implementation, effectively solving the problems of huge and redundant network model scale and increased useless computational amount caused by only relying on network information at the original sub-module level, and improving the efficiency in complex wire network scenarios such as 3D-EFS.

[0084] Through step S108, the true path signal requirements after the clustering module is packed can be reflected, that is, unnecessary consideration of all unit-level connections is avoided, and key paths are ensured to be optimized, fundamentally improving the layout search efficiency and controllability.

[0085] Step S110: Based on the wire network connection weights and module overlap repulsion forces between the clustering modules, construct a quadratic programming model, and iteratively optimize to generate a two-dimensional layout area.

[0086] In step S110, by converting the attracting (wire network) and repelling (overlap) factors between the clustering modules into a quadratic programming module, the optimal two-dimensional placement of the modules can be achieved through a finite number of iterations.

[0087] Among them, by only targeting the clustering modules instead of all units participating in the optimization, the scale of the solution is greatly reduced.

[0088] Among them, when iteratively optimizing to generate a two-dimensional layout area, the total area of the clustering modules also needs to be considered, and the optimal two-dimensional layout area is obtained based on the total area of the clustering modules, the wire network connection weights and the module overlap repulsion forces, that is, the optimal placement positions of the clustering modules at the two-dimensional level are obtained.

[0089] Step S110 includes:

[0090] Step S110a: Based on the clustering modules and a preset wire network model, perform wire network modeling, establish the wire network connection relationship between the clustering modules, and obtain the wire network connection weights;

[0091] Step S110b: Based on the wire network connection weights and module overlap repulsion forces between the clustering modules, construct the coefficient matrix and target vector required for quadratic programming solution, and use the quadratic programming algorithm to iteratively generate a two-dimensional layout area.

[0092] Among them, the wire network weights between the clustering modules are obtained based on the clustering modules and a preset wire network model, so that irrelevant fine-grained units can be excluded, and according to the wire network connection weights and the overlap repulsion forces between the modules, a quadratic optimization objective is constructed, and the coefficient matrix and target vector are constructed, and the goal of "bringing closer modules with strong connections and avoiding overlap" can also be achieved.

[0093] Steps S110a and S110b can significantly reduce the number of calculation objects and redundant edges, improve the optimization speed, and solve the problem that traditional methods are difficult to efficiently apply to large-scale complex 3D-EFS designs. For example, the traditional quadratic programming algorithm directly takes all units as objects and needs to repeatedly calculate massive attraction / repulsion terms. In the 3D-EFS scenario, the calculation amount increases dramatically due to the complex wire network structure, making it difficult to converge.

[0094] Step S110 can break through the inefficiency of traditional algorithms in large-scale 3D scenes, significantly speed up the generation of layout results, and the optimization target is highly consistent with engineering reality, which can provide a high-quality initial solution for subsequent three-dimensional layering and legalization.

[0095] Step S112: Divide the cluster modules in the two-dimensional layout area into top-layer chips and bottom-layer chips.

[0096] Through window partitioning and area utilization evaluation, cluster modules in two-dimensional space are automatically assigned to different chip layers. This not only reflects the layered nature of three-dimensional integrated circuits, but also facilitates balancing the utilization of resources on different layers.

[0097] Step S112 can effectively connect two-dimensional optimization and three-dimensional stratification, realize the automated deployment of stratification strategies in scenarios such as 3D-EFS, and solve problems such as cumbersome manual intervention and uncontrollable stratification effects.

[0098] Step S114 , shrinking the layout area, and iteratively generating a three-dimensional initial layout in the top chip and the bottom chip according to the line network connection weights and module overlap repulsion between the clustering modules.

[0099] Among them, by shrinking the layout area according to the actual chip size and running the optimization algorithm again inside each chip layer, the module placement is refined to ensure that the final solution not only meets the manufacturing size constraints but also optimizes the wire network and space resources to the greatest extent.

[0100] Step S114 can achieve a smooth transition from theoretical optimization to a manufacturing-usable layout, bypassing the failures and contradictions of traditional algorithms caused by large-scale global optimization in three-dimensional scenes, and outputting a high-quality three-dimensional initial layout that can be directly applied in industry.

[0101] Furthermore, step S114 includes dividing the two-dimensional layout area into N*N panes, and dividing the clustering module into the top chip and the bottom chip according to the pane position of the clustering module center point and the area utilization of the top chip and the bottom chip.

[0102] Further, when dividing the clustering module into the top chip and the bottom chip, if the area utilization rate of the top chip or the bottom chip exceeds a preset threshold, the clustering module is preferentially allocated to the chip with a smaller area utilization rate.

[0103] Among them, through the pane mechanism and area utilization rate detection, the module layering can be made more scientific, and the area overload of any chip layer can be avoided, so as to ensure the optimal utilization of layout resources, avoid hot spots and bottlenecks in the 3D-EFS scenario, and improve the stability and robustness of the entire design process.

[0104] Further, the shrinking of the layout area includes: shrinking the area of the layout area according to a preset ratio; in the top chip and the bottom chip, based on the wire connection weight and the module overlap repulsion, iteratively optimize the positions of their respective clustering modules to generate the three-dimensional initial layout.

[0105] Among them, after shrinking the layout area according to a preset ratio, when generating the three-dimensional initial layout based on the wire connection weight and the module overlap repulsion, the total area of the clustering module should also be considered, and the three-dimensional initial layout is iteratively optimized based on its total area.

[0106] As Figure 3 shown, the present invention inputs the hierarchical structure, size and wire relationship of the module; the user specifies the module to be clustered; the unclustered modules are merged into an independent clustering module; the clustering module inherits the network information of the sub-module, constructs an equivalent wire connection relationship, and places the pin positions at the center of the clustering module; according to the wire connection attraction between the clustering modules and the repulsion generated by the module overlap, iteratively generate the two-dimensional optimal layout; use the window to divide the module into the top and bottom chips, and perform legalization on the two chips respectively to obtain the three-dimensional initial solution; output the size, position, wire information of the clustering module and the information of the sub-modules included. Finally, from data collection, clustering reduction, network modeling, optimization algorithm, layering strategy to result legalization, the deficiencies of the existing methods are comprehensively solved, providing a practical and high-quality initial layout scheme for complex three-dimensional integrated circuit design.

[0107] The following is a specific embodiment of the present invention:

[0108] As Figure 4 shown, first traverse all the modules at the user-specified level, and then traverse all the sub-modules submodule included in the module, and add them to the corresponding clustering module cluster of the module i i ​Meanwhile, traverse the pins of the submodule, set the pin positions to the central positions of the clustering modules, and obtain the net corresponding to the pin at the same time. Traverse the other modules connected to the pin in the net, and obtain the clustering module to which it belongs. Then add the cluster to the netlist i the connection relationship with cluster x will strengthen the connection weights between each other, which will affect the gravitational and repulsive forces of each module in the subsequent layout. In this way, the network connection relationship between the clustering modules is completed. Finally, divide the total area of the submodule by the utilization rate specified by the user to obtain the total area of cluster i

[0109] After obtaining all the clustering modules according to the above process, perform netlist modeling based on a specific connection model, construct the matrix and vector for the secondary layout, and only consider the connection gravitational force of the nets between the clustering modules and the repulsive force generated by module overlap, and iteratively generate the 2D optimal layout.

[0110] Finally, as shown in Figure 5 a 4×4 pane is drawn in 2D to divide the upper and lower layer modules. Considering the pane position where the center point of the module is located, the modules within the pane are divided into the top and bottom chips. When dividing, it is also necessary to consider that the area utilization rates of the two chips should be kept as consistent as possible. If one side exceeds a threshold (the default is the chip density before division), then the module is preferentially allocated to the chip with a smaller area utilization rate to balance the area utilization rates of the two chips.

[0111] Finally, after the division is completed, reduce the chip layout area (the default is 2 times), and respectively generate the optimal 3D initial solution iteratively according to the net gravitational force between the modules and the repulsive force generated by overlap in the two chips, that is, finally place the clustering modules on the top chip and the bottom chip in an optimal manner.

[0112] The present invention fully considers the hierarchical relationship of the modules and can use the hierarchical structure specified by the user to guide clustering, so that the cross-layer modules can be divided and laid out quickly in a more reasonable manner. By maintaining the logical integrity of the clustering modules in the layout stage, unnecessary cross-layer connections are reduced, providing a more stable initial solution for the subsequent 3D-EFS layout optimization process.

[0113] ​An embodiment of the present invention further provides a chip initial layout device, including a traversal module, a clustering module, a mapping module, a building module, and an iterative generation module. Among them, the traversal module is used to traverse a specified parent module of a chip hierarchical structure and sub-modules included in the specified parent module, expand the area of the layout region, and traverse the pins of the sub-modules; the clustering module is used to hierarchically cluster the sub-modules to generate corresponding clustering modules, and each clustering module inherits the total area, network connection relationship, and pin information of the corresponding sub-module; the mapping module is used to map the pins of the sub-modules to the central positions of the clustering modules; the building module is used to establish a net connection relationship between the clustering modules according to the network connected by the pins of the sub-modules, where duplicate network connections between the sub-modules can increase the net connection weight between the corresponding clustering modules; the iterative generation module is used to build a quadratic programming model based on the net connection weight and module overlap repulsion between the clustering modules, and iteratively optimize to generate a two-dimensional layout region, divide the clustering modules in the two-dimensional layout region into a top-layer chip and a bottom-layer chip; shrink the area of the layout region, and in the top-layer chip and the bottom-layer chip, iteratively generate a three-dimensional initial layout according to the net connection weight and module overlap repulsion between the clustering modules.

[0114] Among them, the iterative generation module is further used to divide the two-dimensional layout region into N*N panes, and divide the clustering modules into the top-layer chip and the bottom-layer chip according to the pane positions where the center points of the clustering modules are located, and the area utilization rates of the top-layer chip and the bottom-layer chip.

[0115] Among them, when dividing the clustering modules into the top-layer chip and the bottom-layer chip, if the area utilization rate of the top-layer chip or the bottom-layer chip exceeds a preset threshold, the iterative generation module is further used to preferentially allocate the clustering modules to the chip with a smaller area utilization rate.

[0116] Among them, the iterative generation module is further used to shrink the area of the layout region according to a preset ratio; in the top-layer chip and the bottom-layer chip, iteratively optimize the positions of the respective clustering modules based on the net connection weight and the module overlap repulsion to generate the three-dimensional initial layout.

[0117] Among them, the iterative generation module is further used to perform net modeling based on the clustering modules and a preset net model, establish a net connection relationship between the clustering modules, and obtain the net connection weight; based on the net connection weight and module overlap repulsion between the clustering modules, construct a coefficient matrix and a target vector required for quadratic programming solution, and iteratively generate a two-dimensional layout region using a quadratic programming algorithm.

[0118] Among them, the establishment module is further configured to obtain the network information of the pins connected to each of the sub-modules, and determine all the clustering modules to which the pins are connected in the network information; traverse all the network information, and record the netlist connection relationships between the mutually connected clustering modules into the netlist.

[0119] As can be seen from the above, a chip initial layout device provided by an embodiment of the present application effectively simplifies the original layout objects and network scale by specifying the parent module and its sub-modules for orderly screening and hierarchical clustering, inheriting and reducing relevant area, network, and pin information, and combining pin center mapping and weighted netlist relationship modeling; then, using the quadratic programming method based on the netlist connection weight and module overlap repulsion, it realizes an efficient iterative optimization of the two-dimensional initial layout, and through a reasonable partitioning and layering strategy, scientifically divides the clustering modules into the top and bottom layers of the chip, and finally generates a high-quality three-dimensional initial layout scheme that can meet the requirements of complex integrated circuits such as 3D-EFS after size legalization.

[0120] It should be noted that for the information interaction, execution process, etc. between the above-mentioned devices / units, since they are based on the same concept as the method embodiment of the present application, their specific functions and the technical effects brought about can be specifically referred to in the method embodiment part, and will not be elaborated here.

[0121] The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the steps of the chip initial layout method as described in any one of the above.

[0122] The terminal device may include, but is not limited to, a processor, a memory, and may also include input / output devices, network access devices, etc.

[0123] The so-called processor may be a central processing unit (CPU), and this processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or this processor may also be any conventional processor, etc.

[0124] In some embodiments, the memory may be an internal storage unit of the terminal device, such as the memory of the terminal device. In other embodiments, the memory may also be an external storage device of the terminal device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the terminal device. Further, the memory may also include both the internal storage unit and the external storage device of the terminal device. The memory is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of the computer program. The memory may also be used to temporarily store data that has been output or is to be output.

[0125] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiments.

[0126] As described above, the foregoing is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for initial chip layout, characterized in that, Including: Traverse the specified parent module of the chip - level structure and the sub - modules included in the specified parent module, and expand the area of the layout region; Hierarchically cluster the sub - modules to generate corresponding clustering modules, and each of the clustering modules inherits the network connection relationship and pin information of the corresponding sub - module; Traverse the pins of each sub - module in each clustering module, and map the pins of each sub - module to the central position of the clustering module; Establish the netlist connection relationship between the clustering modules according to the network connected by the pins of the sub - modules, wherein the repeated network connections between the sub - modules can increase the netlist connection weight between the corresponding clustering modules; Based on the netlist connection weight and module overlapping repulsion between the clustering modules, construct a quadratic programming model, and iteratively optimize to generate a two - dimensional layout region; Divide the clustering modules in the two - dimensional layout region into the top - layer chip and the bottom - layer chip; Shrink the area of the layout region, and in the top - layer chip and the bottom - layer chip, iteratively generate a three - dimensional initial layout according to the netlist connection weight and module overlapping repulsion between the clustering modules.

2. The chip initial layout method according to claim 1, wherein, The step of dividing the clustering modules in the two - dimensional layout region into the top - layer chip and the bottom - layer chip includes: Divide the two - dimensional layout region into N*N panes, and divide the clustering modules into the top - layer chip and the bottom - layer chip according to the pane position where the center point of the clustering module is located and the area utilization rate of the top - layer chip and the bottom - layer chip.

3. The chip initial layout method according to claim 2, wherein When dividing the clustering modules into the top - layer chip and the bottom - layer chip, if the area utilization rate of the top - layer chip or the bottom - layer chip exceeds the preset threshold, then preferentially allocate the clustering modules to the chip with a smaller area utilization rate.

4. The chip initial layout method according to claim 1, wherein The step of shrinking the area of the layout region includes: Shrink the area of the layout region according to a preset ratio; In the top - layer chip and the bottom - layer chip, based on the netlist connection weight and the module overlapping repulsion, iteratively optimize the positions of their respective clustering modules to generate the three - dimensional initial layout.

5. The chip initial layout method according to claim 1, wherein The clustering modules include specified clustering modules and non - specified clustering modules; The specified clustering modules include the specified sub - modules in the specified parent module, and the non - specified clustering modules include the non - specified sub - modules in the specified parent module.

6. The chip initial layout method according to claim 1, characterized in that The clustering modules are distributed at intervals on the expanded layout region.

7. The chip initial layout method according to claim 1, wherein The step of establishing the netlist connection relationship between the clustering modules according to the network connected by the pins of the sub - modules includes: Obtain the network information connected by the pins of each sub - module, and determine all the clustering modules connected by the pins in the network information; Traverse all the network information, and record the netlist connection relationship between the mutually connected clustering modules into the netlist.

8. The chip initial layout method according to claim 1, wherein The step of constructing a quadratic programming model based on the netlist connection weight and module overlapping repulsion between the clustering modules, and iteratively optimizing to generate a two - dimensional layout region includes: Based on the clustering modules and a preset netlist model, perform netlist modeling, establish the netlist connection relationship between the clustering modules, and obtain the netlist connection weight; Based on the wire connection weights and module overlap repulsion between the clustering modules, construct the coefficient matrix and objective vector required for quadratic programming solution, and use the quadratic programming algorithm to iteratively generate a two-dimensional layout area.

9. A chip initial layout device, characterized in that, Including: Traverse modules, which are used to traverse the specified parent module of the chip hierarchical structure and the sub-modules included in the specified parent module, expand the layout area, and traverse the pins of the sub-modules; Clustering modules, which are used to hierarchically cluster the sub-modules to generate corresponding clustering modules, and each clustering module inherits the total area, network connection relationship and pin information of the corresponding sub-module; Mapping module, which is used to map the pins of the sub-modules to the center positions of the clustering modules; Establishment module, which is used to establish the wire connection relationship between the clustering modules according to the networks connected by the pins of the sub-modules, wherein the repeated network connections between the sub-modules can increase the wire connection weights between the corresponding clustering modules; Iterative generation module, which is used to construct a quadratic programming model based on the wire connection weights and module overlap repulsion between the clustering modules, iteratively optimize and generate a two-dimensional layout area, divide the clustering modules in the two-dimensional layout area into the top-layer chip and the bottom-layer chip; shrink the layout area, and in the top-layer chip and the bottom-layer chip, iteratively generate a three-dimensional initial layout according to the wire connection weights and module overlap repulsion between the clustering modules.

10. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the chip initial layout method according to any one of claims 1 to 8.

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