A memristor-based generative adversarial network circuit

Abstract

The application discloses a generation adversarial network circuit based on a memristor. The generation adversarial network circuit is composed of nine generators and a discriminator; wherein each generator is composed of a sampling module, a weight adjusting module, a neuron module, an activation function module, a signal selecting module and a subtraction module; and the discriminator is composed of a signal selecting module, a weight adjusting module, a neuron module, a sampling module, an activation function module and a subtraction module. Nine noise signals V in1 ‑V in9 and a real image signal x n are connected to the nine generators, and the discriminator is connected with the nine generators and the real image signal x out1 ‑V out9 except that the output signals V n of the nine generators are connected to the discriminator. The discriminator calculates the error between the output image and the real image and returns the error to the generator, so as to guide the generator to optimize the generated image and make the generated image closer to the real image signal. The application uses a memristor array to build the generation adversarial network circuit, and can preliminarily generate some simple images.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of neural network circuit design based on memristor, and particularly relates to a generative adversarial network circuit based on memristor. BACKGROUND

[0002] The concept of memristor was first proposed by the Chinese scientist Chua in 1971. In studying the relationship between current, voltage, charge and magnetic flux, he speculated that in addition to resistors, capacitors and inductors, there should be a device that can represent the relationship between charge and magnetic flux, which is the memristor.

[0003] The remarkable feature of the memristor is the plasticity of resistance, that is, under the excitation of an external electric field, the resistance value of the memristor can change significantly, and the change of the electric field direction will directly lead to the change of the resistance value in the opposite direction.

[0004] The memristor also has a threshold characteristic, which refers to the fact that in the resistance switching phenomenon of the memristor, there is a specific voltage or current threshold, and when the applied voltage or current exceeds this threshold, the resistance state of the memristor will change abruptly.

[0005] As a new type of memory device, the memristor has the advantages of fast operation speed, low power consumption, high integration density, and resistance plasticity, etc. These characteristics make the memristor have potential in simulating biological synaptic plasticity in brain-like computing.

[0006] Generative adversarial networks (GAN) is a widely known complex neural network model, which requires a large amount of computing resources and relies on a large amount of training data, which makes the deployment of GAN on edge devices supported by traditional microprocessor hardware both slow and challenging.

[0007] The training process of GAN involves the adversarial training of the generator and the discriminator. The generator tries to "trick" the discriminator into thinking that the generated fake data is real data, while the discriminator tries to identify real and fake data.

[0008] Based on the resistance plasticity and threshold characteristics of the memristor, the present application proposes a GAN circuit based on the memristor. Unlike previous research that implements GAN through software algorithms, the present application implements hardware acceleration of GAN through a memristor array and improves training efficiency, which provides a certain reference for the hardware of GAN circuit. SUMMARY

[0009] The application provides a memristor-based generative adversarial network circuit.

[0010] The whole generative adversarial network circuit is composed of nine generators and one discriminator, for the generator n, n=1, 2, 3, …, 9, n is the generator number. The generator is composed of a generator input sampling module, a generator weight adjustment module, a generator neuron module, a generator sampling module, a generator activation function module, a generator signal selection module and a generator subtraction module. The discriminator is composed of a discriminator signal selection module, a discriminator weight adjustment module, a discriminator neuron module, a discriminator sampling module, a discriminator activation function module and a discriminator subtraction module.

[0011] The connection relationship of the generator is shown below. Each generator is composed of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator signal selection module and one generator subtraction module. For each component in the generator input sampling module and the generator weight adjustment module, the first two numbers n and m before the subscript represent the first number n representing the generator number and the second number m representing the corresponding mth generator input sampling module and generator weight adjustment module number in the generator n, wherein m=1, 2, 3, …, 9. Taking m=1 as an example below, the connection relationship of the generator input sampling module and the generator weight adjustment module is described, that is, for the first generator input sampling module of the nth generator, the module is composed of a sample and hold device Q n1 , a capacitor C n1 , a positive voltage source and a negative voltage source; wherein the positive and negative voltage sources are connected to the positive and negative voltage source ends of the sample and hold device, for providing working voltage for the sample and hold device; the capacitor C n1 is connected to the capacitor end of the sample and hold device Q n1 , for saving the voltage sampled by the sample and hold device; a noise signal V in1 is connected to the input end of the sample and hold device; a clock signal T1 is connected to the clock end of the sample and hold device, for controlling the working state of the sample and hold device; the output end of the sample and hold device is connected to the generator weight adjustment module; the generator weight adjustment module is composed of an operational amplifier GA n1 , a multiplier MT n1 , a summer SUM n1 , resistors R n11 -R n12 and a voltage-controlled switch S n11 -S n12The components are composed of components whose subscript n indicates that they belong to generator number n, where n = 1, 2, 3, …, 9. The second subscript 1 indicates that the component belongs to the nth generator and is connected to the m=1th input signal V. in1 Connection; Sample-and-hold circuit Q n1 One output path is connected to the voltage-controlled switch S n12 One input is connected to the other, and the other is connected to the multiplier MT. n1 Connected; Multiplier MT n1 The other input terminal is connected to the input signal V. cpn Connect the multiplier output to the operational amplifier GA. n1 Connected, operational amplifier GA n1 The output terminal is connected to the voltage-controlled switch S n11 Connect to the input terminal; voltage-controlled switch S n11 The control terminal is connected to the clock signal T2, and one end of the output terminal is connected to the resistor R. n11 Connected, and simultaneously connected to the adder SUM n1 The input terminal, resistor R n11 The other end is grounded; voltage-controlled switch S n12 The output is also connected to the adder SUM. n1 In the middle, simultaneously with resistor R n12 One end is connected, resistor R n12 The other end is grounded, voltage-controlled switch S n12 The clock control terminal is connected to the clock control signal T3; the adder SUM n1 The output terminal is connected to the synapse in the generator neuron module. For other generator input sampling modules and generator weight adjustment modules where m is not 1, their internal components are connected in the same way as when m is 1. For generator n, its generator neuron module consists of a memristor MR nm1 -MR nm2 Operational amplifier GA n_1 -GA n_3 and resistance R n1 -R n6 Composition, where m = 1, 2, 3, …, 9; memristor MR n11 The positive electrode and the memristor MR n12 The negative terminals are connected together to form a memristor synapse. For other memristor synapses where m is not 1, the connection method is exactly the same as that for the memristor synapse where m=1; Adder SUM n1 The output terminal and MR n11 With MR n12 The connection points are connected, and the memristor MR nm1 The negative terminal and resistor R n1 One end is connected to the operational amplifier GA. n_1 The inverting input terminal is connected, and the resistor Rn1 The other end is connected to the operational amplifier GA n_1 The output terminal is connected to the resistor R. n3 One end is connected; memristor MR nm2 The positive terminal and the resistor R n2 One end is connected to the operational amplifier GA. n_2 The inverting input terminal is connected, and the resistor R n2 The other end is connected to the operational amplifier GA n_2 Connect the output terminal of the operational amplifier GA to the output terminal. n_1 with GA n_2 The non-inverting input terminals of the operational amplifier GA are all grounded. n_1 The output terminal is also connected to resistor R. n3 One end is connected, resistor R n3 The other end is connected to resistor R n5 Connected to, and simultaneously connected to, operational amplifier GA n_3 Connect the inverting input terminal to the resistor R. n5 The other end is connected to the operational amplifier GA n_3 The output terminal is connected; operational amplifier GA n_2 Output terminal and resistor R n4 Connected together, with resistance R n4 The other end is connected to the operational amplifier GA n_3 The inverting input is connected, and the operational amplifier GA... n_3 The non-inverting input terminal and resistor R n6 Connected, resistor R n6 The other end is grounded. The generator sampling module consists of a sample-and-hold circuit Q. n Capacitor C n It consists of positive and negative voltage sources; the positive and negative voltage sources are connected to the sample-and-hold circuit Q. n The power supply terminal is used for the sample-and-hold circuit Q. n Provides operating voltage, capacitor C n The capacitor connected to the sample-and-hold circuit is used to hold the voltage signal sampled by the circuit. The clock signal T3 is connected to Q. n The control terminal is used to control the operating state of the sample-and-hold circuit. The output terminal of the sample-and-hold circuit is connected to the generator activation function module. The generator activation function module consists of positive and negative voltage sources and a PMOS transistor M. n1 -M n2 and NMOS transistor M n3 -M n4 Composition, sample-and-hold circuit Q n The output terminal of the PMOS transistor M n1 and NMOS transistor M n3 The gate of the PMOS transistor is connected to the gate of the PMOS transistor M. n1 The source is connected to a positive voltage, and the drain is connected to the NMOS transistor M. n3The drains of the NMOS transistor M are connected. n3 Gate and sample-and-hold Q n The output terminal is connected, and the source terminal is connected to a negative voltage. M n3 The drain and M n1 The drain of the PMOS transistor M is simultaneously connected to the PMOS transistor M. n2 The gate and NMOS transistor M n4 The gates are connected together, M n2 The source of M is connected to a positive voltage. n4 The source of M is connected to a negative voltage. n2 With M n4 The drains of the electrodes are connected, and the signal at this point is denoted as V. outn V outn It is also connected to the generator subtraction module. The generator subtraction module consists of an operational amplifier GA. n_4 -GA n_5 Pressure-controlled switch S n3 -S n5 Resistance R dn1 -R dn9 SUM adder sn2 Composition, V outn With resistance R dn1 One end is connected, and the resistor R dn1 The other end is connected to the operational amplifier GA n_4 The inverting input terminal and resistor R dn2 Connected, resistor R dn2 The other end is connected to the operational amplifier GA n_4 The output terminal is connected to the operational amplifier GA. n_4 The non-inverting input terminal and resistor R dn4 Connected, resistor R dn4 The other end is grounded, and the resistor R dn3 It is also connected to the operational amplifier GA. n_4 The non-inverting input terminal; operational amplifier GA n_4 The output terminal is connected to the voltage-controlled switch S n3 The input terminals are connected, S n3 Output terminal and resistor R dn5 Connected, R dn5 The other end is grounded, R dn5 With S n3 The connected portion outputs a signal denoted as V. cpn S n3 Control terminal and adder SUM sn2 Connect the output terminal of the adder SUM to the output terminal. sn2 The input terminals are respectively connected to the voltage-controlled switch S n4 and S n5 Connect to the output terminal of S. n4 The output terminal is also connected to resistor R dn8connected, the other end of the resistor R dn8 is connected to ground; the output of the voltage-controlled switch S n5 is also connected to the resistor R dn9 , the other end of the resistor R dn9 is connected to ground; the non-inverting input of the operational amplifier GA n_5 is connected to ground, the output is connected to the input and control terminal of the voltage-controlled switch S n4 , and also to the resistor R dn7 ; the other end of the resistor R dn7 is connected to the inverting input of the operational amplifier GA n_5 ; the other end of the resistor R dn6 is connected to the inverting input of the operational amplifier GA n_5 , the other end of the resistor R dn7 is connected to the voltage V cp , and also to the control and input terminals of the voltage-controlled switch S n5 . The output signal of the generator signal selection module is connected to the generator subtraction module, i.e. through the output of the adder SUM sn1 , one end of the resistor R dn3 is connected; for the generator signal selection module, it consists of the voltage-controlled switch S n1 -S n2 , the resistor R sn1 -R sn2 and the adder SUM sn1 ; the control terminal of the voltage-controlled switch S n1 is connected to the clock signal T c1 , the input is connected to the real image signal x n , the output of the voltage-controlled switch S n1 is connected to the resistor R sn2 , and also to the input of the adder SUM sn1 ; the input of the voltage-controlled switch S n2 is connected to the constant voltage V c , the control terminal is connected to the clock signal T c2 , the output of S n2 is connected to the resistor R sn1 , and also to the adder SUM sn1 , the other end of the resistor R sn1 is connected to ground.

[0012] The working principle of the generator in the generative adversarial network circuit is explained below. Each generator consists of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator subtraction module, and one generator signal selection module. The entire circuit can be divided into two phases from the start to the end of learning: the discriminator learning period is from 0 to 0.13 seconds, and the generator learning period is from 0.13 to 0.25 seconds. These two periods consist of small cycles of 10 milliseconds each. The first 5 milliseconds of each small cycle are the signal input period, and the last 5 milliseconds are the weight adjustment period. Taking the generator input sampling module and the generator weight adjustment module as an example, with the first input signal connected (m=1), the working principle of the generator input sampling module is explained as follows. Noise signal V in1 Input to sample-and-hold circuit Q n1 In the sample-and-hold circuit Q, when the clock signal T1 is high, n1 Sampling is performed, and the sampled voltage is stored in capacitor C. n1 In the middle, when the clock signal T1 is low, the sample-and-hold circuit Q... n1 Sampling stops, and the sampled signal at the output is transmitted to the generator weight adjustment module. The working principle of the generator weight adjustment module is as follows: Clock signals T2 and T3 in the generator weight adjustment module are a pair of inverted signals. During the signal input period, clock signal T2 is low and T3 is high; during the weight adjustment period, clock signal T2 is high and T3 is low. During the signal input period, the sampled signal can be transmitted through the voltage-controlled switch S... n12 Input to adder SUM n1 And input into the memristor synapse of the generator neuron module, at which point the voltage-controlled switch S... n11 Shutdown, from operational amplifier GA n1 The weight adjustment signal cannot be input to the adder. During the weight adjustment period, clock signals T2 are high and T3 is low, at which time the voltage-controlled switch S... n11 Open, S n12 When closed, the weight adjustment signal can be passed through the adder SUM. n1 The input is fed into the memristor synapse of the generator neuron module. The generator neuron module operates as follows: Memristor MR... 1m1 The positive electrode and MR 1m2 The negative terminals are connected, m=1, 2, 3, …, 9, together forming a memristor synapse, which is formed by the memristor MR. 1m1 The voltage signal output from the negative terminal passes through resistor R. n1 With operational amplifier GA n_1 The voltage amplifier, after amplification, outputs the signal to a resistor R. n3 -Rn6 and operational amplifier GA n_3 , as an input signal of the subtraction circuit; similarly, the output signal of the memristor MR 1m2 is input to the voltage amplifier composed of resistors R n2 , and an operational amplifier GA n_2 , and is input to the subtraction circuit as another input signal of the subtraction circuit; the output signal of the voltage amplifier composed of resistors R n3 and an operational amplifier GA n4 is input to the generator neuron module after subtraction of the two signals connected to resistors R n , positive and negative voltage sources, and a capacitor C n , the working principle of the generator sampling module is shown below. The signal from the generator neuron module is input to the sampling end of the sample-and-hold Q n , when T3 is high, the sample-and-hold Q n will sample the output signal from the operational amplifier GA n_3 , when T3 is low, Q n will not sample the signal, but will maintain the last sampling result; during the signal input period, T3 is high, at this time the sample-and-hold Q n will sample; during the weight adjustment period, T3 is low, at this time the sample-and-hold Q n will not sample the input signal, and still maintains the level output during the signal input period. For the generator activation function module, the module is composed of NMOS M n1 -M n2 and PMOS M n3 -M n4 , the output signal of the generator activation function module is denoted as V outn . For the generator subtraction module, the working principle is shown below: V outn is input to the subtraction circuit composed of resistors R dn1 -R dn4 and an operational amplifier GA n_4 , V outn is subtracted from the output signal from the generator signal selection module and is input to the input end of the voltage-controlled switch S n3 , the control end of S n3 is connected to the output end of the adder SUM sn2 , resistors R dn6 -R dn9 , voltage-controlled switch S n4 -S n5 , operational amplifier GA n_3 , and adder SUM sn2 together constitute an absolute value circuit, which is used to calculate Vcp the absolute value of V cp , when the input voltage of V n3 is not 0, the absolute value circuit outputs a positive voltage, at this time the voltage-controlled switch S n3 is turned on, the output voltage of the operational amplifier can make the voltage-controlled switch S n_4 open, the output signal from the operational amplifier GA n3 can be output through the voltage-controlled switch S cpn , and the output voltage signal is recorded as V c1 . For the generator signal selection module, the working principle is as follows: when the clock signal T c2 is high and T n1 is low, at this time the voltage-controlled switch S n is opened, and the pixel signal x n1 corresponding to the real image signal can be input into the adder SUM sn1 through the voltage-controlled switch S c1 , and as one of the input voltages of the subtraction circuit in the generator subtraction module; when T c2 is low and T n is high, x n1 cannot pass through the voltage-controlled switch S c , and the reference voltage signal V n2 can pass through the voltage-controlled switch S sn1 and be input into the adder SUM c1 , and as the input of the subtraction circuit in the generator subtraction module. In 0-0.13 seconds, that is, the discriminator learning period, T c2 is low and T c1 is high; in 0.13-0.25 seconds, that is, the generator learning period, T c2 is high and T d11 is low.

[0013] The connection relationship of the discriminator is as follows. The generative adversarial network circuit proposed in the present application has only one discriminator, which is composed of nine discriminator signal selection modules, nine discriminator weight adjustment modules, one discriminator neuron module, one discriminator sampling module, one discriminator activation function module and one discriminator subtraction module. For the subscripts of the components in the discriminator signal selection module and the discriminator weight adjustment module, the first subscript d represents the position in the discriminator, the second subscript n represents the module number, and n = 1, 2, 3, …, 9, and the third subscript represents the number of the component. For the discriminator signal selection module and the discriminator weight adjustment module, the following are described by taking the connection of the first generator as an example, that is, the second subscript n = 1 of the component. The discriminator signal selection module is composed of a voltage-controlled switch S d12 , a resistor R d11 , a resistor R d12 , a resistor Rand adder SUM d11 comprises a voltage-controlled switch S d11 connected to the output signal V out1 of the generator 1, the control terminal being connected to the clock signal T c2 , S d11 being connected to the output terminal of the resistor R d11 , one terminal of the resistor R d11 being connected to ground; S d11 being further connected to the input terminal of the adder SUM d11 , the real image signal x1 being connected to the input terminal of the voltage-controlled switch S d12 , the control terminal of the voltage-controlled switch S d12 being connected to the clock signal T c1 , the output terminal of S d11 being connected to the input terminal of the adder SUM d12 , one terminal of the resistor R d12 being connected to the output terminal of the adder SUM, the other terminal of the resistor R d1 being connected to ground; the discriminator weight adjustment module comprises an operational amplifier DA d13 , a voltage-controlled switch S d14 , a resistor R d13 , a multiplier MT d14 and an adder SUM d1 , the output terminal of the adder SUM d12 being connected to the input terminal of the multiplier MT d11 and the input terminal of the voltage-controlled switch S d1 , the output terminal of the multiplier MT d13 being connected to the non-inverting input terminal of the operational amplifier DA d1 , the inverting input terminal of the operational amplifier DA d1 being connected to ground, the output terminal of the operational amplifier DA d1 being connected to the input terminal of the voltage-controlled switch S d1 , the output terminal of the voltage-controlled switch S d14 being connected to the output terminal of the resistor R d14 , the other terminal of the resistor R d14 being connected to ground, the output terminal of the voltage-controlled switch S d14 being further connected to the input terminal of the adder SUM d14 , the control terminal of the voltage-controlled switch S d12 being connected to the clock signal T2 d14 , the control terminal of the voltage-controlled switch S d13 being connected to the clock signal T3 d13 , the output terminal of S d12 being connected to the input terminal of the adder SUM d13 and to the resistor R d13 , the other terminal of the resistor R n1 being connected to ground. For the discriminator neuron module, the connection relationship is shown below. The discriminator neuron module comprises a memristor MR n2, operational amplifiers DA1-DA3 and resistors R d1 -R d6 comprise, wherein n = 1, 2, 3, …, 9; wherein, the positive electrode of the memristor MR n1 is connected with the negative electrode of the memristor MR n2 , and together constitute a memristive synapse; the output terminal of the adder SUM d12 is connected with the connection point of the two memristors MR 11 -MR 12 ; the negative electrode of the memristor MR n1 is connected with the inverting input terminal of the operational amplifier DA1, and at the same time is connected with the resistor R d1 , the other end of the resistor R d1 is connected with the output terminal of the operational amplifier DA1, and the non-inverting input terminal of the operational amplifier DA1 is grounded; the positive electrode of the memristor MR n2 is connected with the inverting input terminal of the operational amplifier DA2, and at the same time is connected with the resistor R d2 , the other end of the resistor is connected with the output terminal of the operational amplifier DA2, and the non-inverting input terminal of the operational amplifier DA2 is grounded; the output terminal of the operational amplifier DA1 is connected with the resistor R d3 , the other end of the resistor R d3 is connected with one end of the resistor R d5 and the inverting input terminal of the operational amplifier DA3, the output terminal of the operational amplifier DA2 is connected with the resistor R d4 , and at the same time the other end of the resistor R d4 is connected with the inverting input terminal of the operational amplifier DA3, and at the same time is connected with one end of the resistor R d5 , the other end of the resistor R d5 is connected with the output terminal of the operational amplifier DA3, and the non-inverting input terminal of the operational amplifier DA3 is connected with the resistor R d6 , and at the same time the other end of the resistor R d6The other end is grounded. For the discriminator sampling module, the connection relationship is as follows: the discriminator sampling module is composed of a sample and hold DQ, a capacitor DC and positive and negative voltage sources, the output end of an operational amplifier DA3 is connected with the input end of the sample and hold DQ, the capacitor DC is connected with the capacitor end of the sample and hold DQ, the positive and negative power sources are connected with the positive and negative power end of the sample and hold, for providing working power for the sample and hold, and the control end of the sample and hold DQ is connected with a clock signal T3. The discriminator activation function module is composed of NMOS tubes DM1-DM2, PMOS tubes DM3-DM4 and positive and negative voltage sources, and the connection relationship is as follows: the output end of the sample and hold is connected with the gate of the PMOS tube DM1 and the NMOS tube DM3, the source of the PMOS tube is connected with the positive voltage source, the drain is connected with the drain of the NMOS tube DM3, the source of the DM3 is connected with the negative voltage source, the drains of the DM1 and the DM3 are simultaneously connected with the gates of the DM2 and the DM4, the source of the DM2 is connected with the positive voltage source, the drain of the DM2 is connected with the drain of the DM4, and the source of the DM4 is connected with the negative power source. The discriminator subtraction module is composed of resistors R ds1 -R ds6 , an operational amplifier DA4, a reference voltage V tg , a voltage-controlled switch S d1 -S d2 and an adder SUM s . The connection relationship of the discriminator subtraction module is as follows: the drains of the DM4 and the DM2 are connected with one end of a resistor R ds1 , the other end of the resistor R ds1 is connected with the inverting input end of the operational amplifier DA4, and simultaneously connected with one end of a resistor R ds3 , the other end of the resistor R ds3 is connected with the output end of the operational amplifier DA4, the reference voltage V tg is connected with the resistor R ds2 , the other end of the resistor R ds2 is connected with the non-inverting input end of the operational amplifier DA4, and simultaneously connected with one end of a resistor R ds4 , the other end of the resistor R ds4 is grounded, the output end signal of the operational amplifier DA4 is recorded as a voltage V cp , V cp is connected with the input end of the voltage-controlled switch S d1 , the control end of the voltage-controlled switch S d1 is connected with a clock signal T c1 , the output end of the S d1 is connected with one end of a resistor R ds5 , and simultaneously connected with the input end of the adder SUM s , the other end of the resistor R ds5 is grounded, the input end of the voltage-controlled switch S d2 is grounded, and the output end is connected with a resistor Rds6 connected with the input of the adder SUM s , and the other end of the resistor R ds6 is grounded, the control end of the voltage-controlled switch S d2 is connected with the clock signal T c2 , and the output signal of the adder SUM s is connected with the input of the discriminator weight adjustment module MT dn .

[0014] The working principle of the discriminator is shown as follows. The discriminator learning period is 0-0.13 seconds, and the generator learning period is 0.13-0.25 seconds; during the discriminator learning period, only the discriminator learns the real image signal. The working principles of various modules are shown as follows: for the discriminator signal selection module, during the discriminator learning period, T c1 is high, T c2 is low, the voltage-controlled switch S dn2 is opened, S dn1 is closed, and the real image signal x n can be input into the discriminator weight adjustment module through the voltage-controlled switch S dn2 and the adder SUM dn1 , wherein n = 1, 2, 3, …, 9. During the generator learning period, T c1 is low, T c2 is high, the voltage-controlled switch S dn2 is closed, S dn1 is opened, and the output signal from the generator n can be input into the discriminator weight adjustment module through the voltage-controlled switch S dn1 and the adder SUM dn1 . For the discriminator weight adjustment module, during the weight adjustment period, T2 is high, T3 is low, the voltage-controlled switch S dn4 is opened, S dn3 is closed, and the adjustment signal from the operational amplifier DA d1 can be input into the memristive synapse through the voltage-controlled switch S dn4 and the adder SUM dn2 ; during the signal input period, T2 is low, T3 is high, the voltage-controlled switch S dn4 is closed, S dn3 is opened, and the signal from the adder SUM dn1 can be input into the memristive synapse through the voltage-controlled switch S dn3 and the adder SUM dn2 . For the discriminator neuron module, the working principle is shown as follows: the voltage from the previous stage is subjected to a weighted summation operation, the resistor R d1 and the operational amplifier DA1 together constitute a voltage amplifier, and similarly, the resistor Rd2 With the operational amplifier DA2 also constitutes a voltage amplifier, both sides of the amplified voltage input to the resistance R d3 -R d6 and operational amplifier DA3 subtraction circuit, subtraction can be obtained after the output of the entire discriminator neuron circuit. For discriminator sampling module, the working principle is shown as follows: when T3 is high, the sample and hold DQ will sample the voltage signal from the output of the operational amplifier DA3, and store the sampling voltage in the capacitor DC, when T3 is low, the sample and hold DQ will keep the voltage sampled before and output. For discriminator activation function module, the working principle is shown in the attached Figure 4 , the signal from the discriminator sampling module is processed by the activation function, the positive and negative voltage source in the activation function module is +1V and -1V respectively, so the output of the discriminator activation function module is the voltage between +1V and -1V, the input and output mapping relationship is shown in the attached Figure 4 . For discriminator subtraction module, the working principle is shown as follows: during the discriminator learning period, T c1 is high, T c2 is low, at this time, the voltage controlled switch S d1 is opened, S d2 is closed, V cp can be input to the multiplier MT d1 of the discriminator weight adjustment module through the voltage controlled switch S s and the adder SUM dn , and participate in the adjustment of the discriminator's own memristive synapse weight, during the generator learning period, T c1 is low, T c2 is high, at this time, the voltage controlled switch S d1 is closed, S d2 is opened, the 0V signal grounded can be input to the multiplier MT d2 of the discriminator weight adjustment module through the voltage controlled switch S s and the adder SUM dn , at this time, the discriminator weight adjustment module will not adjust the memristive synapse in the discriminator neuron module. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a circuit structure diagram of a generative adversarial network based on memristor proposed.

[0016] Figure 2 is a schematic diagram of the generator.

[0017] Figure 3 is a schematic diagram of the discriminator.

[0018] Figure 4The input-output mapping relationship diagram of the generator activation function module or the discriminator activation function module is generated.

[0019] Figure 5 The schematic diagram of each clock signal in the generative adversarial network circuit is generated.

[0020] Figure 6 The schematic diagram of the sampled noise signal is generated.

[0021] Figure 7 The schematic diagram of the output voltage of the first generator and the target voltage is generated.

[0022] Figure 8 The schematic diagram of the output voltage of the third generator and the target voltage is generated.

[0023] Figure 9 The schematic diagram of the real image signal and the final generated image of the generator is generated. DETAILED DESCRIPTION

[0024] The present application provides a kind of generative adversarial network circuit based on memristor, it utilizes the resistance plasticity and threshold characteristic of new two-port device memristor to build generative adversarial network circuit, and can generate some simple images by the resistance plasticity of memristor.

[0025] ATTACHMENT Figure 1 The schematic diagram of the connection mode of the generative adversarial network circuit is generated, and the whole circuit is composed of nine generators and a discriminator;Each generator is composed of generator input sampling module, generator weight adjustment module, generator neuron module, generator sampling module, generator activation function module, generator signal selection module and generator subtraction module;Discriminator is composed of discriminator signal selection module, discriminator weight adjustment module, discriminator neuron module, discriminator sampling module, discriminator activation function module and discriminator subtraction module.

[0026] ATTACHMENT Figure 2For the generator schematic diagram, each generator is composed of nine generator input sampling modules, nine generator weight adjustment modules, a generator neuron module, a generator sampling module, a generator activation function module, a generator signal selection module and a generator subtraction module; for the generator n, n = 1, 2, 3, …, 9, n is the generator number. For each component in the generator input sampling module and the generator weight adjustment module, the first two numbers n, m before the subscript represent the first number n representing the generator number and the second number m representing the corresponding mth generator input sampling module and generator weight adjustment module number in the generator n, where m = 1, 2, 3, …, 9. Taking m = 1 as an example below, the connection relationship of the generator input sampling module and the generator weight adjustment module is described, that is, for the first generator input sampling module of the nth generator, the module is composed of a sample holder Q n1 , a capacitor C n1 , a positive voltage source and a negative voltage source; wherein the positive and negative voltage sources are connected to the positive and negative voltage source ends of the sample holder, the capacitor C n1 is connected to the capacitor end of the sample holder Q n1 , and the noise signal V in1 is connected to the input end of the sample holder; the clock signal T1 is connected to the clock end of the sample holder, and the output end of the sample holder is connected to the generator weight adjustment module. The generator weight adjustment module is composed of an operational amplifier GA n1 , a multiplier MT n1 , an adder SUM n1 , a resistor R n11 -R n12 and a voltage-controlled switch S n11 -S n12 , wherein the subscript n of the components represents the generator number n = 1, 2, 3, …, 9, and the second subscript 1 represents the connection with the m = 1th input signal V in1 in the nth generator; one way of the sample holder Q n1 output end is connected to the input end of the voltage-controlled switch S n12 , and the other way is connected to the multiplier MT n1 ; the other input end of the multiplier MT n1 is connected to the input signal V cpn , the multiplier output end is connected to the operational amplifier GA n1 , and the output end of the operational amplifier GA n1 is connected to the input end of the voltage-controlled switch S n11 ; the control end of the voltage-controlled switch S n11 is connected to the clock signal T2, one end of the output end is connected to the resistor R n11 , and is connected to the adder SUM n1the input end of the resistor R n11 , the other end of the resistor R n12 is grounded; the clock control end of the voltage-controlled switch S n1 is connected to the clock control signal T3; the output end of the adder SUM n12 is connected to the one end of the resistor R n12 , the other end of the resistor R n12 is grounded; the clock control end of the voltage-controlled switch S n1 is connected to the clock control signal T3; the output end of the adder SUM nm1 is connected to the synapse in the generator neuron module. For other generator input sampling modules and generator weight adjusting modules in the generator with m not being 1, the internal components are consistent with the connection of m being 1. For the generator n, the generator neuron module thereof is composed of the memristor MR nm2 , the operational amplifier GA n_1 , the resistor R n_3 and the resistor R n1 , wherein m = 1, 2, 3, …, 9; the positive electrode of the memristor MR n6 is connected to the negative electrode of the memristor MR n11 , which together constitute a memristive synapse, and for other memristive synapses with m not being 1, the connection mode is completely consistent with the memristive synapse with m = 1; the output end of the adder SUM n12 is connected to the connection point of MR n1 and MR n11 ; the negative electrode of the memristor MR n12 is connected to the one end of the resistor R nm1 , which is also connected to the inverting input end of the operational amplifier GA n1 ; the other end of the resistor R n_1 is connected to the output end of the operational amplifier GA n1 , which is also connected to the one end of the resistor R n_1 ; the positive electrode of the memristor MR n3 is connected to the one end of the resistor R nm2 , which is also connected to the inverting input end of the operational amplifier GA n2 ; the other end of the resistor R n_2 is connected to the output end of the operational amplifier GA n2 ; the same phase input end of the operational amplifier GA n_2 is grounded; the output end of the operational amplifier GA n_1 is also connected to the one end of the resistor R n_2 ; the other end of the resistor R n_1 is connected to the resistor R n3 , which is also connected to the inverting input end of the operational amplifier GA n3 ; the other end of the resistor R n5 is connected to the resistor R n_3 , which is also connected to the inverting input end of the operational amplifier GA n5The other end is connected to the operational amplifier GA n_3 The output terminal is connected; operational amplifier GA n_2 Output terminal and resistor R n4 Connected together, with resistance R n4 The other end is connected to the operational amplifier GA n_3 The inverting input is connected, and the operational amplifier GA... n_3 The non-inverting input terminal and resistor R n6 Connected, resistor R n6 The other end is grounded. The generator sampling module consists of a sample-and-hold circuit Q. n Capacitor C n It consists of positive and negative voltage sources; the positive and negative voltage sources are connected to the sample-and-hold circuit Q. n At the power supply terminal, capacitor C n The capacitor terminal of the sample-and-hold circuit is connected, and the clock signal T3 is connected to Q. n The control terminal of the sample-and-hold circuit is connected to the output terminal of the generator activation function module. The generator activation function module consists of positive and negative voltage sources and a PMOS transistor M. n1 -M n2 and NMOS transistor M n3 -M n4 Composition, sample-and-hold circuit Q n The output terminal of the PMOS transistor M n1 and NMOS transistor M n3 The gate of the PMOS transistor is connected to the gate of the PMOS transistor M. n1 The source is connected to a positive voltage, and the drain is connected to the NMOS transistor M. n3 The drains of the NMOS transistor M are connected. n3 Gate and sample-and-hold Q n The output terminal is connected, and the source terminal is connected to a negative voltage. M n3 The drain and M n1 The drain of the PMOS transistor is simultaneously connected to the PMOS transistor M n2 The gate and NMOS transistor M n4 The gates are connected together, M n2 The source of M is connected to a positive voltage. n4 The source of M is connected to a negative voltage. n2 With M n4 The drains of the electrodes are connected, and the signal at this point is denoted as V. outn V outn It is also connected to the generator subtraction module. The generator subtraction module consists of an operational amplifier GA. n_4 -GA n_5 Pressure-controlled switch S n3 -S n5 Resistance R dn1 -R dn9 SUM adder sn2 Composition, V outn With resistance Rdn1 One end is connected, and the resistor R dn1 The other end is connected to the operational amplifier GA n_4 The inverting input terminal and resistor R dn2 Connected, resistor R dn2 The other end is connected to the operational amplifier GA n_4 The output terminal is connected to the operational amplifier GA. n_4 The non-inverting input terminal and resistor R dn4 Connected, resistor R dn4 The other end is grounded, and the resistor R dn3 It is also connected to the operational amplifier GA. n_4 The non-inverting input terminal; operational amplifier GA n_4 The output terminal is connected to the voltage-controlled switch S n3 The input terminals are connected, S n3 Output terminal and resistor R dn5 Connected, R dn5 The other end is grounded, R dn5 With S n3 The connected portion outputs a signal denoted as V. cpn S n3 Control terminal and adder SUM sn2 Connect the output terminal of the adder SUM to the output terminal. sn2 The input terminals are respectively connected to the voltage-controlled switch S n4 and S n5 Connect to the output terminal of S. n4 The output terminal is also connected to resistor R dn8 Connected, and resistor R dn8 The other end is grounded, and the voltage-controlled switch S n5 The output terminal is also connected to resistor R dn9 Connected, and resistor R dn9 The other end is grounded; operational amplifier GA n_5 The non-inverting input terminal is grounded, and the output terminal is connected to the voltage-controlled switch S. n4 The input terminal and control terminal are connected, as well as the resistor R. dn7 Connected; resistor R dn7 The other end is with GA n_5 The inverting input terminal is connected; resistor R dn6 One end and GA n_5 The inverting input terminal is connected, and this terminal is also connected to resistor R. dn7 Connect one end to the other end, and connect the other end to the voltage V. cp Connected to, and simultaneously connected to, pressure-controlled switch S n5 The control terminal and input terminal are connected. The output signal of the generator signal selection module is connected to the generator subtraction module, that is, through the adder SUM. sn1 The output terminal and resistor R dn3 One end is connected. For the generator signal selection module, it is controlled by a voltage-controlled switch S.n1 -S n2 Resistance R sn1 -R sn2 SUM adder sn1 Composition; voltage-controlled switch S n1 Control terminal and clock signal T c1 Connected, the input terminal is connected to the real image signal x n Connected, pressure-controlled switch S n1 The output terminal and resistor R sn2 Connected to, and simultaneously with, adder SUM sn1 Connect to the input terminal; voltage-controlled switch S n2 The input terminal is connected to a constant voltage V c Connected to the control terminal and the clock signal T c2 Connected, S n2 The output terminal and resistor R sn1 Connect, and simultaneously with adder SUM sn1 Connected, resistor R sn1 The other end is grounded.

[0027] Appendix Figure 3 The diagram below shows the discriminator's connection relationships. The generative adversarial network circuit proposed in this invention has only one discriminator, which consists of nine discriminator signal selection modules, nine discriminator weight adjustment modules, one discriminator neuron module, one discriminator sampling module, one discriminator activation function module, and one discriminator subtraction module. For the subscripts of the components in the discriminator signal selection module and the discriminator weight adjustment module, the first subscript 'd' indicates the location is a discriminator, the second subscript 'n' represents the module number, where n = 1, 2, 3, …, 9, and the third subscript represents the component number. For the discriminator signal selection module and the discriminator weight adjustment module, the following explanation uses the connection to Generator 1 as an example, i.e., the second subscript n = 1 for the component. The discriminator signal selection module consists of a voltage-controlled switch S… d11 -S d12 Resistance R d11 -R d12 SUM adder d11 Composition, pressure-controlled switch S d11 The input terminal and the output signal V of generator 1 out1 Connected, the control terminal is connected to the clock signal T c2 Connected, S d11 The output terminal is connected to resistor R. d11 One end, resistor R d11 The other end is grounded; S d11 The output is also connected to the adder SUM. d11 Input: Real image signal x1 and voltage-controlled switch S d12 The input terminal is connected to the voltage-controlled switch S.d12 Control terminal and clock signal T c1 Connected, the output is connected to the adder SUM. d11 The input terminal is connected, and it is also connected to resistor R. d12 One end, resistor R d12 The other end is grounded. The discriminator weight adjustment module consists of an operational amplifier DA. d1 Pressure-controlled switch S d13 -S d14 Resistance R d13 -R d14 Multiplier MT d1 SUM adder d12 Composition, adder SUM d11 The output terminal is connected to the multiplier MT. d1 The input terminal and voltage-controlled switch S d13 The input terminal of MT d1 The output terminal of the operational amplifier DA d1 Connect the non-inverting input terminal, DA d1 The inverting input is grounded, DA d1 Output terminal and voltage-controlled switch S d14 The input terminals are connected, S d14 Output terminal and resistor R d14 Connected, resistor R d14 The other end is grounded, and the voltage-controlled switch S d14 The output is also connected to the adder SUM. d12 The input terminal, S d14 The control terminal is connected to the clock signal T2; voltage-controlled switch S d13 The control terminal is connected to the clock signal T3, S d13 Output terminal and adder SUM d12 The input terminal is connected to the resistor R. d13 Connected, resistor R d13 The other end is grounded. For the discriminator neuron module, the connection is as follows; the discriminator neuron module consists of a memristor MR... n1 -MR n2 Operational amplifiers DA1-DA3 and resistor R d1 -R d6 Composition, where n = 1, 2, 3, ..., 9; where the memristor MR n1 The positive electrode and MR n2 The negative terminals are connected together to form a memristor synapse; the adder SUM d12 The output terminal is connected to two memristors MR 11 -MR 12 The connection points are connected. Memristor MR n1 The negative terminal is connected to the inverting input of operational amplifier DA1, and also to resistor R. d1connected, the other end of the resistor R d1 is connected with the output terminal of the operational amplifier DA1, and the non-inverting input terminal of the operational amplifier DA1 is grounded; the positive electrode of the memristor MR n2 is connected with the inverting input terminal of the operational amplifier DA2, and the other end of the resistor R d2 is connected with the output terminal of the operational amplifier DA2, and the non-inverting input terminal of the operational amplifier DA2 is grounded; the output terminal of the operational amplifier DA1 is connected with the resistor R d3 , and the other end of the resistor R d3 is connected with one end of the resistor R d5 and the inverting input terminal of the operational amplifier DA3, and the output terminal of the operational amplifier DA2 is connected with the resistor R d4 , and the other end of the resistor R d4 is connected with the inverting input terminal of the operational amplifier DA3 and one end of the resistor R d5 , and the other end of the resistor R d5 is connected with the output terminal of the operational amplifier DA3, and the non-inverting input terminal of the operational amplifier DA3 is connected with the resistor R d6 , and the other end of the resistor R d6 is grounded. For the discriminator sampling module, the connection relationship is as follows: the discriminator sampling module is composed of a sample and hold DQ, a capacitor DC and positive and negative voltage sources, the output terminal of the operational amplifier DA3 is connected with the input terminal of the sample and hold DQ, the capacitor DC is connected with the capacitor terminal of the sample and hold DQ, the positive and negative power sources are connected with the positive and negative power terminals of the sample and hold, and the control terminal of the sample and hold DQ is connected with the clock signal T3. The discriminator activation function module is composed of NMOS tubes DM1-DM2, PMOS tubes DM3-DM4 and positive and negative voltage sources, and the connection relationship is as follows: the output terminal of the sample and hold is connected with the gate of the PMOS tube DM1 and the NMOS tube DM3, the source of the PMOS tube is connected with the positive voltage source, the drain is connected with the drain of the NMOS tube DM3, the source of the DM3 is connected with the negative voltage source, the drains of the DM1 and the DM3 are connected with the gates of the DM2 and the DM4, the source of the DM2 is connected with the positive voltage source, the drain of the DM2 is connected with the drain of the DM4, and the source of the DM4 is connected with the negative power source. The discriminator subtraction module is composed of resistors R ds1 -R ds6 , an operational amplifier DA4, a reference voltage V tg , a voltage-controlled switch S d1 -S d2 and an adder SUM s . The connection relationship of the discriminator subtraction module is as follows: one end of the resistor R ds1 is connected with the drains of the DM4 and the DM2, the other end of the resistor R ds1 is connected with the inverting input terminal of the operational amplifier DA4, and the resistor Rds3 One end is connected, resistor R ds3 The other end is connected to the output of operational amplifier DA4, with a reference voltage V. tg With resistance R ds2 Connected, resistor R ds2 The other end is connected to the non-inverting input of operational amplifier DA4, and also to resistor R. ds4 One end is connected, resistor R ds4 The other end is grounded, and the output signal of operational amplifier DA4 is denoted as voltage V. cp V cp With pressure control switch S d1 Connect the input terminal to the voltage-controlled switch S. d1 Control terminal and clock signal T c1 Connected, S d1 The output terminal and resistor R ds5 One end is connected to the adder SUM. s The input terminal is connected, and the resistor R ds5 The other end is grounded, voltage-controlled switch S d2 The input terminal is grounded, and the output terminal is connected to resistor R. ds6 Connected to, and simultaneously with, adder SUM s Connected to the input terminal, resistor R ds6 The other end is grounded, and the voltage-controlled switch S d2 Control terminal and clock signal T c2 Connected, adder SUM s Output signal and discriminator weight adjustment module MT dn The input terminal is connected.

[0028] Appendix Figure 4 It is a mapping diagram of the input and output relationships in the generator activation function module and the discriminator activation function module, reflecting the voltage input and output mapping relationship between the two modules.

[0029] Appendix Figure 5 It is a waveform diagram of all clock signals in the generator adversarial network circuit; T c1 The signal is high for 0-0.13 seconds and low for 0.13-0.25 seconds; T c2 The time interval is 10 milliseconds, with the first 2 milliseconds being high and the rest being low. The time interval is 10 milliseconds, with the first 5 milliseconds being low and the last 5 milliseconds being high. The time interval is 10 milliseconds, with the first 5 milliseconds being high and the last 5 milliseconds being high. The time interval is 10 milliseconds, with the first 5 milliseconds being high and the last 5 milliseconds being low.

[0030] Appendix Figure 6 This is a schematic diagram of the noise signal after sampling. The noise signal is sampled by the generator and then a random input signal is generated.

[0031] Appendix Figure 7 The output voltage V of the first generator out1 With target voltage V rd1 The diagram shows that the learning target of the first generator is a high level of 0.6V. The discriminator learns during the period of 0-0.13 seconds, during which the first generator learns the intermediate value between the highest and lowest levels of the real image signal. After 0.13 seconds, the learning voltage of the first generator is a high level of 0.6V, and the output voltage of the first generator converges to 0.6V.

[0032] Appendix Figure 8 It is the output voltage V of the third generator. out3 With target voltage V rd3 The diagram shows that the learning target of the third generator is a low level of 0.1V. The discriminator learns during the period of 0-0.13 seconds, during which the third generator learns the intermediate value between the highest and lowest levels of the real image signal. After 0.13 seconds, the learning voltage of the third generator is a low level of 0.1V, and the output voltage of the third generator converges to 0.1V.

[0033] Appendix Figure 9 This is a schematic diagram of the real image signal and the final generated image from the generator. The image shows the correspondence between each pixel in the generator and the real image signal, which is a 3x3 binary image. Figure 9 (b) is the actual image signal. Figure 9 (c) is the generated image signal output by the generator after learning.

Claims

1. A memristor-based generative adversarial network circuit, comprising: It consists of nine generators and one discriminator; each generator comprises a generator input sampling module, a generator weight adjustment module, a generator neuron module, a generator sampling module, a generator activation function module, a generator signal selection module, and a generator subtraction module; the discriminator comprises a discriminator signal selection module, a discriminator weight adjustment module, a discriminator neuron module, a discriminator sampling module, a discriminator activation function module, and a discriminator subtraction module; nine noise signals V in1 -V in9 and real image signal x n Connected to nine generators, the discriminator, in addition to connecting the output signals V of the nine generators, out1 -V out9 In addition, it is also related to the real image signal x n The discriminator calculates the error between the output image and the real image and returns it to the generator, thereby guiding the generator to optimize the generated image so that it is closer to the real image signal. Each generator is composed of nine generator input sampling modules, nine generator weight adjustment modules, one generator neuron module, one generator sampling module, one generator activation function module, one generator signal selection module and one generator subtraction module; for generator n, n = 1, 2, 3, …, 9, n is the generator number; for each component in the generator input sampling module and the generator weight adjustment module, the first two numbers n, m before the subscript represent the first number n representing the generator number and the second number m representing the corresponding mth generator input sampling module and generator weight adjustment module number in the generator n, wherein m = 1, 2, 3, …, 9; when m = 1, that is, for the first generator input sampling module of the nth generator, the module is composed of a sample holder Q n1 , a capacitor C n1 , a positive voltage source and a negative voltage source; wherein the positive and negative voltage sources are connected to the positive and negative voltage source ends of the sample holder, the capacitor C n1 is connected to the capacitor end of the sample holder Q n1 , the noise signal V in1 is connected to the input end of the sample holder; the clock signal T1 is connected to the clock end of the sample holder, and the output end of the sample holder is connected to the generator weight adjustment module; the generator weight adjustment module is composed of an operational amplifier GA n1 , a multiplier MT n1 , an adder SUM n1 , a resistor R n11 -R n12 and a voltage-controlled switch S n11 -S n12 , wherein the subscript n of the components represents the generator number n = 1, 2, 3, …, 9, and the second subscript 1 represents the connection with the first m = 1 input signal V in1 in the nth generator. sample-and-hold Q n1 One of the output terminals is connected to the input terminal of the voltage-controlled switch S n12 , and the other is connected to the multiplier MT n1 ; the other input terminal of the multiplier MT n1 is connected to the input signal V cpn , and the output terminal of the multiplier is connected to the operational amplifier GA n1 ; the output terminal of the operational amplifier GA n1 is connected to the input terminal of the voltage-controlled switch S n11 ; the control terminal of the voltage-controlled switch S n11 is connected to the clock signal T2, one of the output terminals is connected to the resistor R n11 , and the other is connected to the input terminal of the adder SUM n1 ; the other end of the resistor R n11 is grounded; the output terminal of the voltage-controlled switch S n12 is also connected to the adder SUM n1 , and the other end of the resistor R n12 is connected to the other end of the resistor R n12 ; the clock control terminal of the voltage-controlled switch S n12 is connected to the clock control signal T3; the output terminal of the adder SUM n1 is connected to the synapse in the generator neuron module; for other generator input sampling modules and generator weight adjustment modules in the generator where m is not equal to 1, the internal components are consistent with the connection when m is equal to 1; for the generator n, the generator neuron module of the generator n is composed of the memristor MR nm1 -MR nm2 , the operational amplifier GA n_1 -GA n_3 , and the resistor R n1 -R n6 , where m = 1, 2, 3, …, 9; the positive electrode of the memristor MR n11 is connected to the negative electrode of the memristor MR n12 , and together they form a memristive synapse; for other memristive synapses where m is not equal to 1, the connection mode is completely consistent with the memristive synapse when m is equal to 1; the output terminal of the adder SUM n1 is connected to the connection point of MR n11 and MR n12 ; the negative electrode of the memristor MR nm1 is connected to one end of the resistor R n1 , and the other end of the resistor R n_1 is connected to the inverting input terminal of the operational amplifier GA n1 ; the other end of the resistor R n_1 is connected to the output terminal of the operational amplifier GA n3 , and the other end of the resistor R n3 is connected to the other end of the resistor R nm2 positive electrode of the battery is connected to one end of the resistor R n2 , and the other end of the resistor R n_2 is connected to the inverting input terminal of the operational amplifier GA n2 , and the output terminal of the operational amplifier GA n_2 is connected to the other end of the resistor R n_1 , and the non-inverting input terminal of the operational amplifier GA n_2 is grounded, and the output terminal of the operational amplifier GA n_1 is connected to one end of the resistor R n3 , and the other end of the resistor R n3 is connected to the resistor R n5 , and the other end of the resistor R n_3 is connected to the inverting input terminal of the operational amplifier GA n5 , and the output terminal of the operational amplifier GA n_3 is connected to the other end of the resistor R n_2 ; the output terminal of the operational amplifier GA n4 is connected to the resistor R n4 , and the other end of the resistor R n_3 is connected to the inverting input terminal of the operational amplifier GA n_3 , and the non-inverting input terminal of the operational amplifier GA n6 is connected to the resistor R n6 , and the other end of the resistor R n is grounded; the generator sampling module is composed of a sample and hold Q n , a capacitor C n and a positive and negative voltage source; the positive and negative voltage source is connected to the power supply end of the sample and hold Q n , the capacitor C n is connected to the capacitor end of the sample and hold, the clock signal T3 is connected to the control end of Q n1 , and the output end of the sample and hold is connected to the generator activation function module; the generator activation function module is composed of a positive and negative voltage source, a PMOS tube M n2 -M n3 and an NMOS tube M n4 -M n , the output end of the sample and hold Q n1 is connected to the gate of the PMOS tube M n3 and the NMOS tube M n1 , the source of the PMOS tube M n3 is connected to the positive voltage, the drain is connected to the drain of the NMOS tube M n3 , the gate of the NMOS tube M n is connected to the output end of the sample and hold Q n3 , the source is connected to the negative voltage, the drain of M n1 is connected to the drain of M n2 , the gate of the PMOS tube M n4 The gates are connected together, M n2 The source of M is connected to a positive voltage. n4 The source of M is connected to a negative voltage. n2 With M n4 The drains of the electrodes are connected, and the signal at this point is denoted as V. outn V outn It is also connected to the generator subtraction module; the generator subtraction module consists of an operational amplifier GA. n_4 -GA n_5 Pressure-controlled switch S n3 -S n5 Resistance R dn1 -R dn9 SUM adder sn2 Composition, V outn With resistance R dn1 One end is connected, and the resistor R dn1 The other end is connected to the operational amplifier GA n_4 The inverting input terminal and resistor R dn2 Connected, resistor R dn2 The other end is connected to the operational amplifier GA n_4 The output terminal is connected to the operational amplifier GA. n_4 The non-inverting input terminal and resistor R dn4 Connected, resistor R dn4 The other end is grounded, and the resistor R dn3 It is also connected to the operational amplifier GA. n_4 The non-inverting input terminal; operational amplifier GA n_4 The output terminal is connected to the voltage-controlled switch S n3 The input terminals are connected, S n3 Output terminal and resistor R dn5 Connected, R dn5 The other end is grounded, R dn5 With S n3 The connected portion outputs a signal denoted as V. cpn S n3 Control terminal and adder SUM sn2 Connect the output terminal of the adder SUM to the output terminal. sn2 The input terminals are respectively connected to the voltage-controlled switch S n4 and S n5 Connect to the output terminal of S. n4 The output terminal is also connected to resistor R dn8 Connected, and resistor R dn8 The other end is grounded, and the voltage-controlled switch S n5 The output terminal is also connected to resistor R dn9 Connected, and resistor R dn9 The other end is grounded; operational amplifier GA n_5 The non-inverting input terminal is grounded, and the output terminal is connected to the voltage-controlled switch S. n4 The input terminal and control terminal are connected, as well as the resistor R. dn7 Connected; resistor R dn7 The other end is with GA n_5 The inverting input terminal is connected; resistor R dn6 One end and GA n_5 The inverting input terminal is connected, and this terminal is also connected to resistor R. dn7 Connect one end to the other end, and connect the other end to the voltage V. cp Connected to, and simultaneously connected to, pressure-controlled switch S n5 The control terminal and input terminal are connected; the output signal of the generator signal selection module is connected to the generator subtraction module, that is, through the adder SUM. sn1 The output terminal and resistor R dn3 One end is connected; for the generator signal selection module, it is controlled by a voltage-controlled switch S. n1 -S n2 Resistance R sn1 -R sn2 SUM adder sn1 Composition; voltage-controlled switch S n1 Control terminal and clock signal T c1 Connected, the input terminal is connected to the real image signal x n Connected, pressure-controlled switch S n1 The output terminal and resistor R sn2 Connected to, and simultaneously with, adder SUM sn1 Connect to the input terminal; voltage-controlled switch S n2 The input terminal is connected to a constant voltage V c Connected to the control terminal and the clock signal T c2 Connected, S n2 The output terminal and resistor R sn1 Connect, and simultaneously with adder SUM sn1 Connected, resistor R sn1 The other end is grounded.

2. The memristor-based generative adversarial network circuit of claim 1, wherein, The discriminator is composed of nine discriminator signal selection modules, nine discriminator weight adjustment modules, one discriminator neuron module, one discriminator sampling module, one discriminator activation function module and one discriminator subtraction module. The first subscript d of the subscripts of the components in the discriminator signal selection module and the discriminator weight adjustment module represents the position of the discriminator, the second subscript n represents the module number, wherein n = 1, 2, 3, …, 9, and the third subscript represents the number of the component. For the discriminator signal selection module and the discriminator weight adjustment module, the first subscript n of the components connected to the generator 1 is 1. The discriminator signal selection module is composed of a voltage-controlled switch S d11 -S d12 , a resistor R d11 -R d12 and an adder SUM d11 . The input end of the voltage-controlled switch S d11 is connected to the output signal V out1 of the generator 1, the control end is connected to the clock signal T c2 , the output end of S d11 is connected to one end of the resistor R d11 , and the other end of the resistor R d11 is grounded. The output end of S d11 is also connected to the input end of the adder SUM d11 . The real image signal x1 is connected to the input end of the voltage-controlled switch S d12 , the control end of the voltage-controlled switch S d12 is connected to the clock signal T c1 , the output end is connected to the input end of the adder SUM d11 , and the other end of the resistor R d12 is also connected to the input end of the adder SUM d12 . The discriminator weight adjustment module is composed of an operational amplifier DA d1 , a voltage-controlled switch S d13 -S d14 , a resistor R d13 -R d14 , a multiplier MT d1 and an adder SUM d12 . The output end of the adder SUM d11 is connected to the input end of the multiplier MT d1 and the input end of the voltage-controlled switch S d13 , the output end of MT d1 is connected to the non-inverting input end of the operational amplifier DA d1 , the inverting input end of DA d1 is grounded, and the output end of DA d1 is connected to the input end of the voltage-controlled switch S d14 , the output end of S d14 is connected to one end of the resistor R d14 Connected, resistor R d14 The other end is grounded, and the voltage-controlled switch S d14 The output is also connected to the adder SUM. d12 The input terminal, S d14 The control terminal is connected to the clock signal T2; voltage-controlled switch S d13 The control terminal is connected to the clock signal T3, S d13 Output terminal and adder SUM d12 The input terminal is connected to the resistor R. d13 Connected, resistor R d13 The other end is grounded; for the discriminator neuron module, the connection is as follows; the discriminator neuron module consists of a memristor MR n1 -MR n2 Operational amplifiers DA1-DA3 and resistor R d1 -R d6 Composition, where n = 1, 2, 3, ..., 9; where, memristor MR n1 The positive electrode and MR n2 The negative terminals are connected together to form a memristor synapse; the adder SUM d12 The output terminal is connected to two memristors MR 11 -MR 12 The connection points are connected; memristor MR n1 The negative terminal is connected to the inverting input of operational amplifier DA1, and also to resistor R. d1 Connected, resistor R d1 The other end is connected to the output of operational amplifier DA1, and the non-inverting input of operational amplifier DA1 is grounded; memristor MR n2 The positive terminal is connected to the inverting input of operational amplifier DA2, and also to resistor R. d2 The other end of the resistor is connected to the output of operational amplifier DA2, and the non-inverting input of operational amplifier DA2 is grounded; the output of operational amplifier DA1 is connected to resistor R. d3 Connected, resistor R d3 The other end is connected to resistor R d5 One end is connected to the inverting input of operational amplifier DA3, and the output of operational amplifier DA2 is connected to resistor R. d4 Connected, and resistor R d4 The other end is connected to the inverting input of operational amplifier DA3, and also to resistor R. d5 One end is connected, resistor R d5 The other end is connected to the output of operational amplifier DA3, and the non-inverting input of operational amplifier DA3 is connected to resistor R. d6 Connected, and resistor R d6 The other end is grounded; for the discriminator sampling module, the connection relationship is as follows: the discriminator sampling module is composed of a sample and hold DQ, a capacitor DC and positive and negative voltage sources, the output end of an operational amplifier DA3 is connected with the input end of the sample and hold DQ, the capacitor DC is connected with the capacitor end of the sample and hold DQ, the positive and negative power sources are connected with the positive and negative power end of the sample and hold, the control end of the sample and hold DQ is connected with a clock signal T3; the discriminator activation function module is composed of NMOS tubes DM1-DM2, PMOS tubes DM3-DM4 and positive and negative voltage sources, and the connection relationship is as follows; the output end of the sample and hold is connected with the gate of the PMOS tube DM1 and the NMOS tube DM3, the source of the PMOS tube is connected with the positive voltage source, the drain is connected with the drain of the NMOS tube DM3, the source of DM3 is connected with the negative voltage source, the drains of DM1 and DM3 are connected with the gates of DM2 and DM4 at the same time, the source of DM2 is connected with the positive voltage source, the drain of DM2 is connected with the drain of DM4, and the source of DM4 is connected with the negative power source; the discriminator subtraction module is composed of resistors R ds1 -R ds6 , an operational amplifier DA4, a reference voltage V tg , a voltage-controlled switch S d1 -S d2 and an adder SUM s ; the connection relationship of the discriminator subtraction module is as follows; the drains of DM4 and DM2 are connected with one end of a resistor R ds1 , the other end of the resistor R ds1 is connected with the inverting input end of the operational amplifier DA4, and at the same time is connected with one end of a resistor R ds3 , the other end of the resistor R ds3 is connected with the output end of the operational amplifier DA4, the reference voltage V tg is connected with the resistor R ds2 , the other end of the resistor R ds2 is connected with the non-inverting input end of the operational amplifier DA4, and at the same time is connected with one end of a resistor R ds4 , the other end of the resistor R ds4 is grounded, and the output end signal of the operational amplifier DA4 is recorded as a voltage V cp , V cp is connected with the input end of the voltage-controlled switch S d1 , the control end of the voltage-controlled switch S d1 is connected with a clock signal T c1 , the output end of S d1 is connected with one end of a resistor R ds5 , and at the same time is connected with the input end of the adder SUM s , the other end of the resistor R ds5 is grounded, the input end of the voltage-controlled switch S d2 is grounded, and the output end is connected with a resistor R ds6 connected to the input of the adder SUM s , the other end of the resistor R ds6 is grounded, the control terminal of the voltage-controlled switch S d2 is connected to the clock signal T c2 , and the output signal of the adder SUM s is connected to the input of the discriminator weight adjustment module MT dn .

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