Quantum computing system for realizing double quantum bit gates by using tunable coupler

Abstract

Methods, systems, and apparatus for implementing dual qubit gates using tunable couplers. In one aspect, a quantum computing system includes a first qubit and a second qubit; a tunable coupler disposed between the first qubit and the second qubit; and control electronics configured to apply a predefined unitary transformation control signal to the tunable coupler during operation of the quantum computing system to dynamically tune a coupling interaction between the first qubit and the second qubit, when a predefined unitary transformation control signal is applied to the tunable coupler for a predetermined period of time, the predefined unitary transformation control signal is associated with a target unitary transformation of the first qubit and the second qubit above a predetermined threshold.

Description

[0001] This case is a divisional application of a patent application for invention with an application date of August 27, 2019, an application number of 201980039667.3, and an invention title of "Method for Implementing a Two-Qubit Gate with a Tunable Coupler". Technical Field

[0002] This disclosure relates to quantum computing. Background Art

[0003] A typical computer has a memory consisting of bits, where each bit can represent either zero or one. A quantum computer maintains a sequence of quantum bits, called qubits, where each qubit can represent zero, one, or any quantum superposition of zero and one. A quantum computer operates by, for example, setting the qubits to an initial state and controlling the qubits according to a sequence of quantum logic gates. The computation ends with a readout of the qubits, collapsing the system of qubits to an eigenstate, where each qubit represents either zero or one. Summary of the Invention

[0004] This disclosure describes techniques for implementing a two-qubit quantum logic gate using a tunable coupler.

[0005] Generally, an innovative aspect of the subject matter of this disclosure can be embodied as a method, including: applying a unitary transformation control signal to a tunable coupler arranged between a first data qubit and a second data qubit to obtain a target unitary transformation of the first data qubit and the second data qubit, where the unitary transformation control signal is applied to the tunable coupler for a predetermined period of time to allow coupling between the first data qubit and the second data qubit through the tunable coupler.

[0006] The above and other implementations can each optionally include one or more of the following features. In some implementations, the unitary transformation control signal is selected from a plurality of different candidate control signals, where when the unitary transformation control signal is applied to the tunable coupler for a predetermined period of time, the selected unitary transformation control signal results in a target unitary transformation of the first data qubit and the second data qubit with an accuracy higher than a predetermined threshold.

[0007] In some implementations, selecting a unitary transformation control signal from multiple different candidate control signals includes: for each different candidate control signal, applying the candidate control signal to a tunable coupler, where two or more different candidate control signals include different maximum amplitude values; for each different candidate control signal applied to the tunable coupler, determining the corresponding precision of the unitary transformation of the first data qubit and the second data qubit; and identifying one of the candidate control signals as the selected unitary transformation control signal, where one of the identified candidate control signals has a corresponding precision higher than a predetermined threshold.

[0008] In some implementations, the method further includes: before applying each different candidate control signal to the tunable coupler: applying a disconnection control signal to the tunable coupler to change the coupling between the first data qubit and the second data qubit; and tuning each of the first data qubit and the second data qubit to the same resonance frequency.

[0009] In some implementations, two or more different candidate control signals are applied over different time periods, and the method further includes setting the time period associated with the identified candidate control signal to a predetermined time period.

[0010] In some implementations, for each different candidate control signal, applying the candidate control signal to the tunable coupler includes changing the amplitude of the candidate control signal from a first value to the maximum amplitude value of the candidate control signal.

[0011] In some implementations, for each different candidate control signal, applying the candidate control signal to the tunable coupler further includes changing the candidate control signal back from the maximum amplitude value to the first value.

[0012] In some implementations, the first value corresponds to a value where there is no coupling between the first data qubit and the second data qubit.

[0013] In some implementations, the different time periods are selected based on the two-qubit gate execution time.

[0014] In some implementations, the candidate control signal has a predetermined waveform profile.

[0015] In some implementations, the predetermined waveform includes a continuous waveform profile.

[0016] In some implementations, the predetermined waveform profile is in the form of amplitude(t) = constant*(1 - cos(t)).

[0017] In some implementations, applying the unitary transformation control signal to the tunable coupler causes a change in the operating frequency of the tunable coupler.

[0018] In some implementations, applying a unitary transformation control signal to a tunable coupler includes applying a voltage or current signal to a tunable coupler qubit.

[0019] In some implementations, a two-qubit gate includes a fermionic swap gate.

[0020] In some implementations, the first data qubit and the second data qubit include superconducting qubits.

[0021] In some implementations, the first data qubit and the second data qubit include transmon qubits.

[0022] In some implementations, a quantum computing system includes: a first qubit and a second qubit; a tunable coupler disposed between the first qubit and the second qubit; and a control electronics configured to apply a predefined unitary transformation control signal to the tunable coupler during operation of the quantum computing system to dynamically tune the coupling interaction between the first qubit and the second qubit, wherein when the predefined unitary transformation control signal is applied to the tunable coupler for a predetermined period of time, the predefined unitary transformation control signal is associated with a target unitary transformation of the first qubit and the second qubit that is higher than a predetermined threshold.

[0023] The subject matter described in this specification can be implemented in a particular way to achieve one or more of the following advantages.

[0024] A system implementing a two-qubit quantum logic gate using the techniques described in this specification can implement a two-qubit gate significantly faster than systems implementing other known techniques. For example, in some cases, a two-qubit gate can be implemented in 14 ns or less using the techniques described in this specification. Additionally, when performing a computation, a system implementing a two-qubit gate using the techniques described in this specification achieves a reduction in circuit depth. For example, in some cases, the circuit depth to establish quantum supremacy can be 16 or 10 or less. The improved circuit depth and gate / algorithm execution time improve the operation and efficiency of a quantum computing system implementing the techniques described in this specification.

[0025] Additionally, a two-qubit gate implemented using the techniques described in this specification has high fidelity and small intrinsic errors, e.g., errors not caused by decoherence. For example, in some cases, the intrinsic error can be 8×10 -5 . The implementation of the two-qubit gate is also robust to control pulse shape defects. Despite the pulse shape defects, the two-qubit gate can also be successfully implemented and the desired results achieved.

[0026] A system that uses the techniques described in this specification to implement a two-qubit quantum logic gate can implement quantum gates (unitary operators) that are difficult to simulate for classical computers, such as the Fermi SWAP gate, thus contributing to the establishment of quantum supremacy.

[0027] Additionally, in some cases, implementing a two-qubit gate using the techniques described in this specification requires reducing physical and computational complexity. For example, due to the range and flexibility of the waveform profiles of the pulses of a tunable coupler that can be applied to a two-qubit system. For instance, the techniques described in this specification for implementing a two-qubit gate do not require knowledge of the electron transfer function to reverse-engineer a suitable control sequence or control waveform for directly adjustable control parameters (such as voltage) to achieve the desired gate. Instead, the currently described techniques allow for calibrating and implementing the gate by directly tuning those control parameters. Furthermore, unlike other known techniques, the control waveform is not restricted by a particular coupler implementation or the signal interaction trajectory provided by the coupler. The techniques described in this specification can be used to implement two-qubit gates that, in combination with single-qubit gates, form a universal set of quantum gates. For example, the Fermi SWAP gate, together with single-qubit gates, forms a universal set of quantum gates.

[0028] A system that uses the techniques described in this specification to implement a two-qubit quantum gate can avoid frequency crowding. The two-qubit gates implemented using the techniques described in this specification can be executed simultaneously on a qubit system that includes more than two qubits without frequency conflicts and unnecessary interactions. Unnecessary interactions with adjacent qubits can be turned off using a controllable coupler. Executing the two-qubit gates simultaneously may reduce the circuit depth. For example, compared to not executing the two-qubit gates simultaneously, executing the two-qubit gates simultaneously may reduce the circuit depth by a factor of 2.

[0029] Details of one or more implementations of the subject matter of this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 An exemplary system for implementing a two-qubit gate with a tunable coupler is depicted.

[0031] Figure 2 A flowchart of an exemplary process for implementing a two-qubit gate on a first data qubit and a second data qubit using a tunable coupler arranged between the first data qubit and the second data qubit.

[0032] Figure 3 A flowchart of an example process for selecting a unitary transformation control signal from a plurality of different candidate control signals.

[0033] Figure 4 is a graph showing an exemplary unitary transformation control signal waveform for implementing a two - qubit Fermi SWAP gate.

[0034] Figure 5 is a graph comparing the results of numerically simulating randomly selected quantum gates on a 6 - qubit chain.

[0035] Figure 6 is a graph showing simulation results for a Fermi SWAP gate implemented using the techniques described in the present disclosure. DETAILED DESCRIPTION

[0036] This specification describes methods and systems for implementing high - fidelity two - qubit logic gates with reduced execution time by directly tuning adjustable control parameters associated with corresponding gate parameters.

[0037] A tunable coupler is located between the two qubits. The qubits and the tunable coupler are configured and arranged such that during the operation of the qubits, the tunable coupler provides a dynamic control range for the interaction between the two qubits, including an OFF state of zero interaction between the two qubits. By directly adjusting a control parameter, such as by adjusting a voltage, the tunable coupler is tuned, and thus the interaction between the two qubits is tuned. Accordingly, a two - qubit gate can be implemented by directly adjusting the control parameter according to a corresponding control waveform over a predetermined duration or time period. There is no need to know the functional dependence of the two - qubit gate on the tunable coupler parameters (such as the tunable coupler frequency) or the associated control parameter (such as the voltage).

[0038] The specific form of the control waveform is determined by performing a series of experiments. For example, a set of maximum values of the corresponding control parameter is selected, such as a set of maximum values of the voltage. Then, within a certain fixed selection time period, the corresponding control parameter is continuously increased from an initial voltage to one of the selected maximum values and then decreased back to the initial voltage. This tuning of the coupler results in a corresponding tuning of the interaction between the two qubits and a corresponding unitary transformation of the qubits.

[0039] By determining the initial state of the qubits before the interaction and measuring the state of the qubits after different interactions corresponding to different control waveforms of the control parameter, the unitary transformation associated with the corresponding control waveform of the control parameter (such as the voltage) can be determined. The maximum value of the control parameter and the duration corresponding to a particular unitary transformation only need to be determined once. Thereafter, the unitary transformation can be implemented by continuously increasing the value of the control parameter to the determined corresponding maximum value and continuously decreasing it back to the initial value within the determined time interval. A wide range of waveform curves can be used to implement a particular two - qubit gate operation with high fidelity.

[0040] Example operating environment

[0041] Figure 1 is an example system that can execute the method described with reference to Figures 2 to 3 the description.

[0042] System 100 includes quantum hardware 102, which includes at least a first data qubit 104, a second data qubit 106, and a tunable coupler 108 between the first data qubit and the second data qubit. The first data qubit 104, the second data qubit 106, and the tunable coupler 108 may be sub-components of the quantum hardware 102. For example, the quantum hardware 108 may include additional data qubits and additional tunable couplers. Each of the first data qubit 104, the second data qubit 106, and the tunable coupler 108 may be frequency-tunable.

[0043] The first data qubit 104 and the second data qubit 106 may be superconducting qubits. For example, the first data qubit 104 and the second data qubit 106 may be transmon qubits. Other qubit architectures may be used alternatively.

[0044] A variety of different tunable coupler designs can be used. For example, the tunable coupler 108 can include a three-terminal device constructed from a superconducting material, using a fixed negative mutual inductance and a single current-biased Josephson junction that acts as a tunable positive inductance. Further discussion and examples of tunable couplers are described in detail in “A tunable coupling scheme for implementing high-fidelity two-qubit gates”, Fei Yan et al., arxiv:quant-ph / 180309813v1, “Demonstration of a Tuneable Coupler for Superconducting Qubits Using Coherent, Time Domain, Two-Qubit Operations”, R.C. Bialczak et al., arxiv:quant-ph / 1007.2219v1, “Sign-and magnitude-tunable coupler for superconducting flux qubits”, and R. Harris et al., arxiv:cond-mat / 0608253v4, “Tunable coupler for superconducting Xmon qubits: Perturbative nonlinear model”, Michael R. Geller et al., arxiv:quant-ph / 1405.1915v1, each of which is incorporated herein by reference in its entirety.

[0045] The system 100 includes a control electronics 110. The control electronics 110 can include an arbitrary waveform generator.

[0046] System 100 includes qubit control lines 112 from a control electronic device 110 to a first data qubit 104 and a second data qubit 106 respectively. For example, the qubit control lines 112 can be used to tune the frequencies of the first data qubit 104 and the second data qubit 106. The frequencies of the first data qubit 104 and the second data qubit 106 can be tuned by applying a control signal to the qubit control lines 112 via the control electronic device 110. Additionally, the control electronic device 110 can perform measurements on the first data qubit 104 and the second data qubit 106 via the qubit control lines 112. The measurements of the first data qubit 104 and the second data qubit 106 respectively determine the states of the first data qubit 104 and the second data qubit 106. The control electronic device 110 can store, display, and / or further process the results of each measurement of the first data qubit 104 and the second data qubit 106.

[0047] System 100 includes a tunable coupler control line 114. By applying a control signal to the tunable coupler control line 114 to tune the frequency of the tunable coupler 108, the control electronic device 110 can dynamically tune the coupling or interaction between the first data qubit 104 and the second data qubit 106. For example, the control electronic device 110 can apply a voltage pulse to the tunable coupler control line 114 to tune the frequency of the tunable coupler 108. In some implementations, the control electronic device 110 can include data processing means and associated memory. The memory can include a computer program having instructions that, when executed by the data processing means, cause the data processing means to perform one or more functions described herein, such as applying a control signal to a qubit and / or a tunable coupler.

[0048] Example method for implementing a two-qubit gate using a tunable coupler

[0049] Figure 2 is a flowchart of an example process 200 for implementing a two-qubit gate on a first data qubit and a second data qubit using a tunable coupler arranged between the first data qubit and the second data qubit. For example, process 200 can be used to implement a fermionic SWAP gate on the first data qubit and the second data qubit. For convenience, process 200 is described as being performed by quantum hardware in communication with a control electronic device located at one or more locations. For example, a Figure 1 system 100 programmed appropriately according to this specification can perform process 200.

[0050] In the first step of the process, a unitary transformation control signal is selected from a plurality of different candidate control signals to implement a two-qubit when applied to a first data qubit and a second data qubit (step 202). When the unitary transformation control signal is applied to the tunable coupler for a predetermined period of time, the selected unitary transformation control signal results in a target unitary transformation of the first data qubit and the second data qubit with an accuracy higher than a predetermined threshold.

[0051] The predetermined threshold for the accuracy of the target unitary transformation can be determined based on the target fidelity of the two-qubit gate. For example, the predetermined threshold for the accuracy can be selected to be higher than a critical value to successfully execute a quantum algorithm using the two-qubit gate or to successfully establish quantum supremacy using the two-qubit gate.

[0052] The plurality of different candidate control signals can have a predetermined waveform profile. In some cases, the predetermined waveform profile can be a continuous waveform profile, for example, of the form amplitude(t) = constant*(1 - cos(t)). However, the waveform profile can vary as long as the maximum amplitude, the predetermined period of time, and the area under the amplitude trajectory are fixed at predetermined values. This allows for various different control waveforms to implement the two-qubit gate. In some cases, the period of the sine wave can also be changed. However, to minimize the effects of decoherence, a shorter total pulse length that does not reduce the inherent fidelity of the gate can be selected. Referring below Figure 3 to describe an example process for determining the unitary transformation control signal.

[0053] In the second step of the process, the unitary transformation control signal selected in step 202 is applied to the tunable coupler to obtain a target unitary transformation of the first data qubit and the second data qubit (step 204). Applying the unitary transformation control signal to the tunable coupler can include applying a voltage or current signal to the tunable coupler, thereby causing a change in the operating frequency of the tunable coupler. The unitary transformation control signal is applied to the tunable coupler over a predetermined period of time to allow coupling between the first data qubit and the second data qubit through the tunable coupler. The predetermined period of time can be selected based on the target two-qubit gate execution time, as described below Figure 3 is described.

[0054] Figure 3 is a flowchart of an example process 300 for selecting a unitary transformation control signal from a plurality of different candidate control signals. For convenience, process 300 is described as being executed by quantum hardware in communication with control electronics located at one or more locations. For example, a system 100 appropriately programmed according to this specification Figure 1 can execute process 300.

[0055] In the first step of the process, each different candidate control signal is applied to the tunable coupler (step 302). Two or more different candidate control signals have different maximum amplitude values. Different maximum amplitude values for the different candidate control signals can be selected based on the hardware implementing the two-qubit gate. For example, the maximum amplitude value can be selected to be below a critical value that may cause an undesired transition of the first data qubit or the second data qubit to a non-computational basis state.

[0056] Before applying the candidate control signal to the tunable coupler, the first data qubit and the second data qubit can be tuned to the same resonant frequency. Tuning the first data qubit and the second data qubit to the same resonant frequency aligns the first qubit and the second qubit and enables the tunable coupler to facilitate the interaction between the first qubit and the second qubit. For example, the first data qubit and the second data qubit can be tuned to a resonant frequency of 6 GHz or a resonant frequency in the range between 5 GHz and 7 GHz. Additionally, a disconnect control signal can be applied to the tunable coupler to change the coupling between the first data qubit and the second data qubit. Then the candidate control signal can be applied to the tunable coupler.

[0057] Applying two or more different candidate control signals to the tunable coupler can include applying the two or more different candidate control signals to the tunable coupler at different time periods. The different time periods can be selected based on the target two-qubit gate execution time and the details of the hardware implementing the two-qubit gate. For example, the candidate time periods can include time periods slow enough so as not to cause an undesired transition of the first data qubit or the second data qubit to a non-computational basis state, but close enough to the target gate execution time. For example, in some cases, the minimum distance between the computational basis state and the non-computational basis state can be at least 200 - 250 MHz. In these cases, the candidate time periods can be selected to be longer than 1 / 200 MHz, such as 5 ns, 6 ns, 7 ns, 8 ns or slower.

[0058] Applying the candidate control signal to the tunable coupler can include changing the candidate control signal amplitude from a first value (e.g., a value where there is no coupling between the first data qubit and the second data qubit) to the maximum amplitude value of that particular candidate control signal. Optionally, this can further include changing the candidate control signal back from the maximum amplitude value to the first value.

[0059] In the second step of the process, for each different candidate control signal applied to the tunable coupler, the corresponding accuracy of the unitary transformation of the first data qubit and the second data qubit is determined (step 304). The accuracy can be determined by measuring the states of the first data qubit and the second data qubit after each application of one of the different candidate control signals to the tunable coupler.

[0060] In the third step of the process, candidate control signals for unitary transformations that result in a precision higher than a predetermined threshold are identified (step 306). The time period associated with the identified candidate control signals can be set to a predetermined time period. The following refers to Figures 4 to 6 Describe an example unitary transformation control signal for implementing the two-qubit Fermi SWAP gate identified using processes 200 and 300.

[0061] Figure 4 FIG. 400 is a graph showing an exemplary unitary transformation control signal waveform for implementing a two-qubit Fermi SWAP gate represented by a 4×4 matrix.

[0062]

[0063] The graph includes a horizontal axis 404 representing time (ns) and a vertical axis 406 representing coupling strength (MHz) (voltage applied to the tunable coupler control line). The unitary transformation control signal waveform 402 is an example of a waveform determined using processes 200 and 300 described with reference to Figure 2 and Figure 3 For example, the unitary transformation control signal waveform 302 is configured to implement a Fermi SWAP gate on a first data qubit and a second data qubit by applying to a tunable coupler located between the first data qubit and the second data qubit.

[0064] The unitary transformation control signal waveform 402 is a non-limiting example of many unitary transformation control signal waveforms that can implement a Fermi SWAP gate. For example, the same target unitary transformation can also be achieved using control signal waveforms with different durations combined with different maximum amplitudes. As long as the maximum amplitude, duration, and the area under the amplitude curve are the same, the same target unitary transformation can also be achieved for different waveform profiles. Generally, processes 200 described with reference to Figure 2 can be used to determine different unitary transformation control signal waveforms combined with the same or different durations and maximum amplitudes to achieve different target unitary transformations.

[0065] As shown in graph 400, the unitary transformation control signal waveform 402 can perform a two-qubit Fermi SWAP operation in 14 ns. An alternative method of implementing the two-qubit Fermi SWAP operation may be three times slower. Additionally, the Fermi SWAP gate implemented by the unitary transformation control signal waveform 402 has an inherent error of 8×10 -5 .

[0066] Figure 5FIG. 500 is a graph comparing the results of numerically simulating randomly selected quantum gates on a 6 - qubit chain. The graph includes a horizontal axis 502 representing the number of cycles of gate application and a vertical axis 504 representing the distance from the Porter - Thomas distribution (i.e., a measure of computational complexity). The first line 506 shows the result of simulating randomly selected quantum gates using the controlled - Z (CZ) gate. The second line 508 shows the result of simulating randomly selected quantum gates using the Fermi SWAP gate implemented by controlling the signal waveform with the unitary transformation described herein.

[0067] As shown in FIG. 500, using the Fermi SWAP gate instead of the CZ gate results in the convergence of the Porter - Thomas distribution and a 2.5 - fold reduction in circuit depth.

[0068] Figure 6 FIG. 600 is a graph showing the simulation results for the Fermi SWAP gate implemented using the techniques described in the present disclosure. The graph includes a horizontal axis 602 representing the circuit depth and a vertical axis 604 representing the performance metrics purity and cross - entropy benchmarking (XEB), both of which take values between 0 and 1. The cross - entropy measures the overall fidelity of the Fermi SWAP gate. The purity measures the error due to decoherence.

[0069] The simulation results show that the cross - entropy (606) and the purity measurement (608) almost coincide, indicating that the quantum algorithm using the Fermi SWAP gate is a coherence - limited algorithm. Further, the simulation results show that, as described with reference to Figure 2 and Figure 3 the Fermi SWAP gate implemented by applying a unitary transformation control signal to a tunable coupler has high fidelity, with an error of approximately 0.4% or approximately 0.2% for each Fermi SWAP gate. The 0.2% error is approximately 3 times the minimum two - qubit gate error achievable using other known techniques.

[0070] Implementations of the subject matter and the operations described in this specification can be realized in a tangible - embodied software or firmware, in computer hardware in digital electronic circuits, analog electronic circuits, suitable quantum circuits, or more generally in a quantum computing system, including the structures disclosed in this specification and their equivalent structures, or combinations of one or more of them. The term "quantum computing system" can include, but is not limited to, a quantum computer, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0071] Implementations of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access storage device, one or more qubits, or a combination of one or more of them. Optionally or additionally, the program instructions can be encoded on an artificially generated propagated signal capable of encoding digital and / or quantum information, such as a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode the digital and / or quantum information for transmission to a suitable receiver device for execution by the data processing apparatus.

[0072] The terms quantum information and quantum data refer to information or data carried, held, or stored by a quantum system, where the smallest non-trivial system is a qubit, i.e., the system that defines the unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be suitably approximated as two-level systems in the corresponding context. Such quantum systems can include, for example, multi-level systems having two or more levels. For example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified with the ground state and the first excited state, but it should be understood that other settings for identifying the computational states with higher levels of excitation are also possible.

[0073] The term "data processing apparatus" refers to digital and / or quantum data processing hardware and includes various devices, apparatuses, and machines for processing digital and / or quantum data, such as including programmable digital processors, programmable quantum processors, digital computers, quantum computers, multiple digital and quantum processors or computers and their combinations. The apparatus can also be or further include dedicated logic circuits, such as FPGAs (field-programmable gate arrays), ASICs (application-specific integrated circuits), or quantum simulators, i.e., quantum data processing apparatuses designed to simulate or generate information about a particular quantum system. In particular, a quantum simulator is a dedicated quantum computer that does not have the ability to perform general quantum computing. In addition to the hardware, the apparatus can optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code that constitutes processor firmware, protocol stacks, database management systems, operating systems, or a combination of one or more of them.

[0074] A digital computer program, which may also be referred to as or described as a program, software, software application, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A quantum computer program, which may also be referred to as or described as a program, software, software application, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted languages or declarative or procedural languages, and translated into a suitable quantum programming language, or can be written in a quantum programming language (e.g., QCL or Quipper).

[0075] A computer program may or may not correspond to a file in a file system. The program can be stored in a part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a data communication network. A quantum data communication network is understood to be a network that can send quantum data using a quantum system (e.g., qubits). Generally, a digital data communication network cannot send quantum data, but a quantum data communication network can send both quantum data and digital data.

[0076] The processing and logical flows described in this specification can be performed by one or more programmable computers, operating appropriately with one or more processors, executing one or more computer programs to perform functions by operating on input data and generating output. The processing and logical flows can also be performed by dedicated logic circuitry (e.g., FPGA or ASIC) or a quantum simulator, or the apparatus can be implemented as dedicated logic circuitry or a quantum simulator, or by dedicated logic circuitry or a quantum simulator and one or more programmed digital and / or quantum computers.

[0077] For a system of one or more computers to be “configured to” perform a particular operation or action means that the system has software, firmware, hardware, or a combination thereof installed on it, which in operation causes the system to perform those operations or actions. For one or more computer programs to be configured to perform a particular operation or action means that the one or more programs include instructions that, when executed by a data processing apparatus, cause the apparatus to perform the operation or action. For example, a quantum computer can receive instructions from a digital computer that, when executed by a quantum computing apparatus, cause the apparatus to perform the operation or action.

[0078] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose processor or any other kind of central processing unit. Generally, the central processing unit will receive instructions and data from a read-only memory, a random access memory, or a quantum system suitable for transmitting quantum data (e.g., photons or a combination thereof).

[0079] The components of a computer include a central processing unit for performing or executing instructions and one or more storage devices for storing instructions and digital, analog, and / or quantum data. The central processing unit and the memory can be supplemented or incorporated by dedicated logic circuits or quantum simulators. Generally, a computer will also include or be operatively coupled to receive data from or transfer data to one or more mass storage devices (e.g., magnetic, magneto-optical, optical disks, or quantum systems suitable for storing quantum information) for storing data or both. However, a computer need not have such devices.

[0080] Quantum circuit elements (also referred to as quantum computing circuit elements) include circuit elements for performing quantum processing operations. That is, quantum circuit elements are configured to perform operations on data in a non-deterministic manner using quantum mechanical phenomena such as superposition and entanglement. Particular quantum circuit elements (such as qubits) can be configured to represent and operate on information in more than one state simultaneously. Examples of superconducting quantum circuit elements include circuit elements such as quantum LC oscillators, qubits (e.g., flux qubits, phase qubits, or charge qubits), and superconducting quantum interference devices (SQUIDs) (e.g., RF-SQUIDs or DC-SQUIDs).

[0081] In contrast, classical circuit elements generally process data in a deterministic manner. Classical circuit elements can be configured to jointly execute the instructions of a computer program by performing basic arithmetic, logical, and / or input / output operations on data, where the data is represented in analog or digital form. In some implementations, classical circuit elements can be used to send data to and / or receive data from quantum circuit elements via electrical or electromagnetic connections. Examples of classical circuit elements include circuit elements based on CMOS circuits, rapid single flux quantum (RSFQ) devices, reciprocal quantum logic (RQL) devices, and ERSFQ devices, which are energy-efficient versions of RSFQ that do not use bias resistors.

[0082] In certain cases, some or all of the quantum and / or classical circuit elements can be implemented using, for example, superconducting qubits and / or classical circuit elements. The fabrication of superconducting circuit elements may require depositing one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, these materials can be deposited using deposition processes, such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among other deposition processes. The processes described herein for fabricating circuit elements may require removing one or more materials from the device during fabrication. Depending on the materials to be removed, the removal processes can include, for example, wet etching techniques, dry etching techniques, or lift-off processes. Known lithography techniques (e.g., photolithography or electron beam lithography) can be used to pattern the materials forming the circuit elements described herein.

[0083] During operation of a quantum computing system using superconducting quantum circuit elements and / or superconducting classical circuit elements (such as the circuit elements described herein), the superconducting circuit elements are cooled within a cryostat to a temperature that allows the superconducting material to exhibit superconducting properties. A superconductor (alternatively superconducting) material can be understood as a material that exhibits superconducting performance at or below a superconducting critical temperature. Examples of superconducting materials include aluminum (superconducting critical temperature of 1.2 Kelvin) and niobium (superconducting critical temperature of 9.3 Kelvin). Thus, superconducting structures, such as superconducting traces and superconducting ground planes, are formed from materials that exhibit superconducting properties at or below the superconducting critical temperature.

[0084] In some implementations, classical circuit elements that are electrically and / or electromagnetically coupled to the quantum circuit elements can be used to provide control signals for the quantum circuit elements (e.g., qubits and qubit couplers). The control signals can be provided in digital and / or analog form.

[0085] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile digital and / or quantum memories, media, and storage devices, including, for example, semiconductor storage devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; CD-ROM and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It can be understood that a quantum memory is a device that can store quantum data with high fidelity and high efficiency for a long time, such as an optical-matter interface, where light is used for transmission and matter is used to store and preserve the quantum characteristics of the quantum data, such as superposition or quantum coherence.

[0086] Control of the various systems or portions thereof described in this specification can be implemented in a computer program product that includes instructions stored on one or more non-transitory machine-readable storage media and executable on one or more processing devices. The systems or portions thereof described in this specification can each be implemented as an apparatus, method, or system that can include one or more processing devices and a memory to store executable instructions to perform the operations described in this specification.

[0087] Although this specification contains many specific implementation details, these details should not be construed as limitations on any invention or the scope of what is claimed, but rather as descriptions of features specific to particular implementations of particular inventions. The specific features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, the various features described in the context of a single implementation can also be implemented separately in multiple implementations or in any suitable sub-combination. Moreover, although the features may be described above as acting in a particular combination and even initially claimed as such, in some cases, one or more features from the claimed combination can be deleted from the combination, and the claimed combination can be used in a sub-combination or variation of a sub-combination.

[0088] Similarly, although the operations are depicted in the drawings in a particular order and recited in the claims, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. In addition, the separation of the various system modules and components in the above-described implementations should not be understood as required in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0089] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. For example, the acts recited in the claims can be performed in a different order and still achieve the desired result. As one example, the processing depicted in the figures does not necessarily need the particular order or sequential order shown to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous.

Claims

1. A quantum computing system, comprising: A first qubit and a second qubit; A tunable coupler disposed between the first qubit and the second qubit; And A control electronic device configured to apply a predefined unitary transformation control signal to the tunable coupler during the operation of the quantum computing system to dynamically tune the coupling interaction between the first qubit and the second qubit, Wherein, when the predefined unitary transformation control signal is applied to the tunable coupler within a predetermined time period, the predefined unitary transformation control signal is associated with a target unitary transformation of the first qubit and the second qubit that is higher than a predetermined threshold.

2. The quantum computing system according to claim 1, wherein, The control electronic device is configured to, before applying the predefined unitary transformation control signal to the tunable coupler: Apply a disconnection control signal to the tunable coupler to turn off the coupling between the first qubit and the second qubit; and Tune each of the first qubit and the second qubit to the same resonant frequency.

3. The quantum computing system according to claim 1, wherein Each of the first qubit and the second qubit includes a superconducting qubit.

4. The quantum computing system according to claim 3, wherein, Each superconducting qubit includes a transmon qubit.

5. The quantum computing system according to claim 1, wherein The control electronic device is configured to measure the first qubit and the second qubit.

6. The quantum computing system according to claim 1, wherein The control electronic device is configured to apply the predefined unitary transformation control information to the tunable coupler by changing the amplitude of the predefined unitary transformation control signal from a first value to a maximum amplitude value, where the first value corresponds to a value where there is no coupling between the first qubit and the second qubit.

7. The quantum computing system according to claim 1, wherein The predetermined time period is based on the two-qubit gate execution time.

8. The quantum computing system according to claim 7, wherein, The application of the predefined unitary transformation control signal within the predetermined time period implements a two-qubit gate, where the two-qubit gate includes a Fermi SWAP gate.

9. The quantum computing system according to claim 1, wherein, The predefined unitary transformation control signal includes a continuous waveform profile.

10. The quantum computing system according to claim 9, wherein, The continuous waveform profile is in the form of amplitude(t) = constant*(1 - cos(t)).

11. The quantum computing system according to claim 1, wherein, The control electronic device being configured to apply the unitary transformation control signal to the tunable coupler includes applying a voltage or current signal to the tunable coupler.

12. The quantum computing system according to claim 1, wherein, The first qubit and the second qubit include superconducting qubits.

13. The quantum computing system according to claim 1, wherein, The first qubit and the second qubit include transmon qubits.

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