Three-dimensional circuit board testing method, device and system

Abstract

The invention discloses a three-dimensional circuit board test method, device and system, which can improve the calculation speed in a three-dimensional model test process. The three-dimensional circuit board testing method comprises the following steps: acquiring a standard format file of a circuit board; the standard format file is used for describing manufacturing parameters of the circuit board; generating a plurality of scalable vector graphs based on the standard format file of the circuit board; wherein each scalable vector graph corresponds to different working layers of the circuit board; generating a three-dimensional model of the circuit board based on the plurality of scalable vector graphs; extracting element graph coordinates from the scalable vector graph, and correspondingly generating a two-dimensional picture; wherein the two-dimensional picture comprises key pixel points corresponding to the element graph coordinates; and based on the mapping relationship between the two-dimensional picture and the scalable vector graph and the mapping relationship between the scalable vector graph and the three-dimensional model, mapping the key pixel points of the two-dimensional picture to the three-dimensional model.

Description

Technical Field

[0001] This application relates to the technical field of circuit board testing, and particularly to a three-dimensional circuit board testing method, apparatus, and system. Background Art

[0002] A printed circuit board (PCB) is a common component in daily electronic products. The connection between electronic components is achieved by soldering the electronic components to the surface wires and pads, and then a complete circuit system is built. The production process of a circuit board involves multiple links such as design, proofing, and production. It is necessary to reduce the possibility of failures in each link to improve the overall yield of circuit board manufacturing. Currently, the common testing method in the circuit board manufacturing link is to generate a simulated three-dimensional PCB model through simulation detection software, and then perform manufacturability analysis on the simulated three-dimensional PCB model to eliminate the layout problems of the PCB before production. However, due to the complexity of the three-dimensional model, when constructing a three-dimensional model for manufacturability testing, the required computing method is relatively complex and the amount of computation is relatively large, resulting in a slow testing process. Summary of the Invention

[0003] To solve the above technical problems, this application is proposed. Embodiments of this application provide a three-dimensional circuit board testing method, apparatus, and system, which can improve the calculation speed during the three-dimensional model testing process.

[0004] According to a first aspect of this application, a three-dimensional circuit board testing method is provided, including: obtaining a standard format file of the circuit board; the standard format file is used to describe the manufacturing parameters of the circuit board; based on the standard format file of the circuit board, generating multiple scalable vector graphics; where each scalable vector graphic corresponds to a different working layer of the circuit board; based on the multiple scalable vector graphics, generating a three-dimensional model of the circuit board; extracting element graphic coordinates from the scalable vector graphics and correspondingly generating two-dimensional pictures; where the two-dimensional pictures include key pixel points corresponding to the element graphic coordinates; based on the mapping relationship between the two-dimensional pictures and the scalable vector graphics, and the mapping relationship between the scalable vector graphics and the three-dimensional model, mapping the key pixel points of the two-dimensional pictures to the three-dimensional model.

[0005] As a possible implementation, based on the standard format file of the circuit board, generating multiple scalable vector graphics includes: parsing the standard format file of the circuit board to generate scalable vector graphics corresponding to each layer of the circuit board; where the layers of the circuit board include a solder mask layer, a solder paste layer, a copper layer, and a drilling layer.

[0006] As a possible implementation, extract the element graphic coordinates from the scalable vector graphic and correspondingly generate a two-dimensional picture, including: converting the scalable vector graphic into a two-dimensional picture; extracting the element graphic coordinates in the scalable vector graphic; corresponding the element graphic coordinates to the pixel points of the two-dimensional picture to generate key pixel points; wherein, each of the element graphic coordinates corresponds to one pixel point.

[0007] As a possible implementation, after corresponding the element graphic coordinates to the pixel points of the two-dimensional picture to generate key pixel points, the three-dimensional circuit board testing method further includes: checking the coincidence of the key pixel points between preset targets in the two-dimensional picture based on the key pixel points of the two-dimensional picture; wherein, the preset targets include the elements corresponding to the element graphic coordinates; generating a test result according to the coincidence of the key pixel points between the preset targets.

[0008] As a possible implementation, after generating a test result according to the distance between the preset targets, the three-dimensional circuit board testing method includes: feeding back the test result to the three-dimensional model testing interface to display and use the test result; wherein, the test result includes at least one of normal, warning or error results.

[0009] As a possible implementation, the key pixel points include the pixel points corresponding to the trace coordinates of the copper layer, the pixel points corresponding to the window coordinates of the solder mask layer, the pixel points corresponding to the hole coordinates of the drilling layer, and the pixel points corresponding to the pad coordinates of the solder paste layer.

[0010] As a possible implementation, generate a three-dimensional model of the circuit board based on multiple scalable vector graphics, including: converting multiple scalable vector graphics into a three-dimensional model of the circuit board based on a first calculation formula; extracting the element graphic coordinates from the scalable vector graphics and correspondingly generating a two-dimensional picture, including: converting the scalable vector graphic into a two-dimensional picture based on a second calculation formula.

[0011] As a possible implementation, map the key pixel points of the two-dimensional picture to the three-dimensional model based on the mapping relationship between the two-dimensional picture and the scalable vector graphic, and the mapping relationship between the scalable vector graphic and the three-dimensional model, including: determining a first mapping relationship between the two-dimensional picture and the scalable vector graphic based on the first calculation formula; determining a second mapping relationship between the scalable vector graphic and the three-dimensional model based on the second calculation formula; obtaining a third mapping relationship between the two-dimensional picture and the three-dimensional model based on the first mapping relationship and the second mapping relationship; mapping the key pixel points of the two-dimensional picture to the three-dimensional model based on the third mapping relationship.

[0012] According to a second aspect of the present application, a three-dimensional circuit board testing device is provided, including: an acquisition module for acquiring a standard format file of the circuit board; the standard format file is used to describe the manufacturing parameters of the circuit board; a first generation module for generating a plurality of scalable vector graphics based on the standard format file of the circuit board; wherein each scalable vector graphic corresponds to a different working layer of the circuit board; a second generation module for generating a three-dimensional model of the circuit board based on the plurality of scalable vector graphics; a third generation module for extracting element graphic coordinates from the scalable vector graphics and correspondingly generating two-dimensional pictures; wherein the two-dimensional pictures include key pixel points corresponding to the element graphic coordinates; a mapping module for mapping the key pixel points of the two-dimensional pictures to the three-dimensional model based on the mapping relationship between the two-dimensional pictures and the scalable vector graphics and the mapping relationship between the scalable vector graphics and the three-dimensional model.

[0013] According to a third aspect of the present application, a three-dimensional circuit board testing system is provided, including: a three-dimensional model testing and display module for displaying a three-dimensional model and test results; the three-dimensional circuit board testing device as described in the second aspect above, and the three-dimensional circuit board testing device is communicatively connected to the three-dimensional model testing and display module.

[0014] The three-dimensional circuit board testing method, device and system provided by the present application can generate a three-dimensional model and scalable vector graphics according to the standard format file of the circuit board, generate two-dimensional pictures through the scalable vector graphics, and establish a coordinate correspondence relationship among the three-dimensional model, the scalable vector graphics and the two-dimensional pictures. Based on this, the complex calculations originally in the three-dimensional scene are placed in the two-dimensional pictures for calculation, such as collision detection, etc., thereby reducing the amount of computation, improving the calculation speed, and enhancing the detection efficiency of the circuit board model. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other objects, features and advantages of the present application will become more obvious. The drawings are used to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to explain the present application together with the embodiments of the present application, and do not constitute a limitation to the present application. In the drawings, the same reference numerals generally represent the same components or steps.

[0016] Figure 1 It is a schematic flowchart of a three-dimensional circuit board testing method provided by an exemplary embodiment of the present application.

[0017] Figure 2 It is a schematic flowchart of a three-dimensional circuit board testing method provided by another exemplary embodiment of the present application.

[0018] Figure 3 It is a schematic structural diagram of a three-dimensional circuit board testing device provided by an exemplary embodiment of the present application.

[0019] Figure 4 It is a structural diagram of an electronic device provided by an exemplary embodiment of the present application. Detailed implementation manners

[0020] Next, exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. It should be understood that the present application is not limited by the exemplary embodiments described herein.

[0021] Application overview

[0022] When a printed circuit board (PCB) is designed and manufactured, a 3D (three-dimensional) model is created for calculation and display, which can truly simulate the shape, size, and layout of the circuit board in the real world, so that potential problems and errors can be discovered at the design stage. For example, through the 3D model, the designer can intuitively view the structure and layout of the circuit board to ensure that the spacing, position, and orientation between each component meet the design requirements. In addition, in the 3D model, the distance between components on the circuit board, as well as potential collisions between components and the edge of the circuit board or other components, can be measured, which helps to avoid rework and increased costs caused by size or position errors during the actual manufacturing process. Moreover, the 3D model provides a more intuitive and three-dimensional layout method, enabling the designer to arrange the positions of components and wiring more efficiently, simulate the assembly process of the circuit board, discover potential assembly problems and solve them in advance, simplify the assembly process, and improve the accuracy and efficiency of assembly. However, when performing distance measurement and collision testing on the 3D model, due to the complexity of the three-dimensional space in terms of the number of parameters, degrees of freedom, space mapping, as well as the collision detection algorithm and computational complexity, the calculation speed is slow. In a three-dimensional space, distance measurement involves three parameters (such as x, y, and z coordinates), which means that more information is required to determine the position of a point in the three-dimensional space. Therefore, the calculation process is more complex. Three-dimensional distance measurement requires mapping the object into the three-dimensional space for calculation, increasing the complexity of the possible positions and orientations of the object in space, thus increasing the difficulty of distance measurement. In addition, in a three-dimensional space, the collision detection algorithm needs to handle more complex geometric shapes (such as polyhedrons, spheres, etc.), increasing the difficulty and complexity of the algorithm. It is necessary to calculate the position and shape of the object in the three-dimensional space, involving a large amount of mathematical operations and geometric calculations.

[0023] To solve the problem of slow calculation speed of 3D models, the 3D circuit board testing method, device and system provided in this application can generate a 3D model and a scalable vector graphic based on the standard format file of the circuit board, and generate a 2D picture through the scalable vector graphic. At the same time, a coordinate correspondence relationship is established among the 3D model, the scalable vector graphic, and the 2D picture. That is, the (x, y, z) coordinates in the three-dimensional scene are mapped to the (x, y) pixel points in the 2D picture. Mapping the object onto a plane for calculation reduces the complexity of the calculation and improves the calculation speed. After the calculation is completed, the coordinates are mapped to the 3D model of the corresponding layer, and the test result is returned. The calculation result is displayed and used in the 3D model. The entire process does not perform calculations in the 3D interface, reducing the amount of computation, thereby achieving an improvement in the speed of testing the 3D circuit board model.

[0024] Exemplary method

[0025] To solve the problem of slow calculation speed of 3D models, Figure 1 is a schematic flow chart of the 3D circuit board testing method provided by an exemplary embodiment of this application. Taking Figure 1 as an example, first, obtain the standard format file of the circuit board (see Figure 1 S100), and the standard format file is used to describe the manufacturing parameters of the circuit board. The standard format file can be a gerber file, and the gerber file is an important file format used in the electronics industry for the manufacturing of printed circuit boards (PCBs) and surface mount technology (SMT) processing. Then, based on the standard format file of the circuit board, generate multiple scalable vector graphics (see Figure 1 S200). The scalable vector graphic is an SVG (Scalable Vector Graphics) file, which is a vector graphic format based on XML. Then, based on the multiple scalable vector graphics, generate a 3D model of the circuit board (see Figure 1 S300). The gerber file contains vector graphics, and through system parsing, the SVG corresponding to each layer and the corresponding model can be generated. Then, extract the element graphic coordinates from the scalable vector graphic and correspondingly generate a 2D picture (see Figure 1 S400). Among them, the 2D picture includes key pixel points corresponding to the element graphic coordinates. The svg can be converted into a 2D picture through a tool, and the element graphic coordinates are correspondingly projected. Finally, based on the mapping relationship between the 2D picture and the scalable vector graphic, and the mapping relationship between the scalable vector graphic and the 3D model, map the key pixel points of the 2D picture onto the 3D model (see Figure 1In the S500). Since the three-dimensional model is generated based on scalable vector graphics, it is possible to know the algorithm for mapping the coordinates of the scalable vector graphics to the three-dimensional model coordinates. Moreover, since the two-dimensional picture is also generated based on the scalable vector graphics, it is possible to know the algorithm for mapping the coordinates of the scalable vector graphics to the two-dimensional picture. By establishing a corresponding relationship between the two equations, it is possible to obtain the mapping from the coordinates of the two-dimensional picture to the three-dimensional model, thereby obtaining the three-dimensional model display result and improving the calculation speed of the three-dimensional model test.

[0026] The following combines Figure 1 to introduce the three-dimensional circuit board testing method provided by the embodiments of the present application in more detail.

[0027] In S100, a standard format file of the circuit board is obtained; the standard format file is used to describe the manufacturing parameters of the circuit board. The standard format file can be a Gerber file. The Gerber file is an important file used in the electronics industry for printed circuit board (PCB) manufacturing and surface mount technology (SMT) processing. The Gerber file defines the digital structure diagram of the PCB, including the graphic information of each layer on the circuit board, such as wiring, surface mount components, drilling, etc. This file allows circuit board manufacturers to accurately produce through electronic manufacturing equipment (such as drilling machines, pin insertion machines, chip mounters, etc.), thereby greatly improving the manufacturing efficiency and accuracy. The Gerber file is an indispensable part of the PCB design and manufacturing process, ensuring that the design information can be accurately transformed into an actual circuit board product. The Gerber file is usually generated by professional electronic design automation (EDA) software. These software provide rich drawing and editing tools, allowing designers to create complex PCB designs. After the design is completed, the software can export the design information in the Gerber file format for manufacturers to produce. Therefore, the Gerber file is the standard file for PCB manufacturing. After obtaining the Gerber file, the manufacturing parameters of the circuit board to be produced can be obtained, and then converted into other files or pictures for further analysis.

[0028] In S200, based on the standard format file of the circuit board, multiple scalable vector graphics are generated. Each scalable vector graphic corresponds to a different working layer of the circuit board. For example, if the layers of the circuit board include: solder mask layer, solder paste layer, copper layer, drilling layer, then 4 scalable vector graphics are generated. The Gerber file contains vector graphics, and through system parsing, the SVG (scalable vector graphic) corresponding to each layer and the corresponding model can be generated.

[0029] One implementation of S200 may be: parsing the standard format file of the circuit board to generate scalable vector graphics corresponding to each layer of the circuit board; wherein, the layers of the circuit board include solder mask layer, solder paste layer, copper layer and drilling layer. For example, to parse the standard format file into multiple scalable vector graphics, necessary software and libraries can be installed, then read and parse the Gerber file to obtain the required layers, then create an SVG file, traverse all elements in the selected Gerber layer, such as lines, arcs, etc., convert each Gerber element into an SVG element, and add it to the SVG file. For example, for a line element, it can be converted into an SVG <line>Elements, and set corresponding start and end coordinates, line colors, widths and other attributes. Finally, the line colors, widths and other attributes in the SVG file can be adjusted according to requirements, and annotations and labels can be added to the SVG file for subsequent processing and analysis.

[0030] In S300, a three-dimensional model of the circuit board is generated based on multiple scalable vector graphics.

[0031] In some embodiments, SVG can be converted into a three-dimensional model through a variety of tools and software, such as svg-mesh-3d, Blender (combined with Python scripts or other plugins), and online conversion services. After importing the scalable vector graphics, adjust the conversion parameters as needed, such as the resolution, smoothness, material, etc. of the three-dimensional model, start the conversion process, and wait for the tool to complete the conversion of SVG to a three-dimensional model.

[0032] In other embodiments, a three-dimensional model can also be directly generated through the standard format file (Gerber file) in S100. Given the corresponding relationship between the known Gerber file and SVG, generating a three-dimensional model through the Gerber file can also establish the corresponding relationship between SVG and the three-dimensional model. For example, using PCB design software that supports three-dimensional model generation, such as Altium Designer, Eagle, KiCad, etc., these software usually provide the function of importing PCB layouts from Gerber files and allow generating three-dimensional views or models.

[0033] In S400, the element graphic coordinates are extracted from the scalable vector graphics, and a two-dimensional picture is correspondingly generated; among them, the two-dimensional picture includes key pixel points corresponding to the element graphic coordinates. All graphic information is extracted in SVG, that is, the svg vector diagram is drawn on a picture with a preset size. Which specific graphics and coordinate data are used will be calculated and analyzed on the two-dimensional picture. In addition, since the picture is not losslessly scaled, in order to ensure that incorrect results will not be caused by the scaling loss of the picture in subsequent PCB inspections, the real size of the PCB described in the Gerber file can be combined with the minimum precision of the factory production process (usually 1 mil) to generate the preset size of the picture, ensuring that the real size corresponding to each pixel point in the picture is less than the minimum precision of the factory production process. To convert the scalable vector graphics into a two-dimensional picture, general tools can be used. For example, most graphic editing software, such as Adobe Illustrator, Inkscape, GIMP, etc., supports importing SVG files and exporting them to other picture formats. The two-dimensional picture can be a JPG format picture. To improve the calculation efficiency, it can also be converted into a png grayscale picture, and finally extracted as a two-dimensional matrix for calculation and use.

[0034] Figure 2 It is a schematic flowchart of a three - dimensional circuit board testing method provided by another exemplary embodiment of the present application. Taking Figure 2 as an example, one implementation of S400 may be: converting a scalable vector graphic into a two - dimensional picture (see S410 in Figure 2 ); extracting the coordinate of the element graphic in the scalable vector graphic (see S420 in Figure 2 ); mapping the coordinate of the element graphic to the pixel points of the two - dimensional picture to generate key pixel points (see S430 in Figure 2 ). Among them, each coordinate of the element graphic corresponds to a pixel point. Extracting the coordinate of the element graphic in the SVG file and mapping it to the PNG picture, each coordinate of the element graphic is a pixel point. Among them, the key pixel points include the pixel points corresponding to the trace coordinates of the copper layer, the opening coordinates of the solder mask layer, the hole coordinates of the drilling layer, and the pad coordinates of the solder paste layer. Therefore, the key coordinate points can be the coordinates of the copper layer - trace, the solder mask layer - opening coordinate, the drilling layer - hole coordinate, and the solder paste layer - pad coordinate. Because the SVG file has a clear coordinate and drawing structure, the coordinate of the element graphic in the SVG file can be extracted first, and then according to the SVG coordinate, it can be mapped to the png pixel, and each coordinate of the element graphic is a pixel point.

[0035] Taking Figure 2 as an example, after generating the key pixel points, in some embodiments, the three - dimensional circuit board testing method may further include: checking the coincidence of the key pixel points between preset targets in the two - dimensional picture based on the key pixel points of the two - dimensional picture (see S600 in Figure 2 ); where the preset targets include the elements corresponding to the element graphic coordinates; generating a test result according to the coincidence of the key pixel points between the preset targets (see S700 in Figure 2 ). In a two - dimensional space, ranging usually involves two parameters (such as x and y coordinates). In a three - dimensional scene, calculating whether two objects cross or collide requires a complex calculation process. However, in a two - dimensional picture (such as a grayscale picture), it only needs to judge whether there is a value for the pixel points within the range to perform a collision check. For example, in a grayscale picture, a pixel value of 0 represents empty, and a non - zero value represents an object. If it is necessary to judge whether a drill hole coincides with a copper wire, find the pixel position of the drill hole in the "drill hole picture", and then judge whether there is a pixel value at the same position in the "copper wire picture" to determine whether the drill hole coincides with the copper wire. Judging whether there is a coincidence in a two - dimensional picture is more efficient and faster, thereby reducing the amount of calculation, improving the calculation speed, and enhancing the detection efficiency of the circuit board model.

[0036] As a possible implementation, the hole coordinates of the drilling layer (such as pad holes, vias, etc.) should generally not exactly coincide with the coordinates of the copper layer traces or the solder mask openings, especially at the edges of the holes. This is to ensure that the drilling process does not damage the traces or the opening areas. The solder mask openings usually correspond to the pad coordinates on the copper layer to ensure that components can be correctly soldered. The hole coordinates of the drilling layer (especially pad holes) need to correspond to the pad coordinates on the solder assist layer. To ensure that components can be correctly soldered onto the PCB and the solder can flow smoothly between the pads and component pins to form a reliable electrical connection, the trace coordinates on the copper layer need to correspond to the coordinates of the component pins or pads to ensure that the current can be correctly transmitted and meet the circuit design requirements. It can be understood that the above rules are not absolute and specifically depend on the specific requirements and specifications of the PCB design. In some special cases, it may be necessary to adjust the relationship between the coordinates to meet specific design requirements.

[0037] Taking Figure 2 as an example, after obtaining the test results, the three-dimensional circuit board test method may further include: feeding back the test results to the three-dimensional model test interface to display and use the test results (see Figure 2 S800 therein); where the test results include at least one of normal, warning, or error. For example, if the hole coordinates of the drilling layer exactly coincide with the coordinates of the copper layer traces or the solder mask openings, a warning result or an error result is generated to provide a reference for user review, helping to achieve a more reliable and efficient board-making review and reducing the probability of production failure.

[0038] In 500, based on the mapping relationship between the two-dimensional picture and the scalable vector graphic, and the mapping relationship between the scalable vector graphic and the three-dimensional model, the key pixel points of the two-dimensional picture are mapped onto the three-dimensional model.

[0039] For example, based on the first calculation formula, multiple scalable vector graphics are converted into a three-dimensional model of the circuit board, and based on the second calculation formula, the scalable vector graphic is converted into a two-dimensional picture. Therefore, a possible implementation of S500 is to determine the first mapping relationship between the two-dimensional picture and the scalable vector graphic based on the first calculation formula; determine the second mapping relationship between the scalable vector graphic and the three-dimensional model based on the second calculation formula; obtain the third mapping relationship between the two-dimensional picture and the three-dimensional model based on the first mapping relationship and the second mapping relationship; and map the key pixel points of the two-dimensional picture onto the three-dimensional model based on the third mapping relationship.

[0040] That is to say, when the scalable vector graphics is SVG and the two-dimensional picture is a PNG picture, according to the relationship between SVG and the three-dimensional model and the relationship between SVG and PNG, the corresponding relationship between the three-dimensional model and PNG is deduced, and then the calculation result on the PNG is mapped onto the three-dimensional model. For example, the coordinates of SVG are (x, y), the pixel points of the grayscale PNG are (x, y), and the coordinates of the three-dimensional model are (x, y, z). There is a formula to correspond SVG to the three-dimensional model, and there is also a formula for SVG to PNG. Based on these two formulas, the mapping formula from PNG to the three-dimensional model can be deduced. Finally, the test results are fed back to the three-dimensional model test interface. The entire process is not calculated in the three-dimensional interface, reducing the amount of computation, thereby achieving the improvement of the testing speed of the three-dimensional circuit board model.

[0041] Exemplary device

[0042] Figure 3 is a schematic structural diagram of a three-dimensional circuit board testing device provided by an exemplary embodiment of the present application, as Figure 3 shown, the three-dimensional circuit board testing device 3 includes: an acquisition module 31, configured to acquire a standard format file of the circuit board; the standard format file is used to describe the manufacturing parameters of the circuit board; a first generation module 32, configured to generate multiple scalable vector graphics based on the standard format file of the circuit board; wherein each scalable vector graphic corresponds to a different working layer of the circuit board; a second generation module 33, configured to generate a three-dimensional model of the circuit board based on the multiple scalable vector graphics; a third generation module 34, configured to extract the element graphic coordinates from the scalable vector graphics and correspondingly generate two-dimensional pictures; wherein the two-dimensional pictures include key pixel points corresponding to the element graphic coordinates; a mapping module 35, configured to map the key pixel points of the two-dimensional pictures onto the three-dimensional model based on the mapping relationship between the two-dimensional pictures and the scalable vector graphics and the mapping relationship between the scalable vector graphics and the three-dimensional model.

[0043] The three-dimensional circuit board testing device provided by the present application can generate a three-dimensional model and scalable vector graphics according to the standard format file of the circuit board, generate two-dimensional pictures through the scalable vector graphics, and establish the coordinate correspondence relationship between the three-dimensional model, the scalable vector graphics, and the two-dimensional pictures. Based on this, the complex calculations originally in the three-dimensional scene are placed in the two-dimensional pictures for calculation, such as collision detection, etc., thereby reducing the amount of computation, improving the calculation speed, and enhancing the detection efficiency of the circuit board model.

[0044] As a possible implementation manner, the first generation module 32 can be configured to: parse the standard format file of the circuit board and generate scalable vector graphics corresponding to each layer of the circuit board; wherein the layers of the circuit board include a solder mask layer, a solder paste layer, a copper layer, and a drilling layer.

[0045] As a possible implementation, the third generation module 34 can be configured to: convert a scalable vector graphic into a two-dimensional picture; extract the coordinate of the element graphic in the scalable vector graphic; map the coordinate of the element graphic to the pixel points of the two-dimensional picture to generate key pixel points; where each coordinate of the element graphic corresponds to one pixel point.

[0046] As a possible implementation, the three-dimensional circuit board testing device 3 can be configured to: check the coincidence of the key pixel points between preset targets in the two-dimensional picture based on the key pixel points of the two-dimensional picture; where the preset targets include the elements corresponding to the coordinates of the element graphics; generate a test result according to the coincidence of the key pixel points between the preset targets.

[0047] As a possible implementation, the three-dimensional circuit board testing device 3 can be configured to: feedback the test result to the three-dimensional model testing interface for displaying and using the test result; where the test result includes at least one of normal, warning or error.

[0048] As a possible implementation, the three-dimensional circuit board testing device 3 can be configured to: the key pixel points include the pixel points corresponding to the trace coordinates of the copper layer, the pixel points corresponding to the opening coordinates of the solder mask layer, the pixel points corresponding to the hole coordinates of the drilling layer, and the pixel points corresponding to the pad coordinates of the solder paste layer.

[0049] As a possible implementation, the second generation module 33 can be configured to: convert multiple scalable vector graphics into a three-dimensional model of the circuit board based on a first calculation formula; the third generation module 34 can be configured to: convert the scalable vector graphic into a two-dimensional picture based on a second calculation formula.

[0050] As a possible implementation, the mapping module 35 can be configured to: determine a first mapping relationship between the two-dimensional picture and the scalable vector graphic based on a first calculation formula; determine a second mapping relationship between the scalable vector graphic and the three-dimensional model based on a second calculation formula; obtain a third mapping relationship between the two-dimensional picture and the three-dimensional model based on the first mapping relationship and the second mapping relationship; map the key pixel points of the two-dimensional picture to the three-dimensional model based on the third mapping relationship.

[0051] Exemplary system

[0052] A 3D model test display module, which is used to display 3D models and test results; the 3D circuit board test device provided by the present application is communicatively connected to the 3D model test display module. After mapping the key pixel points of the 2D image onto the 3D model through the 3D circuit board test device, the calculation results can be displayed and used through the 3D model test display module, so that users can intuitively view the calculation results, improve the accuracy and efficiency of design, and optimize the production and assembly processes.

[0053] Exemplary electronic device

[0054] An electronic device, which includes: a processor; a memory for storing processor-executable instructions; the processor is used to execute the 3D circuit board test method described in the embodiments provided by the present application.

[0055] Next, refer to Figure 4 to describe the electronic device according to the embodiments of the present application. The electronic device can be any one or both of the first device and the second device, or a stand-alone device independent of them. The stand-alone device can communicate with the first device and the second device to receive the input signals collected from them.

[0056] Figure 4 The block diagram of the electronic device according to the embodiments of the present application is illustrated.

[0057] As Figure 4 shown, the electronic device 10 includes one or more processors 11 and a memory 12.

[0058] The processor 11 can be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and can control other components in the electronic device 10 to perform desired functions.

[0059] The memory 12 can include one or more computer program products, and the computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory can include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions can be stored on the computer-readable storage medium, and the processor 11 can run the program instructions to implement the 3D circuit board test methods of the various embodiments of the present application described above and / or other desired functions. Various contents such as input signals, signal components, and noise components can also be stored in the computer-readable storage medium.

[0060] In one example, the electronic device 10 may further include: an input device 13 and an output device 14, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0061] When the electronic device is a stand-alone device, the input device 13 may be a communication network connector for receiving the collected input signals from a first device and a second device.

[0062] In addition, the input device 13 may further include, for example, a keyboard, a mouse, and so on.

[0063] The output device 14 may output various information to the outside, including the determined distance information, direction information, and so on. The output device 14 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, and so on.

[0064] Of course, for simplicity, Figure 4 only some of the components related to the present application in the electronic device 10 are shown, and components such as a bus, an input / output interface, and so on are omitted. In addition, according to specific application scenarios, the electronic device 10 may further include any other appropriate components.

[0065] The computer program product may be written in any combination of one or more programming languages for executing the program code of the operations of the embodiments of the present application. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0066] A computer-readable storage medium stores a computer program, and the computer program is used to execute the three-dimensional circuit board testing method described in the embodiments provided by the present application.

[0067] The computer-readable storage medium may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0068] The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.< / line>

Claims

1. A three-dimensional circuit board testing method, characterized in that, Including: Obtain the standard format file of the circuit board; The standard format file is used to describe the manufacturing parameters of the circuit board; Based on the standard format file of the circuit board, generate multiple scalable vector graphics; wherein, each scalable vector graphic corresponds to a different working layer of the circuit board; Based on the multiple scalable vector graphics, generate a 3D model of the circuit board; Extract the element graphic coordinates from the scalable vector graphics and correspondingly generate a 2D picture; wherein, the 2D picture includes key pixel points corresponding to the element graphic coordinates; Based on the mapping relationship between the 2D picture and the scalable vector graphics, and the mapping relationship between the scalable vector graphics and the 3D model, map the key pixel points of the 2D picture onto the 3D model.

2. The three-dimensional circuit board testing method according to claim 1, wherein Based on the standard format file of the circuit board, generate multiple scalable vector graphics, including: Parse the standard format file of the circuit board to generate scalable vector graphics corresponding to each layer of the circuit board; wherein, the layers of the circuit board include the solder mask layer, the solder paste layer, the copper layer, and the drilling layer.

3. The three-dimensional circuit board testing method according to claim 1, wherein, Extract the element graphic coordinates from the scalable vector graphics and correspondingly generate a 2D picture, including: Convert the scalable vector graphics into a 2D picture; Extract the element graphic coordinates in the scalable vector graphics; Correspond the element graphic coordinates to the pixel points of the 2D picture to generate key pixel points; wherein, each element graphic coordinate corresponds to one pixel point.

4. The three-dimensional circuit board testing method according to claim 3, characterized in that, After corresponding the element graphic coordinates to the pixel points of the 2D picture to generate key pixel points, the 3D circuit board testing method further includes: Based on the key pixel points of the 2D picture, check the coincidence of the key pixel points between preset targets in the 2D picture; wherein, the preset targets include the elements corresponding to the element graphic coordinates; Generate a test result according to the coincidence of the key pixel points between the preset targets.

5. The three-dimensional circuit board testing method according to claim 4, wherein, After generating a test result according to the distance between the preset targets, the 3D circuit board testing method includes: Feed back the test result to the 3D model testing interface for displaying and using the test result; wherein, the test result includes at least one of normal, warning, or error results.

6. The three-dimensional circuit board testing method according to claim 1, wherein The key pixel points include pixel points corresponding to the trace coordinates of the copper layer, pixel points corresponding to the opening coordinates of the solder mask layer, pixel points corresponding to the hole coordinates of the drilling layer, and pixel points corresponding to the pad coordinates of the solder paste layer.

7. The three-dimensional circuit board testing method according to claim 1, characterized in that Based on the multiple scalable vector graphics, generate a 3D model of the circuit board, including: Based on the first calculation formula, convert the multiple scalable vector graphics into a 3D model of the circuit board; Extract the element graphic coordinates from the scalable vector graphics and correspondingly generate a 2D picture, including: Based on the second calculation formula, convert the scalable vector graphics into a 2D picture.

8. The three-dimensional circuit board testing method according to claim 7, wherein Based on the mapping relationship between the 2D picture and the scalable vector graphics, and the mapping relationship between the scalable vector graphics and the 3D model, map the key pixel points of the 2D picture onto the 3D model, including: Based on the first calculation formula, determine the first mapping relationship between the 2D picture and the scalable vector graphics; Determine the second mapping relationship between the scalable vector graphic and the 3D model based on the second calculation formula; Obtain the third mapping relationship between the 2D picture and the 3D model based on the first mapping relationship and the second mapping relationship; Map the key pixel points of the 2D picture to the 3D model based on the third mapping relationship.

9. A three-dimensional circuit board testing device, characterized in that, Comprising: An acquisition module for acquiring a standard format file of a circuit board; The standard format file is used to describe the manufacturing parameters of the circuit board; A first generation module for generating multiple scalable vector graphics based on the standard format file of the circuit board; wherein, each scalable vector graphic corresponds to a different working layer of the circuit board; A second generation module for generating a 3D model of the circuit board based on the multiple scalable vector graphics; A third generation module for extracting the element graphic coordinates from the scalable vector graphics and correspondingly generating a 2D picture; wherein, the 2D picture includes key pixel points corresponding to the element graphic coordinates; A mapping module for mapping the key pixel points of the 2D picture to the 3D model based on the mapping relationship between the 2D picture and the scalable vector graphic and the mapping relationship between the scalable vector graphic and the 3D model.

10. A three-dimensional circuit board testing system, characterized in that, Comprising: A 3D model test display module for displaying the 3D model and the test results; The 3D circuit board test device as described in claim 9 above, the 3D circuit board test device is communicatively connected to the 3D model test display module.

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