A ferroelectric memory circuit and a method for flexibly controlling the voltage across a ferroelectric capacitor

Abstract

The present invention discloses a ferroelectric memory circuit and a method for flexibly controlling the voltage across a ferroelectric capacitor. The circuit comprises a plurality of plate lines, word lines and bit lines, and a self-boosting control circuit connected to the plate lines. The self-boosting control circuit is used to charge at least one unselected plate line to a high level during a write "1" operation, thereby utilizing at least one selected word line to open a conductive channel but utilizing the parasitic capacitance of an NMOS transistor of an unselected plate line to raise the voltage of the selected word line to a level greater than or equal to V wL +V t , so that the bit line voltage V BL This solution charges the unselected plate lines to a high level and uses the voltage coupling of the capacitor to raise the voltage of the selected word line, allowing the bit line voltage VBL to be fully transmitted to the capacitor plates of the corresponding memory cells, thereby resolving the potential problem of insufficient voltage for writing "1".

Description

Technical Field

[0001] The present invention belongs to the field of circuits, and in particular to a ferroelectric memory circuit and a method for flexibly controlling the voltage across a ferroelectric capacitor. Background Art

[0002] The storage unit of ferroelectric memory is composed of NMOS transistor and ferroelectric capacitor. One NMOS transistor corresponds to one ferroelectric capacitor, and the NMOS transistor acts as a single-transistor transmission gate. However, the signal transmission of a single-transistor transmission gate will have threshold loss. For example, when the gate of the NMOS single-transistor transmission gate is connected to the power supply VCC, the maximum signal voltage that can be transmitted between the source and drain can only reach VCC-V t , V t is the threshold voltage of the NMOS tube. In this case, the maximum voltage at the end of the ferroelectric capacitor connected to the NMOS tube can only reach VCC-V t When the voltage at the other end of the ferroelectric capacitor reaches VCC, the end connected to the NMOS tube will find it difficult to reach the coercive voltage, making it difficult to successfully write data.

[0003] Furthermore, in actual manufacturing processes, ferroelectric capacitors are not completely symmetrical, meaning that the polarization strengths generated by the ferroelectric material at +VCC and -VCC are different. When the memory cell is read and written a certain number of times, a positive or negative imprinting effect will appear. If the cell moves in the positive direction, the difficulty of positive polarization will increase, and vice versa, resulting in an asymmetric polarization strength between the positive and negative sides. Summary of the Invention

[0004] The purpose of the present invention is to address the above two phenomena, provide a ferroelectric memory circuit and a method for flexibly controlling the voltage across a ferroelectric capacitor, and flexibly design a storage unit-related voltage driving circuit, including a word line driving circuit, a plate line driving circuit, and a bit line voltage and a plate line voltage during a write operation.

[0005] A ferroelectric memory circuit includes a plurality of plate lines, word lines, and bit lines, and also includes a self-boosting control circuit connected to the plate lines. The self-boosting control circuit is used to charge at least one unselected plate line to a high level when performing a write "1" operation, so as to use at least one selected word line to open a conductive channel but the parasitic capacitance of the NMOS transistor of the corresponding unselected plate line to raise the voltage of the selected word line to greater than or equal to V wL +V t , the bit line voltage V used for writing “1” operation BL is completely transferred to the capacitor plate of the corresponding storage unit;

[0006] V wL Represents the high-level voltage provided by the high-level power supply to the word line; Vt Indicates the NMOS threshold voltage of the storage unit.

[0007] This solution takes advantage of the fact that the parasitic capacitance between the gate and drain of the NMOS transistor in the memory cell increases due to the opening of the conductive channel of the NMOS transistor. By charging the unselected plate line to a high level, the voltage of the selected word line is raised to a level greater than or equal to V by using the voltage coupling effect of the capacitor. wL +V t , so that the bit line voltage V BL The voltage is fully transmitted to the capacitor plate of the corresponding storage unit, thereby solving the problem of insufficient voltage for writing "1".

[0008] In the above-mentioned ferroelectric memory circuit, the self-boosting control circuit is used to charge multiple unselected plate lines to a high level when performing a write "1" operation, so as to use the parasitic capacitance of the NMOS transistors of the unselected plate lines of the multiple selected word lines to open the conductive channel based on the voltage coupling effect to raise the voltage of the selected word line to a level greater than or equal to V wL +V t , such as using the parasitic capacitance of three or more NMOS tubes to make the bit line voltage V BL is completely transferred to the capacitor plate of the corresponding storage unit.

[0009] In the above-mentioned ferroelectric memory circuit, the self-boosting control circuit includes a plurality of boosting control sub-circuits respectively and one by one connected to corresponding plate lines;

[0010] When writing "1",

[0011] The boost control subcircuit of the selected plate line outputs a write drive signal to the corresponding plate line based on the plate line selection signal, the write control signal and the word line boost signal;

[0012] The boost control subcircuit of the unselected plate lines outputs a plate line high-level signal to the corresponding plate line based on the plate line unselected signal, the write control signal and the word line boost signal, so as to raise the voltage of the selected word line by utilizing the parasitic capacitance of the NMOS tube of the unselected NMOS tube to open the conductive channel of the selected word line.

[0013] In the above ferroelectric memory circuit, the boost control subcircuit includes a logic gate circuit having inputs of a write control signal, a plate line selection signal, and a word line boost signal, and the output of the logic gate circuit is connected to the plate line;

[0014] The write control signal includes a write 1 control signal and a write 0 control signal;

[0015] The plate line selection signal includes a plate line selected signal and a plate line unselected signal. Specifically, the plate line selection signal of each boost control sub-circuit is input into the plate line selected signal or the plate line unselected signal according to the write requirement.

[0016] In the above-mentioned ferroelectric memory circuit, the logic gate circuit includes a first NOT gate, a second NOT gate, a third NOT gate, a first OR gate, a second OR gate, a first NAND gate and a second NAND gate;

[0017] The write 1 control signal, the write 0 control signal, and the plate line selection signal are connected to the first NOT gate, the second NOT gate, and the third NOT gate respectively;

[0018] The word line boost signal and the output of the third NOT gate are connected to the input of the first NAND gate;

[0019] The first NAND gate output and the first NOT gate / second NOT gate output are connected to the first OR gate input;

[0020] The third NOT gate output and the second NOT gate / first NOT gate output are connected to the second OR gate input;

[0021] The second OR gate output and the first OR gate output are connected to the second NAND gate input;

[0022] The output of the second NAND gate is connected to the plate line.

[0023] In the above ferroelectric memory circuit, each word line is connected to a word line driver circuit, which is used to output a high level voltage V to the corresponding word line using a high level power supply when receiving a working signal. wL , and when receiving the word line boost signal, it cuts off the path between the corresponding word line and the high level power supply and keeps the word line at a high level voltage V wL , so that the selected word line can be raised to a level greater than the high-level voltage V by the parasitic capacitance of the corresponding NMOS tube wL .

[0024] In the above-mentioned ferroelectric memory circuit, the word line driving circuit includes:

[0025] The PMOS transistor P0 and the NMOS transistor N0 form a first inverter. The gates of the two transistors are connected to the working signal SEL, and the drains are connected to output the first signal SELN. The source of the PMOS transistor P0 is connected to the high-level power supply VCC, and the source of the NMOS transistor N0 is connected to the low-level power supply VN.

[0026] The PMOS transistor P1 and the NMOS transistor N1 form a second inverter, the gates of the two transistors are connected to the first signal SELN, the drains are connected to output the second signal SELR, the source of the PMOS transistor P1 is connected to the high-level power supply VCC, and the source of the NMOS transistor N1 is connected to the low-level power supply VN;

[0027] The PMOS transistor P2 and the NMOS transistor N2 form a third inverter. The gates of the two transistors are connected to the word line boost signal WL_BOOST, and the drains are connected to output the third signal BOOSTN. The source of the PMOS transistor P2 is connected to the high-level power supply VCC, and the source of the NMOS transistor N2 is connected to the low-level power supply.

[0028] Also included are NMOS tube N3, NMOS tube N4 and NMOS tube N5;

[0029] The gate of the NMOS transistor N3 is connected to the high-level power supply VCC, the drain is connected to the third signal BOOSTN, and the source is connected to the gate of the NMOS transistor N4;

[0030] The drain of the NMOS transistor N4 is connected to the second signal SELR, and the source is connected to the corresponding word line WL and the drain of the NMOS transistor N5;

[0031] The gate of the NMOS transistor N5 is connected to the first signal, and the source is connected to the low-level power supply VN.

[0032] In the above ferroelectric memory circuit, each plate line is connected to a plate line driving circuit;

[0033] The plate line driving circuit is connected to a high level potential selection signal and a low level potential selection signal, and the boost control subcircuit is connected to the corresponding plate line through the plate line driving circuit;

[0034] a plate line driving circuit, configured to select a high level output or a low level output based on the output of the boost control subcircuit;

[0035] For selecting a high level output, outputting a high potential high level or a low potential high level based on a high level potential selection signal;

[0036] Used to output a high potential low level or a low potential low level based on the low level potential selection signal when selecting the low level output.

[0037] A method for flexibly controlling the voltage across a ferroelectric capacitor of a ferroelectric memory, the method comprising:

[0038] In response to a write "1" operation, the selected word line is set to a high level and the corresponding bit line is set to a high level;

[0039] The selected plate line is set to a low level and the unselected plate line is set to a high level, so that the voltage of the selected word line is raised to a level greater than or equal to V based on the voltage coupling effect by using the parasitic capacitance of the NMOS transistor of at least one selected word line to open the conductive channel but the corresponding plate line is not selected. wL +V t ;

[0040] V wLRepresents the high-level voltage provided by the high-level power supply to the word line; V t Indicates the NMOS threshold voltage of the storage unit;

[0041] Based on greater than or equal to V wL +V t The word line voltage, bit line voltage V BL is completely transferred to the capacitor plate of the corresponding storage unit.

[0042] In the above method for flexibly controlling the voltage across the ferroelectric capacitor of the ferroelectric memory,

[0043] The method further comprises:

[0044] In response to the write "1" operation, the path between the selected word line and the high-level power supply is cut off and the word line is kept at a high-level voltage V wL , so that the selected word line can be raised to a value greater than or equal to V by the parasitic capacitance of the corresponding MOS tube wL +V t ;

[0045] The method further comprises:

[0046] When a high level output of the plate line is required, a high potential high level is output to the corresponding plate line in response to a high level high potential selection signal, and a low potential high level is output to the corresponding plate line in response to a high level low potential selection signal;

[0047] When a low level output of the plate line is required, a high potential low level is output to the corresponding plate line in response to a low level high potential selection signal, and a low potential low level is output to the corresponding plate line in response to a low level low potential selection signal.

[0048] The advantages of the present invention are: this solution uses the parasitic capacitance of adjacent memory cells to raise the selected word line voltage through a configurable self-boosting control circuit and a WL drive circuit to compensate for the threshold voltage loss of the NMOS transistor, ensuring that the voltage transmitted by the bit line can be fully transmitted to the top plate of the ferroelectric capacitor, thereby overcoming the problem of insufficient polarization voltage caused by threshold loss;

[0049] This scheme flexibly adjusts the voltage difference across the ferroelectric capacitor by configuring registers to form a symmetrical or asymmetrical polarized electric field, and compensates for the imprinting effect of the ferroelectric material by purposefully enhancing the reverse electric field strength or the forward electric field strength. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 An array structure diagram of a ferroelectric memory circuit is provided for embodiment 1 of the present invention;

[0051] Figure 2 Provides an optional schematic diagram of a logic gate circuit of a boost control subcircuit in a ferroelectric memory circuit according to a first embodiment of the present invention;

[0052] Figure 3 Provides an optional circuit structure diagram of a WL driving circuit in a ferroelectric memory circuit for embodiment 1 of the present invention;

[0053] Figure 4 This is an optional circuit structure diagram of a PL driving circuit in a ferroelectric memory circuit provided in the second embodiment of the present invention;

[0054] Figure 5 This is a flow chart of a method for flexibly controlling the voltage across the ferroelectric capacitor of a ferroelectric memory circuit provided by the third embodiment of the present invention. DETAILED DESCRIPTION

[0055] Example 1

[0056] like Figure 1 As shown in Figure 1, if the memory cells contained in a plate line PL are divided into a memory array, there are m memory arrays in total. Since each memory array contains x word lines WL and n bit lines BL, the total storage capacity is (m*n*x) bits.

[0057] This embodiment takes "the polarization direction is reverse after writing 1 and the polarization direction is forward after writing 0" as an example, and the following description will use this as an example. When writing 1, the bit line BL voltage needs to output a high level, and when writing 0, the bit line BL voltage needs to output a low level.

[0058] A brief introduction to the write operation principle:

[0059] right Figure 1 When the ferroelectric capacitor FC00 is writing "0", the WL driving circuit is first used to charge WL0 from zero potential VSS to high potential VCC, turning on the NMOS tube M00. Then the PL driving circuit is used to charge the PL <0> After charging to the high level VCC, BL transmits the data "0", which is the zero potential VSS or negative voltage VN, to the upper plate of FC00 through M00.

[0060] At this time, the polarization direction of FC00 is positive. If you want to write "1", drive the PL <0> When discharged to low level VN, BL transmits data "1" (high level VCC) to the upper plate of F00 through M00, and the polarization direction of FC00 is reversed. At this time, the voltage actually transmitted to the upper plate will be less than or equal to VCC-V t , it may be difficult to reach the coercive voltage, resulting in difficulty in successfully writing data.

[0061] This solution makes a simple improvement to the ferroelectric memory circuit. By using a few control signals, symmetrical or asymmetrical electric field strengths can be applied to the forward and reverse polarizations of the ferroelectric capacitor, helping to solve the problem of insufficient voltage for writing "1". The details are as follows:

[0062] A self-boosting control circuit is designed for a ferroelectric memory circuit. The plate line PL is connected to the self-boosting control circuit. When writing a "1" operation, the corresponding NMOS transistor is selected to open the conductive channel. The self-boosting control circuit is used to charge at least one unselected plate line to a high level when writing a "1" operation. The voltage coupling effect of the parasitic capacitance voltage of the MOS transistor connected to the corresponding ferroelectric capacitor is used to raise the voltage of the selected word line to a level greater than or equal to V wL +V t , so that the bit line voltage V BL The bit line voltage V used for write operation is fully transferred to the capacitor plate of the corresponding memory cell. BL Usually it is the power supply VCC. wL Represents the high-level voltage VCC provided by the high-level power supply to the word line WL; V t Indicates the MOS tube threshold voltage of the storage unit.

[0063] The more MOS transistors involved in voltage boosting, the faster the boosting speed will be. Therefore, it is preferred that all NMOS transistors corresponding to the storage cells of the unselected PL in the selected WL participate in voltage boosting. Specifically, the self-boosting control circuit includes several boosting control sub-circuits that are respectively and one by one connected to the corresponding plate lines. Figure 1 and Figure 2 As shown, the boost control subcircuit includes a logic gate circuit whose inputs are a write control signal, a plate line select signal, and a word line boost signal. The output of the logic gate circuit is connected to the plate line PL driver circuit. The write control signal includes a write-one control signal WKICK and a write-zero control signal RKICK. In this embodiment, when the write-one control signal is present (i.e., WKICK = 1), the word line voltage is boosted. The plate line select signal PL0_SEL includes a plate line selected signal PL0_SEL = 1 and a plate line unselected signal PL0_SEL = 0.

[0064] When writing 1,

[0065] The boost control sub-circuit of the selected plate line outputs a write drive signal VN to the corresponding plate line based on the plate line selection signal PL0_SEL=1, the write 1 control signal WKICK=1, the write 0 control signal RKICK=0 and the word line boost signal WL_BOOST=1;

[0066] The boost control sub-circuits of all unselected plate lines output plate line high-level signals VCC to the corresponding plate lines based on the plate line unselected signal PL0_SEL=0, the write 1 control signal WKICK=1, the write 0 control signal RKICK=0, and the word line boost signal WL_BOOST=1, so as to raise the voltage of the selected word line by utilizing the parasitic capacitance of the MOS transistors whose channels are opened by the selected word line but whose corresponding plate lines are unselected.

[0067] like Figure 2 As shown, the logic gate circuit includes a first NOT gate I10, a second NOT gate I11, a third NOT gate I8, a first OR gate I12, a second OR gate I13, a first NAND gate I9 and a second NAND gate I14;

[0068] The write 1 control signal WKICK, the write 0 control signal RKICK, and the plate line selection signal PL0_SEL are connected to the first NOT gate I10, the second NOT gate I11, and the third NOT gate I8 respectively;

[0069] The input of the third NOT gate I8 is the plate line selection signal PL0_SEL, which is provided by the plate line decoding circuit through address decoding.

[0070] The word line boost signal WL_BOOST and the output of the third NOT gate I8 are connected to the input of the first NAND gate I9;

[0071] The output of the first NAND gate I9 and the output of the first NOT gate I10 are connected to the input of the first OR gate I12;

[0072] The output of the third NOT gate I8 and the output of the second NOT gate I11 are connected to the input of the second OR gate I13;

[0073] The output of the second OR gate I13 and the output of the first OR gate I12 are connected to the input of the second NAND gate I14;

[0074] The output of the second NAND gate I14 is connected to the plate line PL.

[0075] Through the above logic processing, when Write 1 is selected, the logic gate circuit will output a low level, and when Write 1 is not selected, the logic gate circuit will output a high level.

[0076] like Figure 1 As shown, when RKICK and PL0_SEL are pulled from "0" to "1", they pass through inverters I11 and I8 to the input of OR gate I13, I13 outputs "0", and then passes through NAND gate I14, outputs "1" to PL <0> The input of the driving circuit makes PL <0> Charged to high level "1".

[0077] When WKICK and PL0_SEL are pulled from "0" to "1", WKICK outputs a low level "0" to the input of OR gate I12 through inverter I10, and PL0_SEL outputs a low level "0" to the input of NAND gate I9 through inverter I8. I9 outputs a high level "1" to the input of OR gate I12, then I12 outputs "1". Since RKICK is "0" when writing "1", it outputs "1" to the input of I14 through I11 and I13, so I14 outputs "0" to connect to PL <0> The input of the driving circuit makes PL <0> Discharge to low level "0".

[0078] The signals mentioned in this solution, such as the write control signals WKICK and RKICK, the word line boost signal WL_BOOST, the bit line, word line, plate line selection signals and other signals not generated by this storage circuit are controlled and generated by the ferroelectric memory controller, and the details are not repeated here.

[0079] Furthermore, each word line is connected to a WL driving circuit for outputting a high level voltage V to the corresponding word line using a high level power supply VCC when receiving a working signal SEL. wL , high level voltage V wL Usually directly VCC. And when receiving the word line boost signal WL_BOOST=1, it cuts off the path between the corresponding word line and the high level power supply and keeps the word line at a high level voltage V wL So that the selected word line can be raised to a level greater than the high-level voltage V by the parasitic capacitance of the corresponding MOS tube wL .

[0080] Specifically, the WL driving circuit is as follows Figure 3 As shown, its input is connected to the row decoding circuit, which selects the word line to start operation through address decoding. The operating signal SEL of the selected word line (WL) driver circuit jumps from low level VN (or VSS) to high level VCC, turning on NMOS transistor N0. At this time, the first signal SELN jumps from high level VCC to low level VN (or VSS), and PMOS transistor P1 turns on, causing the second signal SELR to jump from low level VN to high level VCC. When WL_BOOST is low, PMOS transistor P2 turns on, and the third signal BOOSTN jumps from VN to VCC. Since the gate of NMOS transistor N3 is connected to VCC, it is normally open. The initial voltage of the third signal BOOSTN transmitted to BOOST through N3 is VCC-Vt. Therefore, the channel of NMOS transistor N4 is open, and the parasitic capacitance CGS of N4 is maximum. When the second signal SELR jumps from VN to VCC, the voltage of BOOST increases to 2VCC-Vt due to the action of CGS. t , so the voltage of WL will jump from VN to VCC.

[0081] WL self-boosting circuit control: When writing "1" to the storage unit, the NMOS tube in the storage unit is used to generate a channel (the gate voltage is greater than V t ) That is, when WL is selected, the parasitic capacitance is large. By pulling the unselected plate line PL from a low level to a high level, the WL voltage is boosted from VCC to a voltage greater than (VCC+V t The specific process is as follows:

[0082] When WL_BOOST jumps from "0" to "1", the NMOS tube N2 in the WL drive circuit is turned on, causing BOOSTN to discharge from VCC to VN. Since N3 is in the normally open state, the voltage of BOOST will also discharge to VN, turning off N4, and the WL voltage remains at VCC.

[0083] When PL0_SEL is selected and changes from "0" to "1", the other unselected PL1_SEL, PL2_SEL, ..., PL(m-1)_SEL are all "0", so when WL_BOOST changes from "0" to "1", except for PL <0> , other unselected PL <1> , PL <2> ,…,PL <m-1>All are charged from "0" to "1", and the WL voltage is increased from VCC to greater than VCC+V through the parasitic capacitance of m NMOS tubes. t .

[0084] Therefore, if WL_BOOST is "0", the selected WL voltage is VCC. When writing "1", the voltage when BL transmits VCC through the N-tube to the upper plate of the ferroelectric capacitor is VCC-V t .

[0085] If WL_BOOST is "1", the selected WL voltage will be greater than VCC+V because the above circuit improvements cause the parasitic capacitance to increase the WL voltage. t , the voltage when BL transmits VCC through the N tube to the upper plate of the ferroelectric capacitor is VCC.

[0086] Thus, the voltage of the selected word line is raised by utilizing the parasitic capacitance of the adjacent unselected memory cells, thereby making the bit line voltage V BL is completely transferred to the capacitor plate of the corresponding storage unit.

[0087] Example 2

[0088] This embodiment is similar to the first embodiment, except that the plate line PL driving circuit of this embodiment is connected to the high-level potential selection signal OPTVCC and the low-level potential selection signal OPTVSS, and the boost control subcircuit is connected to the corresponding plate line through the respective plate line driving circuits.

[0089] The plate line driver circuit is used to select a high-level output or a low-level output based on the output of the boost control subcircuit. Specifically, the high-level output or low-level output is determined based on the write control signal and the plate line select signal. When selecting a high-level output, the plate line driver circuit outputs a high-level VCCA or a low-level VCC based on the high-level potential select signal OPTVCC. When selecting a low-level output, the plate line driver circuit outputs a high-level VSS or a low-level VN based on the low-level potential select signal OPTVSS.

[0090] PL drive circuit such as Figure 4 As shown, its input is connected to the plate line decoding circuit through the boost control sub-circuit. When there is no plate line boost signal, that is, when the plate line boost signal WL_BOOST is at the low level VSS, the address decoding is used to select which plate line to start working.

[0091] When writing a "0," the input signal IN of the selected PL driver circuit jumps from a low level, VN, to a high level, VCC. Inverters I0 and I1 cause INR to also jump from a low level, VN, to a high level, VCC. NMOS transistors N9 and N10 turn on, pulling the voltages of the NDRVN and NDRVSS signals to VN, turning off NMOS transistors N6 and N15.

[0092] If OPTVSS and OPTVCC are at low level VN, the two transmission gates composed of N17 and P9, P6 and N12 are opened, and NDRVN discharges the gate of PMOS tube P12 to VN through these two transmission gates. P12 is opened to charge PL to VCCA.

[0093] If OPTVCC is at a high level VCCA, the transmission gate formed by N13 and P7 opens, and NDRVN discharges the gate of PMOS tube P5 to VN through the transmission gate. P5 opens, charging PL to VCC.

[0094] When writing "1", the input signal IN jumps from the high level VCCA to the low level VN, and after passing through the two inverters I0 and I1, the INR also jumps from the high level VCCA to the low level VN. At this time, the two PMOS tubes P10 and P13 are turned on.

[0095] If OPTVCC and OPTVSS are both at low level VN, VCCA charges NDRVN to high level VCCA through the two transmission gates composed of N17 and P9, P6 and N12, turns on NMOS tube N6, and PL discharges to low level VN through N6.

[0096] If OPTVSS is a high-level VCCA, the transmission gate composed of N14 and P8 is opened, and the high-level VCCA passes through N17 and P9. The two transmission gates composed of N14 and P8 charge NDRVSS to the high-level VCCA, turn on the NMOS tube N15, and PL discharges to the low-level VSS through N15.

[0097] In this way, according to the individual differences caused by the material, process, size, etc. of the storage unit, OPTVCC and OPTVSS are configured to be high or low through the register, and the high level is selected as high voltage or low voltage, and the low level is selected as high voltage or low voltage, thereby weakening the imprinting effect of the ferroelectric capacitor.

[0098] In addition to selecting PL as a specific high-level voltage or a specific low-level voltage based on the OPTVCC and OPTVSS signals, the remaining high-level VCC and VCCA are replaceable, and the low-level VSS and VN are replaceable.

[0099] Example 3

[0100] like Figure 5 As shown, this embodiment uses the ferroelectric memory circuit provided in the first embodiment to implement a method for flexibly controlling the voltage across the ferroelectric capacitor of the ferroelectric memory, specifically including:

[0101] In response to a write "1" operation requiring the corresponding bit line to output a high level, the selected word line is set to 1 and the corresponding bit line is set to 1;

[0102] The conductive channel of the NMOS transistor corresponding to the selected word line is opened, thereby increasing the corresponding parasitic capacitance.

[0103] The selected plate line is set to 0 and at least one unselected plate line is set to 1, so that the voltage of the selected word line is raised to a value greater than or equal to V based on the voltage coupling effect by using the parasitic capacitance of the MOS transistor of the unselected MOS transistor to open the conductive channel of at least one selected word line. wL +V t ;

[0104] V wL Represents the high-level voltage provided by the high-level power supply to the word line; V t Indicates the MOS tube threshold voltage of the storage unit;

[0105] Based on greater than or equal to V wL +V t The word line voltage, bit line voltage V BL is completely transferred to the capacitor plate of the corresponding storage unit.

[0106] Setting it to 1 indicates providing a high-level signal VCC to the corresponding target, and setting it to 0 indicates providing a low-level signal VSS or VN to the corresponding target.

[0107] Furthermore, the method further includes, in response to the write "1" operation, shutting off the path between the selected word line and the high level power supply and keeping the word line at the high level voltage V wL So that the selected word line can be raised to a value greater than or equal to V by the parasitic capacitance of the corresponding MOS tube wL +V t .

[0108] Example 4

[0109] This embodiment is similar to the third embodiment, except that the method of this embodiment corresponds to the circuit provided in the second embodiment, and further includes:

[0110] When a high level output of the plate line is required, a high potential high level is output to the corresponding plate line in response to a high level high potential selection signal, and a low potential high level is output to the corresponding plate line in response to a high level low potential selection signal;

[0111] When a low level output of the plate line is required, a high potential low level is output to the corresponding plate line in response to a low level high potential selection signal, and a low potential low level is output to the corresponding plate line in response to a low level low potential selection signal.

[0112] As described above, the structure and method proposed in this scheme utilize logic circuit control and the parasitic capacitance of the MOS tube to flexibly adjust the voltage required for the ferroelectric capacitor to write "0" and "1", which can overcome the problem of insufficient polarization voltage caused by threshold loss. In addition, it can weaken the imprinting effect of the ferroelectric capacitor to a certain extent, effectively increase the service life of the ferroelectric memory and improve the yield of ferroelectric storage.

[0113] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Persons skilled in the art may make various modifications, additions, or substitutions to the described specific embodiments without departing from the spirit of the present invention or exceeding the scope of the appended claims.

Claims

1. A ferroelectric memory circuit comprising a plurality of plate lines, word lines and bit lines, characterized in that: The self-boosting control circuit is connected to the plate line, and the self-boosting control circuit is used to charge at least one unselected plate line to a high level when performing a write "1" operation, so as to use the parasitic capacitance of the NMOS transistor of the unselected NMOS transistor of the selected plate line to open the conductive channel of at least one selected word line based on voltage coupling to raise the voltage of the selected word line to a level greater than or equal to V wL +V t , the bit line voltage V used for writing "1" operation BL is completely transferred to the capacitor plate of the corresponding storage unit; V wL Represents the high-level voltage provided by the high-level power supply to the word line; V t Indicates the NMOS threshold voltage of the storage unit; The self-boosting control circuit includes a plurality of boosting control sub-circuits connected to corresponding plate lines one by one; When writing "1", The boost control subcircuit of the selected plate line outputs a write drive signal to the corresponding plate line based on the plate line selection signal, the write control signal and the word line boost signal; The boost control subcircuit of the unselected plate lines outputs a plate line high level signal to the corresponding plate line based on the plate line unselected signal, the write control signal and the word line boost signal, so as to raise the voltage of the selected word line by utilizing the parasitic capacitance of the NMOS transistor of the unselected plate line but opening the conductive channel of the selected word line; The boost control subcircuit includes a logic gate circuit having a write control signal, a plate line selection signal and a word line boost signal as inputs, and the output of the logic gate circuit is connected to the plate line; The write control signal includes a write 1 control signal and a write 0 control signal; The plate line selection signal includes the plate line selected signal and the plate line unselected signal; The logic gate circuit includes a first NOT gate, a second NOT gate, a third NOT gate, a first OR gate, a second OR gate, a first NAND gate and a second NAND gate; The write 1 control signal, the write 0 control signal, and the plate line selection signal are connected to the first NOT gate, the second NOT gate, and the third NOT gate respectively; The word line boost signal and the output of the third NOT gate are connected to the input of the first NAND gate; The first NAND gate output and the first NOT gate / second NOT gate output are connected to the first OR gate input; The third NOT gate output and the second NOT gate / first NOT gate output are connected to the second OR gate input; The second OR gate output and the first OR gate output are connected to the second NAND gate input; The output of the second NAND gate is connected to the plate line.

2. The ferroelectric memory circuit according to claim 1, wherein: The self-boosting control circuit is used to charge multiple unselected plate lines to a high level when performing a write "1" operation, so as to use the parasitic capacitance of the NMOS transistors of the unselected plate lines of the selected word lines to open the conductive channel based on the voltage coupling effect to raise the voltage of the selected word line to a level greater than or equal to V wL +V t , the bit line voltage V used for writing "1" operation BL is completely transferred to the capacitor plate of the corresponding storage unit.

3. The ferroelectric memory circuit according to claim 1, wherein: Each word line is connected to a word line driver circuit, which is used to output a high level voltage V to the corresponding word line using a high level power supply when receiving a working signal. wL , and when receiving the word line boost signal, it cuts off the path between the corresponding word line and the high level power supply and keeps the word line at a high level voltage V wL , so that the selected word line can be raised to a level greater than the high-level voltage V by the parasitic capacitance of the corresponding NMOS tube wL .

4. The ferroelectric memory circuit according to claim 3, wherein: The word line driving circuit includes: The PMOS transistor P0 and the NMOS transistor N0 form a first inverter. The gates of the two transistors are connected to the working signal, and the drains are connected to output the first signal. The source of the PMOS transistor P0 is connected to the high-level power supply, and the source of the NMOS transistor N0 is connected to the low-level power supply. The PMOS transistor P1 and the NMOS transistor N1 form a second inverter, the gates of the two transistors are connected to the first signal, the drains are connected to output the second signal, the source of the PMOS transistor P1 is connected to the high-level power supply, and the source of the NMOS transistor N1 is connected to the low-level power supply; The PMOS transistor P2 and the NMOS transistor N2 form a third inverter. The gates of the two transistors are connected to the word line boost signal, and the drains are connected to output the third signal. The source of the PMOS transistor P2 is connected to the high-level power supply, and the source of the NMOS transistor N2 is connected to the low-level power supply. Also included are NMOS tube N3, NMOS tube N4 and NMOS tube N5; The gate of the NMOS transistor N3 is connected to a high-level power supply, the drain is connected to the third signal, and the source is connected to the gate of the NMOS transistor N4; The drain of the NMOS transistor N4 is connected to the second signal, and the source is connected to the corresponding word line and the drain of the NMOS transistor N5; The gate of the NMOS transistor N5 is connected to the first signal, and the source is connected to the low-level power supply.

5. The ferroelectric memory circuit according to claim 1, wherein: Each plate line is connected to a plate line driving circuit; The plate line driving circuit is connected to a high level potential selection signal and a low level potential selection signal, and the boost control subcircuit is connected to the corresponding plate line through the plate line driving circuit; a plate line driving circuit, configured to select a high level output or a low level output based on the output of the boost control subcircuit; For selecting a high level output, outputting a high potential high level or a low potential high level based on a high level potential selection signal; Used to output a high potential low level or a low potential low level based on the low level potential selection signal when selecting the low level output.

6. A method for flexibly controlling the voltage across a ferroelectric capacitor of a ferroelectric memory based on the ferroelectric memory circuit according to any one of claims 1 to 5, characterized in that: The method includes: In response to a write "1" operation, the selected word line is set to a high level and the corresponding bit line is set to a high level; The conductive channel of the NMOS transistor corresponding to the selected word line is opened, increasing its corresponding parasitic capacitance; The selected plate line is set to a low level, and at least one unselected plate line is set to a high level, so as to raise the voltage of the selected word line to a level greater than or equal to V based on the voltage coupling effect by utilizing the parasitic capacitance of the NMOS transistor of the unselected NMOS transistor of the at least one selected word line to open the conductive channel. wL +V t ; V wL Represents the high-level voltage provided by the high-level power supply to the word line; V t Indicates the NMOS threshold voltage of the storage unit; Based on greater than or equal to V wL +V t The word line voltage, bit line voltage V BL is completely transferred to the capacitor plate of the corresponding storage unit.

7. The method for flexibly controlling the voltage across the ferroelectric capacitor of a ferroelectric memory according to claim 6, characterized in that: The method further comprises: In response to a write "1" operation, the path between the selected word line and the high-level power supply is cut off and the word line is kept at a high-level voltage V wL , so that the selected word line can be raised to a value greater than or equal to V by the parasitic capacitance of the corresponding NMOS tube wL +V t ; The method further comprises: When a high level output of the plate line is required, a high potential high level is output to the corresponding plate line in response to a high level high potential selection signal, and a low potential high level is output to the corresponding plate line in response to a high level low potential selection signal; When a low level output of the plate line is required, a high potential low level is output to the corresponding plate line in response to a low level high potential selection signal, and a low potential low level is output to the corresponding plate line in response to a low level low potential selection signal.

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