Storage control module, memory controller and three-dimensional stacked memory

Abstract

The present invention provides a storage control module, a memory controller, and a three-dimensional stacked memory, which can convert a configured test data vector in the storage control module into a first mapping relationship according to the column address to be tested, and then write the configured test data vector into a multi-bit bit line corresponding to the physical layer of the storage unit according to a second mapping relationship determined by the physical layout wiring inside the storage unit. In this way, the bits of the configured test data vector can be one-to-one correspondence with the bits of the physical layer bit line of the storage unit, thereby meeting some special testing requirements of the memory, such as meeting the need to test the physical layer bit lines of the memory.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a storage control module, a memory controller and a three-dimensional stacked memory. Background Art

[0002] Dynamic Random Access Memory (DRAM), with its advantages such as high density, simple architecture, low latency, and low power consumption, has been widely used as memory in various application systems, covering multiple fields such as high-performance computing and mobile applications. DRAM performance is closely related to system performance and stability, necessitating a series of DRAM tests.

[0003] Among them, due to the influence of the physical layout and wiring of the peripheral circuits (such as sense amplifiers) of the internal memory array of the DRAM, when testing the DRAM chip, the bits of the test data vector (test data pattern) input to the DRAM do not correspond one-to-one with the bits of the data vector stored on the corresponding bit line BL in the DRAM physical layer (or "with the actual position of the corresponding bit line BL in the memory array"), which will affect certain specific DRAM testing requirements, such as testing the bit lines BL of the DRAM physical layer with 0x55, 0xAA, 0x00, and 0xFF. Summary of the Invention

[0004] The purpose of the present invention is to provide a storage control module, a memory controller and a three-dimensional stacked memory, which can make the bits of the configured test data vector correspond one-to-one with the bits of the multi-bit bit lines in the memory physical layer, thereby meeting certain specific memory testing requirements.

[0005] To achieve the above objectives, the present invention provides a storage control module for testing the physical layer bit lines of a memory cell coupled thereto, wherein the memory cell includes a plurality of bit lines, each of which is addressed by a corresponding column address. The storage control module is configured to:

[0006] During testing, a multi-bit test data vector is configured, and the configured test data vector is first converted bit by bit according to a first mapping relationship based on the column address to be tested, and then written bit by bit to a multi-bit bit line corresponding to the physical layer of the storage unit according to a second mapping relationship determined by the physical layout and wiring of the storage unit;

[0007] The combination of the first mapping relationship and the second mapping relationship enables the bits of the configured test data vector to correspond one-to-one with the bits of the multiple bit lines.

[0008] Optionally, the second mapping relationship of the storage unit is determined by the physical layout wiring from the storage interface of the storage unit to the physical layer bit line.

[0009] Optionally, the second mapping relationship of the odd column address to be tested is determined by the physical layout wiring of the peripheral circuit between the storage interface and the odd column bit line of the storage cell; the second mapping relationship of the even column address to be tested is determined by the physical layout wiring of the peripheral circuit between the storage interface and the even column bit line of the storage cell; wherein, the peripheral circuit between the storage interface and the odd column bit line includes the odd column sensitive amplifier inside the storage cell; the peripheral circuit between the storage interface and the even column bit line includes the even column sensitive amplifier inside the storage cell.

[0010] Optionally, the test includes a stress test performed on the corresponding target bit line in the storage cell, and the storage control module is also used to read data from the multi-bit bit line consisting of the target bit line and its adjacent bit lines to check whether the read data has changed relative to the data of the test data vector, and then analyze whether there is interference between the target bit line and its adjacent bit lines.

[0011] Optionally, the stress test mode includes a write-read interference test mode. In the write-read interference test mode, the storage control module is further configured to: first initialize the target bit line and the adjacent bit lines of the target bit line to a known data vector, and then perform multiple write operations on the target bit line to write the target bit line and the adjacent bit lines to other data vectors different from the known data vector, and read the data of the target bit line and the adjacent bit line after each write operation to check whether the adjacent bit lines have data changes. If so, it indicates that there is interference between the target bit line and the adjacent bit line.

[0012] Optionally, the stress test mode includes a read-read interference test mode. In the read-read interference test mode, the storage control module is further configured to: first initialize the target bit line and the adjacent bit lines of the target bit line to known data vectors, and then perform multiple continuous read operations on the target bit line, and read the data of the target bit line and the adjacent bit lines after each continuous read operation to check whether the data of the adjacent bit lines has changed. If so, it means that there is interference between the target bit line and the adjacent bit lines.

[0013] Optionally, the stress test mode includes a write-write interference test mode. In the write-write interference test mode, the storage control module is further configured to: first initialize the target bit line and the adjacent bit lines of the target bit line to a known data vector, and then alternately perform write operations on the target bit line and the adjacent bit lines to write the target bit line and the adjacent bit lines to other data vectors different from the known data vector. Each time the target bit line and the adjacent bit line alternately perform a write operation, the data of the target bit line and the adjacent bit line are read to check whether the adjacent bit lines have data changes. If so, it indicates that there is interference between the target bit line and the adjacent bit line.

[0014] Optionally, the known data vector includes any one of 0x55, 0xAA, 0x00, and 0xFF.

[0015] Optionally, the storage unit includes a plurality of stacked storage array bodies, each of the storage array bodies has the plurality of bit lines, the storage control module is coupled to each of the storage array bodies, and the storage control module is further configured to: receive address information and test configuration content of a corresponding test instruction, and activate a chip select signal corresponding to the storage unit based on the address information and the test configuration content to select a corresponding storage array body in the storage unit for access, and then test the physical layer bit lines of the selected storage array body.

[0016] Optionally, the storage control module simultaneously manages a plurality of the storage units located in the same memory stack, the memory stack having a plurality of stacked memory bare cores, and each storage array body of each storage unit is a part of a corresponding memory bare core in the memory stack; the storage control module is also configured to select the same layer of storage array bodies of all the storage units it manages to access according to the address information and the test configuration content, and then perform synchronous testing on the physical layer bit lines of the same layer of storage array bodies of all the storage units it manages.

[0017] Optionally, the storage control module includes a test interface and test control logic, wherein the test interface is used to receive address information and test configuration content of a corresponding test instruction and output data read from the storage unit;

[0018] The test control logic is used to activate a chip select signal corresponding to the storage unit according to the address information and the test configuration content to select a corresponding storage array body in the storage unit for access, and the test control logic further includes:

[0019] a configuration register coupled to the test interface and configured to configure the corresponding multi-bit test data vector for the storage array body according to the corresponding address information and the test configuration content;

[0020] an inverse conversion module, coupled to the configuration register, and configured to convert the test data vector configured by the configuration register into a first mapping relationship bit by bit according to the column address to be tested of the memory array;

[0021] The data input and output port is coupled to the storage interface of the storage array body and is used to send the data vector converted by the inverse conversion module to the storage array body through the storage interface.

[0022] Based on the same inventive concept, the present invention further provides a memory controller for testing the physical layer bit lines of multiple memory cells of a corresponding memory stack, wherein the memory stack includes multiple layers of stacked memory die, and each memory array in each memory cell is a portion of the memory die in the corresponding layer. The memory controller includes a host device interface, a memory test control management module, and several memory control modules according to the present invention; wherein:

[0023] The main device interface is connected to the corresponding test host for communication and is used to receive the test instructions to be executed and their address information and test configuration content;

[0024] The memory test control management module is coupled to the master device interface and each of the memory control modules, and is configured to parse the address information and test configuration content of the test instructions received by the master device interface to generate corresponding address information, and determine the memory control module and memory unit targeted by each test instruction based on the address information, and then provide the address information and test configuration content to the targeted memory control module;

[0025] Each of the storage control modules is coupled to at least one of the storage cells in the memory stack, and is used to receive the address information and the test configuration content, and then implement a test of the physical layer bit line of the coupled storage cell according to the address information and the test configuration content.

[0026] Optionally, the memory test control management module includes a test manager, a register and an address decoder;

[0027] The test manager is coupled to the main device interface, the address decoder, the register and each of the storage control modules. The test manager is used to send the address information of the test instruction received by the main device interface to the address decoder for address resolution, so as to determine the storage control module hit by each of the test instructions to be executed, the hit storage unit and the target bit line in the hit storage unit and the adjacent bit line of the target bit line, and then transmit the test configuration content and the column address of the target bit line and the adjacent bit line resolved by the address decoder to the hit storage control module.

[0028] Optionally, the memory controller is arranged in the buffer bare core, and the multi-layer memory bare cores and the buffer bare cores are hybrid bonded through silicon vias; or, the memory controller is arranged in the logic bare core, and the multi-layer memory bare cores and the logic bare cores are hybrid bonded through silicon vias.

[0029] Based on the same inventive concept, the present invention further provides a three-dimensional stacked memory, which includes a memory stack and a coupled memory controller as described in the present invention.

[0030] Compared with the prior art, the technical solution of the present invention converts the configured test data vector into a first mapping relationship of a storage control module bit by bit according to the column address to be tested before writing the configured test data vector into the physical layer bit line of a storage unit (for example, a storage unit of a DRAM), and then writes the configured test data vector into a multi-bit bit line corresponding to the physical layer of the storage unit according to a second mapping relationship determined by the physical layout wiring inside the storage unit. Thus, by utilizing the secondary mapping of the first mapping relationship and the second mapping relationship, the bits of the configured test data vector are made to correspond one-to-one with the bits of the physical layer bit line of the storage unit, thereby facilitating certain specific testing requirements for the memory, such as testing the physical layer bit line BL of the memory with 0x55, 0xAA, 0x00, 0xFF, etc. as test data vectors (for example, performing stress testing), analyzing the degree of influence between adjacent bit lines, and thus determining the read and write performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0032] Figure 1 This is a schematic diagram of the system architecture under the existing test solution.

[0033] Figure 2 yes Figure 1The corresponding relationship between the bits of the test data vector and the bits of the bit lines of the even column addresses in the test scheme shown is shown.

[0034] Figure 3 yes Figure 1 The corresponding relationship between the bits of the test data vector and the bits of the bit lines of the odd column addresses in the test scheme shown is shown.

[0035] Figure 4 FIG. 4 is a schematic diagram of an exemplary architecture of a storage control module according to a specific embodiment of the present invention.

[0036] Figure 5 It is a schematic structural diagram of a storage array of a storage array body tested by a storage control module according to a specific embodiment of the present invention.

[0037] Figure 6 This is the correspondence between the test data vector configured in the storage control module of a specific embodiment of the present invention, the data vector outputted therefrom, and the bits of the data vector of the bit line of the even column address.

[0038] Figure 7 This is the correspondence between the test data vector configured in the storage control module of a specific embodiment of the present invention, the data vector outputted therefrom, and the bits of the data vector of the bit lines of the odd column addresses.

[0039] Figure 8 This is the correspondence between the test data vector configured in the storage control module of a specific embodiment of the present invention, the data vector outputted therefrom, and the bits of the data vector of the bit line of the even column address (k=7).

[0040] Figure 9 This is the correspondence between the test data vector configured in the storage control module of a specific embodiment of the present invention, the data vector outputted therefrom, and the bits of the data vector of the bit lines of the odd column addresses (k=7).

[0041] Figure 10 FIG. 2 is another exemplary architecture diagram of a storage control module according to a specific embodiment of the present invention.

[0042] Figure 11 4 is a schematic diagram of an exemplary architecture of a memory controller and a three-dimensional stacked memory according to a specific embodiment of the present invention.

[0043] Figure 12 It is a schematic diagram of a packaging structure of a memory controller and a three-dimensional stacked memory according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0044] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] The following combination Figures 1 to 3 Taking the example of a test data pattern input to the storage interface (also known as the "DRAM interface") of a DRAM memory unit DU (DRAM unit) and the data vector stored on the physical layer bit line BL of the memory unit DU, both of which are 8 bits, this paper explains in detail the problem that under existing test schemes, the test data pattern input to the DRAM is different from the data vector stored on the corresponding bit line BL in the actual DRAM internal physical layer (that is, the bits of the test data pattern do not match the bits of the bit line BL of the memory unit DU).

[0046] Please refer to Figures 1 to 3 The storage interface (also called "DRAM interface") 30 of the storage unit DU is coupled to the corresponding test control logic IP. The storage interface 30 includes a data interface DU_DIO. The test data vector configured by the test control logic IP is provided to the storage unit DU through the data interface DU_DIO, and then further written to the physical layer bit line of the storage unit DU through the peripheral circuit between the data interface DU_DIO and the physical layer bit line of the storage unit DU (for example, the sensitive amplifier SA corresponding to each column).

[0047] In order to save circuit area and other reasons, when designing DRAM, the physical layout wiring of the peripheral circuits (such as the sense amplifier SA corresponding to each column) between the data interface DU_DIO of the storage interface 30 of the memory unit DU and its physical layer bit line BL may have windings, such as Figure 2 and Figure 3 In the embodiment, the physical layout wiring of the sense amplifiers SA in the odd-numbered columns and the sense amplifiers SA in the even-numbered columns of the memory unit DU may use different wiring schemes. It is worth noting that the present invention is not limited to this and is also applicable to scenarios where the physical layout wiring of the sense amplifiers SA in the odd-numbered columns and the sense amplifiers SA in the even-numbered columns use the same wiring scheme.

[0048] When testing a DRAM chip, the data burst size or data bit width of the data interface DU_DIO is generally the test data vector MR[k:0] configured by the test control logic IP (not shown in the figure). Figure 1 You can refer to Figure 4 ). When the test data vector MR[k:0] configured by the test control logic IP is 8 bits, for example, when the data burst size of the data interface DU_DIO is 128 bits, 256 bits, or 272 bits, the test control logic IP uses the 8-bit test data vector MR[k:0] as a repetition unit, repeats it 16 times, 32 times, or 34 times, and then provides it to the data interface DU_DIO. Figure 2 and Figure 3 The figure shows that the configured test data vector MR[k:0] is 8 bits (i.e., k+1=8), the data interface DU_DIO repeats the test data vector for the n / 8th time, and the test data vector repeated for the n / 8th time by the data interface DU_DIO is written to the corresponding bit line BL of the memory unit DU.

[0049] When the column address DU_CADD to be written is an even column address (which may be referred to as an "even address" for short, and is used to address the even column bit lines in the memory unit DU), please refer to Figure 2, the bit DU_DIO[n+7] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+7], the bit DU_DIO[n+6] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+5], the bit DU_DIO[n+5] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+3], the bit DU_DIO[n+4] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+1], the bit DU_DIO[n+3] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+6], the bit DU_DIO[n+2] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+4], the bit DU_DIO[n+1] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+2], and the bit DU_DIO[n] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n]. That is to say, when the test control logic IPb inputs the test data vector 0x55 to the corresponding storage unit DU of the DRAM according to the data interface DU_DIO[n+7:n], under the existing test scheme, since the bits of DU_DIO[n+7:n] do not correspond one-to-one with the bits of the bit line BL[n+7:n] of the even column address of the storage unit DU, even if the reading and writing of the storage unit DU are correct, the data IO[n+7:n] or ION[n+7:n] read from the BL[n+7:n] will also be 0x33, that is, the configured test data vector is different from the data read from the physical layer bit line of the storage unit.

[0050] Please refer to Figure 3, when the column address DU_CADD is an odd column address (which may be referred to as "odd address" for short, and is used to address odd column bit lines in the memory unit DU), the bit DU_DIO[n+7] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+3], the bit DU_DIO[n+6] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+1], the bit DU_DIO[n+5] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+7], and the bit DU_DIO[n+6] in the data interface DU_DIO corresponds to the DRAM physical layer bit line BL[n+1]. DIO[n+4] corresponds to DRAM physical layer bit line BL[n+5], bit DU_DIO[n+3] in the data interface DU_DIO corresponds to DRAM physical layer bit line BL[n+2], bit DU_DIO[n+2] in the data interface DU_DIO corresponds to DRAM physical layer bit line BL[n], bit DU_DIO[n+1] in the data interface DU_DIO corresponds to DRAM physical layer bit line BL[n+6], and bit DU_DIO[n] in the data interface DU_DIO corresponds to DRAM physical layer bit line BL[n+4]. Obviously, this will also cause the bits of the data interface DU_DIO[n+7:n] to not correspond to the bits of the bit lines BL[n+7:n] of the odd column address corresponding to the memory cell DU, that is, the test data vector configured by the test control logic IP does not match the data read from the physical layer bit lines of the memory cell.

[0051] When testing DRAM chips, the mismatch between the test data pattern configured by the test control logic IPb and the bits of the actual DRAM physical layer bit lines BL can affect certain specific DRAM testing requirements. For example, testing the DRAM physical layer bit lines BL with test data patterns such as 0x55, 0xAA, 0x00, and 0xFF (e.g., stress testing) can occur.

[0052] Based on this, please refer to Figure 4 One embodiment of the present invention provides a storage control module IP for testing the physical layer bit lines BL of a coupled storage unit DU. It is worth noting that in certain subsequent embodiments, the storage unit DU may be a memory array of a single-layer memory chip. In other embodiments, the storage unit DU may also include a multi-layer memory array of stacked multi-layer memory chips.

[0053] Among them, please refer to Figure 5 The storage unit DU includes a storage interface 30 (such as Figure 5 ), a plurality of bit lines BL, a plurality of word lines WL, and a memory array (not shown in the figure) determined by the intersection of the plurality of bit lines BL and the plurality of word lines WL. Figure 4 The memory array includes a memory cell (e.g., a memory interface 30) and peripheral circuits such as sense amplifiers SA between the memory interface 30 and the bit lines BL of the memory array. Each storage node cell in the memory array is located at the intersection of a corresponding word line WL and a bit line BL, corresponding to a storage address. Each word line WL (wordline) is addressed by the row address (RADD) in the corresponding storage address, and each bit line BL (bitline) is addressed by the column address (CADD) in the corresponding storage address. The memory unit DU can be a memory block, sector, page, or any other suitable management unit above the cell level in a memory device such as a DRAM. A page contains multiple bytes (the address range of which can be determined by multiple word lines and bit lines), a sector contains multiple pages, and a memory block contains multiple sectors.

[0054] The storage control module IP of this embodiment is configured as follows:

[0055] During the test, a (k+1)-bit test data vector MR[k:0] is configured, and the configured test data vector MR[k:0] is first converted bit by bit according to the column address DU_CADD to be tested, and then written bit by bit to the multi-bit bit line BL[n+k:n] (i.e., Figure 4 BLa[n+k:n] or BLb[n+k:n] in the memory control module IP), wherein (k+1) bits are the bit width of the test data vector MR[k:0], which is also the bit width of the storage data vector of the actual DRAM physical layer bit line BL, k+1 can be equal to any suitable value such as 4, 8, 16, or 32, and n is a multiple of k+1. The second mapping relationship is reversed through the first mapping relationship, so that the test data vector MR[k:0] configured by the storage control module IP corresponds one-to-one with the bits of the corresponding multi-bit bit line BL[n+k:n] in the memory unit DU.

[0056] Optionally, the storage control module IP is coupled to the storage interface 30 of the storage unit DU, and the storage interface 30 includes a data interface DU_DIO, a chip select interface, an address interface, and the like.

[0057] The data interface DU_DIO is coupled to the data input / output port DIO of the storage control module IP and is used to receive data from or output data to the data input / output port DIO. The data burst size (burst size) or data bit width of the data interface DU_DIO is an integer multiple of (k+1). After conversion through the first mapping relationship, MR[k:0] is repeated multiple times by the data input / output port DIO of the storage control module IP and then output to the data interface DU_DIO of the storage unit DU to meet the data burst size or data bit width requirements of the data interface DU_DIO.

[0058] The chip select interface is used to receive chip select signals DU_CS0, DU_CS1, etc. provided by the storage control module IP.

[0059] The address interface is used to receive the row address DU_RADD and column address DU_CADD provided by the storage control module IP.

[0060] It is worth noting that Figures 4-10 Only the (k+1)-bit portion of DU_DIO and the bit line BL is shown, i.e., a unit range where the first mapping relationship is used to reverse the second mapping relationship (or, alternatively, "the second mapping relationship reverses the first mapping relationship"). In this embodiment, the configured test data vector MR[k:0] is (k+1) bits, while the data bit width of the actual data interface DU_DIO is s times (s is an integer and s ≥ 1) of (k+1) bits). That is, the (k+1)-bit data vector converted from the configured test data vector MR[k:0] using the first mapping relationship is used as a repeating unit, repeated s times, and the s*(k+1)-bit data vector is provided to the data interface DU_DIO. In other words, every k+1 bit lines BL are grouped together, and during testing, s*(k+1) bit lines BL are synchronously activated for testing. Figures 4 to 10 Only the bit lines BL[n+k:n] corresponding to the n / (k+1)th group (i.e., the n / (k+1)th repetition) in the memory unit DU are shown, where n is a multiple of k+1 and 1≤n≤s, for ease of description.

[0061] In addition, in this embodiment, when the physical layout wiring of the peripheral circuits (i.e., the circuits peripheral to the memory array array in the memory unit DU, such as the sense amplifiers of the odd columns and the sense amplifiers of the even columns) connected to the bit lines (Bitline, BL) of the corresponding odd columns and even columns in the memory unit DU are different (e.g., the layout winding is different), the first mapping relationship corresponding to the odd column address and the even column address is different, and the second mapping relationship between the odd column address and the even column address is also different. Moreover, when the memory is shipped, the physical layout wiring of each memory unit DU is fixed, so The second mapping relationship between the odd column address and the even column address of each memory cell remains fixed. The second mapping relationship of the odd column address is determined by the physical layout and wiring of the peripheral circuit between the data interface DU_DIO of the memory cell DU and the odd column bit lines therein (for example, the physical layout and wiring of the sense amplifiers or other circuits of the odd columns). The second mapping relationship of the even column address is determined by the physical layout and wiring of the peripheral circuit between the data interface DU_DIO of the memory cell DU and the even column bit lines therein (for example, the physical layout and wiring of the sense amplifiers or other circuits of the even columns).

[0062] That is to say, the first mapping relationship in the present invention depends on the second mapping relationship (in fact, the first mapping relationship is the inverse conversion of the second mapping relationship), and the second mapping relationship depends on the physical layout and wiring inside the storage unit DU (for example, the physical layout and wiring of peripheral circuits such as the sense amplifier). For memories and storage units thereof with different layout and wiring (also referred to as "winding") designs, under the guidance of the inventive concept of the technical solution of the present invention, technicians can adaptively configure their first mapping relationship according to their second mapping relationship to achieve a one-to-one correspondence between the configured test data vector MR[k:0] and the bit positions of the multi-bit bit line BL[n+k:n] in the storage unit. Therefore, the specific design of the first mapping relationship and the second mapping relationship in the present invention is not specifically limited.

[0063] For example, when the column address DU_CADD is an even column address (referred to as an "even address"), please refer to Figure 6, after the configured test vector MR[k:0] is converted according to the first mapping relationship corresponding to the bit position, the following corresponding relationship will be established with the data interface DU_DIO of the storage unit DU according to the bit position: MR[k] corresponds to DU_DIO[n+k], MR[k-1] corresponds to DU_DIO[n+k-4], MR[k-2] corresponds to DU_DIO[n+k-1], ... MR[0] corresponds to DU_DIO[n], and after DU_DIO[n+k:n] is converted according to the second mapping relationship corresponding to the bit position, the following corresponding relationship will be established with the physical layer bit line BL of the storage unit DU according to the bit position: DU_DIO[n+k] corresponds to BL[n+k], DU_DIO[n+k-1] corresponds to BL[n+k-2], ... DU_DIO[n] corresponds to BL[n]. After the test vector MR[k:0] configured in this way undergoes two mapping conversions of the first mapping relationship and the second mapping relationship, the following corresponding relationship will be established with the physical layer bit line BL of the storage unit DU on a bit-by-bit basis: MR[k] corresponds to BL[n+k], MR[k-1] corresponds to BL[n+k-1], MR[k-2] corresponds to BL[n+k-2], MR[k-3] corresponds to BL[n+k-3], MR[k-4] corresponds to BL[n+k-4], and so on, MR[2] corresponds to BL[n+2], MR[1] corresponds to BL[n+1], and MR[0] corresponds to BL[n]. Obviously, each bit of MR[k:0] corresponds one-to-one to each bit of BL[n+k:n]. Therefore, when performing special tests such as stress testing on BL[n+k:n], by determining whether the data read from BL[n+k:n] has changed relative to the data in MR[k:0], it is possible to quickly analyze whether there is interference between adjacent bit lines BL in BL[n+k:n].

[0064] Similarly, when the column address DU_CADD is an odd column address (abbreviated as "odd address"), please refer to Figure 7, after the configured test vector MR[k:0] is converted into the corresponding first mapping relationship according to the bit position, the following corresponding relationship will be established with a unit range DU_DIO[n+k:n] of the data interface DU_DIO of the storage unit DU according to the bit position: MR[k] corresponds to DU_DIO[n+k-2], MR[k-1] corresponds to DU_DIO[n+1], MR[k-2] corresponds to DU_DIO[n+k-3], MR[k-3] corresponds to DU_DIO[n], MR[k-4] corresponds to DU_DIO[n+k], ..., MR[0] corresponds to DU_DIO[n+2], and the number After a unit range DU_DIO[n+k:n] of the data interface DU_DIO is converted into a corresponding second mapping relationship according to the bit position, the following corresponding relationship will be established with the physical layer bit line BL of the storage unit DU according to the bit position: DU_DIO[n+k] corresponds to BL[n+k-4], ..., DU_DIO[n+k-2] corresponds to BL[n+k], DU_DIO[n+k-3] corresponds to BL[n+k-2], ..., DU_DIO[n+2] corresponds to BL[n], DU_DIO[n+1] corresponds to BL[n+k-1], and DU_DIO[n] corresponds to BL[n+k-3]. After the test vector MR[k:0] configured in this way undergoes two mapping conversions of the first mapping relationship and the second mapping relationship, the following corresponding relationship will be established with the physical layer bit line BL of the storage unit DU on a bit-by-bit basis: MR[k] corresponds to BL[n+k], MR[k-1] corresponds to BL[n+k-1], MR[k-2] corresponds to BL[n+k-2], MR[k-3] corresponds to BL[n+k-3], MR[k-4] corresponds to BL[n+k-4], and so on, MR[2] corresponds to BL[n+2], MR[1] corresponds to BL[n+1], and MR[0] corresponds to BL[n]. Obviously, each bit of MR[k:0] corresponds one-to-one to each bit of BL[n+k:n]. Therefore, when performing special tests such as stress testing on BL[n+k:n], by determining whether the data read from BL[n+k:n] has changed relative to the data in MR[k:0], it is possible to quickly analyze whether there is interference between adjacent bit lines BL in BL[n+k:n].

[0065] Take k=7 as an example, please refer to Figure 8 When the column address DU_CADD is an even column address, please refer to Figure 6, after the configured test vector MR[7:0] is converted into the corresponding first mapping relationship according to the bit position, the following corresponding relationship will be established with a unit range DU_DIO[n+7:n] of the data interface DU_DIO of the storage unit DU according to the bit position: MR[7] corresponds to DU_DIO[n+7], MR[6] corresponds to DU_DIO[n+3], MR[5] corresponds to DU_DIO[n+6], MR[4] corresponds to DU_DIO[n+2], MR[3] corresponds to DU_DIO[n+5], MR[2] corresponds to DU_DIO[n+1], MR[0] corresponds to DU_DIO[n], and the number After a unit range DU_DIO[n+7:n] of the data interface DU_DIO is converted into the corresponding second mapping relationship according to the bit, the following corresponding relationship will be established with the physical layer bit line BL of the storage unit DU according to the bit: DU_DIO[n+7] corresponds to BL[n+7], DU_DIO[n+6] corresponds to BL[n+5], DU_DIO[n+5] corresponds to BL[n+3], DU_DIO[n+4] corresponds to BL[n+1], DU_DIO[n+3] corresponds to BL[n+6], DU_DIO[n+2] corresponds to BL[n+4], and DU_DIO[n] corresponds to BL[n]. After the configured test vector MR[k:0] undergoes two mapping conversions, the first mapping relationship and the second mapping relationship, the following correspondence relationship is established with the physical layer bit line BL of the memory unit DU: MR[7] corresponds to BL[n+7], MR[6] corresponds to BL[n+6], MR[5] corresponds to BL[n+5], MR[4] corresponds to BL[n+4], MR[3] corresponds to BL[n+3], MR[2] corresponds to BL[n+2], MR[1] corresponds to BL[n+1], and MR[0] corresponds to BL[n]. Obviously, each bit of MR[7:0] corresponds to each bit of BL[n+7:n]. Therefore, when performing special tests such as stress testing on BL[n+7:n], by determining whether the data read from BL[n+7:n] has changed relative to the data of MR[7:0], it is possible to quickly analyze whether there is interference between adjacent bit lines BL in BL[n+7:n].

[0066] Similarly, when the column address DU_CADD is an odd column address, please refer to Figure 9, after the configured test vector MR[k:0] is converted into the corresponding first mapping relationship according to the bit position, the following corresponding relationship will be established with a unit range DU_DIO[n+7:n] of the data interface DU_DIO of the storage unit DU according to the bit position: MR[7] corresponds to DU_DIO[n+5], MR[6] corresponds to DU_DIO[n+1], MR[5] corresponds to DU_DIO[n+4], MR[4] corresponds to DU_DIO[n], MR[3] corresponds to DU_DIO[n+7], MR[2] corresponds to DU_DIO[n+3], MR[1] corresponds to DU_DIO[n+7], MR[0] corresponds to DU_DIO[n+2], and the data After a unit range DU_DIO[n+7:n] of the interface DU_DIO is converted into the corresponding second mapping relationship according to the bit position, the following correspondence relationship will be established with the physical layer bit line BL of the storage unit DU according to the bit position: DU_DIO[n+7] corresponds to BL[n+3], DU_DIO[n+6] corresponds to BL[n+1], DU_DIO[n+5] corresponds to BL[n+7], DU_DIO[n+4] corresponds to BL[n+5], DU_DIO[n+3] corresponds to BL[n+2], DU_DIO[n+2] corresponds to BL[n], DU_DIO[n+1] corresponds to BL[n+6], and DU_DIO[n] corresponds to BL[n+4]. After the configured test vector MR[k:0] undergoes two mapping conversions, the first mapping relationship and the second mapping relationship, the following correspondence relationship is established with the physical layer bit line BL of the memory unit DU: MR[7] corresponds to BL[n+7], MR[6] corresponds to BL[n+6], MR[5] corresponds to BL[n+5], MR[4] corresponds to BL[n+4], MR[3] corresponds to BL[n+3], MR[2] corresponds to BL[n+2], MR[1] corresponds to BL[n+1], and MR[0] corresponds to BL[n]. Obviously, each bit of MR[7:0] corresponds to each bit of BL[n+7:n]. Therefore, when performing special tests such as stress testing on BL[n+7:n], by determining whether the data read from BL[n+7:n] has changed relative to the data of MR[7:0], it is possible to quickly analyze whether there is interference between adjacent bit lines BL in BL[n+7:n].

[0067] That is to say, when the test data vector MR[k:0] configured by the storage control module IP is 0x55, under the technical solution of this embodiment, regardless of whether the column address DU_CADD to be tested in the storage unit DU is an even column address or an odd column address, since the bit positions of the test data vector MR[k:0] correspond one-to-one to the bit positions of the bit line BL[n+k:n] of the column address to be tested in the storage unit DU, when the storage unit DU is read and written correctly, the data read from the BL[n+k:n] will still be 0x55, that is, the configured test data and the read data are the same (in other words, the configured test data vector and the read data vector are the same).

[0068] Therefore, the storage control module IP of this embodiment can facilitate certain specific testing requirements for the storage unit DU, such as testing the physical layer bit line BL of the storage unit DU with test data vectors such as 0x55, 0xAA, 0x00, and 0xFF (such as stress testing), analyzing the degree of influence between adjacent bit lines BL, and thus determining the read and write performance of the storage unit DU.

[0069] In which, when the storage control module IP of this embodiment is used to perform a stress test on the corresponding target bit line BL in the storage unit DU, the storage control module IP is also used to configure a (k+1)-bit test vector MR[k:0], and read data IO[n+k:n] or ION[n+k:n] from the (k+1)-bit bit line BLa[n+k:n] or BLb[n+k:n] composed of the target bit line and its adjacent bit lines, so as to check whether the read data IO[n+k:n] or ION[n+k:n] has changed relative to the data of the configured test data vector MR[k:0], and then analyze whether there is interference between the target bit line BL and its adjacent bit lines.

[0070] In one example, the stress test mode includes a write-read disturb test mode. In the write-read disturb test mode, the storage control module IP is further configured as follows:

[0071] (1) Initializing the target bit line BL and the bit lines BL adjacent to the target bit line BL to a known data vector, that is, initializing the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the bit lines adjacent to the target bit line BL to a known data vector;

[0072] (2) performing multiple write operations on the target bit line BL to write the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the adjacent bit line BL to another data vector different from the known data vector (i.e., a configured test data vector; when k=7, the known data vector is, for example, 0xAA or 0x55, and the other data vector is, for example, 0xFF or 0x00);

[0073] (3) After each write operation, the stored data on the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the adjacent bit line BL is read to check whether the data of the adjacent bit lines of the target bit line BL has changed (that is, check whether the data of BL[n+k:n] is the same as the data of other data vectors written);

[0074] (4) If yes, it means that there is interference between the target bit line BL and its adjacent bit line BL.

[0075] In another example, the stress test mode includes a read disturb test mode. In the read disturb test mode, the storage control module IP is further configured as follows:

[0076] (1) Initializing the target bit line BL and the bit lines BL adjacent to the target bit line BL to a known data vector (i.e., a configured test data vector, when k=7, the known data vector is, for example, 0xAA or 0x55), that is, initializing the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the bit lines adjacent to the target bit line BL to a known data vector;

[0077] (2) performing multiple consecutive read operations on the target bit line BL;

[0078] (3) After each consecutive read operation, the stored data on the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the adjacent bit line BL is read to check whether the data of the adjacent bit lines of the target bit line BL has changed (that is, check whether the data of BL[n+k:n] is the same as the data of the known data vector);

[0079] (4) If yes, it means that there is interference between the target bit line BL and its adjacent bit line BL.

[0080] In another example, the stress test mode includes a write-write disturb test mode. In the write-write disturb test mode, the storage control module IP is further configured as follows:

[0081] (1) Initializing the target bit line BL and the bit lines BL adjacent to the target bit line BL to a known data vector, that is, initializing the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the bit lines adjacent to the target bit line BL to a known data vector;

[0082] (2) alternately performing write operations on the target bit line BL and its adjacent bit line, so as to write the (k+1)-bit bit line BL[n+k:n] composed of the target bit line BL and the adjacent bit line BL to other data vectors different from the known data vector (i.e., configured test data vectors, when k=7, the known data vector is, for example, 0xAA or 0x55, and other data vectors are, for example, 0xFF or 0x00);

[0083] (3) Each time a write operation is performed on the target bit line BL and its adjacent bit line, the stored data on the (k+1)-bit bit line BL[n+k:n] consisting of the target bit line BL and the adjacent bit line BL is read to check whether the data of the adjacent bit lines of the target bit line BL has changed (that is, check whether the data of BL[n+k:n] is the same as the data of other data vectors written);

[0084] (4) If yes, it means that there is interference between the target bit line BL and its adjacent bit line BL.

[0085] In other examples, the aforementioned known data vector may include any one of 0x55, 0xAA, 0x00, and 0xFF.

[0086] The storage control module IP of the present invention can be applied to the testing of three-dimensional stacked memories (eg, packaged memories).

[0087] Please combine Figure 4 、 Figure 11 and Figure 12As shown, the memory unit DU includes a plurality of stacked memory array bodies, each of which has a memory array (not shown), a plurality of bit lines BL and a peripheral circuit coupled to the memory array (such as a sense amplifier SA, etc.). The memory control module IP is coupled to each memory array body of the memory unit DU, and the memory control module IP is further configured to: receive decoding information of a corresponding test instruction (which includes address information of the test instruction) and a test configuration content LTC_REGDIN, and activate the corresponding chip select signal DU_CS0, DU_CS1, etc. of the memory unit DU according to the received decoding information and test configuration content LTC_REGDIN, so as to select a corresponding memory array body in the memory unit DU for access, and then test the physical layer bit line BL of the selected memory array body. Among them, the decoding information includes the test interface enable signal LTC_MODE, the address signal LTC_ID for selecting the storage control module IP (that is, a type of address information in the decoding information), the address signal LTC_MASK_ID for selecting multiple storage control module IPs in parallel (that is, another type of address information in the decoding information), and the address signal LTC_REGADD for the configuration register (that is, another type of address information in the decoding information), etc.

[0088] In another example, see Figures 10 to 12 The storage control module IP can simultaneously manage p+1 memory units DU0-DUp located in the same memory stack 3. The memory stack 3 has j+1 stacked memory dies 300-30j. Each memory array of each memory unit DU is part of a corresponding memory die in the memory stack 3. Figure 11 Each layer of memory bare core is divided into (q+1)*(p+1) storage units DU. The first storage array body in DU0~DUp managed by the storage control module IP0 is part of the memory bare core 300, the second storage array body in DU0~DUp managed by the storage control module IP0 is part of the memory bare core 302, and so on.

[0089] Each storage control module IP is also configured to select the same layer of storage array body of all storage units DU0~DUp managed by it for access according to the address information and test configuration content of the test instruction it receives, and then perform synchronous testing on the physical layer bit lines BL of the same layer of storage array body of all storage units DU0~DUp managed by it.

[0090] In this example, the storage interface 30 of storage unit DU0 includes a data interface DU0_DIO, a chip select interface, and an address interface. The data interface DU0_DIO is coupled to the corresponding data input / output port DIO in the storage control module IP and is used to receive data from the data input / output port DIO or output data to the data input / output port DIO. The chip select interface is used to receive chip select signals DU0_CS0 and DU0_CS1 provided by the storage control module IP, and the address interface is used to receive the row address DU0_RADD and column address DU0_CADD provided by the storage control module IP.

[0091] Similarly, the storage interface 30 of the storage unit DUp includes a data interface DUp_DIO, a chip select interface, and an address interface. The data interface DUp_DIO is coupled to the corresponding data input / output port DIO in the storage control module IP and is used to receive data from the data input / output port DIO or output data to the data input / output port DIO. The chip select interface is used to receive chip select signals DUp_CS0, DUp_CS1, etc. provided by the storage control module IP, and the address interface is used to receive row addresses DUp_RADD and column addresses DUp_CADD provided by the storage control module IP.

[0092] Alternatively, refer to Figure 4 and Figure 11 The storage control module IP of this embodiment includes a test interface IPa and a test control logic IPb.

[0093] Among them, the test interface IPa can be coupled to the memory test control management module 21 in the memory controller 2 to receive the decoding information of the test instruction (including the address information of the test instruction) and the test configuration content LTC_REGDIN provided by the memory test control management module 21, and output the data LTC_REGDOUT read from the storage unit DU managed by it to the memory test control management module 21, wherein the decoding information includes the test interface enable signal LTC_MODE, the address signal LTC_ID for selecting the storage control module IP (that is, one type of address information in the decoding information), the address signal LTC_MASK_ID for selecting multiple storage control modules IP in parallel (that is, another type of address information in the decoding information), and the address signal LTC_REGADD for the configuration register (that is, another type of address information in the decoding information), etc.

[0094] The test control logic IPb is used to activate the chip select signal (such as DU_CS0) corresponding to the memory unit DU it manages according to the address information and test configuration content LTC_REGDIN in the decoded information received by the test interface IPa, so as to select a memory array body corresponding to the memory unit DU for access.

[0095] Optionally, the high-order address of the corresponding address signal (i.e., the corresponding address information) in the decoded information of the test instruction received by the test interface IPa carries chip select information. The test control logic IPb can parse the high-order address of the address signal of the test instruction received by the test interface IPa to derive the chip select signal DU_CS corresponding to the test instruction. In other embodiments of the present invention, the test control logic IPb can also generate the chip select signal DU_CS corresponding to the test instruction based on the decoded information of the test instruction received by the test interface IPa and the test configuration content LTC_REGDIN, etc., using any other suitable method.

[0096] As an example, the test control logic IPb further includes:

[0097] The configuration register MR is coupled to the test interface IPa and is used to configure the corresponding k+1-bit test data vector MR[k:0] for the memory array to be tested (also "chip-selected" or "hit") based on the decoded information and test configuration content LTC_REGDIN received by the test interface IPa. The configuration register MR can be a single register with a larger capacity or a register group consisting of multiple smaller registers (each register is used to store corresponding configuration content).

[0098] The inverse conversion module IPb0 is coupled to the configuration register MR and is used to parse decoding information, which includes address information or address signals such as LTC_MASK_ID, LTC_ID and LTC_REGADD, so as to obtain the column address DU_CADD to be tested in the chip-selected memory array body and its characteristics (such as parity), and according to the obtained column address DU_CADD and its characteristics (such as parity), the test data vector MR[k:0] configured by the configuration register MR is converted to the corresponding first mapping relationship bit by bit.

[0099] The data input / output port DIO is coupled to the storage interface 30 of the storage unit DU and is used to send the data vector converted by the inverse conversion module IPb0 to the chip-selected memory array in the storage unit DU through the storage interface 30, and then write the data vector to the corresponding multi-bit bit line BL[n+k:n] (i.e., the physical layer of the chip-selected memory array) of the chip-selected memory array according to the second mapping relationship determined by the physical layout wiring (e.g., the physical layout wiring of the sense amplifier SA) inside the chip-selected memory array. Figure 4 on BLa[n+k:n] or BLb[n+k:n]).

[0100] It should be understood that the storage control module IP of this embodiment not only includes the above-mentioned test interface IPa and test control logic IPb, but may also include any other required functional modules, such as an ECC (Error Checking and Correcting) module, a latch module, etc., and the present invention does not make specific limitations on this.

[0101] The storage control module IP of this embodiment can perform a first internal mapping relationship conversion and a second mapping relationship conversion determined by the physical layout wiring inside the storage unit DU based on the characteristics of the column address DU_CADD to be tested (such as parity) before writing the configured test data vector to the DU physical layer bit line of the storage unit it manages (such as a DRAM storage unit). Utilizing the secondary mapping of the first mapping relationship and the second mapping relationship, the bits of the configured test data vector are matched one-to-one with the bits of the physical layer bit line of the storage unit DU, thereby facilitating certain specific testing requirements for the memory, such as testing the physical layer bit line BL of the memory with test data vectors such as 0x55, 0xAA, 0x00, and 0xFF (such as a stress test), analyzing the degree of influence between adjacent bit lines, and thus determining the read and write performance of the memory.

[0102] Based on the same invention concept, please refer to Figure 11 One embodiment of the present invention further provides a memory controller 2 for testing the physical layer bit lines BL of a corresponding memory stack 3. The memory stack 3 includes j+1 stacked layers of memory die 300-30j. The storage space of the memory stack 3 is divided into multiple memory units DU. Each memory unit DU includes multiple stacked memory arrays. Each memory array of each memory unit DU is a portion of a corresponding memory die. Each memory array of each memory unit DU has a number of bit lines BL. The memory controller 2 includes a multi-IO master device interface 20, a memory test control management module 21, and q+1 memory control modules IP0-IPq of the present invention. Wherein, q and j are both integers greater than or equal to 1.

[0103] The master device interface 20 is used to communicate with a test host (i.e., a device accessing memory) 1, implement interface conversion between the test host 1 and the memory controller 2, receive information or signals such as test instructions and their address information, and test configuration content (including data to be written to the memory stack 3) sent by the test host 1, and transmit signals such as read data back to the test host 1. The master device interface 20 can be any suitable parallel communication protocol interface that supports multiple I / Os, such as an AXI (Advanced eXtensible Interface) interface. The AXI interface is an on-chip bus interface designed for high-performance, high-bandwidth, and low-latency master-slave architecture. Its address, instruction, and data phases are separated, supporting unaligned data transmission. In burst transmission, only the first address is required. Separate read and write data channels are available, supporting access to a large number of outstanding pending instructions (e.g., the number of outstanding transactions such as read and write instructions) and out-of-order access, making timing closure easier and suitable for high-speed memory access. It is worth noting that although the master device interface 20 shown in the drawings of the specification is the AXI protocol, the present invention is not limited to this. The master device interface 20 can also adopt any other suitable high-bandwidth interface protocol, such as the AHB (Advanced High-performance Bus) protocol or the CHI (Coherent Hub Interface) protocol.

[0104] The test host 1 can be a pre-shipment test machine for memory devices. It can be coupled to the memory controller 2 via a probe card to apply corresponding test stimuli to the memory controller 2, thereby enabling the memory controller 2 to activate corresponding word lines WL or bit lines BL in the memory stack 3, thereby performing corresponding tests on the memory stack 3. The test host 1 can also be integrated into a post-shipment logic chip (logic die) of the memory device and include any type of processing device with computing capabilities, such as a central processing unit (CPU), digital signal processor (DSP), network processor, application processor (AP), field programmable gate array (FPGA), or dedicated processor. The processing device can be configured to execute instructions or software (including code, operating system, or application, etc.) executable by one or more computers, firmware, or a combination thereof. The memory controller 2 can be integrated within the logic chip or in a buffer die between the logic chip and the memory stack 3. The test host 1 applies corresponding test stimuli to the memory controller 2, thereby enabling the memory controller 2 to activate corresponding word lines WL or bit lines BL in the memory stack 3, thereby performing corresponding tests on the memory stack 3.

[0105] The memory test control management module (logic test controller) 21 is coupled to the host device interface 20 and each memory control module IP0~IPq, and is used to parse the test instructions received by the host device interface 20 to generate corresponding decoding information (which includes the address information of the parsed test instructions). Based on the decoding information, it determines the memory control module IP and memory unit DU hit by each test instruction, and then provides the corresponding content in the decoding information (which includes the corresponding address information) and test configuration content (which includes the "input test data vector") LTC_REGDIN to the hit memory control module IP. Please refer to Figure 4 In this embodiment, the decoding information provided by the memory test control management module 21 to the hit memory control module IP includes:

[0106] (1) Test interface enable signal LTC_MODE, which is used to enable or disable the storage control module IP. Usually, a hit storage control module IP is enabled by the test interface enable signal LTC_MODE it receives, and a non-hit storage control module IP is disabled by the test interface enable signal LTC_MODE it receives;

[0107] (2) The storage control module address LTC_ID to be tested (i.e., an execution address of the test instruction), which is used to determine which specific (i.e., hit) storage control module IP executes the test instruction;

[0108] (3) The storage control module address LTC_MASK_ID to be tested in parallel (i.e., another execution address of the test instruction), which is used to determine (or "select") which storage control module IPs (i.e., multiple hit storage control module IPs) have to execute the test instruction in parallel;

[0109] (4) The column address LTC_REGADD of the memory cell to be tested (i.e., another execution address of the test instruction), which is used to determine which bit lines BL in the hit memory cell DU are to be tested;

[0110] Each storage control module IP0~IPq is coupled to p+1 storage units DU0~DUp in the memory stack 3, and is used to receive corresponding decoding information (including corresponding address information) and test configuration content LTC_REGDIN, and then implement testing of the physical layer bit line BL of the coupled storage unit DU based on the decoding information (including corresponding address information) and test configuration content LTC_REGDIN.

[0111] Optionally, the memory test control management module 21 includes a test manager 211 , a register 210 and an address decoder 212 .

[0112] The test manager 211 is coupled to the host interface 20, the address decoder 212, the register 210, and each memory control module IP0-IPq. The test manager 211 is configured to transmit the execution address (i.e., the address information of the test instruction) contained in the decoded information of the test instruction received by the host interface 20 to the address decoder 212 for address resolution. This determines the memory control module IP targeted by each test instruction to be executed, the targeted memory unit DU, the target bit line BL in the targeted memory unit DU, and the adjacent bit lines BL of the targeted bit line BL. Furthermore, the column address of the target bit line BL and the adjacent bit lines BL, as resolved by the address decoder 212, is transmitted to the targeted memory control module IP.

[0113] Register 210 can be used to store information related to test instructions and their address information, test configuration content (including test data, some test parameters configured by the user, or some configuration values ​​generated by the test manager 211 according to the test instructions, etc.). It can be a register group composed of multiple registers with smaller capacity, or it can be a single register with larger capacity.

[0114] Please refer to Figure 12 In one embodiment, the memory controller 2 of the present invention is disposed on a buffer die 200 (also called a base die). The memory stack 3 includes j+1 layers of stacked memory dies 300-30j. The logic die 100, buffer die 200, and memory stack 3 are stacked sequentially. The logic die 100 and buffer die 200 are hybrid-bonded via through-silicon vias (TSVs). Hybrid TSVs are also used to bond the multiple memory dies 300-30j to each other and to the buffer die 200. In other embodiments, only the buffer die 200 and the memory stack 3 are stacked sequentially, while the logic die 100 and buffer die 200 are connected via other means.

[0115] In other embodiments, please combine Figure 11 and Figure 12 Buffer die 200 can be omitted, and memory controller 2 can be placed in logic die 100. Multi-layer memory die 300-30j are hybrid-bonded to each other and to logic die 100 via through-silicon vias. Test host 1 is an independent test host. For example, test host 1 is a test machine used to test memory chip products (including memory stack 3 and memory controller 2) before shipment. In other embodiments, test host 1 can also be placed in logic die 100.

[0116] Furthermore, each memory die 300-30j may be any suitable type of memory die structure, such as DRAM. The DRAM may be any type, such as synchronous DRAM (SDRAM) or wide I / O DRAM. The memory stack 3 may be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), or the like.

[0117] This TSV hybrid bonding technology, on the one hand, expands the capacity of the storage units DU managed by each storage control module IP, thereby expanding the capacity of the memory stack 3 managed by the corresponding memory controller 2, while reducing the chip area. On the other hand, the storage control module IP can load corresponding information or data into itself or into each storage unit DU it manages through TSVs, solving the problem of large lane occupation when loading this information through dedicated routing (such as EFUSE bus lines) in the existing technology.

[0118] It should be understood that the memory controller 2 can implement interface conversion between the test host 1 and the j+1-layer memory die 300-30j, complete address decoding and data format conversion (such as data bit width) between the test host 1 and the j+1-layer memory die 300-30j, and convert test instructions such as read and write issued by the test host 1 into signals that can be recognized by the j+1-layer memory die 300-30j, thereby implementing the necessary control of the test host 1's access to the j+1-layer memory die 300-30j for read and write operations (including control of address signals, data signals, and various instruction signals). The test host 1 is enabled to access (or "use," "operate") and test the storage resources (i.e., the corresponding storage units) on the j+1 layer memory bare cores 300-30j according to user needs. Therefore, the internal circuit of the memory controller 2 may not be limited to the aforementioned host device interface 20, memory test control management module 21, and q+1 storage control modules IP0-IPq, but may also include any other required functional modules. Alternatively, the memory test control management module 21 may include not only the test manager 211 and the address decoder 212, but may also include any other required functional modules. The present invention does not impose any specific limitations on this.

[0119] Based on the same invention concept, please refer to Figure 11 and Figure 12One embodiment of the present invention further provides a three-dimensional stacked memory, which includes a memory stack 3 and a memory controller 2 according to the present invention, wherein the memory controller 2 is provided on a buffer die 200 (different from Figure 12 In an embodiment where the logic die 100 is not provided, the memory controller 2 is provided in the logic die 100), and the memory stack 3 includes j+1 layers of memory die 300~30j stacked in three dimensions, wherein the memory die 300~30j are hybrid bonded to each other and to the buffer die 200 through silicon vias.

[0120] Since the memory controller and three-dimensional stacked memory provided by the present invention adopt the storage control module of the present invention, the configured test data vector (i.e., the input test data vector) in the storage control module can be converted into a first mapping relationship according to the parity of the column address to be tested, and then after the converted data is sent to the interior of the storage unit, it is converted into a data vector corresponding one-to-one to the bit position of the physical layer bit line BL of the storage unit through the second mapping relationship of the sensitive amplifier inside the storage unit. In this way, the test data under the test data vector can be accurately written to the physical layer bit line BL of the storage unit in a one-to-one correspondence with the bit position, thereby meeting some special testing requirements of the memory, such as meeting the need to test the physical layer bit line of the memory.

[0121] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A storage control module for testing the physical layer bit lines of a memory cell coupled thereto, characterized in that: The storage unit includes a plurality of bit lines, each of which is addressed by a corresponding column address, and the storage control module is configured as follows: During testing, a multi-bit test data vector is configured, and the configured test data vector is first converted bit by bit according to a first mapping relationship based on the column address to be tested, and then written bit by bit to a multi-bit bit line corresponding to the physical layer of the storage unit according to a second mapping relationship determined by the physical layout and wiring of the storage unit; The combination of the first mapping relationship and the second mapping relationship enables the bits of the configured test data vector to correspond one-to-one with the bits of the multiple bit lines; And the second mapping relationship of the storage unit is determined by the physical layout wiring of the peripheral circuit between the storage interface of the storage unit and the physical layer bit line, wherein the second mapping relationship of the odd column address to be tested is determined by the physical layout wiring of the peripheral circuit between the storage interface and the odd column bit line of the storage unit; the second mapping relationship of the even column address to be tested is determined by the physical layout wiring of the peripheral circuit between the storage interface and the even column bit line of the storage unit.

2. The storage control module according to claim 1, wherein: The peripheral circuit between the storage interface and the odd column bit lines includes an odd column sense amplifier inside the storage unit; the peripheral circuit between the storage interface and the even column bit lines includes an even column sense amplifier inside the storage unit.

3. The storage control module according to any one of claims 1 to 2, wherein: The test includes a stress test on the corresponding target bit line in the storage cell. The storage control module is also used to read data from the multi-bit bit line consisting of the target bit line and its adjacent bit lines to check whether the read data has changed relative to the data of the test data vector, and then analyze whether there is interference between the target bit line and its adjacent bit lines.

4. The storage control module according to claim 3, wherein: The stress test mode includes a write-read interference test mode. In the write-read interference test mode, the storage control module is further configured to: first initialize the target bit line and the adjacent bit lines of the target bit line to a known data vector, and then perform multiple write operations on the target bit line to write the target bit line and the adjacent bit lines to other data vectors different from the known data vector, and read the data of the target bit line and the adjacent bit line after each write operation to check whether the adjacent bit lines have data changes. If so, it means that there is interference between the target bit line and the adjacent bit line.

5. The storage control module according to claim 3, wherein: The stress test mode includes a read-read interference test mode. In the read-read interference test mode, the storage control module is further configured to: first initialize the target bit line and the adjacent bit lines of the target bit line to known data vectors, and then perform multiple continuous read operations on the target bit line, and read the data of the target bit line and the adjacent bit lines after each continuous read operation to check whether the adjacent bit lines have data changes. If so, it means that there is interference between the target bit line and the adjacent bit lines.

6. The storage control module according to claim 3, wherein: The stress test mode includes a write-write interference test mode. In the write-write interference test mode, the storage control module is further configured to: first initialize the target bit line and the adjacent bit lines of the target bit line to a known data vector, and then alternately perform write operations on the target bit line and the adjacent bit line to write the target bit line and the adjacent bit line to other data vectors different from the known data vector. After each write operation is alternately performed on the target bit line and the adjacent bit line, the data of the target bit line and the adjacent bit line are read to check whether the adjacent bit line has undergone data changes. If so, it indicates that there is interference between the target bit line and the adjacent bit line.

7. The storage control module according to any one of claims 4 to 6, wherein: The known data vector includes any one of 0x55, 0xAA, 0x00, and 0xFF.

8. The storage control module according to any one of claims 1-2 and 4-6, wherein: The storage unit includes multiple stacked storage array bodies, each of which has the multiple bit lines. The storage control module is coupled to each of the storage array bodies, and the storage control module is also configured to: receive address information and test configuration content of a corresponding test instruction, and activate the chip select signal corresponding to the storage unit based on the address information and the test configuration content to select a corresponding storage array body in the storage unit for access, and then test the physical layer bit lines of the selected storage array body.

9. The storage control module according to claim 8, wherein: The storage control module simultaneously manages multiple storage units located in the same storage stack, and the memory stack has multiple stacked memory bare cores, and each storage array body of each storage unit is a part of a corresponding memory bare core in the memory stack; the storage control module is also configured to select the same layer of storage array bodies of all the storage units it manages to access according to the address information and the test configuration content, and then perform synchronous testing on the physical layer bit lines of the same layer of storage array bodies of all the storage units it manages.

10. The storage control module according to claim 8, wherein: The storage control module includes a test interface and test control logic, wherein the test interface is used to receive address information and test configuration content of a corresponding test instruction and output data read from the storage unit; The test control logic is used to activate a chip select signal corresponding to the storage unit according to the address information and the test configuration content to select a corresponding storage array body in the storage unit for access, and the test control logic further includes: a configuration register coupled to the test interface and configured to configure the corresponding multi-bit test data vector for the storage array body according to the corresponding address information and the test configuration content; an inverse conversion module, coupled to the configuration register, and configured to convert the test data vector configured by the configuration register into a first mapping relationship bit by bit according to the column address to be tested of the memory array; The data input and output port is coupled to the storage interface of the storage array body and is used to send the data vector converted by the inverse conversion module to the storage array body through the storage interface.

11. A memory controller for testing physical layer bit lines of a plurality of memory cells of a corresponding memory stack, characterized in that: The memory stack includes multiple layers of stacked memory die, each memory array in each memory unit is a portion of the memory die in the corresponding layer, and the memory controller includes a host device interface, a memory test control management module, and several memory control modules according to any one of claims 1 to 10; wherein: The main device interface is connected to the corresponding test host for communication and is used to receive the test instructions to be executed and their address information and test configuration content; The memory test control management module is coupled to the master device interface and each of the memory control modules, and is configured to parse the address information and test configuration content of the test instructions received by the master device interface, determine the memory control module and memory unit targeted by each test instruction based on the address information, and then provide the address information and test configuration content to the targeted memory control module; Each of the storage control modules is coupled to at least one of the storage cells in the memory stack, and is used to receive the address information and the test configuration content, and then implement a test of the physical layer bit line of the coupled storage cell according to the address information and the test configuration content.

12. The memory controller according to claim 11, wherein: The memory test control management module includes a test manager, a register and an address decoder; The test manager is coupled to the main device interface, the address decoder, the register and each of the storage control modules. The test manager is used to send the address information of the test instruction received by the main device interface to the address decoder for address resolution, so as to determine the storage control module hit by each of the test instructions to be executed, the hit storage unit and the target bit line in the hit storage unit and the adjacent bit line of the target bit line, and then transmit the test configuration content and the column address of the target bit line and the adjacent bit line resolved by the address decoder to the hit storage control module.

13. The memory controller according to claim 11, wherein: The memory controller is arranged in the buffer bare core, and the multi-layer memory bare cores and the buffer bare cores are hybrid bonded through silicon vias; or, the memory controller is arranged in the logic bare core, and the multi-layer memory bare cores and the logic bare cores are hybrid bonded through silicon vias.

14. A three-dimensional stacked memory, characterized in that: A memory controller according to any one of claims 11 to 13 comprising a memory stack and coupled thereto.

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