Test algorithm for screening security indexes of storage chips

Abstract

The invention relates to the technical field of memory chip testing, and particularly discloses a test algorithm for screening security indexes of a memory chip, which comprises the following steps of: firstly, establishing a plurality of groups of monitoring environments with different temperatures according to a fixed temperature difference interval, and determining the security indexes of the memory chip by combining read-write data of each read-write operation of the memory chip in a read-write test; according to the method, the read-write abnormal coefficient of each storage chip in the read-write operation process can be calculated, the data reflect whether the read-write state of the storage chip in one read-write operation in different test environments is qualified or not, and then the read-write stability is analyzed by combining the test data of each storage chip in one read-write test. According to the method and the device, the read-write frequency of each storage chip is estimated in combination with the data, and the security of the storage chips is analyzed in combination with the preset read-write operation frequency threshold, so that a large amount of read-write operation tests can be reduced, and the test efficiency of the security of the storage chips is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of storage chip testing, and specifically to a test algorithm for screening the security indicators of storage chips. Background Art

[0002] The security test of storage chips is a means for evaluating the security of storage chips, mainly including basic performance tests, environmental adaptability tests, stress tests, mechanical property tests, and tests under other specific conditions, which helps to ensure the stability and reliability of storage chips under various environments and usage conditions.

[0003] Since storage chips are widely used and their application environments are variable, for the security tests of different types of storage chips, the environmental adaptability test is extremely important. To test the security of storage chips working in high and low temperature environments, multiple monitoring environments with different temperatures are usually established, and read and write operations of storage chips are performed in each monitoring environment. Then, by monitoring whether the number of read and write operations of each storage chip reaches the preset threshold of the read and write operation test times, a judgment is made on the environmental adaptability of the storage chip, so as to evaluate its security based on the environmental adaptability of the storage chip, and different types of storage chips are screened according to the evaluation results.

[0004] The traditional environmental adaptability test of storage chips generally places the storage chips in monitoring environments with different temperatures and makes a judgment on the environmental adaptability of the storage chips according to whether the number of read and write operations of the storage chips reaches the preset threshold of the read and write operation test times. Although this method has high accuracy, since it needs to be compared with the preset threshold of the read and write operation test times, a large amount of time is consumed for the read and write operation tests, thus affecting the test efficiency of the security of storage chips. Summary of the Invention

[0005] The purpose of the present invention is to provide a test algorithm for screening the security indicators of storage chips, and solve the following technical problems:

[0006] How to improve the test efficiency of the security of storage chips.

[0007] The purpose of the present invention can be achieved by the following technical solutions:

[0008] A test algorithm for screening the security indicators of storage chips, the algorithm includes the following steps:

[0009] S1: First, set multiple test environments with different temperatures at a fixed temperature difference interval, and place each same type of storage chip in each of the test environments for read and write tests;

[0010] S2: Collect the real-time read / write data generated by each of the storage chips during each read / write operation through the data collection module;

[0011] S3: By combining a number of the collected read / write data, map them one by one to the read / write anomaly coefficients of each storage chip during the corresponding read / write operation, and calculate the read / write anomaly coefficients;

[0012] S4: By combining the read / write anomaly coefficients of each storage chip during a read / write operation, analyze whether there is an anomaly in this read / write operation, and label the abnormal read / write operations;

[0013] S5: By combining the test data of all storage chips in a read / write test, calculate the fluctuation value of the read / write anomaly coefficients of each storage chip in the read / write test, and analyze the read / write stability of each storage chip based on this data;

[0014] S6: By combining the fluctuation values of the read / write anomaly coefficients of each storage chip in a read / write test, estimate the number of read / write operations of each storage chip, analyze the security of the storage chips in combination with the preset threshold of the number of read / write operations, and screen the storage chips according to the analysis results.

[0015] Further, the calculation process in S3 includes:

[0016] Through the formula Calculate the read / write anomaly coefficient y of the a-th storage chip during the i-th read / write operation ai ;

[0017] Where a is any one of the test storage chips, and each storage chip corresponds to a monitoring environment, i is any one of the read / write operations in a read / write test, dq ai Is the read time of the a-th storage chip during the i-th read / write operation, dq y Is the preset read time, xr ai Is the write time of the a-th storage chip during the i-th read / write operation, xr y Is the preset write time, sj y Is the total preset duration of a read / write operation, dx ai The number of read / write errors of the a-th storage chip during the i-th read / write operation, dx y Is the preset number of read / write errors, dx b Is the standard value of dx ai Is the preset storage space size of the storage chip, xp y Is the storage space size of the a-th storage chip after the i-th read / write operation is completed, f ai For z(x) is a defined function. If f z (x) ≥ 1, let f z (x) = x. If f z (x) < x, then let f z (x) = 1.

[0018] Furthermore, the comparison process in S4 includes:

[0019] By comparing the read / write exception coefficient y ai of the a-th storage chip during the i-th read / write operation with the preset read / write exception coefficient threshold y 01 ;

[0020] If y ai ≥ y 01 , it is determined that there is a read / write exception in the a-th storage chip during this read / write operation, and this read / write operation is marked;

[0021] If y ai < y 01 , it is determined that there is no read / write exception in the a-th storage chip during this read / write operation, and this read / write operation does not need to be marked.

[0022] Furthermore, the analysis process in S5 includes:

[0023] By using the formula to calculate the read / write exception coefficient fluctuation value

[0024] [[ID= of the a-th storage chip in a read / write test where n is the total number of read / write operations in a read / write test, is the average value of all y ai , is the maximum value of all y ai , is the minimum value of all y ai , sl a is the number of read / write operation exceptions of the a-th storage chip in a read / write test, sl y is the preset number of read / write operation exceptions, and g is a proportionality coefficient set by empirical fitting.

[0025] Furthermore, the analysis process in S5 also includes:

[0026] By comparing the read / write exception coefficient fluctuation values of all storage chips in a read / write test with the preset fluctuation value threshold respectively;

[0027] If any is greater than or equal to Determining that the read / write stability of the storage chip is poor means that when the storage chip is used in a monitoring environment based on this storage chip, the read / write of the storage chip is prone to anomalies, indicating that this type of storage chip cannot adapt to different monitoring environments, and determining that the security of this type of storage chip is poor;

[0028] If all are less than Determining that the read / write stability of all storage chips is good means that when used in all monitoring environments established by this type of storage chip, the read / write of the storage chip is not prone to anomalies, indicating that this type of storage chip can adapt to different monitoring environments, and determining that the security of this type of storage chip is high.

[0029] Furthermore, the analysis process in S6 includes:

[0030] By combining the test data of the a-th storage chip in a single read / write test, establish the change curve w a (t)

[0031] Through the formula Calculate the estimated number of read / write operations p of the a-th storage chip a ;

[0032] where t1 is the first read / write operation in a single read / write test, t2 is the last read / write operation in a single read / write test, and f k is the adjustment coefficient comparison table function, and is obtained based on the influence degree of the value range of the value in the empirical data on the number of read / write operations of the storage chip according to the test data.

[0033] Furthermore, the analysis process in S6 also includes:

[0034] By comparing the estimated number of read / write operations p of all storage chips a with the preset read / write operation threshold respectively p 01 ;

[0035] If any p a is less than or equal to p 01 , determine that the read / write life of the storage chip in its corresponding monitoring environment is lower than the threshold, which means that the environmental adaptability of this type of storage chip is poor, and determine that the security index of this type of storage chip is poor;

[0036] If all p a are greater than p 01 , determine that the read / write life of all storage chips in their respective corresponding monitoring environments is higher than the threshold, which means that the environmental adaptability of this type of storage chip is strong, and determine that the security index of this type of storage chip is high.

[0037] Further, the maximum temperature value of all monitored environments in S1 does not exceed 85°C, and the minimum temperature value is not lower than -45°C.

[0038] Advantages of the present invention:

[0039] (1) By combining the read and write data of each read and write operation in the read and write test of the storage chip, the present invention can calculate the read and write anomaly coefficient of each storage chip during the read and write operation. This data reflects whether the read and write status of the storage chip in a read and write operation is qualified in different test environments. Then, by combining the test data of each storage chip in a read and write test to analyze the read and write stability, estimating the read and write times of each storage chip based on this data, and analyzing the security of the storage chip in combination with a preset read and write operation times threshold, a large number of read and write operation tests can be reduced, thereby improving the test efficiency of the security of the storage chip.

[0040] (2) By comparing the read and write anomaly coefficient y of the a-th storage chip during the i-th read and write operation ai with the preset read and write anomaly coefficient threshold y 01 , an accurate judgment can be made on whether there is a read and write anomaly in the a-th storage chip during the read and write operation. When there is a read and write anomaly in the storage chip, it will lead to a decrease in system stability, resulting in the data in the chip being read or leaked in an unexpected way. Therefore, through this comparison method, the abnormal read and write operations can be marked, and diversified data support can be provided for subsequent judgment of the stability of the read and write operations of the a-th storage chip in a read and write test.

[0041] (3) By comparing the read and write anomaly coefficient fluctuation values of all storage chips in a read and write test with the preset fluctuation value threshold respectively, a judgment can be made on the read and write stability of each storage chip, and further judgment can be made on whether there will be a situation of read and write anomaly of the storage chip when used under all monitored environments established by this type of storage chip. If there is such a situation, it means that this type of storage chip cannot adapt to different monitored environments, that is, it represents that the adaptability of this type of storage chip is poor. By setting like this, a judgment can be made on whether this type of storage chip can adapt to different temperature monitored environments, and a preliminary analysis can be made on the security index of this type of storage chip.

[0042] (4) By comparing the estimated read and write times p of all storage chips a with the preset read and write times threshold p respectively 01, Through this comparison method, the read / write lifetimes of all storage chips in their corresponding monitoring environments during a single read / write test can be analyzed. By combining the above analysis results, the environmental adaptability of this type of storage chip can be analyzed, and further analysis can be carried out on the high or low safety indicators of this type of storage chip. Moreover, since this data is obtained based on diversified data calculations, it not only has high reliability but also does not require a large amount of time to conduct a large number of read / write tests, thereby improving the test efficiency of the safety of storage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described below with reference to the accompanying drawings.

[0044] Figure 1 is a flowchart of the steps of a test algorithm for screening the safety indicators of storage chips in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] Please refer to Figure 1 As shown, in one embodiment, the present application provides a test algorithm for screening the safety indicators of storage chips, and the algorithm includes the following steps:

[0047] S1: First, set multiple test environments with different temperatures at a fixed temperature difference interval, and place each storage chip of the same type in each of the test environments for read / write tests;

[0048] S2: Collect the real-time read / write data generated by each storage chip during each read / write operation through a data acquisition module;

[0049] S3: By combining a number of collected read / write data, map them one by one to the read / write anomaly coefficients of each storage chip during the corresponding read / write operation, and calculate the read / write anomaly coefficients;

[0050] S4: By combining the read / write anomaly coefficients of each storage chip during a single read / write operation, analyze whether there is an anomaly in this read / write operation and mark the abnormal read / write operations;

[0051] S5: By combining the test data of all storage chips in a single read / write test, calculate the fluctuation value of the read / write anomaly coefficient of each storage chip in the single read / write test, and analyze the read / write stability of each storage chip based on this data;

[0052] S6: Estimate the read / write times of each memory chip by combining the fluctuations of the read / write anomaly coefficients of each memory chip in a single read / write test, analyze the security of each memory chip by combining a preset threshold of read / write operation times, and screen the memory chips according to the analysis results;

[0053] Through the above technical solution, this embodiment provides a test algorithm for screening the security indicators of memory chips. The algorithm includes the following steps: First, set multiple test environments with different temperatures at fixed temperature difference intervals, and place each memory chip of the same type in each of the test environments for read / write tests. Then, use a data acquisition module to collect the read / write data of each read / write operation of all memory chips in real time during the read / write tests, and map the read / write data of any one read / write operation of each memory chip to the read / write anomaly coefficient of each memory chip during the corresponding read / write operation, and calculate the read / write anomaly coefficient. Then, combine the read / write anomaly coefficients of each memory chip during a single read / write operation to analyze whether there is an anomaly in this read / write operation, mark the abnormal read / write operations, and calculate the fluctuation value of the read / write anomaly coefficient of each memory chip in a single read / write test by combining the test data of each memory chip in the single read / write test, and analyze the read / write stability of each memory chip based on this data. Finally, estimate the read / write times of each memory chip by combining the fluctuation values of the read / write anomaly coefficients of each memory chip in a single read / write test, analyze the security of the memory chips by combining a preset threshold of read / write operation times, and finally screen different types of memory chips by combining the security analysis results of different types of memory chips to ensure the quality of the memory chips;

[0054] Through the above technical solution, by combining the read / write data of each read / write operation of a memory chip during the read / write test, the read / write anomaly coefficient of each memory chip during this read / write operation can be calculated. This data reflects whether the read / write state of the memory chip in a single read / write operation in different test environments is qualified. Then, analyze the read / write stability by combining the test data of each memory chip in a single read / write test, estimate the read / write times of each memory chip based on this data, and analyze the security of the memory chips by combining a preset threshold of read / write operation times, so as to reduce a large number of read / write operation tests and improve the test efficiency of the security of memory chips;

[0055] Moreover, by calculating the read / write anomaly coefficients of each storage chip during this read / write operation, the status of the storage chip during each read / write operation in different test environments can be analyzed, thereby realizing the environmental adaptability monitoring of the storage chip. By combining the test data of each storage chip in a single read / write test and calculating the fluctuation value of the read / write anomaly coefficient of each storage chip in the single read / write test, the read / write stability of the storage chip in different test environments during the single read / write test can be judged, and a preliminary judgment on the environmental adaptability of the storage chip can be further made. And the two sets of data can provide diversified data support for estimating the read / write times of each storage chip subsequently, thereby improving the accuracy of the estimation result.

[0056] The calculation process in S3 includes:

[0057] Through the formula Calculate the read / write anomaly coefficient y of the a-th storage chip during the i-th read / write operation ai ;

[0058] Among them, a is any one of the test storage chips, and each storage chip corresponds to a monitoring environment. i is any one of the read / write operations in a single read / write test. dq ai Is the reading time of the a-th storage chip during the i-th read / write operation, dq y Is the preset reading time, xr ai Is the writing time of the a-th storage chip during the i-th read / write operation, xr y Is the preset writing time, sj y Is the preset total duration of a single read / write operation, dx ai The number of read / write errors of the a-th storage chip during the i-th read / write operation, dx y Is the preset number of read / write errors, dx b Is the standard value of dx ai The above standard value can be selected and set according to the allowable error in the empirical data, xp y Is the preset storage space size of the storage chip, xp ai Is the storage space size of the a-th storage chip after the i-th read / write operation is completed, f z (x) is a defined function. If f z (x)≥1, let f z (x) = x. If f z [[ID=,43]](x)<x, then let f z (x) = 1;

[0059] Through the above technical solution, this example provides the read / write anomaly coefficient y of the a-th storage chip during the i-th read / write operation ai , which can be obtained through the formula It is calculated that obviously, when the reading time and writing time of the a-th storage chip during the i-th reading and writing operation are longer, the number of reading and writing errors of the a-th storage chip during the i-th reading and writing operation is more, and the storage space of the a-th storage chip after the i-th reading and writing operation is smaller, then the reading and writing anomaly coefficient y of the a-th storage chip during the i-th reading and writing operation ai will be larger, indicating that when the a-th storage chip performs reading and writing operations in its corresponding test environment, its reading and writing performance is abnormal, that is, it represents poor environmental adaptability of the storage chip in a short time. On the contrary, when the reading time and writing time of the a-th storage chip during the i-th reading and writing operation are shorter, the number of reading and writing errors of the a-th storage chip during the i-th reading and writing operation is less, and the storage space of the a-th storage chip after the i-th reading and writing operation is larger, then the reading and writing anomaly coefficient y of the a-th storage chip during the i-th reading and writing operation ai will be smaller, indicating that when the a-th storage chip performs reading and writing operations in its corresponding test environment, its reading and writing performance is normal, that is, it represents good environmental adaptability of the storage chip in a short time;

[0060] Through this calculation method, it can provide accurate data for subsequent judgment of whether there are abnormalities in the reading and writing operations of each storage chip. And based on the high-quality data obtained through diversified data fusion, it can improve the reliability of the data, thereby improving the accuracy of the judgment result.

[0061] The comparison process in S4 includes: <www.

[0062] By comparing the reading and writing anomaly coefficient y of the a-th storage chip during the i-th reading and writing operation ai with the preset reading and writing anomaly coefficient threshold y 01 for comparison;

[0063] If y ai ≥y 01 , it is judged that the a-th storage chip has reading and writing anomalies during this reading and writing operation, and this reading and writing operation is marked;

[0064] If y ai <y 01 , it is judged that the a-th storage chip has no reading and writing anomalies during this reading and writing operation, and this reading and writing operation does not need to be marked;

[0065] Through the above technical solution, in this example, the reading and writing anomaly coefficient y of the a-th storage chip during the i-th reading and writing operation ai is compared with the preset reading and writing anomaly coefficient threshold y 01By making a comparison, it is possible to accurately determine whether there are any read / write abnormalities in the a-th storage chip during this read / write operation. When there are read / write abnormalities in the storage chip, it will lead to a decrease in system stability, resulting in the data in the chip being read or leaked in an unexpected manner. Therefore, through this comparison method, abnormal read / write operations can be marked, providing diversified data support for subsequent judgment of the stability of the read / write operations of the a-th storage chip in a read / write test.

[0066] The analysis process in S5 includes:

[0067] Through the formula Calculate the fluctuation value of the read / write abnormality coefficient of the a-th storage chip in a read / write test

[0068] where n is the total number of read / write operations in a read / write test, is the average value of all y ai and is the maximum value among all y ai and is the minimum value among all y ai sl a is the number of abnormal read / write operations of the a-th storage chip in a read / write test, sl y is the preset number of abnormal read / write operations, and g is a proportionality coefficient set by empirical fitting;

[0069] Through the above technical solution, this example provides the fluctuation value of the read / write abnormality coefficient of the a-th storage chip in a read / write test which can be calculated through the formula Through the above technical solution, this data reflects the read / write stability of the storage chip in a read / write test in different test environments. By judging the read / write stability of the storage chip in a read / write test in different test environments, the environmental adaptability of the storage chip can be further judged, and it can be used as diversified high-quality fusion data to provide additional data support for subsequent estimation of the read / write times of the a-th storage chip to ensure the accuracy of the estimation result.

[0070] The analysis process in S5 also includes:

[0071] By comparing the fluctuation values of the read / write abnormality coefficients of all storage chips in a read / write test with the preset fluctuation value threshold respectively;

[0072] If any is greater than or equal to Determining that the read / write stability of the storage chip is poor means that when the storage chip is used in a monitoring environment based on this storage chip, the read / write of the storage chip is prone to anomalies, indicating that this type of storage chip cannot adapt to different monitoring environments, and it is determined that the security of this type of storage chip is poor;

[0073] If all are less than Determining that the read / write stability of all storage chips is good means that when used in all monitoring environments established by this type of storage chip, the read / write of the storage chip is not prone to anomalies, indicating that this type of storage chip can adapt to different monitoring environments, and it is determined that the security of this type of storage chip is high;

[0074] Through the above technical solution, in this example, the fluctuation values of the read / write anomaly coefficients of all storage chips in a single read / write test are respectively compared with the preset fluctuation value threshold to determine the read / write stability of each storage chip, and further determine whether there will be anomalies in the read / write of the storage chip when used in all monitoring environments established by this type of storage chip. If such a situation exists, it indicates that this type of storage chip cannot adapt to different monitoring environments, that is, it represents that the adaptability of this type of storage chip is poor. By setting it like this, it can be determined whether this type of storage chip can adapt to different temperature monitoring environments, and a preliminary analysis of the security index of this type of storage chip can be carried out.

[0075] The analysis process in S6 includes:

[0076] By combining the test data of the a-th storage chip in a single read / write test, establish the read / write anomaly coefficient change curve w a (t)

[0077] Through the formula calculate the estimated read / write times p of the a-th storage chip a ;

[0078] where, t1 is the first read / write operation in a single read / write test, t2 is the last read / write operation in a single read / write test, and f k is the adjustment coefficient comparison table function, and is obtained based on the influence degree of the value range of the value in the empirical data on the read / write times of the storage chip according to the test data;

[0079] Through the above technical solution, this example provides the estimated read / write times p of the a-th storage chip a , which can be calculated through the formula Calculated. Through this calculation method, by combining the change amount of the read / write exception coefficient of the a-th storage chip in a read / write test with the fluctuation value of the read / write exception coefficient of the a-th storage chip in a read / write test after that, it is possible to estimate the read / write times of the a-th storage chip by combining diversified data, thereby improving the accuracy of the calculation result. Then, by using the estimated read / write times p of the a-th storage chip obtained through calculation a and comparing it with the preset read / write times threshold, it is possible to judge the read / write life of each storage chip, and thus judge the environmental adaptability of the storage chip.

[0080] The analysis process in S6 also includes:

[0081] By comparing the estimated read / write times p of all storage chips a with the preset read / write times threshold respectively 01 ;

[0082] If any p a is less than or equal to p 01 , it is judged that the read / write life of this storage chip in its corresponding monitoring environment is lower than the threshold, which means that the environmental adaptability of this type of storage chip is poor, and it is judged that the safety index of this type of storage chip is poor;

[0083] If all p a are greater than p 01 , it is judged that the read / write life of all storage chips in their corresponding monitoring environments is higher than the threshold, which means that the environmental adaptability of this type of storage chip is strong, and it is judged that the safety index of this type of storage chip is high;

[0084] Through the above technical solution, in this example, by comparing the estimated read / write times p of all storage chips a with the preset read / write times threshold respectively 01 , through this comparison method, it is possible to analyze the read / write life of all storage chips in their corresponding monitoring environments in a read / write test. By combining the above analysis results, it is possible to analyze the environmental adaptability of this type of storage chip, and further analyze the level of the safety index of this type of storage chip. And because this data is obtained based on diversified data, it not only has high reliability, but also does not require a large amount of time to do a large number of read / write tests, thereby improving the test efficiency of the storage chip safety.

[0085] The maximum temperature value of all monitoring environments in S1 does not exceed 85°C, and the minimum temperature value is not lower than -45°C;

[0086] Through the above technical solutions, this example provides the monitoring of the maximum and minimum temperatures of the environment. By setting it in this way, not only can the environmental adaptability of the storage chip under normal use conditions be analyzed, but also the environmental adaptability of the storage chip under extremely high or low temperature use environments can be analyzed, thereby improving the sensitivity of the security test of the storage chip and improving the quality control of the storage chip.

[0087] The above has described an embodiment of the present invention in detail, but the content described is only a preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the application of the present invention should still fall within the scope covered by the patent of the present invention.

Claims

1. A test algorithm for screening the security indicators of storage chips, characterized in that, The algorithm includes the following steps: S1: First, set multiple test environments with different temperatures at fixed temperature difference intervals, and place each storage chip of the same type under each of the test environments for read-write tests; S2: Collect the real-time read-write data generated by each of the storage chips in each read-write operation through a data acquisition module; S3: By combining a number of the collected read-write data, map them one by one to the read-write anomaly coefficients of each storage chip during the corresponding read-write operation, and calculate the read-write anomaly coefficients; S4: By combining the read-write anomaly coefficients of each storage chip during a read-write operation, analyze whether there is an anomaly in this read-write operation, and mark the abnormal read-write operations; S5: By combining the test data of all storage chips in a read-write test, calculate the fluctuation value of the read-write anomaly coefficients of each storage chip in a read-write test, and analyze the read-write stability of each storage chip based on this data; S6: By combining the fluctuation values of the read-write anomaly coefficients of each storage chip in a read-write test, estimate the number of read-write operations of each storage chip, analyze the security of the storage chip in combination with a preset threshold value of the number of read-write operations, and screen the storage chips according to the analysis results.

2. The test algorithm for screening the security indicators of a storage chip according to claim 1, characterized in that, The calculation process in S3 includes: Obtained through the formula Calculate the read / write anomaly coefficient y of the a-th storage chip during the i-th read / write operation ai ; Among them, a is any one of the test memory chips, and each memory chip corresponds to a monitoring environment. i is any read / write operation in a read / write test, and dq ai is the read time of the a-th memory chip during the i-th read / write operation, dq y is the preset read time, xr ai is the write time of the a-th memory chip during the i-th read / write operation, xr y is the preset write time, sj y is the preset total duration of a read / write operation, dx ai The number of read / write errors of the a-th memory chip during the i-th read / write operation, dx y is the preset number of read / write errors, dx b is dx ai the standard value of, xp y is the preset storage space size of the memory chip, xp ai is the storage space size of the a-th memory chip after the i-th read / write operation is completed, f z (x) is a defined function. If f z (x) ≥ 1, let f z (x) = x. If f z (x) < x, then let f z (x) = 1.

3. The test algorithm for screening the security indicators of a storage chip according to claim 2, wherein, The comparison process in S4 includes: By comparing the read / write anomaly coefficient y of the a-th storage chip during the i-th read / write operation ai with the preset read / write anomaly coefficient threshold y 01 for comparison; If y ai ≥ y 01 , it is determined that there is a read / write anomaly in the a-th memory chip during this read / write operation, and this read / write operation is marked; If y ai <y 01 , it is determined that there is no read / write anomaly in the a-th memory chip during this read / write operation, and it is not necessary to label this read / write operation.

4. The test algorithm for screening the security indicators of a storage chip according to claim 3, characterized in that, The analysis process in S5 includes: Obtained through the formula Calculate the fluctuation value θ of the read / write anomaly coefficient of the a-th storage chip in a read / write test a ; where n is the total number of read / write operations in a single read / write test, is the average value of all y ai , is the maximum value among all y ai , is the minimum value among all y ai , sl a is the number of abnormal read / write operations of the a-th memory chip in a single read / write test, sl y is the preset number of abnormal read / write operations, and g is a proportionality coefficient set by empirical fitting.

5. A test algorithm for screening the security indicators of a storage chip according to claim 4, characterized in that, The analysis process in S5 further includes: By comparing the fluctuation value θ of the read / write anomaly coefficient of all memory chips in a single read / write test a with the preset fluctuation value threshold θ 01 respectively; If any θ a is greater than or equal to θ 01 , it is determined that the read / write stability of the storage chip is poor, which means that when the storage chip is used in a monitoring environment based on this storage chip, the read / write of the storage chip is likely to be abnormal, indicating that this type of storage chip cannot adapt to different monitoring environments, and it is determined that the security of this type of storage chip is poor; If all θ a are less than θ 01 , it is determined that the read / write stability of all storage chips is good, which means that when used in all monitoring environments established by this type of storage chip, the read / write of the storage chip is not likely to be abnormal, indicating that this type of storage chip can adapt to different monitoring environments and it is determined that the security of this type of storage chip is high.

6. The test algorithm for screening the security indicators of a storage chip according to claim 5, characterized in that, The analysis process in S6 includes: By combining the test data of the a-th memory chip in a single read-write test, establish the change curve w a (t) of the read-write anomaly coefficient of the a-th memory chip Obtained through the formula Calculate the estimated read / write times p of the a-th storage chip a ; Among them, t1 is the first read / write operation in a read / write test, t2 is the last read / write operation in a read / write test, and f k is the adjustment coefficient comparison table function, and is obtained based on test data according to the influence degree of the value range of the numerical values in the empirical data on the number of read / write operations of the storage chip.

7. A test algorithm for screening the security indicators of a storage chip according to claim 6, characterized in that, The analysis process in S6 further includes: By comparing the estimated number of read / write cycles p of all storage chips a with a preset read / write cycle threshold respectively 01 ; If any p a is less than or equal to p 01 , it is determined that the read / write lifespan of the storage chip in its corresponding monitoring environment is lower than the threshold, which means that the environmental adaptability of this type of storage chip is poor, and it is determined that the security index of this type of storage chip is poor; If all p a are greater than p 01 , it is determined that the read / write lifetimes of all storage chips in their respective monitoring environments are higher than the threshold, which means that the environmental adaptability of this type of storage chip is strong, and it is determined that the security index of this type of storage chip is high.

8. The test algorithm for screening the security indicators of a storage chip according to claim 1, characterized in that, The maximum temperature value of all the monitoring environments in S1 does not exceed 85°C, and the minimum temperature value is not lower than -45°C.

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