High-precision bonding chip manufacturing method and high-precision bonding chip

Abstract

The invention belongs to the field of semiconductor device manufacturing, and particularly relates to a high-precision bonding chip manufacturing method and a high-precision bonding chip. The method comprises the following steps: carrying out hybrid bonding on a plurality of first bare chips and a second wafer and completing annealing treatment to form a first bonded chip assembly; depositing a first silicon oxide layer from one side of the plurality of first bare chips in a manner that gaps between the bare chips are filled and the height exceeds the outer surfaces of the core particles; turning over the first bonding chip assembly up and down so as to enable the first bare chip to be located at the lower part and the second wafer to be located at the upper part; and reducing the thickness of the second wafer, and forming a conductive silicon through hole which is used for being interconnected with an external high-density metal wire. According to the invention, the improvement of the electrical properties of the final stacked core particles is realized only through the optimization of the existing technological process.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device manufacturing, and particularly relates to a method for manufacturing a high-precision bonded chip and a high-precision bonded chip. Background Art

[0002] In the traditional method for manufacturing high-precision bonded chips, the bonding quality is relatively poor. Due to the inevitable cutting of the bare chips, unevenness will occur at the edges, and particle contamination is more likely to occur at the bonding interface, resulting in unevenness at the bonding interface. In addition, compared with the relatively mature wafer-to-wafer hybrid bonding process, the warpage control of the bare chips is worse, and factors such as contamination caused by Q-time control and machine capabilities limit the bonding interface to be uneven. For subsequent high-precision metal wiring, the damascene copper process needs to be adopted. Among them, due to the deviation of the position of the bare chip from the original designed position in high-precision lithography alignment, the lithography process cannot be accurately carried out. Similarly, in the plasma etching process, especially in the etching process of high aspect ratio such as TSV, due to the uneven bonding height of the etched film thickness, the etching depth is inconsistent during the etching process, resulting in an unsatisfactory final etching effect. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention provides a method for manufacturing a high-precision bonded chip, including the following steps: Step S1, performing hybrid bonding on a plurality of first bare chips formed by cutting from a first wafer and a second wafer, and completing the annealing process to form a first bonded chip combination; Step S2, depositing a first silicon oxide layer on the first bonded chip combination from one side of the plurality of first bare chips in a manner that fills the gaps between the bare chips and has a height exceeding the outer surface of the die on the plurality of first bare chips; Step S3, turning the first bonded chip combination upside down, so that the plurality of first bare chips deposited with the first silicon oxide layer are located below, and the second wafer is located above; Step S4, thinning the thickness of the second wafer, and forming conductive silicon through holes for interconnecting with external high-density metal wires in the thinned second wafer.

[0004] In addition, preferably, in the chip manufacturing method of the present invention, after Step S2, it further includes: Step 21, leveling the surface of the first silicon oxide layer through a polishing process and / or a chemical mechanical polishing process.

[0005] In addition, preferably, in the chip manufacturing method of the present invention, it further includes: Step S5, performing hybrid bonding on the second wafer in the first bonded chip combination and a plurality of third bare chips formed by cutting from a third wafer, and completing the annealing process to form a second bonded chip combination.

[0006] In addition, preferably, in the chip manufacturing method of the present invention, it further includes: step S6, depositing a second silicon oxide layer on the second bonded chip assembly from one side of the plurality of third dies in such a manner that the gaps between the dies are filled and the height exceeds the outer surface of the cores on the plurality of third dies.

[0007] In addition, preferably, in the chip manufacturing method of the present invention, after step S6, it further includes: step 61, planarizing the surface of the second silicon oxide layer through a polishing process and / or a chemical mechanical polishing process.

[0008] In addition, preferably, the present invention also provides a high-precision bonded chip obtained by using the chip manufacturing method according to any one of claims 1 to 5.

[0009] By using the present invention, under the existing completion effect of die-to-wafer hybrid bonding, without imposing higher requirements on die-to-wafer hybrid bonding, only by using the existing processes and optimizing the process flow, subsequent process flows such as Si thinning, lithography, etching, and TSV fabrication can be completed with high quality. Thus, after die-to-wafer hybrid bonding, high-precision and high-density electrical interconnection processes such as TSV fabrication, copper damascene process, and aluminum metal pad process can be realized, and combined with the high-density electrical interconnection between the hybrid-bonded chips, the electrical performance of the final stacked cores is significantly improved. Description of the Drawings

[0010] Figure 1 is a schematic diagram of the collective die-to-wafer hybrid bonding process flow in the high-precision bonded chip manufacturing method according to an embodiment of the present invention.

[0011] Figure 2 is a schematic diagram of the single die-to-wafer hybrid bonding process flow in the high-precision bonded chip manufacturing method according to an embodiment of the present invention.

[0012] Figure 3 is a schematic diagram of the subsequent process flow of chip-to-wafer hybrid bonding in the high-precision bonded chip manufacturing method according to an embodiment of the present invention.

[0013] Figure 4 is a schematic diagram of the influence of uneven chip-to-wafer hybrid bonding height on lithography and etching in the high-precision bonded chip manufacturing method according to an embodiment of the present invention.

[0014] Figure 5 is a schematic diagram of the TSV morphology defect caused by uneven die Si thinning thickness in the high-precision bonded chip manufacturing method according to an embodiment of the present invention.

[0015] Figure 6It is a schematic diagram of the process flow in the high-precision bonding chip manufacturing method according to an embodiment of the present invention.

[0016] Figure 7 It is a detailed schematic diagram of the high-precision bonding chip manufacturing method according to an embodiment of the present invention.

[0017] Figure 8 It is a schematic diagram of the CIS three-layer stacking process flow in the high-precision bonding chip manufacturing method according to an embodiment of the present invention.

[0018] Figure 9 It is a schematic diagram of the CIS three-layer stacking process flow in the high-precision bonding chip manufacturing method according to an embodiment of the present invention. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Other embodiments or variant embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application all fall within the scope of protection of the present application.

[0020] There are mainly two technical routes for die-to-wafer hybrid bonding, namely collective die-to-wafer hybrid bonding and direct die-to-wafer hybrid bonding.

[0021] The main process flows of the two are briefly described below.

[0022] Collective die-to-wafer hybrid bonding: The main process flow is to cut the wafer (Wafer). Align and bond the back of the cut dielets with the carrier wafer (Carrier Wafer). At this time, a new wafer is formed. Then, processes such as cleaning and plasma activation are performed on this new wafer. Next, bond this combined wafer with another wafer (Wafer). This step is similar to the wafer-to-wafer hybrid bonding process. Subsequently, the carrier wafer is removed, thus completing the process of collective die-to-wafer hybrid bonding. The schematic diagram of the process flow is as Figure 1 shown.

[0023] Die-to-Wafer Hybrid Bonding: The main process flow is to cut the wafer. Then, these dielets are subjected to processes such as plasma activation and cleaning. Next, each dielet is picked up, aligned, and bonded to another wafer. This step is repeated to complete the die-to-wafer hybrid bonding process for all dielets. The schematic diagram of the process flow is as shown in Figure 2 shown.

[0024] Whether it is collective die-to-wafer hybrid bonding or single-die-to-wafer hybrid bonding, a stacked structure of wafer + die is obtained. Subsequently, high-density electrical interconnection is required to lead out the electricity (which will be achieved through the copper damascene process). First, it is necessary to continue with the subsequent high-density annealing process to form more chemical bonds between the dielectric layers and improve the bonding strength between the chip and the wafer. At the same time, the Cu dishing defect expands due to heat, and electrical connections are formed between the chips. Subsequently, the gaps between the dielets are filled using chemical vapor deposition, and then chemical mechanical polishing is performed to flatten the surface and thin the dielets. TSV, copper damascene metal interconnection process, aluminum metal pad fabrication, etc. are continued on the back of the chip to lead out the electricity of the stacked dielets. The schematic diagram of the process is as shown in Figure 3 shown, and the schematic diagram of the problem details (generated particles, also known as "particle") is as shown in Figure 4 shown.

[0025] Influence of post-bonding processes on bonding: After hybrid bonding, a high-temperature annealing process will be carried out. Due to the small mass of the die, during the annealing process, the protrusion of the copper bonding pad (Cu Bonding Pad) will cause the die to have a small displacement, and there will be a small lifting phenomenon. At the same time, for the subsequent ultra-thick silicon oxide filling the gap (the thickness needs to be at least greater than the thickness of the dielet), due to the stress mismatch between the filled material silicon dioxide and silicon, after deposition, it will undergo some high-temperature processes, and the die will be extruded by the silicon dioxide in the gap, and there will also be a certain degree of displacement (similar to the first point). In summary, it will lead to inconsistent die heights, thus triggering a series of problems encountered in the above lithography and etching.

[0026] During the process of thinning the die, due to the uneven bonding interface, the thickness of the Si after thinning is also uneven, which significantly increases the difficulty of subsequent TSV step-by-step etching. During the TSV Si Bosch etching process, some positions have been etched to the bottom, while some have not, which poses a great challenge to the process consistency and will reduce the final completion effect of the TSV. The schematic diagram is as shown in Figure 5 shown.

[0027] The root cause of this problem currently is the process issue of die-to-wafer hybrid bonding, which makes it difficult for the bonding interface to reach the high-quality level of wafer-to-wafer hybrid bonding. To solve the problems in this regard, the single-point process and process flow of die-to-wafer hybrid bonding are correspondingly optimized, so as to improve the surface flatness of the chip after bonding, and further enhance the precision of subsequent processes such as lithography and etching after die-to-wafer hybrid bonding. However, this requires process adjustment and also the support of hardware manufacturers, so the overall difficulty is huge and it is difficult to achieve in a short time. Even if it can be achieved, the cost is also huge. Therefore, there is an urgent need for a technical solution that can improve the process precision of lithography, etching, etc. in the subsequent TSV, copper damascene, and aluminum metal pad manufacturing after die-to-wafer hybrid bonding only by using the existing technical capabilities.

[0028] The present invention realizes the fabrication of a high-precision electrical interconnection process after die-to-wafer hybrid bonding, including TSV process, copper damascene process, aluminum metal pad process, etc. by optimizing the process flow and using the existing process technology capabilities of die-to-wafer hybrid bonding. This can maximize the advantages of hybrid bonding for high-density electrical signal interconnection and maximize the electrical performance of the packaged chip.

[0029] The existing process is to thin the die side after die-to-wafer hybrid bonding, form TSV, and complete processes such as copper damascene and aluminum metal pad. While the present invention performs the above-mentioned related processes on the wafer side after bonding, thus well realizing the implementation of high-precision processes such as lithography and etching described above.

[0030] By optimizing the existing related process flow, the requirements for finally performing related processes on the wafer side are met.

[0031] The existing solution is to connect the electricity from the die side through the processing of the die side. This solution is to connect the electricity from the wafer side through the processing of the wafer side.

[0032] The complete technical implementation solution of the present invention

[0033] The process flow of the present invention is described in detail as follows:

[0034] Use the existing process to cut the wafer to form dies, then perform the die-to-wafer hybrid bonding process on the dies and wafers, and perform annealing to enhance the bonding strength between the dies and wafers and realize the electrical connection between the chips (the process here is the same as the original process).

[0035] Deposit a thick silicon oxide film layer to fill the gaps between the dies and be higher than the die chips by a part.

[0036] Use processes such as grinding and chemical mechanical polishing to grind the deposited silicon oxide flat.

[0037] Place the die below and the wafer above, and perform subsequent thinning, TSV, copper damascene, aluminum metal pads, etc. on the wafer part. Instead of the existing solution that conducts electrical interconnection through one side of the die, the bonded chips are electrically connected through high-density metal wire interconnection on the wafer part.

[0038] The process flow schematic diagram is as Figure 6 shown.

[0039] Subsequent circuit fabrication is continued on the stacked chips (die or wafer) above. To achieve high-density circuit interconnection, the commonly used damascene process in the Fab is usually adopted, and the TSV fabrication is also a similar damascene process. Lithography and etching are two key process steps among them. First is lithography. Due to the bonding of the die in the original process, the surface of the die is uneven. Therefore, in the lithography alignment process, there will be a situation where the OVL deviation is too large, which will ultimately lead to a decrease in the overall process accuracy. In addition, during the etching process, due to the uneven horizontal height of the die, during the etching process, there will be a situation where some areas are etched and some areas are not etched, affecting the final etching morphology. At the same time, due to the deviation of the lithography process, there will be a situation where the landing of the pad to the metal is inaccurate in the final etching (this description was in Figure 4 ). However, after adopting this solution, after the hybrid bonding of the die to the wafer, ultra-thick silicon dioxide is used to fill the gaps between the dies, and it is also a certain thickness higher than the die. Subsequently, processes such as polishing and chemical mechanical polishing are carried out to planarize and level the silicon dioxide, and the wafer is already in a flat state. Therefore, whether it is aligning the lithography with the metal marks on the wafer or etching, the problems introduced by the uneven die in the existing process will not occur. High-precision lithography, etching and other damascene processes can be carried out. At the same time, the thickness of the thinned Si is consistent, and the uniformity of the TSV morphology in different regions is also better. The detailed schematic diagram is as Figure 7 shown.

[0040] After flipping the chip over, during the process, the electrostatic chuck directly contacts the silicon dioxide material of the stacked dielets. In the conventional process, the electrostatic chuck of the machine tool contacts the silicon material. To meet the requirements of Mix Run with common structures in the Fab or reduce the workload of debugging the machine tool due to the change of materials. After the planarization of the silicon dioxide surface, a layer of silicon material can be formed on the silicon dioxide surface by using a furnace tube process. In this way, when the wafer is flipped over for subsequent processes, the electrostatic chuck contacts the conventional Si material, which is the same as the conventional wafer.

[0041] After adopting the process of the present invention, the process of hybrid bonding of 1 die + 1 wafer is completed. Only the electrical property is led out from the wafer end. Therefore, compared with the original process, only the order of the die and the wafer in the original process needs to be swapped, then the process of this patent is adopted, and then the stacked 1 die + 1 wafer is cut to obtain stacked die chips that are the same as those of the existing process.

[0042] After adopting this solution, since the surface of the wafer is very flat, the related processes such as lithography, etching, Si thinning, TSV, etc. described above achieve better effects. Therefore, adopting this solution can significantly improve the electrical interconnection density after die-to-wafer hybrid bonding, and a more refined circuit structure can be fabricated, thereby improving the electrical performance of the stacked chips.

[0043] In the existing three-layer wafer stacking process similar to CIS (CMOS image sensor), when the die sizes of the logic processing chip, the memory processing chip, and the pixel chip are different, the die-to-wafer hybrid bonding method is used for stacking. The existing solution is to first cut the memory wafer into dies, and then bond the dies to the logic wafer by the hybrid bonding method. Then, circuit fabrication is continued on the memory chip, and the pixel chip is stacked on the memory chip by the die-to-wafer hybrid bonding method to complete the whole process. The process flow of this solution is to first cut the logic processing chip wafer into dies and then bond them to the memory processing wafer, and then perform the fabrication of Damascus processes such as TSV and hybrid bonding pads on the memory processing wafer, and then bond it to the pixel chip as a wafer to finally complete the stacking of the three-layer chips.

[0044] The process flow of three-layer die-to-wafer hybrid bonding in the existing process can actually only meet the high-precision production of the first die-to-wafer hybrid bonding process. However, subsequent circuit interconnections and the second die-to-wafer hybrid bonding will not be completed with high quality. The advantage of this solution is that the bonding between the first die and the wafer not only uses high-density interconnection of hybrid bonding between the die and the wafer, but also subsequent electrical interconnections can use the high-density damascene process. At the same time, the process flow of the second die-to-wafer hybrid bonding will not be affected by the first die-to-wafer hybrid bonding process at all, but the precision of the related processes after the second die-to-wafer hybrid bonding will be relatively reduced. This characteristic is very suitable for the process production of CIS because the chip stacking order from bottom to top is a logic processing chip, a memory processing chip, and a pixel chip. Among them, the electrical interconnection density of the logic processing chip and the memory processing chip is relatively high, and Damascus process is also required for the two chips to continue with the related processes. The interconnection density of the pixel chip is relatively low. After bonding with the hybrid bonding process, only thinning is required subsequently, and large-scale devices such as color filters and on-chip lenses are formed. Compared with the damascene process, the precision is a little lower. Therefore, it is very suitable to adopt the related process flow of the present invention.

[0045] Schematic diagrams of the process flows for fabricating 3-layer CIS chips using the existing process and the process of the present invention are as Figure 8 , Figure 9 shown.

[0046] According to the high-precision bonding chip manufacturing method of the embodiment of the present invention, the advantages are as follows:

[0047] Under the completion effect of the existing die-to-wafer hybrid bonding, without putting forward higher requirements for die-to-wafer hybrid bonding, using the existing process, through the optimization of the process flow, subsequent process flows such as Si thinning, lithography, etching, and TSV fabrication are completed with high quality. Thus, after die-to-wafer hybrid bonding, high-precision and high-density electrical interconnection processes such as TSV fabrication, copper damascene process, and aluminum metal pad process are realized, and the high-density electrical interconnection between chips with hybrid bonding is matched, significantly improving the electrical performance of the final stacked dielets.

[0048] The existing process continues with high-density electrical interconnection from the die after bonding. This solution conducts the related processes from the wafer. Just replace the die in the existing process with the wafer in this solution and the wafer with the die. The final implementation effect is the same as that of the existing solution. At the same time, there is no investment cost for new production equipment in the process adopted, and the process difficulty will not be increased additionally. The number of process steps is also almost the same as that of the existing process, so almost no additional cost is increased. In summary, it can be mass-produced on a large scale.

[0049] The present invention can also grow a layer of Si on the silica on one side of the die through a furnace tube process to maintain consistency with the conventional wafer material, thereby further reducing various workloads such as machine debugging caused by inconsistent contact materials with the electrostatic chuck, and maximizing the realization of the mixed operation (Mix Run) with the existing conventional wafers.

[0050] The present invention can be applied to the CIS three-layer chip stacking process, and the structural order is a logic processing chip, a memory processing chip, and a pixel chip. When bonding, a die-to-wafer hybrid bonding process flow is adopted, where the logic chip is a die and the memory chip is a wafer. The process of die-to-wafer hybrid bonding of the logic chip die and the memory chip wafer is carried out for the first time. Next, subsequent processes such as through-silicon vias (TSVs), damascene electrical interconnections, hybrid bonding conductive vias / pads, pixel chip thinning, color filters, and large-scale devices such as on-chip lenses are carried out on the memory wafer. The advantage is that the process implementation effect after bonding the logic processing chip and the memory processing chip is maximally improved, and at the same time, the influence of the first die-to-wafer hybrid bonding process (logic processing chip and memory processing chip) on the second die-to-wafer hybrid bonding process (logic processing chip + memory processing chip and pixel chip) in the existing process is avoided. After adopting this patent, the final implementation effect of die-to-wafer hybrid bonding of the CIS three-layer chip can be significantly improved.

[0051] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0052] Each embodiment in this specification is described in a related manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments.

[0053] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

[0054] The above embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation manner of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A method for manufacturing a high-precision bonded chip, characterized in that, Including the following steps: Step S1: Hybrid bond multiple first dies formed by cutting from a first wafer with a second wafer and complete annealing treatment to form a first bonded chip assembly; Step S2: Deposit a first silicon oxide layer on the first bonded chip assembly from one side of the multiple first dies in a manner that fills the gaps between the dies and has a height exceeding the outer surface of the dielets on the multiple first dies; Step S3: Flip the first bonded chip assembly upside down so that the multiple first dies deposited with the first silicon oxide layer are located below and the second wafer is located above; Step S4: Thin the thickness of the second wafer and form conductive silicon vias for interconnecting with external high-density metal wires in the thinned second wafer.

2. The high-precision bonded chip manufacturing method according to claim 1, wherein After step S2, it further includes: Step 21: Planarize the surface of the first silicon oxide layer by a polishing process and / or a chemical mechanical polishing process.

3. The high-precision bonding chip manufacturing method according to claim 1 or 2, characterized in that, It further includes: Step S5: Hybrid bond the second wafer in the first bonded chip assembly with multiple third dies formed by cutting from a third wafer and complete annealing treatment to form a second bonded chip assembly.

4. The high-precision bonded chip manufacturing method according to claim 3, wherein, It further includes: Step S6: Deposit a second silicon oxide layer on the second bonded chip assembly from one side of the multiple third dies in a manner that fills the gaps between the dies and has a height exceeding the outer surface of the dielets on the multiple third dies.

5. The high-precision bonding chip manufacturing method according to claim 4, wherein After step S6, it further includes: Step 61: Planarize the surface of the second silicon oxide layer by a polishing process and / or a chemical mechanical polishing process.

6. A high-precision bonded chip obtained by using the high-precision bonded chip manufacturing method according to any one of claims 1 to 5.

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