Double Damascus steel processing method

Abstract

This invention provides a double damascene process method, relating to the field of semiconductor technology. The double damascene process method includes: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer, and a patterned second hard mask layer on a substrate; forming vias stopping at the substrate surface using dry etching with the second hard mask layer; removing the second hard mask layer and the first planarization layer; forming trenches using dry etching with the first hard mask layer; removing the first hard mask layer; and forming a metal layer to fill the vias and trenches to obtain a double damascene structure. This process method ensures the continuity of the formed vias, low resistance in the subsequent metal interconnect structure formed at the bottom of the vias, and smooth flow; simultaneously, the removal of the first hard mask layer after the via formation ensures the accurate transfer of critical dimensions of the vias, improving the accuracy of critical dimensions of the subsequent metal interconnect structure formation, thereby improving chip product yield and device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a double damask process method. Background Technology

[0002] Dual damascene technology refers to a process in which trenches and vias are formed in a dielectric layer, followed by metal filling to ultimately form a metal interconnect structure. It is now widely used in the back end of line (BEOL) process of integrated circuit manufacturing.

[0003] In related technologies, a first hard mask layer (Metal Hard Mask, MHM) is generally used as the pattern transfer layer for metal lines and as a self-aligned hard mask during all-in-one etching (AIO) of vias and trenches. The first hard mask layer needs to be removed by wet etching in conjunction with a composite etch stop layer. The composite etch stop layer generally includes three etch stop layers (ESL). Correspondingly, after the all-in-one etching and removal of the first hard mask layer, the three etch stop layers at the bottom of the via topography need to be removed sequentially by wet etching, dry etching, and wet etching again, i.e., EWEW. However, the wet etching process has the risk of not being able to completely remove the etch stop layer at the bottom, resulting in high resistance or open circuits in the metal interconnect structure, thereby reducing chip product yield and device performance. Summary of the Invention

[0004] The purpose of this invention is to provide a double damask process method to solve the technical problem in related technologies where there is a risk that the bottom etch stop layer cannot be completely removed, resulting in high resistance or open circuits in the metal interconnect structure, which reduces the yield of chip products and the performance of devices.

[0005] To address the above problems, the present invention provides a double damask process method, comprising:

[0006] A dielectric layer, a patterned first hard mask layer, a first planarization layer, and a patterned second hard mask layer are sequentially formed on a substrate.

[0007] The via is formed by dry etching using the second hard mask layer, stopping at the surface of the substrate;

[0008] Remove the second hard mask layer and the first planarization layer;

[0009] The trench is formed by dry etching using the first hard mask layer;

[0010] Remove the first hard mask layer;

[0011] A metal layer is formed to fill the through-holes and the trenches to obtain a double damask structure.

[0012] Optionally, the step of forming a via stopping at the substrate surface by dry etching using the second hard mask layer includes dry etching of the dielectric layer using the second hard mask layer, wherein the process gas used includes a fluorocarbon gas and an oxygen-containing gas, and the flow rate ratio of the fluorocarbon gas to the oxygen-containing gas is 1:50 to 1:1.

[0013] Optionally, a barrier layer is formed between the substrate and the dielectric layer.

[0014] Optionally, the step of forming a via stopping at the substrate surface by dry etching using the second hard mask layer includes dry etching of the barrier layer using the second hard mask layer, wherein the process gas used includes chlorine-containing gas and nitrogen-containing gas, and the flow ratio of the chlorine-containing gas and the nitrogen-containing gas is 1:3.5 to 1:0.15.

[0015] Optionally, the chlorine-containing gas includes Cl2 and BCl3, and the flow ratio of Cl2 to BCl3 is 1:3 to 1:0.1.

[0016] Optionally, the step of removing the first hard mask layer includes:

[0017] An insulating layer is formed to fill the vias and the trenches, and to fully expose the first hard mask layer;

[0018] The first hard mask layer and the isolation layer are removed sequentially.

[0019] Optionally, the step of forming an insulating layer that fills the vias and the trenches and fully exposes the first hard mask layer includes:

[0020] A second planarization layer is formed to fill the vias and the trenches, and to cover the first hard mask layer;

[0021] The second planarization layer is etched back to form the isolation layer, so as to fully expose the first hard mask layer.

[0022] Optionally, the step of sequentially removing the first hard mask layer and the insulating layer includes:

[0023] The first hard mask layer was removed by wet etching.

[0024] The insulating layer is removed using an ashing process.

[0025] Optionally, the step of forming a metal layer to fill the through-holes and the trenches to obtain a double damask structure includes:

[0026] Fill the through holes and the trenches with metallic material;

[0027] A chemical mechanical polishing planarization process is performed to remove excess metal, form the metal layer, and obtain a double damask structure.

[0028] Optionally, a first etch stop layer is formed between the first hard mask layer and the dielectric layer;

[0029] And / or, a second etch stop layer is formed between the first planarization layer and the second hard mask layer.

[0030] In the double damask process method provided by this invention, a patterned second hard mask layer is used as the mask layer. A dry etching process is used to etch through the first planarization layer, the first hard mask layer, and the dielectric layer, stopping at the upper surface of the substrate to form a via. A patterned first hard mask layer is used as the mask layer. A dry etching process is used to etch a trench that extends downward and stops at a predetermined depth in the dielectric layer, thereby obtaining a double damask structure. In this method, no composite etch stop layer is required between the substrate and the dielectric layer. Consequently, there are no residual parts formed by incomplete removal of the composite etch stop layer, thus ensuring the continuity of the via and the low resistance and pathway of the subsequent metal interconnect structure formed at the bottom of the via. Furthermore, it can effectively reduce the film layer structure, simplify the process steps, and improve the process efficiency.

[0031] Meanwhile, the removal step of the first hard mask layer is located after the dry etching step of forming the via. During the process of forming the via using the dry etching process, the first hard mask layer can protect the dielectric layer below it, so as to ensure the accurate transmission of the critical dimensions of the via and reduce the loss caused to the dielectric layer. This reduces the possibility of short circuits between the via and the trench due to large dielectric layer loss during the etching process, which could lead to short circuits in the subsequently formed metal interconnect structure. In this way, the accuracy of the critical dimensions of the subsequently formed metal interconnect structure is ensured, thereby improving the yield of chip products and device performance. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 A schematic diagram of a device structure in which the composite etch stop layer is not completely removed by the dual damask process in related technologies;

[0034] Figure 2This is a schematic diagram of the first process of the double damask process provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the second process of the double damask process provided in an embodiment of the present invention;

[0036] Figure 4A-4M This is a schematic diagram of the device structure for each step in the double damask process provided according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10A - Residual area; 101 - Composite etch stop layer; 101a - Aluminum nitride layer; 101b - First oxygen-doped silicon carbide layer; 101c - Alumina layer; 200 - Substrate; 31 - Via; 32 - Trench; 310 - Barrier layer; 320 - Dielectric layer; 330 - First etch stop layer; 340 - First hard mask layer; 341 - Trench opening; 30B - Via mask stack; 350 - First planarization layer; 360 - Second etch stop layer; 370 - Second hard mask layer; 371 - Via opening; 381 - Isolation layer; 382 - Second planarization layer; 391 - Metal layer; 392 - Metal material layer. Detailed Implementation

[0039] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0042] Figure 1 This is a schematic diagram of a device structure where the composite etch stop layer is not completely removed using the dual damask process in related technologies.

[0043] In related technologies, such as Figure 1 As shown, a composite etch stop layer 101, a dielectric layer 320, and a first etch stop layer 330 are formed on the substrate 200. The composite etch stop layer 101 includes an aluminum nitride layer 101a, a first oxygen-doped silicon carbide layer 101b, and an aluminum oxide layer 101c stacked sequentially. After forming trenches 32 and via openings in the dielectric layer 103 through integrated etching, the via openings stop at the surface of the aluminum oxide layer 101c. Then, wet etching-dry etching-wet etching are performed sequentially. Etching removes the aluminum oxide layer 101c, the first oxygen-doped silicon carbide layer 101b, and the aluminum nitride layer 101a. However, due to the very narrow linewidth in advanced processes, wet etching cannot completely remove the aluminum oxide layer 101c and the aluminum nitride layer 101a at the bottom of the via 31. The unremoved material forms a residue 10A. After a metal layer is formed in the via 31, the presence of the residue 10A will cause high resistance or open circuit in the metal interconnect structure formed there, thereby reducing the yield of chip products and device performance.

[0044] This invention provides a dual damascene process method in which the via 31 is formed by dry etching, and no composite etching stop layer is required between the substrate 200 and the dielectric layer 320. This ensures the passage and low resistance of the metal interconnect structure formed in the via 31 and trench 32. At the same time, during the dry etching process of the via 31, the first hard mask layer 340 acts as a mask layer to protect the dielectric layer 320 below it, thereby reducing the loss caused to the dielectric layer 320 and ensuring the accurate transfer of the via 31 and trench 32. This ensures the accuracy of the key dimensions of the metal interconnect structure, thereby improving the yield of chip products and the performance of devices.

[0045] Figure 2 This is a schematic diagram of the first process of the double damask process provided in an embodiment of the present invention. Figure 4A-4M This is a schematic diagram of the device structure for each step in the double damask process provided according to an embodiment of the present invention.

[0046] like Figure 2 The double damask process shown includes the following steps:

[0047] Step S201: A dielectric layer 320, a patterned first hard mask layer 340, a first planarization layer 350 and a patterned second hard mask layer 370 are sequentially formed on the substrate 200.

[0048] The substrate 200, dielectric layer 320, first hard mask layer 340, first planarization layer 350, and second hard mask layer 370 are stacked sequentially from bottom to top, wherein, as shown in the figure... Figure 4A As shown, after the first hard mask layer 340 is formed, as Figure 4B As shown, a first patterning etching can be performed to open the area of ​​the first hard mask layer 340 that defines the position and width of the trench 32, forming the trench opening 341. Specifically, the first patterning etching can be performed as follows: photoresist is spin-coated onto the first hard mask layer 340, a trench pattern is formed on the photoresist by photolithography, a dry etching process is used to open the area where the trench pattern is located, and the photoresist is removed, thereby forming the trench opening 341. Figure 4C As shown, after the second hard mask layer 370 is formed, as Figure 4D As shown, a second patterning etching can be performed to open an area that defines the location and width of the via 31, forming a via opening 371. Specifically, the second patterning etching can be performed as follows: spin-coating photoresist on the second hard mask layer 370, photolithographically forming a via pattern on the photoresist, using an etching process to open the area where the via pattern is located, and removing the photoresist to form the via opening 371.

[0049] Specifically, the substrate 200 can be a substrate or other structural layers formed on the substrate, or it can simultaneously include a substrate and other structural layers formed on the substrate, wherein the substrate can provide a supporting foundation for other structural layers on the substrate. The substrate can include semiconductor materials, and the semiconductor materials include, but are not limited to, any one or more of single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compounds, gallium arsenide compounds, gallium phosphide compounds, gallium sulfide compounds, silicon carbide, and multi-element semiconductor materials composed of group III-V elements, wherein multi-element semiconductor materials composed of group III-V elements include InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc. Specifically, the substrate can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In this embodiment of the invention, the semiconductor material substrate 200 can be a bulk silicon substrate. Other structural layers can be at least one of dielectric layers, semiconductor layers, and conductive layers.

[0050] The dielectric layer 320 serves as an insulating layer, internally forming metal interconnect structures to reduce parasitic capacitance between these interconnect structures and decrease RC delay. Specifically, the dielectric layer 320 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative permittivity less than 2.6), such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), spin-coated glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (SiCOH), etc. In this embodiment of the invention, the material of the dielectric layer 320 can be an ultra-low-k dielectric material, specifically SiOCH.

[0051] The first hard mask layer 340 serves as the mask layer for the etching trench 32, and its material may include at least one of titanium nitride (TiN), titanium oxide (TiO), tungsten carbide (WC), tungsten nitride (WN), silicon oxide (SiO), silicon oxycarbonate (SiOC), and silicon oxycarbonitrile (SiONC). In this embodiment of the invention, the material of the first hard mask layer 340 may be titanium nitride (TiN).

[0052] The first planarization layer 350 is used to fill the trench opening 341 and form a planarized surface on the surface of the first hard mask layer 340. Specifically, the first planarization layer 350 may include at least one of organic planarization material, silicon oxide, and amorphous carbon. The organic planarization material includes bottom anti-reflective coating (BARC), spin-on carbon (SOC), etc. In this embodiment of the invention, the material of the first planarization layer 350 can be spin-on carbon (SOC). Spin-on carbon has good filling performance and is easy to etch, which helps to reduce the difficulty of formation and subsequent removal. In use, the spin-on carbon material is filled into the trench opening 341 and uniformly coated onto the surface of the first hard mask layer 340 using a spin coating process. The thickness can be 1000 angstroms to 1500 angstroms, thereby forming the first planarization layer 350.

[0053] The second hard mask layer 370 serves as a mask layer for etching the via 31, and its material may include oxygen-doped silicon carbide (ODC).

[0054] Step S202: Using the second hard mask layer 370, a through hole 31 is formed by dry etching, stopping at the surface of the substrate 200.

[0055] Using a second hard mask layer 370 with a via opening 371 as a mask layer, dry etching is performed on the via opening 371 to propagate downwards and stop at the upper surface of the substrate 200, thereby forming a via 31. This ensures the continuity of the via 31 and the low resistance and pathway for the subsequent formation of metal interconnect structures in the bottom region of the via 31. At the same time, during the dry etching process to form the via 31, the first hard mask layer 340 can protect the dielectric layer 320 below it to ensure the accurate propagation of the critical dimensions of the via 31, thereby ensuring the accuracy of the critical dimensions of the subsequent metal interconnect structures, improving the yield of chip products and device performance.

[0056] Step S203: Remove the second hard mask layer 370 and the first planarization layer 350.

[0057] Step S204: Use the first hard mask layer 340 to dry etch and form the trench 32.

[0058] Using a first hard mask layer 340 with trench openings 341 as a mask layer, a dry etching process is performed on the trench openings 341 to make them penetrate downwards and stop at a predetermined depth in the dielectric layer 320, thereby forming trench 32.

[0059] Step S205: Remove the first hard mask layer 340.

[0060] The removal step of the first hard mask layer 340 is located after the dry etching step to form the via 31, so as to ensure the protection of the dielectric layer 320 below it during the dry etching process of forming the via 31, thereby ensuring the accurate transfer of the critical dimensions of the via 31 and the accuracy of the critical dimensions of the subsequent metal interconnect structure, thereby improving the yield of chip products and device performance.

[0061] Step S206: Form a metal layer 391 to fill the through holes 31 and trenches 32 to obtain a double damask structure.

[0062] The metal layer 391 filling the vias 31 and trenches 32 forms a metal interconnect structure, and the surface of the metal interconnect structure is approximately coplanar with the surface of the dielectric layer 320. Specifically, the metal layer 391 may include any one of copper, copper alloy, nickel, nickel alloy, tin, tin alloy, cobalt, cobalt alloy, ruthenium, ruthenium alloy, silver, and silver alloy grown by electrochemical deposition (ECD), as well as the necessary metal barrier layer and seed layer required for electrochemical deposition. In this embodiment of the invention, the metal layer 391 may include copper, a metal barrier layer, and a seed layer.

[0063] In the dual damascene process provided in this embodiment of the invention, a patterned second hard mask layer 370 is used as the mask layer. A dry etching process is used to etch through the first planarization layer 350, the first hard mask layer 340, and the dielectric layer 320 and stop at the upper surface of the substrate 200 to form a via 31. A patterned first hard mask layer 340 is used as the mask layer. A dry etching process is used to etch a trench 32 that extends downward and stops at a predetermined depth in the dielectric layer 320, thereby obtaining a dual damascene structure. There is no need to set a composite etching stop layer between the substrate 200 and the dielectric layer 320. Accordingly, there is no residual portion 10A formed by incomplete removal of the composite etching stop layer, thereby ensuring the continuity of the via 31 and the low resistance and pathway of the subsequent metal interconnect structure formed at the bottom region of the via 31. It can also effectively reduce the film layer structure, simplify the process steps, and improve the process efficiency.

[0064] Meanwhile, the removal step of the first hard mask layer 340 is located after the dry etching step of forming the via 31. During the dry etching process of forming the via 31, the first hard mask layer 340 can protect the dielectric layer 320 below it to ensure the accurate transfer of the critical dimensions of the via 31, reduce the loss caused to the dielectric layer 320, thereby reducing the occurrence of short circuits between the via 31 and the trench 32 due to large losses in the dielectric layer 320 during the etching process, which would cause the subsequent metal interconnect structure to be connected. This ensures the accuracy of the critical dimensions of the subsequent metal interconnect structure, thereby improving the yield of chip products and device performance.

[0065] In this embodiment of the invention, step S202: using the second hard mask layer 370 to dry etch and form a via 31 that stops at the surface of the substrate 200, specifically may include: using the second hard mask layer 370 to dry etch the dielectric layer 320, the process gas used includes fluorocarbon gas and oxygen-containing gas, and the flow ratio of fluorocarbon gas and oxygen-containing gas is 1:50 to 1:1.

[0066] Fluorocarbon gases, including CF4, C4F8, or C5F8, are used as the main etching gas at a flow rate of 10–50 sccm. Oxygen-containing gases are used as the sidewall polymer control gas at a flow rate of 50–500 sccm. An inert gas, such as Ar, can be added as a dilution gas at a flow rate of 30–800 sccm. The total flow rate of the etching gas, consisting of fluorocarbon gases, oxygen-containing gases, and inert gases, is 40–800 sccm. The chamber pressure is 50–300 mTorr, and the chamber temperature is 20–100 °C. The upper electrode power is 100–400 W, and the lower electrode power is 100–800 W.

[0067] Specifically, the process parameters for step S202 can be executed using ICP or CCP dry etching processes.

[0068] In this embodiment of the invention, a barrier layer 310 is formed between the substrate 200 and the dielectric layer 320. The barrier layer 310 separates the substrate 200 and the dielectric layer 320, protecting the semiconductor devices or interconnect structures within the substrate 200 from subsequent processes and preventing the diffusion of the metal layer 391 formed within the dielectric layer 320 to lower layers. Specifically, the barrier layer 310 can be a nitride material layer, and may include one or more layers selected from various films such as silicon nitride (SiN), silicon oxynitride (SiON), nitrogen-doped silicon carbide (NDC), and aluminum nitride (AlN). In this embodiment of the invention, the barrier layer 310 may be an aluminum nitride film.

[0069] In this embodiment of the invention, when a barrier layer 310 is provided between the dielectric layer 320 and the substrate 200, step S202: forming a via 31 that stops at the surface of the substrate 200 by dry etching using a second hard mask layer 370, specifically may include: dry etching the barrier layer 310 using a second hard mask layer 370, wherein the process gas used includes chlorine-containing gas and nitrogen-containing gas, and the flow ratio of chlorine-containing gas to nitrogen-containing gas is 1:3.5 to 1:0.15.

[0070] The chlorine-containing gas may include Cl2 and BCl3, with a flow rate ratio of Cl2 to BCl3 of 1:3 to 1:0.1; the nitrogen-containing gas may include N2, wherein Cl2 is used as the main etching gas with a flow rate of 10 to 50 sccm; BCl3 and N2 are used as auxiliary gases, with a flow rate of BCl3 of 5 to 30 sccm and a flow rate of N2 of 10 to 50 sccm; a mixed gas composed of Cl2, BCl3 and N2 is used as the etching gas, with a total flow rate of 10 to 50 sccm, and the flow rate ratio of Cl2, BCl3 and N2 in the etching gas is approximately 2:1:2; the chamber pressure is 5 to 50 mTorr; the chamber temperature is 20 to 40 °C; the upper electrode power is 300 to 500 W; the lower electrode power is 20 to 50 W; and the etching ratio of the barrier layer 310 to the substrate 200 is greater than 20:1.

[0071] The use of the above process parameters to dry etch the barrier layer 310 to form the via 31 ensures the complete removal of the barrier layer 310, thereby ensuring low resistance and a smooth path for the subsequent formation of a metal interconnect structure in the bottom region of the via 31.

[0072] like Figure 4A and 4BAs shown, a first etch stop layer 330 is formed between the first hard mask layer 340 and the dielectric layer 320. The first etch stop layer 330 serves as a stop layer for the first patterning etching, i.e., the trench opening 341 etch stop layer, ensuring that the trench opening 341 stops at the first etch stop layer 330. This allows for control over the depth of the trench opening 341, reducing uncontrollable damage to the underlying dielectric layer 320 caused by dry etching of the trench opening 341. Specifically, the first etch stop layer 330 can be a nitrogen-free dielectric anti-reflective coating (NFDARC).

[0073] In this embodiment of the invention, when a first etch stop layer 330 is provided between the first hard mask layer 340 and the dielectric layer 320, step S202: forming a via 31 stopping at the surface of the substrate 200 by dry etching using the second hard mask layer 370, specifically may include: dry etching the first etch stop layer 330 using the second hard mask layer 370, wherein the process gas used includes fluorocarbon gases and oxygen-containing gases, wherein the fluorocarbon gases as the main etching gases include C4F8, C4F6, C5F8, and C6F6. F4, CHF3, CH2F2, or CH2F, oxygen-containing gas is used as the control gas for the sidewall polymer. An inert gas can also be added as a dilution gas, such as Ar. The total flow rate of the etching gas, composed of fluorocarbon gas, oxygen-containing gas, and inert gas, is 10–500 sccm, the chamber pressure is 5–50 mTorr, and the chamber temperature is 20–100℃. The upper electrode power is 100–400 W, the lower electrode power is 20–50 W, and the etching time is 30–120 s.

[0074] like Figure 4C and 4D As shown, a second etch stop layer 360 is formed between the first planarization layer 350 and the second hard mask layer 370. The second etch stop layer 360 serves as a stop layer for the second patterning etch, i.e., the via opening 371 etch stop layer, causing the via opening 371 to stop at the second etch stop layer 360. Specifically, the second etch stop layer 360 may include at least one of silicon oxynitride (SiON), tetraethyl orthosilicate (TEOS), and low-temperature oxide (LTO). In this embodiment of the invention, the second etch stop layer 360 may be low-temperature oxide (LTO) and is grown using a plasma-enhanced atomic layer deposition (PEALD) process. Its thickness may be 200 to 300 angstroms, and its process temperature may be less than 100 degrees Celsius to reduce the impact on the first planarization layer 350.

[0075] In embodiments of the present invention, such as Figure 4C-4EAs shown, the first planarization layer 350, the second etch stop layer 360, and the second hard mask layer 370 together constitute the via mask stack 30B. Specifically, the via mask stack 30B can be removed by an ashing process. After the via 31 is formed, the first planarization layer 350, the second etch stop layer 360, and the second hard mask layer 370 of the via mask stack 30B can be completely removed by the ashing process, thereby simplifying the process steps and improving process efficiency. Specifically, the ashing process can be in-situ ashing or extra-situ ashing, and the processing gas used includes at least one of O2, N2, H2, CO2, CH4, and NH3. In this embodiment of the invention, O2 can be used as the processing gas, and the processing time is approximately tens of seconds.

[0076] In this embodiment of the invention, step S205, removing the first hard mask layer 340, may specifically include the following steps: forming an insulating layer 381 to fill the via 31 and trench 32, and completely exposing the first hard mask layer 340; sequentially removing the first hard mask layer 340 and the insulating layer 381. The insulating layer 381 is formed by filling the via 31 and trench 32 with material to shield the exposed area of ​​the substrate 200 at the bottom of the via 31; the upper surface of the insulating layer 381 is not higher than the upper surface of the first hard mask layer 340 and not lower than the upper surface of the dielectric layer 320, thereby completely exposing the first hard mask layer 340 and isolating the first hard mask layer 340 and the substrate 200 on both sides, while also providing insulation and protection for the dielectric layer 320, thereby reducing damage to the exposed area of ​​the substrate 200 and the dielectric layer 320 caused by the subsequent removal of the first hard mask layer 340.

[0077] Continuing, the first hard mask layer 340 is etched away, and then the insulating layer 381 is removed to fully expose the via 31 and the trench 32. Specifically, the first hard mask layer 340 can be removed first by wet etching. When the material of the first hard mask layer 340 is titanium nitride, the etching solution used for wet etching of the first hard mask layer 340 can be a mixed solution of NH4OH, H2O2 and water (SC1 cleaning solution), or a mixed solution of HCl, H2O2 and water (SC2 cleaning solution), or FOTOPURR-2360. In this embodiment of the invention, an SC1 cleaning solution with a formulation of NH4OH:H2O2:H2O = 1:1:5 to 1:2:7 is used as the etching solution, and the process temperature is 40℃ to 80℃.

[0078] The material of the insulating layer 381 may include at least one of organic planarization material, silicon oxide, and amorphous carbon. Specifically, the material of the insulating layer 381 may be the same as that of the first planarization layer 350. After the first hard mask layer 340 is removed, the insulating layer 381 may be removed by an ashing process. Specifically, the ashing process may be in-situ ashing or extra-situ ashing, and the processing gas used may include at least one of O2, N2, H2, CO2, CH4, and NH3. In this embodiment of the invention, O2 may be used as the processing gas, and the processing time is approximately tens of seconds.

[0079] In this embodiment of the invention, the step of forming an insulating layer 381 to fill the vias 31 and trenches 32 and completely expose the first hard mask layer 340 includes: forming a second planarization layer 382 to fill the vias 31 and trenches 32 and cover the first hard mask layer 340; performing a back-etching process on the second planarization layer 382 to form the insulating layer 381, thereby completely exposing the first hard mask layer 340. The second planarization layer 382 is formed by filling the vias 31 and trenches 32 with material and completely covering the surface of the first hard mask layer 340. Specifically, the second planarization layer 382 can be spin-coated carbon (SOC). In use, the spin-coated carbon material is filled into the vias 31 and trenches 32, and a spin coating process is used to uniformly coat the spin-coated carbon material onto the surface of the first hard mask layer 340, thereby forming the second planarization layer 382.

[0080] After the second planarization layer 382 is formed, it is etched back until the upper surface of the second planarization layer 382 is not higher than the bottom surface of the first hard mask layer 340, thereby ensuring that the first hard mask layer 340 is fully exposed for subsequent removal processes. At the same time, the upper surface of the second planarization layer 382 is not lower than the upper surface of the dielectric layer 320, to ensure its isolation effect on both the dielectric layer 320 and the substrate 200 from the first hard mask layer 340, and to reduce the damage caused to the exposed areas of the dielectric layer 320 and the substrate 200 by the etching process of the first hard mask layer 340. The remaining part of the second planarization layer 382 after the etch-back process serves as an isolation layer 381.

[0081] Specifically, dry etching can be used to perform a reverse etching process on the second planarization layer 382. The dry etching process has a high etching rate on the second planarization layer 382 and a low etching rate on the first hard mask layer 340, which can achieve efficient reverse etching of the second planarization layer 382 and complete exposure of the first hard mask layer 340.

[0082] In this embodiment of the invention, step S206: forming a metal layer 391 to fill the vias 31 and trenches 32 to obtain a double damask structure, specifically may include: filling the vias 31 and trenches 32 with metal material; performing a chemical mechanical polishing (CMP) process to remove excess metal to form the metal layer 391 and obtain the double damask structure. Specifically, the metal material layer 392 can be formed by depositing metal material in the vias 31 and trenches 32 through electrochemical deposition (ECD), and the upper surface of the metal material layer 392 is higher than the dielectric layer 320; for example... Figure 4L As shown, the height of the metal material layer 392 filling the through-hole 31 and the trench 32 is higher than that of the first etch stop layer 330 and covers the surface of the first etch stop layer 330.

[0083] Continuing, chemical mechanical polishing is performed on the portion of the metal material layer 392 above the dielectric layer 320 until the upper surface of the metal material layer 392 and the upper surface of the dielectric layer 320 are approximately coplanar to form a metal layer 391. When a first etch stop layer 330 is provided on the upper layer of the dielectric layer 320, the first etch stop layer 330 is removed simultaneously during the chemical mechanical polishing process, thereby obtaining a double damask structure.

[0084] Figure 3 This is a schematic diagram of the second process of the double damask process provided according to an embodiment of the present invention. Figure 3 As shown, the process includes:

[0085] Provide a base.

[0086] S301: As Figure 4A As shown, a barrier layer 310, a dielectric layer 320, a first etch stop layer 330, and a first hard mask layer 340 are sequentially formed on a substrate 200.

[0087] S302: As Figure 4B As shown, the first hard mask layer 340 is patterned and etched to form the trench opening 341.

[0088] S303: As Figure 4C As shown, a first planarization layer 350, a second etch stop layer 360, and a second hard mask layer 370 are sequentially formed, wherein the first planarization layer 350 fills the trench opening 341 and covers the first hard mask layer 340.

[0089] S304: As Figure 4D As shown, a second patterning etching is performed on the second hard mask layer 370 to form a via opening 371.

[0090] S305: As Figure 4E As shown, the via opening 371 is transferred to the surface of the substrate 200 by dry etching to form the via 31.

[0091] S306: As Figure 4F As shown, the first planarization layer 350, the second etch stop layer 360, and the second hard mask layer 370 are removed by an ashing process.

[0092] S307: As Figure 4G As shown, the trench opening 341 is transferred to the dielectric layer 320 by dry etching to form the trench 32.

[0093] S308: As Figure 4H As shown, a second planarization layer 382 is formed to fill the vias 31 and trenches 32, and covers the first hard mask layer 340.

[0094] S309: As Figure 4I As shown, the second planarization layer 382 is etched back to form an isolation layer 381 to fully expose the first hard mask layer 340.

[0095] S310: As Figure 4J As shown, the first hard mask layer 340 is removed by wet etching.

[0096] S311: As Figure 4K As shown, the insulating layer 381 is removed using an ashing process.

[0097] S312: As Figure 4L As shown, a metal material layer 392 is filled into the through hole 31 and the trench 32.

[0098] S313: As Figure 4M As shown, a chemical mechanical polishing planarization process is performed to remove excess metal, form a metal layer 391, and obtain a double damask structure.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual damascene process method, characterized by, The method comprises the following steps: sequentially forming a dielectric layer (320), a patterned first hard mask layer (340), a first planarization layer (350) and a patterned second hard mask layer (370) on a substrate (200); the second hard mask layer (370) has a via opening (371) capable of defining a via (31), dry etching the via opening (371) downward to the surface of the substrate (200) to form the via (31) with the second hard mask layer (370) as a mask; removing the second hard mask layer (370) and the first planarization layer (350); dry etching the first hard mask layer (340) to form a trench (32); removing the first hard mask layer (340); forming a metal layer (391) to fill the via (31) and the trench (32) to obtain a dual damascene structure.

2. The dual damascene process method of claim 1, wherein, In the step of dry etching the second hard mask layer (370) to form the via (31) stopping on the surface of the substrate (200), the dielectric layer (320) is dry etched by using the second hard mask layer (370), and the process gas comprises fluorocarbon gas and oxygen-containing gas, and the flow ratio of the fluorocarbon gas to the oxygen-containing gas is 1:50-1:

1.

3. The dual damascene process method of claim 1, wherein, A barrier layer (310) is formed between the substrate (200) and the dielectric layer (320).

4. The dual damascene process method of claim 3, wherein, In the step of dry etching the second hard mask layer (370) to form the via (31) stopping on the surface of the substrate (200), the barrier layer (310) is dry etched by using the second hard mask layer (370), and the process gas comprises chlorine-containing gas and nitrogen-containing gas, and the flow ratio of the chlorine-containing gas to the nitrogen-containing gas is 1:3.5-1:0.

15.

5. The dual damascene process method of claim 4, wherein, The chlorine-containing gas comprises Cl2 and BCl3, and the flow ratio of Cl2 to BCl3 is 1:3-1:0.

1.

6. Dual damascene process method according to any one of claims 1 to 5, characterized in that, In the step of removing the first hard mask layer (340), the following steps are included: forming an isolation layer (381) to fill the via (31) and the trench (32) and completely expose the first hard mask layer (340); sequentially removing the first hard mask layer (340) and the isolation layer (381).

7. The dual damascene process method of claim 6, wherein, In the step of forming the isolation layer (381) to fill the via (31) and the trench (32) and completely expose the first hard mask layer (340), the following steps are included: forming a second planarization layer (382) to fill the via (31) and the trench (32) and cover the first hard mask layer (340); performing a back etching process on the second planarization layer (382) to form the isolation layer (381) to completely expose the first hard mask layer (340).

8. The dual damascene process of claim 6, wherein, In the step of sequentially removing the first hard mask layer (340) and the isolation layer (381), the following steps are included: adopting wet etching to remove the first hard mask layer (340); adopting a gray etching process to remove the isolation layer (381).

9. The dual damascene process of any of claims 1-5, wherein, The step of forming the metal layer (391) to fill the via (31) and the trench (32) to obtain a dual damascene structure comprises: filling a metal material into the via (31) and the trench (32); performing a chemical mechanical polishing planarization process to remove the excess metal to form the metal layer (391) and obtain a dual damascene structure.

10. The dual damascene process of any of claims 1-5, wherein, A first etching stop layer (330) is formed between the first hard mask layer (340) and the dielectric layer (320). And / or, a second etching stop layer (360) is formed between the first planarization layer (350) and the second hard mask layer (370).

Images