A new parallel machine anti-current backflow circuit and anti-current backflow method

Abstract

The present invention discloses a novel parallel machine anti-current backflow circuit and anti-current backflow method, including a transformer, multiple power switch tubes, two operational amplifier circuits, multiple resistors and capacitors, one side of the transformer is connected to the power switch tubes Q1 and Q2, and the other side is connected to the power switch tubes Q3 and Q4; the source of the power switch tube Q3 is connected to the source of the power switch tube Q4, and then the capacitors C1 and C2 are connected in parallel with the other side of the transformer, the two ends of the resistor R5 are connected to SEN2 and SEN1 respectively, and the two ends of the parallel circuit of the capacitors C1 and C2 are connected to +Vo and -Vo; SEN2 and SEN1 are connected to the circuit of the differential sampling operational amplifier U2A, +Vo and -Vo are connected to the circuit of the differential sampling operational amplifier U1A, and the analog signals output by the two differential sampling operational amplifiers are input to the ADC chip, which converts the analog signals into digital signals to complete the analog-to-digital conversion of the signals. Internal space is saved and the current backflow phenomenon is effectively prevented.

Description

Technical Field

[0001] The invention relates to a power supply, and in particular to a novel parallel machine current backflow prevention circuit and current backflow prevention method. Background Art

[0002] In military and industrial production, there is a huge demand for high-power density, high-reliability DC / DC module power supplies, and the demand for high-power module power supplies is also increasing. Currently, in the market, high-power module power supplies require multiple units in parallel mode in some use cases, which helps reduce the heat generated by a single module and improve product utilization. However, when multiple units are connected in parallel, if one module abnormally has no output, current backflow will occur. That is, the module with normal output will output current to the module without output, thus affecting the normal operation of the entire system. To address this problem, the current methods used by the industry and their shortcomings are as follows:

[0003] Current treatment methods and shortcomings:

[0004] 1. To prevent the current backflow phenomenon mentioned above when using the modules in parallel, the first solution is to connect a forward diode (such as Figure 1 When paralleling, if one of the modules is damaged, the diode's forward conduction and reverse blocking characteristics can effectively prevent current backflow.

[0005] 2. The second processing method is: in the output circuit inside the module, connect two MOS tubes and a triode in series (such as Figure 2 (as shown). During normal operation, Q6 is high and conducting. Because Q6 is a conducting MOS, its gate is low. Q7 and Q8, both PMOS transistors, are conducting, allowing the module to output normally. During parallel operation, if one module fails, Q6 is low, turning off Q6 and Q7 and Q8 to prevent backflow.

[0006] The above two processing methods have the following disadvantages:

[0007] (1) Adding a diode to the external output end of the module will cause inconvenience to customers when using it. It is necessary to add an additional circuit outside the module, which also increases the cost for customers.

[0008] (2) It is necessary to add MOS tubes, transistors and other devices inside the module, which increases the design difficulty and production cost of the module.

[0009] Therefore, there is an urgent need to provide a new current backflow prevention circuit to solve this problem. Summary of the Invention

[0010] In order to solve the problem of additional circuit cost due to current backflow prevention, the present invention provides a novel parallel machine current backflow prevention circuit.

[0011] The present invention provides the following technical solutions:

[0012] A novel parallel current backflow prevention circuit includes a transformer, multiple power switching tubes, two operational amplifier circuits, multiple resistors, and capacitors. One side of the transformer is connected to the power switching tubes Q1 and Q2, and the other side of the transformer is connected to the power switching tubes Q3 and Q4. The power switching tubes Q1, Q2, Q3, and Q4 have internal diodes. The source of the power switching tube Q3 is connected to the source of the power switching tube Q4, and then connected to the other side of the transformer in parallel with capacitors C1 and C2. One end of capacitor C1 and capacitor C2 is connected to resistor R5, and the two ends of resistor R5 are connected to SEN2 and SEN1 respectively. The two ends of the parallel circuit of capacitors C1 and C2 are connected to +Vo and -Vo.

[0013] The two operational amplifier circuits are a circuit of a differential sampling operational amplifier U2A and a circuit of a differential sampling operational amplifier U1A;

[0014] SEN2 and SEN1 are connected to the circuit of differential sampling op amp U2A, +Vo and -Vo are connected to the circuit of differential sampling op amp U1A, and the analog signals output by the two differential sampling op amps are input to the ADC chip, which converts the analog signals into digital signals to complete the analog-to-digital conversion of the signals.

[0015] Furthermore, a resistor R1 is provided between the gate and source of the power switch tube Q1, a capacitor C3 is provided between the drain and source of the power switch tube Q1, a resistor R2 is provided between the gate and source of the power switch tube Q2, and a capacitor C4 is provided between the drain and source of the power switch tube Q2; and resistors R3 and R4 are connected between the gate of the power switch tube Q3 and the gate of the power switch tube Q4.

[0016] Furthermore, transformer T2_1 couples the energy of the left circuit to the right.

[0017] Furthermore, capacitors C3 and C4 are used for input filtering, and capacitors C1 and C2 are used for output filtering.

[0018] Furthermore, the circuit of the differential sampling amplifier U2A is divided into:

[0019] Input stage: After the SEN1 output signal is limited by resistor R6, it is input to the inverting input terminal of the differential sampling amplifier U2A; the SEN2 output signal is limited by resistor R7, and then passes through resistor R9 to DGND to form a bias loop, and then input to the non-inverting input terminal of the differential sampling amplifier U2A;

[0020] Amplification stage: The differential sampling op amp U2A amplifies the signal based on the differential input through the feedback loop formed by R8, and outputs the amplified analog signal from pin 1;

[0021] Conversion stage: The analog signal output by the differential sampling op amp U2A is limited by the resistor R10 and then input to the ADC228035. The ADC chip converts the analog signal into a digital signal, completing the analog-to-digital conversion of the signal for subsequent system processing.

[0022] Furthermore, the circuit of the differential sampling operational amplifier U1A is divided into:

[0023] Input link: After the +Vo signal is limited by resistor R11, it is input to the inverting input terminal of the differential sampling amplifier U1A; the -Vo signal is limited by resistor R12, and then passes through resistor R13 to DGND to form a bias loop, and is input to the non-inverting input terminal of the differential sampling amplifier U1A;

[0024] Amplification link: The differential sampling op amp U1A amplifies the signal based on the differential signal between the inverting terminal and the non-inverting terminal through the feedback network formed by resistor R14. The amplified analog signal is output from pin 1.

[0025] Analog-to-digital conversion link: The analog signal output by the differential sampling op amp U1A is limited by the resistor R15 and then input into the ADC128035. The ADC chip converts the analog signal into a digital signal, completing the analog-to-digital conversion process of the signal.

[0026] A novel method for preventing current backflow in parallel operation includes the following steps:

[0027] S1. Output voltage sampling process:

[0028] When the system is in parallel working mode and the module has no output, the output voltage signal will enter the sampling and processing link as a key monitoring parameter. This signal is first transmitted to the differential sampling amplifier U1A, which processes the input output voltage signal and converts it into a standard level signal suitable for subsequent circuit processing;

[0029] S2. Current sampling and conversion process:

[0030] The current-to-voltage conversion is achieved by using the resistor R5 in the current sampling circuit. The output current flowing through R5 will generate a voltage drop across the resistor. This voltage drop is proportional to the output current. The generated voltage signal is then sent to the differential sampling op amp U2A for processing.

[0031] S3, signal transmission to DSP and sampling processing:

[0032] The output voltage signal and current voltage signal processed by U1A and U2A are transmitted to the ADC sampling port of the digital signal processor DSP28035;

[0033] S4. PWM output adjustment based on algorithm:

[0034] After receiving the sampled digital signal, the DSP28035 uses a pre-programmed algorithm to perform in-depth calculations and analysis on the data. Based on the algorithm results, the DSP28035 adjusts the output parameters of the PWM signal. By changing the characteristics of the PWM signal, it accurately controls the switching states of the MOS tubes Q3 and Q4.

[0035] S5, MOS tube control to achieve current backflow prevention:

[0036] The PWM signal adjusted by DSP28035 is output to the drive circuit of synchronous rectifier MOS tubes Q3 and Q4. The drive circuit will generate appropriate drive voltage and current according to the changes of PWM signal to control the conduction and shutdown of MOS tubes.

[0037] Furthermore, in step S4, the time and amplitude judgment of abnormality is added to the DSP control algorithm. When the collected abnormal signal is greater than or less than the given time and amplitude, the DSP determines that the module is abnormal.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. The present invention eliminates the need to add an additional diode anti-backflow circuit outside the module output, and also eliminates the need to add an additional MOS anti-backflow circuit inside the module. Instead, the inherent synchronous rectification MOS tubes Q3 and Q4 inside the product are used to prevent current backflow. When the module is in parallel operation, there is no output, and the output voltage passes through the differential sampling amplifier U1A. The current sampling circuit R5 resistor multiplies the output current to convert it into voltage, and at the same time passes through the differential sampling amplifier U2A and then sent to the DSP28035 ADC sampling port. After the sampling signal is sent to the DSP, it is processed by algorithm to achieve PWM output adjustment, thereby controlling the switching of the MOS tubes Q3 and Q4 to achieve current backflow prevention.

[0040] 2. Use the internal algorithm of DSP to realize the control of output rectifier MOS, without adding additional internal and external circuits, and effectively prevent the current backflow problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a circuit diagram of the first current backflow processing method in the prior art;

[0042] Figure 2 This is a circuit diagram of the second current backflow processing method in the prior art;

[0043] Figure 3 Schematic diagram of the circuit of the present invention;

[0044] Figure 4This is an operational amplifier circuit diagram of the present invention;

[0045] Figure 5 This is another operational amplifier circuit diagram of the present invention;

[0046] Figure 6 This is the circuit diagram for the DC power supply in parallel (online). DETAILED DESCRIPTION

[0047] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0048] See also Figure 3-5 A novel parallel current backflow prevention circuit of the present invention includes a transformer, multiple power switch tubes, two operational amplifier circuits, multiple resistors and capacitors. One side of the transformer is connected to the power switch tubes Q1 and Q2, and the other side of the transformer is connected to the power switch tubes Q3 and Q4. The power switch tubes Q1, Q2, Q3, and Q4 have internal diodes.

[0049] A resistor R1 is set between the gate and source of the power switch tube Q1, and a capacitor C3 is set between the drain and source of the power switch tube Q1.

[0050] A resistor R2 is set between the gate and source of the power switch tube Q2, and a capacitor C4 is set between the drain and source of the power switch tube Q2.

[0051] Resistors R3 and R4 are connected between the gate of the power switch tube Q3 and the gate of the power switch tube Q4.

[0052] The source of the power switch tube Q3 is connected to the source of the power switch tube Q4, and then capacitors C1 and C2 are connected in parallel with the other side of the transformer. One end of capacitor C1 and capacitor C2 is connected to resistor R5, and the two ends of resistor R5 are connected to SEN2 and SEN1 respectively. The two ends of the parallel circuit of capacitors C1 and C2 are connected to +Vo and -Vo.

[0053] The two op amp circuits are the differential sampling op amp U2A circuit and the differential sampling op amp U1A circuit.

[0054] SEN2 and SEN1 are connected to the circuit of the differential sampling op amp U2A, +Vo and -Vo are connected to the circuit of the differential sampling op amp U1A, and the analog signals output by the two differential sampling op amps are input to the ADC chip, which converts the analog signals into digital signals to complete the analog-to-digital conversion of the signals.

[0055] Transformer T2_1 couples the energy from the left circuit to the right.

[0056] Capacitors C3 and C4 on the left side of the circuit are used for input filtering, and capacitors C1 and C2 on the right side of the circuit are used for output filtering.

[0057] Signal flow:

[0058] Input side (left side): The power supply is connected through PGND, and the control signal (or drive signal) drives the power switches Q1 and Q2 to alternately turn on / off, converting the DC input into a high-frequency pulse signal, which is coupled to the secondary side by electromagnetic induction through the primary winding of transformer T2_1.

[0059] Secondary side of the transformer (right side): The high-frequency pulse signal induced by the secondary side passes through the circuit composed of power switch tubes Q3 and Q4, and is filtered and current-limited by capacitors and resistors. The final output voltage is the resistor R5 and the subsequent load forming the output circuit to achieve energy transfer and voltage conversion.

[0060] The circuit of differential sampling op amp U2A is divided into:

[0061] 1. Input stage: The SEN1 output signal is current-limited by resistor R6 and then input to the inverting input terminal (pin 2) of the differential sampling op amp U2A. The SEN2 output signal is current-limited by resistor R7, then passes through resistor R9 to DGND to form a bias loop, and is then input to the non-inverting input terminal (pin 3) of the differential sampling op amp U2A.

[0062] 2. Amplification stage: The differential sampling op amp U2A amplifies the signal based on the differential input (the difference between the signals at pins 2 and 3) through the feedback loop formed by R8, and outputs the amplified analog signal from pin 1.

[0063] 3. Conversion stage: The analog signal output by the differential sampling op amp U2A is limited by the resistor R10 and then input into the ADC228035. The ADC chip converts the analog signal into a digital signal, completing the analog-to-digital conversion of the signal for subsequent system processing.

[0064] The circuit of differential sampling op amp U1A is divided into:

[0065] 1. Input link: After the +Vo signal is limited by resistor R11, it is input to the inverting input terminal (pin 2) of the differential sampling op amp U1A. The -Vo signal is limited by resistor R12, then passes through resistor R13 to DGND to form a bias loop, and is input to the non-inverting input terminal (pin 3) of the differential sampling op amp U1A.

[0066] 2. Amplification link: The differential sampling op amp U1A amplifies the signal based on the differential signal between the inverting terminal (pin 2) and the non-inverting terminal (pin 3) through the feedback network formed by resistor R14. The amplified analog signal is output from pin 1.

[0067] 3. Analog-to-digital conversion: The analog signal output by the differential sampling op amp U1A is limited by resistor R15 and then input to ADC128035. The ADC chip converts the analog signal into a digital signal, completing the analog-to-digital conversion process.

[0068] MOS tube anti-backflow principle:

[0069] The product design integrates synchronous rectifier MOSFETs Q3 and Q4, whose operating characteristics can be used to implement a current backflow prevention mechanism. Synchronous rectifier MOSFETs have low on-resistance and fast switching capabilities. By properly controlling their on and off states, they can prevent current from flowing in the opposite direction from the high-voltage side to the low-voltage side, thereby preventing current backflow. In parallel operation, if a module experiences an abnormal output failure, this mechanism plays a key role in ensuring the normal operation of the system and the safety of each module.

[0070] A novel method for preventing current backflow in parallel operation of the present invention comprises the following steps:

[0071] S1. Output voltage sampling process:

[0072] When the system is in parallel operation and the module has no output, the output voltage signal enters the sampling and processing phase as a key monitoring parameter. This signal is first transmitted to the differential sampling op amp U1A. This amplifier suppresses common-mode interference and improves signal sampling accuracy. It processes the input output voltage signal and converts it into a standard level signal suitable for subsequent circuit processing. Precision circuit design and parameter configuration ensure that the output voltage signal is accurately and stably sampled and transmitted, providing a reliable data foundation for subsequent analysis and control.

[0073] S2. Current sampling and conversion process:

[0074] The current sampling method uses resistor sampling, utilizing resistor R5 in the current sampling circuit to achieve current-to-voltage conversion. According to Ohm's law, the output current flowing through R5 generates a voltage drop across the resistor, which is proportional to the output current. The resulting voltage signal is then fed into differential sampling amplifier U2A for processing. Similarly, differential sampling amplifier U2A amplifies and filters the voltage signal to remove noise interference and adjust it to the voltage range required by the DSP28035 ADC sampling port input, ensuring sampling accuracy and stability.

[0075] S3, signal transmission to DSP and sampling processing:

[0076] After processing by U1A and U2A, the output voltage and current signals are transmitted to the ADC sampling port of the DSP28035 digital signal processor. The DSP28035 has a built-in high-performance analog-to-digital conversion module that quickly and accurately samples and quantizes the input analog signals, converting them into digital signals. During the sampling process, the DSP28035 processes the signals according to the preset sampling frequency and accuracy, ensuring that the collected data fully and accurately reflects the actual status of the output voltage and current.

[0077] S4. PWM output adjustment based on algorithm:

[0078] After receiving the sampled digital signal, the DSP28035 uses pre-programmed algorithms to perform in-depth computation and analysis on the data. These algorithms are typically designed based on the system's control objectives and operational logic. By comprehensively analyzing the output voltage and current data, they determine the system's current operating status and whether there is a risk of current backflow. Based on the algorithmic results, the DSP28035 adjusts the output parameters of the PWM (pulse width modulation) signal, such as pulse width and frequency. By changing the characteristics of the PWM signal, it precisely controls the switching state of MOS transistors Q3 and Q4.

[0079] S5, MOS tube control to achieve current backflow prevention:

[0080] The PWM signal adjusted by the DSP28035 is output to the driver circuit of synchronous rectifier MOSFETs Q3 and Q4. Based on the PWM signal, the driver circuit generates appropriate drive voltage and current to control the on and off state of the MOSFETs. When a potential current backflow is detected, the DSP28035 adjusts the PWM signal to cut off MOSFETs Q3 and Q4, effectively preventing the reverse current flow. During normal operation, proper PWM control ensures efficient power transmission from the MOSFETs and stable system operation.

[0081] The core controller used in the present invention is TMS320F28035, which obtains voltage and current sampling signals through ADC sampling, and then controls the rectifier MOS through internal algorithm control.

[0082] The working principle of this circuit is:

[0083] 1. When the module power starts working, (from Figure 3 、 4As can be seen from Figure 5, +Vo and -Vo are the positive and negative output terminals connected to the load. The voltage and current sampling signals are sent to the DSP after being calculated by the differential sampling operational amplifiers U1A and U2A. The output voltage and current of the module are then controlled by the internal algorithm of the DSP.

[0084] 2. For example, if the module output is 28V / 50A, the voltage sampling is calculated by the resistor R14 on the differential sampling amplifier U1A and the ratio of the resistor R11 is equal to 0.1. The voltage sent to the DSP ADC1 sampling port is 28*0.1, which is equal to 2.8V. Similarly, the current sampling resistor R5 is 0.0005Ω, so the voltage on the resistor R5 is 0.0005*40=0.02V. After the differential sampling amplifier U2A and the ratio of the resistor R8 to the resistor R6 are equal to 100, the voltage sent to the DSP ADC2 sampling port is 0.02*100, which is equal to 2V. After the DSP collects the voltage at the ADC port, it controls the output voltage and current respectively.

[0085] When multiple DC power modules are connected in parallel (such as Figure 6 shown):

[0086] +Vin, -Vin input DC / DC module: This is the core power unit, responsible for converting the input DC voltage (+Vin, -Vin) into stable positive and negative outputs (+Vo, -Vo, +Vc, -Vc in the figure are output terminals), realizing voltage conversion, isolation and other functions;

[0087] Parallel logic: Multiple identical DC / DC modules are connected in parallel, with inputs sharing the +Vin and -Vin power supplies and outputs providing the +Vc and -Vc voltages. This is done to increase total output power (load sharing across multiple modules) or improve reliability.

[0088] For example, if a device requires a 1000W output and a single 500W module is not enough, two (or more) modules can be connected in parallel to solve the problem of insufficient power for a single module. After parallel connection, even if one module fails, the others can still maintain power supply, improving system reliability.

[0089] If a module malfunctions and stops outputting for a moment, the signals collected by the output voltage and output current will change.

[0090] The calculation method for changes is as described in the previous two points. That is, whenever the module's output current changes, the DSP ADC collects the current change in real time and performs signal analysis. In this case, we can incorporate abnormality time and amplitude determination into the DSP control algorithm. If the acquired abnormal signal is greater than or less than the specified time and amplitude, the DSP will determine that the module has an abnormality.

[0091] When the DSP determines that the module is abnormal, it turns off the PWM drive signal of the power switch tubes Q3 and Q4. After the power switch tube (MOS tube) drive switch signal is turned off, the internal diode inside the MOS tube package can also prevent the backflow of current by utilizing the unidirectional conduction characteristic of the diode, thereby not affecting the normal operation of other parallel modules.

[0092] Advantages of the present invention:

[0093] 1. Compared with the existing circuits on the market, it not only reduces the complexity of the external circuit when the modules are used in parallel, but also avoids the complexity of the circuit design inside the module, saves internal space, and reduces design costs and failure rates.

[0094] 2. The saved space can further improve the power density of the module power supply.

[0095] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A new parallel current backflow prevention circuit, characterized by: The system includes a transformer, multiple power switching tubes, two operational amplifier circuits, multiple resistors, and capacitors. One side of the transformer is connected to the power switching tubes Q1 and Q2, and the other side of the transformer is connected to the power switching tubes Q3 and Q4. Internal diodes are present in the power switching tubes Q1, Q2, Q3, and Q4. The source of the power switching tube Q3 is connected to the source of the power switching tube Q4, and then connected to the other side of the transformer in parallel with capacitors C1 and C2. One end of capacitor C1 and capacitor C2 is connected to resistor R5, and the two ends of resistor R5 are connected to SEN2 and SEN1 respectively. The two ends of the parallel circuit of capacitors C1 and C2 are connected to +Vo and -Vo. The two operational amplifier circuits are a circuit of a differential sampling operational amplifier U2A and a circuit of a differential sampling operational amplifier U1A; SEN2 and SEN1 are connected to the circuit of differential sampling op amp U2A, +Vo and -Vo are connected to the circuit of differential sampling op amp U1A, and the analog signals output by the two differential sampling op amps are input to the ADC chip, which converts the analog signals into digital signals, completing the analog-to-digital conversion of the signals. The circuit of the differential sampling amplifier U2A is divided into: Input stage: After the SEN1 output signal is limited by resistor R6, it is input to the inverting input terminal of the differential sampling amplifier U2A; the SEN2 output signal is limited by resistor R7, and then passes through resistor R9 to DGND to form a bias loop, and then input to the non-inverting input terminal of the differential sampling amplifier U2A; Amplification stage: The differential sampling op amp U2A amplifies the signal based on the differential input through the feedback loop formed by R8, and outputs the amplified analog signal from pin 1; Conversion stage: The analog signal output by the differential sampling op amp U2A is limited by the resistor R10 and then input to the ADC228035. The ADC chip converts the analog signal into a digital signal, completing the analog-to-digital conversion of the signal for subsequent system processing. The circuit of the differential sampling amplifier U1A is divided into: Input link: After the +Vo signal is limited by resistor R11, it is input to the inverting input terminal of the differential sampling amplifier U1A; the -Vo signal is limited by resistor R12, and then passes through resistor R13 to DGND to form a bias loop, and is input to the non-inverting input terminal of the differential sampling amplifier U1A; Amplification link: The differential sampling op amp U1A amplifies the signal based on the differential signal between the inverting terminal and the non-inverting terminal through the feedback network formed by resistor R14. The amplified analog signal is output from pin 1. Analog-to-digital conversion: The analog signal output by the differential sampling amplifier U1A is limited by the resistor R15 and then input to the ADC128035. The ADC chip converts the analog signal into a digital signal, completing the analog-to-digital conversion process. The current backflow prevention method based on the novel parallel current backflow prevention circuit includes the following steps: S1. Output voltage sampling process: When the system is in parallel working mode and the module has no output, the output voltage signal will enter the sampling and processing link as a key monitoring parameter. This signal is first transmitted to the differential sampling amplifier U1A, which processes the input output voltage signal and converts it into a standard level signal suitable for subsequent circuit processing; S2. Current sampling and conversion process: The current-to-voltage conversion is achieved by using the resistor R5 in the current sampling circuit. The output current flowing through R5 will generate a voltage drop across the resistor. This voltage drop is proportional to the output current. The generated voltage signal is then sent to the differential sampling op amp U2A for processing. S3, signal transmission to DSP and sampling processing: The output voltage signal and current voltage signal processed by U1A and U2A are transmitted to the ADC sampling port of the digital signal processor DSP28035; S4. PWM output adjustment based on algorithm: After receiving the sampled digital signal, the DSP28035 uses a pre-programmed algorithm to perform in-depth calculations and analysis on the data. Based on the algorithm results, the DSP28035 adjusts the output parameters of the PWM signal. By changing the characteristics of the PWM signal, it accurately controls the switching states of the MOS tubes Q3 and Q4. S5, MOS tube control to achieve current backflow prevention: The PWM signal adjusted by DSP28035 is output to the drive circuit of synchronous rectifier MOS tubes Q3 and Q4. The drive circuit will generate appropriate drive voltage and current according to the changes of PWM signal to control the conduction and shutdown of MOS tubes.

2. The novel parallel current backflow prevention circuit according to claim 1, characterized in that: A resistor R1 is set between the gate and source of the power switch tube Q1, a capacitor C3 is set between the drain and source of the power switch tube Q1, a resistor R2 is set between the gate and source of the power switch tube Q2, and a capacitor C4 is set between the drain and source of the power switch tube Q2; resistors R3 and R4 are connected between the gate of the power switch tube Q3 and the gate of the power switch tube Q4.

3. The novel parallel current backflow prevention circuit according to claim 1, characterized in that: Transformer T2_1 couples the energy from the left circuit to the right.

4. The novel parallel current backflow prevention circuit according to claim 2, characterized in that: Capacitors C3 and C4 are used for input filtering, and capacitors C1 and C2 are used for output filtering.

5. The novel parallel current backflow prevention circuit according to claim 1 is characterized in that: In step S4, the time and amplitude judgment of abnormality is added to the DSP control algorithm. When the collected abnormal signal is greater than or less than the given time and amplitude, the DSP determines that the module is abnormal.

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