Motor control system and control method based on DSP

Abstract

The invention discloses a DSP-based motor control system and control method, and relates to the technical field of motor control. The method comprises the following steps: acquiring armature voltage and current signals, and preprocessing the voltage and current signals; a motor position signal is collected, and position information is calculated according to the motor position signal; a position loop is generated according to the position information, a current loop is generated according to the current signal, error calculation is carried out on two independent CPU cores by adopting a dynamic task allocation method based on double-closed-loop control of the current loop and the position loop, the CPU core 2 runs a control algorithm to carry out error calculation, and the CPU core 2 runs a control algorithm to carry out error calculation. The CPU core 1 performs external communication and performs task supervision and distribution based on a dynamic task distribution method; and generating a modulation signal according to the calculated error, and controlling the motor by using the modulation signal. According to the invention, a separation control algorithm is combined with external communication, so that the precision and speed of motor control are fully improved.

Description

Technical Field

[0001] The present invention relates to the technical field of motor control, and in particular to a motor control system and a control method based on DSP. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] With the development of electric vehicles, motor control algorithms must exhibit fast responsiveness, minimal overshoot, and good tracking performance to meet the requirements for high efficiency and power density. Traditional DSP control solutions, exemplified by the TMS320F28335 chip, rely solely on the DSP's (digital signal processor) internal peripherals such as PWM, UART, and ADC for controller communication, sampling, and control. The traditional TMS320F28335 control solution requires integrating external communication and control systems into a single core. This results in frequent external communication interruptions and heavy data throughput, requiring significant memory and CPU processing power, hindering the ability to achieve higher computational speeds. This can only be addressed by increasing the number of chips, which requires high-speed inter-chip communication to achieve real-time communication at the control level. However, mainstream DSPs lack high-speed data I / O peripherals, limiting the scalability of multi-chip solutions.

[0004] FPGAs offer the advantage of high-speed, parallel hardware operations, enabling the implementation of all critical real-time control algorithms, control logic, and communication functions, greatly enhancing the ability to meet high-precision control strategies. While single-FPGA control offers excellent real-time performance, a separate FPGA architecture requires custom-designed peripherals such as PWM modulation modules. Developing an FPGA chip architecture requires significantly more complex and costly development than traditional DSP architectures.

[0005] In summary, how to obtain high-performance processing capabilities without introducing high-cost control chips such as FPGAs, reducing development costs, and shortening development cycles has become a technical problem that needs to be urgently solved by existing technologies. Summary of the Invention

[0006] In response to the shortcomings of the existing technology, the purpose of the present invention is to provide a DSP-based motor control system and control method. By combining the separation control algorithm with external communication, it solves the problems of high difficulty and high cost of FPGA pre-development, and has higher performance processing capabilities than traditional DSP architecture, fully improving the accuracy and speed of motor control.

[0007] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0008] The first aspect of the present invention provides a DSP-based motor control method, including the following steps:

[0009] Collect armature voltage and current signals, and preprocess the voltage and current signals;

[0010] Collect motor position signals, and calculate position information based on the motor position signals;

[0011] Generate a position loop according to the position information, generate a current loop according to the current signal, and perform error calculation based on the dual closed-loop control of the current loop and the position loop by using a dynamic task allocation method on two independent CPU cores. Among them, CPU core 2 runs the control algorithm to perform error calculation, and CPU core 1 performs external communication and supervises and allocates tasks based on the dynamic task allocation method;

[0012] Generate a modulation signal according to the calculated error, and use the modulation signal to control the motor.

[0013] The second aspect of the present invention provides a DSP-based motor control system, including:

[0014] An ADC module for collecting armature voltage and current signals and preprocessing the voltage and current signals;

[0015] An EQEP module for collecting motor position signals and calculating position information based on the motor position signals;

[0016] A CPU core 2 module for generating a position loop according to the position information, generating a current loop according to the current signal, and performing error calculation by using the dual closed-loop control based on the current loop and the position loop;

[0017] An ePWM module for generating a modulation signal according to the calculated error and using the modulation signal to control the motor.

[0018] The third aspect of the present invention provides a medium on which a program is stored, and when the program is executed by a processor, it implements the steps in the DSP-based motor control method described in the first aspect of the present invention.

[0019] The fourth aspect of the present invention provides a device, including a memory, a processor, and a program stored on the memory and executable on the processor. When the processor executes the program, it implements the steps in the DSP-based motor control method described in the first aspect of the present invention.

[0020] The fifth aspect of the present invention provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the steps in the DSP-based motor control method described in the first aspect of the present invention.

[0021] The above one or more technical solutions have the following beneficial effects:

[0022] The present invention discloses a motor control system and a control method based on DSP, aiming to improve the accuracy and efficiency of motor control. Through the double closed-loop control of the position loop and the current loop, while achieving precise control of the motor torque, the motor does not deviate according to the predetermined trajectory. The algorithm of the present invention has the characteristics of fast responsiveness, small overshoot, and good followability.

[0023] Through the dual-core DSP architecture and modular API design, the system of the present invention realizes efficient data processing and control signal output. By allocating tasks on two independent CPU cores, CPU core 1 completes human-computer interaction and data processing, and CPU core 2 runs the control algorithm. This enables the two functions to be executed independently, realizing the separation of data interaction and motor control. By stripping the original communication and interaction functions of CPU core 2, the number of interrupts of CPU core 2 can be reduced, and the algorithm execution efficiency can be improved. At the same time, by utilizing the high real-time performance of the bare core of CPU core 2, highly real-time motor control is realized, and the PWM control frequency is increased. The present invention uses the on-chip 16-bit ADC and eQEP module to accurately collect the armature voltage, current, and position signals of the motor, and executes the double closed-loop control algorithm on CPU core 2 to generate PWM signals for motor control. The rich communication interfaces support efficient data exchange with other devices, enhancing the flexibility and adaptability of the system, and providing reliable technical support for industrial automation.

[0024] The present invention designs a motor controller for a motor control system based on the TMS320F28377D chip of Texas Instruments, which has two 32-bit C28x floating-point CPU cores. Based on the requirements of existing motors for high efficiency and high power density, the present invention designs a motor control system in which external communication and control algorithms are isolated, which can support signal processing of large amounts of data, and greatly improves the control rate and accuracy, meeting the requirements of fast response, high accuracy, and high flexibility of motor control. At the same time, the present invention does not need to introduce high-cost control chips such as FPGA. Under the background of the increasing application range and expanding application scope of motor controllers, the requirements of low development cost and short development cycle are realized.

[0025] The present invention designs a dynamic task allocation method with an interrupt nesting mechanism, which evenly distributes the computing tasks to CPU core 2, CLA1, and CLA2, enabling the algorithm to be processed in parallel by three cores, further improving the algorithm execution rate and control performance. And it is equipped with a corresponding three-level protection mechanism with low latency, which performs fault protection on the control process from three perspectives: CMPSS, CLA, and CPU core. Through the three-level fault protection mechanism, the impact of the fault state on the motor is reduced, and at the same time, the obstacle handling is simplified through the on-site protection function of the CPU core.

[0026] Advantages of additional aspects of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not unduly limit the present invention.

[0028] Figure 1 It is a flowchart of a DSP-based motor control method in Embodiment 1 of the present invention;

[0029] Figure 2 It is a structural diagram of a DSP-based motor control system in Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0031] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof;

[0032] Embodiment 1:

[0033] Embodiment 1 of the present invention provides a DSP-based motor control method, as Figure 1 shown, including the following steps:

[0034] Step 1: Collect armature voltage and current signals and preprocess the voltage and current signals.

[0035] Among them, the preprocessing step includes linearly transforming and restoring the collected signals.

[0036] In a specific embodiment, a on-chip 16-bit ADC module is used to collect the armature voltage and current signals of the motor. The ADC module provides high-precision sampling capabilities to ensure the accuracy of the input data.

[0037] Since the ADC acquisition range of the DSP chip is only 0 - 3.3V, the acquired analog signal is the signal processed by the AFE (Analog Front End). It is first restored by linear transformation and then sent into the current loop algorithm to obtain the PWM modulation signal. The PPB (Post-Processing Block) in the ADC module has overvoltage and overcurrent protection functions and can directly turn off the output of the PWM module; at the same time, it supports fault output and shutdown input and can directly turn off the output of the PWM module.

[0038] Step 2: Collect the motor position signal and calculate the position information according to the motor position signal. After comparing with the predetermined position, a position error is generated as the input signal of the current loop to generate the current loop control signal.

[0039] In a specific implementation, the motor position signal is obtained through a motor encoder, and a three-wire incremental encoder is adopted. The motor rotation angle is obtained by counting the number of pulses in phases A and B, and phase Z is used to represent the counting initial. The high-level pulse of phase Z can clear the pulse counters of phases A and B. The motor rotation direction is identified and read out from the phase relationship between phases A and B.

[0040] Step 3: Generate a position loop according to the position information and generate a current loop according to the current signal. Error calculation is performed based on the dual closed-loop control of the current loop and the position loop by using the dynamic task allocation method on two independent CPU cores.

[0041] Among them, the tasks are allocated on two independent CPU cores. CPU core 2 runs the control algorithm for error calculation, and CPU core 1 completes human-computer interaction and data processing. Specifically, it performs external communication and supervises and allocates tasks based on the dynamic task allocation method.

[0042] In a specific implementation, in this embodiment, CPU core 1 and CPU core 2 of the dual-core DSP28377D are respectively responsible for external communication and the control algorithm, and the inter-core communication is carried out through the IPC communication protocol. This design supports the real-time processing of large amounts of data, greatly improving the real-time performance, flexibility, computing power, and computing accuracy of the controller. At the same time, the modulation of the PWM control signal is completed by a separate PWM peripheral device, eliminating the need for independent development and greatly reducing the development cycle and development cost.

[0043] In the control scheme, CPU core 2 (CORE2) focuses on executing the motor control algorithm. This includes the dual closed-loop control of the current loop and the position loop. The current loop is used to adjust the torque output of the motor, and the position loop is used to ensure that the motor operates along the predetermined trajectory.

[0044] The initial motor speed is 0, and the soft start algorithm starts to execute. By sampling the armature voltage and current cycle by cycle, the duty cycle of the PWM output is dynamically controlled to control the current, voltage, and power during startup. After starting up to the rated current and voltage, the soft start ends, and the double closed-loop algorithm of the position loop and current loop starts to execute. According to the set current reference value and the actually collected current value, the CPU core 2 uses the PI or PID control algorithm to adjust the current error and generate the PWM modulation signal. The position loop calculates the position error by comparing the actual position and the target position of the motor, and adjusts the output of the current loop based on this error. At the same time, when overcurrent, overvoltage, or external fault input is detected, the PWM is immediately turned off. After the corresponding event occurs, the cycle-by-cycle overcurrent protection algorithm starts to execute. By intermittently outputting low-frequency, positive narrow pulses through the PWM module, if the overcurrent or overvoltage event still exists, the PWM output is turned off; if the overcurrent or overvoltage time disappears, the soft start algorithm starts to execute again until the motor works normally.

[0045] In the process of calculating the error in this embodiment, a dynamic task allocation method with an interrupt nesting mechanism is designed. Specifically, a real-time operating system runs in the CPU core 1 to monitor the load status of the dual CPU cores and the dual CLAs. Interrupt service programs are preset in the CLAs to complete tasks such as current loop, position loop, FOC, and SVPWM modulation respectively. The CPU core 1 monitors the occupancy status of the CPU core 2. If the CPU core 2 is fully loaded, the task allocation of the CLA1 and CLA2 is regulated by triggering a specified interrupt. If the CPU core 2 is in an idle state, the processing tasks will be preferentially arranged to be executed by the CPU core 2. The CPU core 1 works at a low main frequency in the absence of external communication. After the UART interrupt is triggered, it resumes to the maximum main frequency, executes the communication data transfer and human-computer interaction functions, and then returns to the low main frequency mode.

[0046] According to the corresponding rate of the algorithm and the real-time performance of the interrupt function, the interrupt nesting mechanism is divided into three priorities: the hardware protection of CMPSS is the highest priority to ensure system security; the current loop algorithm is the second priority; the position loop algorithm is the third priority. The corresponding interrupt priorities are realized by the CPU core 1 dynamically controlling the interrupt vector table to bind the interrupt priorities with the tasks and dynamically control the interrupt priorities. The CPU core 1 first queries the status of the CPU core 2 to decide whether to allocate tasks to the CLA1 and CLA2; if tasks are allocated to the CLA1 and CLA2, it decides the allocation object and the specific tasks to be allocated. After the allocated tasks are determined, the interrupt vector of the CLA1 or CLA2 in the interrupt vector table is assigned to the corresponding processing function address, and then the CPU core 1 triggers the interrupt to execute the corresponding function in the CLA1 or CLA2.

[0047] Based on the above dynamic task allocation method, a low-latency three-level protection mechanism is designed in this embodiment. The first level is hardware protection based on the on-chip CMPSS (window comparator) of TMS320F28377D. The second level is fault diagnosis of the interrupt service program based on the CLA (control law accelerator). The third level is lockstep operation, field protection, and system recovery based on the CPU core.

[0048] Among them, CMPSS faces component-level faults, including overcurrent, overvoltage, overtemperature, etc. of power devices. CLA faces device-level faults, including excessive harmonics, damage to power devices, etc. The CPU core faces program protection, including lockstep operation, field protection, and backup cut-in. CMPSS monitors the current and voltage of the device. When some data exceeds the threshold, CMPSS requests an interrupt from CLA and the CPU core. CLA starts to perform fault diagnosis to judge the working state of the power device. For power devices that have been burned out, the PWM output is directly turned off; for normal power devices, the CPU core is uploaded to perform backup cut-in, and the output power is continuously observed. If the overcurrent fault disappears, only the upload is performed without turning off the PWM output; if the overcurrent state still exists, the PWM output is turned off, and the fault state is uploaded. CLA executes the fixed-point FFT algorithm to monitor current harmonics. When the harmonics exceed 5%, CLA requests an interrupt from the CPU core, uploads the fault state, and does not turn off the PWM output. Temperature control is jointly completed by CMPSS and CLA. The main control temperature is monitored by CLA and the on-chip ADC, and the temperature of the power device is monitored by CMPSS. After the power device overtemperature, CMPSS requests an interrupt from CLA. CLA judges the current state. If the forced heat dissipation is not turned on, the external heat dissipation is turned on; if the overtemperature state still exists, the PWM output is turned off, and the fault state is reported to the CPU core. The main control temperature is monitored by CLA. The on-chip ADC collects the temperature of the main control chip. After the main control overtemperature event occurs, ADC requests an interrupt from CLA, and CLA controls to preferentially turn on the forced heat dissipation. After the forced heat dissipation is turned on and the overtemperature event still exists, the main control chip starts to be gradually downclocked, decreasing the rated main frequency by 5% successively. Program fault detection is jointly completed by the dual-core CPU core. Hardware lockstep operation is performed inside the CPU core. For the control algorithms of the current loop and the position loop, the dual cores execute synchronously, and the output results are compared by CPU core 2. If the comparison results are consistent, they are sent to the PWM module for modulation output; if they are inconsistent, the PWM output is turned off, and all the data in the status register inside the CPU core is transferred to the external ROM. At the same time, under normal operation, the CPU core controls the off-chip RAM to save the sampled data within 1 s. After the CPU core receives the fault interrupt, the data is immediately transferred to the off-chip ROM for storage and uploaded through the serial port to complete field protection.

[0049] Combined with the dynamic task allocation method mentioned above, the computing tasks are evenly distributed to CPU core 2, CLA1, and CLA2, enabling the algorithm to be processed in parallel by three cores, further improving the algorithm execution rate and control performance. At the same time, through a three-level fault protection mechanism, the impact of the fault state on the motor is reduced, and the obstacle handling is simplified through the on-site protection function of the CPU core.

[0050] Step 4: Generate a modulation signal based on the calculated error and use the modulation signal to control the motor.

[0051] In a specific embodiment, as Figure 2 shown, the reference signal generated by the control algorithm is transmitted to the on-chip ePWM module. This module generates 24 PWM output signals based on the input signal. The PWM signals are output as 5V square waves after level conversion. The PWM signals are directly used to control the power electronic devices in the inverter circuit. Through precise PWM signal modulation, precise control of the motor speed, direction, and torque is achieved.

[0052] In this embodiment, the controller uses communication protocols such as IIC, SPI, and CAN to exchange data with other controllers and devices, ensuring efficient communication inside and outside the system. The equipped 2-channel UART interface is used for data and instruction interaction with the host computer, facilitating system monitoring and parameter adjustment.

[0053] Embodiment 2:

[0054] The second embodiment of the present invention provides a motor control system based on DSP, as Figure 2 shown, a high-performance motor controller software architecture based on TI's DSP chips is developed. This architecture aims to improve the accuracy and efficiency of motor control. The DSP (such as TMS320F2837xD, TMS320F2838xD, etc.) chips integrate two C2000 cores, and the cores communicate through IPC and shared RAM. CPU core 1 completes human-machine interaction and data processing, and CPU core 2 runs the control algorithm. Through the dual-core DSP architecture, combined with high-precision signal acquisition and diverse control signal output capabilities. Through this innovative design, the controller achieves high-speed data processing and flexible communication interfaces, and can effectively handle complex control tasks. At the same time, its modular hardware design and powerful processing performance provide reliable technical support for industrial automation applications.

[0055] In the architecture, the dual-core processor operates using the heterogeneous multi-processing (AMP) architecture. CPU core 1 (CORE1) is responsible for communication interaction and the operation of the on-chip operating system, while the motor control algorithm is executed on CPU core 2 (CORE2). The two CPU cores communicate through the IPC (Inter-Processor Communication) peripheral, ensuring that the communication function is independent of the real-time processing tasks and improving the processing capacity of the overall controller.

[0056] The specific structure includes:

[0057] The ADC module is used to collect the armature voltage and current signals and preprocess the voltage and current signals; the on-chip 16-bit ADC module is used to collect the armature voltage and current signals of the motor. The ADC module provides high-precision sampling capabilities to ensure the accuracy of the input data. Since the ADC module is integrated inside the chip, CPU core 1 and CPU core 2 can directly access its registers to efficiently read and process the signal data.

[0058] The peripheral module is used to collect the motor position signal and calculate the position information based on the motor position signal; in the control scheme, CPU core 2 (CORE2) focuses on executing the motor control algorithm. This includes the double closed-loop control of the current loop and the position loop. The current loop is used to regulate the torque output of the motor, while the position loop is used to ensure that the motor operates along the predetermined trajectory.

[0059] It is carried out by the enhanced quadrature encoder pulse (eQEP) peripheral. This module is designed specifically for incremental encoder signal processing. CPU core 1 and CPU core 2 obtain accurate position information by accessing the eQEP registers.

[0060] The position signal of the motor is processed by the enhanced quadrature encoder pulse (eQEP) built into the DSP. The eQEP is designed specifically for incremental encoders and can accurately capture the position information of the motor, which is particularly important for the position control loop.

[0061] The CPU core 2 module is used to generate the position loop based on the position information, generate the current loop based on the current signal, and perform error calculation using the double closed-loop control based on the current loop and the position loop.

[0062] Based on the set current reference value and the actually collected current value, CPU core 2 uses the PI or PID control algorithm to adjust the current error and generate the PWM modulation signal. The position loop calculates the position error by comparing the actual position and the target position of the motor, and adjusts the output of the current loop based on this error.

[0063] The ePWM module is used to generate the modulation signal based on the calculated error and control the motor using the modulation signal.

[0064] The reference signal generated by the control algorithm is transmitted to the on-chip ePWM module. This module generates 24 PWM output signals according to the input signal. After level conversion, the PWM signals are output as 5V square waves, which are suitable for driving the inverter circuit on the controller board. The PWM signals are directly used to control the power electronic devices in the inverter circuit. Through precise PWM signal modulation, precise control of the motor speed, direction, and torque is achieved.

[0065] The controller uses communication protocols such as IIC, SPI, and CAN to exchange data with other controllers and devices, ensuring efficient communication inside and outside the system. The equipped 2-channel UART interface is used for data and instruction interaction with the host computer, facilitating system monitoring and parameter adjustment.

[0066] For some devices with CLB (Configurable Logic Block) (such as TMS320F28379D) in this embodiment, a new PWM control logic is designed, which supports instant shutdown and error output, improving system scalability and security. By designing a software ADCPPB (ADC Post-Processing Block) module, the CPU core calculation overhead is reduced, and hardware overcurrent and overvoltage protection are achieved. The PWM modulation signal output is directly turned off through the post-processing block, further improving system security.

[0067] In this embodiment, CPU core 1 and CPU core 2 of the dual-core DSP28377D are respectively responsible for external communication and control algorithms, and communicate with each other through the IPC communication protocol. This design supports real-time processing of large amounts of data, greatly improving the real-time performance, flexibility, computing power, and computing accuracy of the controller. At the same time, the modulation of the PWM control signal is completed by a separate PWM peripheral, eliminating the need for independent development, and greatly reducing the development cycle and development cost.

[0068] Embodiment Three:

[0069] Embodiment Three of the present invention provides a medium on which a program is stored, and when the program is executed by a processor, the steps in the DSP-based motor control method described in Embodiment One of the present invention are implemented.

[0070] Embodiment Four:

[0071] Embodiment Four of the present invention provides a device, including a memory, a processor, and a program stored on the memory and executable on the processor. When the processor executes the program, the steps in the DSP-based motor control method described in Embodiment One of the present invention are implemented.

[0072] Embodiment Five:

[0073] Embodiment 5 of the present invention provides a computer program product, including a computer program which, when executed by a processor, implements the steps in the DSP-based motor control method described in Embodiment 1 of the present invention.

[0074] The steps involved in Embodiments 2, 3, 4, and 5 above correspond to those in Method Embodiment 1. For specific implementation manners, reference may be made to the relevant description part of Embodiment 1. The term "computer-readable storage medium" should be understood to include a single medium or multiple media containing one or more instruction sets; it should also be understood to include any medium that can store, encode, or carry an instruction set for execution by a processor and cause the processor to execute any method in the present invention.

[0075] Those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general-purpose computer device. Optionally, they can be implemented by program codes executable by a computing device, so that they can be stored in a storage device and executed by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. The present invention is not limited to any specific combination of hardware and software.

[0076] Although the specific implementation manners of the present invention have been described above in conjunction with the accompanying drawings, this is not a limitation on the protection scope of the present invention. Those skilled in the art should understand that, based on the technical solutions of the present invention, various modifications or deformations that can be made without creative efforts by those skilled in the art are still within the protection scope of the present invention.

Claims

1. A motor control method based on DSP, characterized in that It includes the following steps: Collect armature voltage and current signals, and preprocess the voltage and current signals; Collect motor position signals, and calculate position information based on the motor position signals; Adopt a dynamic task allocation method on two independent CPU cores to calculate errors based on the dual closed-loop control of the current loop and the position loop. Among them, CPU core 2 runs the control algorithm to calculate errors, and CPU core 1 conducts external communication and supervises and allocates tasks based on the dynamic task allocation method; Generate a modulation signal according to the calculated error, and use the modulation signal to control the motor.

2. The DSP-based motor control method according to claim 1, wherein, Preprocessing the voltage and current signals is to perform linear transformation reduction on the collected signals.

3. The DSP-based motor control method according to claim 1, wherein The specific steps for calculating position information based on the motor position signal are: Obtain the motor position signal through the motor encoder; Obtain the motor rotation angle by counting the number of pulses in phases A and B; The motor rotation direction is identified and read out from the phase relationship between phases A and B.

4. The DSP-based motor control method according to claim 1, characterized in that, The specific steps for CPU core 1 to conduct external communication and supervise and allocate tasks based on the dynamic task allocation method are: A real-time operating system runs inside CPU core 1 to monitor the load status of the dual CPU cores and the dual CLAs. Specifically, preset interrupt service programs are inside the CLA to complete the current loop, position loop, FOC, and SVPWM modulation tasks respectively. CPU core 1 monitors the occupancy status of CPU core 2. If CPU core 2 is fully loaded, the task allocation of CLA1 and CLA2 is regulated by triggering a specified interrupt. If CPU core 2 is in an idle state, the processing tasks will be preferentially arranged to be executed by CPU core 2.

5. The DSP-based motor control method according to claim 2, wherein Introduce an interrupt nesting mechanism in the dynamic task allocation method, and divide the interrupt nesting mechanism into three priorities: the hardware protection of CMPSS is the highest priority to ensure system security; the current loop algorithm is the second priority; The position loop algorithm is the third priority.

6. The DSP-based motor control method according to claim 1, wherein, Equip a low-latency three-level protection mechanism based on the above dynamic task allocation method. The first level is the hardware protection based on the on-chip CMPSS of TMS320F28377D, the second level is the fault diagnosis of the interrupt service program based on the CLA, and the third level is the lockstep operation, field protection and system recovery based on the CPU core.

7. A motor control system based on DSP, characterized in that, It includes: An ADC module, which is used to collect armature voltage and current signals, and preprocess the voltage and current signals; A peripheral module, which is used to collect motor position signals, and calculate position information based on the motor position signals; A CPU core 2 module, which is used to generate a position loop according to the position information, generate a current loop according to the current signal, and calculate errors by using the dual closed-loop control based on the current loop and the position loop; An ePWM module, which is used to generate a modulation signal according to the calculated error, and use the modulation signal to control the motor.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the DSP-based motor control method described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, Among them, multiple instructions are stored, and the instructions are suitable for being loaded and executed by the processor of the terminal device to implement the DSP-based motor control method described in any one of claims 1-7.

10. A terminal device, characterized in that, It includes a processor and a computer-readable storage medium. The processor is used to implement various instructions; the computer-readable storage medium is used to store multiple instructions, and the instructions are adapted to be loaded and executed by the processor for the DSP-based motor control method according to any one of claims 1-7.

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