Multi-mode power amplifier with variable load impedance

Abstract

Aspects of the present disclosure relate to a multimode power amplifier circuit. A power amplifier circuit may include a first power amplifier core, a second power amplifier core, an output combiner, and an adjustable termination impedance circuit connected to an output combiner port. The adjustable termination circuit may provide different terminations for different modes of the multimode power amplifier circuit. In some embodiments, the different modes may include a Doherty mode, a segmentation mode, and / or a balanced mode. In some applications, the multimode power amplifier circuit may operate in different modes based on one or more of a load impedance, a voltage standing wave ratio change, or a beam angle.

Description

Technical Field

[0001] The disclosed technology relates to radio frequency systems and power amplifiers. Embodiments of the present disclosure relate to multi-mode power amplifiers. Background Art

[0002] Radio systems can transmit and receive signals in the form of electromagnetic waves having frequencies in the range of approximately 30 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems can be used for wireless communication, such as cellular communication and / or other wireless network communication.

[0003] Radio systems that transmit signals typically include a power amplifier for amplifying a radio frequency signal for transmission via one or more antennas. Power amplifiers can encounter technical challenges related to efficiency, output power, and / or linearity. There is a need for high-performance power amplifiers. Summary of the Invention

[0004] The innovations described in the claims have several aspects, none of which are solely responsible for its desirable attributes. Without limiting the scope of the claims, some of the prominent features of the present disclosure will now be briefly described.

[0005] One aspect of the present invention is a power amplifier system including a first power amplifier core, a second power amplifier core, an output combiner, and an adjustable termination impedance circuit. The first power amplifier core is configured to provide a first radio frequency signal. The second power amplifier core is configured to provide a second radio frequency signal. The output combiner is configured to receive the first radio frequency signal and the second radio frequency signal. The output combiner includes an output port and an isolation port. The adjustable termination impedance circuit is electrically connected to the isolation port. The adjustable termination impedance circuit is configured to provide different terminations for the isolation port in different modes. The different modes include a segmented power amplifier mode.

[0006] The different modes can include a Doherty mode. The different modes can include a balanced mode.

[0007] The adjustable termination impedance circuit can be configured to adjust the termination impedance at the isolation port based on an indication of a change in voltage standing wave ratio (VSWR).

[0008] The different modes can include three modes. The three modes can include a Doherty mode, a segmented power amplifier mode, and a balanced mode. For a change in voltage standing wave ratio (VSWR) within the Doherty mode range, the power amplifier system can operate in the Doherty mode, for a VSWR change greater than the Doherty mode and less than the balanced mode, it can operate in the segmented power amplifier mode, and for a VSWR change greater than the segmented power amplifier mode, it can operate in the balanced mode.

[0009] The adjustable termination impedance circuit can provide a resistive termination in a segmented power amplifier mode and a low impedance or high impedance termination in another mode. For example, the adjustable termination impedance circuit can provide a resistive termination in a segmented power amplifier mode and a short circuit termination in another mode. The adjustable termination impedance circuit can provide a first resistive termination in a segmented power amplifier mode and a termination impedance in the range of 25 ohms to 100 ohms in another mode. For example, the adjustable termination impedance circuit can provide a first resistive termination in a segmented power amplifier mode and a 50-ohm termination in another mode.

[0010] In the segmented power amplifier mode, the first power amplifier core can be biased differently from the second power amplifier core. In the segmented power amplifier mode, both the first power amplifier core and the second power amplifier core can be activated.

[0011] The adjustable termination impedance circuit can provide a resistive termination in the segmented power amplifier mode. The power amplifier system can adaptively bias the second power amplifier core in the segmented power amplifier mode. The biasing signal for the second power amplifier core can include at least one first tone component having a non-zero frequency to eliminate the non-linearity of the second power amplifier core in the segmented mode.

[0012] The power amplifier system can include an antenna array. The power amplifier system can be configured to perform beam scanning using the antenna array. The adjustable termination impedance circuit can be configured to adjust the termination impedance at the isolation port based on an indication of the beam angle. The power amplifier system can include a second multi-core power amplifier operable in different modes. The second multi-core power amplifier can be configured to drive a second antenna of the antenna array. The second multi-core power amplifier can be configured to operate in the same mode as the first and second power amplifier cores.

[0013] The output combiner can be a hybrid combiner. The hybrid combiner can be configured to combine the second RF signal with a phase shift in the range of 60 degrees to 130 degrees relative to the first RF signal. For example, the hybrid combiner can be configured to combine the second RF signal with a 90-degree phase shift relative to the first RF signal.

[0014] The power amplifier system can include a hybrid input splitter configured to phase shift the second RF signal by an angle in the range of 60 degrees to 130 degrees relative to the first RF signal.

[0015] The first power amplifier core may be included in a first power amplifier section. The first power amplifier section may include a first input matching circuit connected to the input of the first power amplifier core and a first adaptive biasing circuit connected to the first power amplifier core. The first input matching circuit and the first adaptive biasing circuit may be adjusted in different modes. The second power amplifier core may be included in a second power amplifier section. The second power amplifier section may include a second input matching circuit connected to the input of the second power amplifier core and a second adaptive biasing circuit connected to the second power amplifier core. The second input matching circuit and the second adaptive biasing circuit may be adjusted in different modes. The first input matching circuit may include at least one controllable passive element. The first input matching circuit may be adjusted based on an indication of at least one of a reflected power change or a load voltage standing wave ratio (VSWR) change. The first input matching network and / or the second input matching network may be controlled to provide a phase shift between the input signals of the first power amplifier core and the second power amplifier core, thereby increasing and / or maximizing the combined output signal after the output combiner. Each of the first adaptive biasing circuit and the second adaptive biasing circuit may generate a respective biasing signal that includes a direct current (DC) biasing component and at least one non-DC radio frequency tone. The magnitude of the DC biasing component and the magnitude of the non-DC radio frequency tone are adjusted based on an indication of a reflected power change.

[0016] Another aspect of the present disclosure is a power amplifier system including a first power amplifier core, a second power amplifier core, a hybrid combiner, and an adjustable termination impedance circuit. The first power amplifier core is configured to provide a first radio frequency signal. The second power amplifier core is configured to provide a second radio frequency signal. The hybrid combiner is configured to receive the first radio frequency signal and the second radio frequency signal. The hybrid combiner includes an output port and an isolation port. The adjustable termination impedance circuit is electrically connected to the isolation port. The adjustable termination impedance circuit is configured to provide different terminations for the isolation port in at least three different modes of the power amplifier system.

[0017] The three different modes may include a Doherty mode, a balanced mode, and another mode.

[0018] The adjustable termination impedance circuit may be adjusted based on an indication of a reflected power change. The power amplifier system may be configured to operate in three different modes within different ranges of load voltage standing wave ratio changes.

[0019] Another aspect of the present disclosure is a method for multi-mode radio frequency (RF) signal amplification. The method includes amplifying an RF signal in a segmented mode by a power amplifier circuit, the segmented mode being different from the Doherty mode and the balanced mode, the power amplifier circuit including a first power amplifier core, a second power amplifier core, an output combiner configured to combine output signals from the first and second power amplifier cores, and an adjustable termination impedance circuit connected to an output combiner port; adjusting a termination impedance provided by the adjustable termination impedance circuit for a mode different from the segmented mode; and amplifying the RF signal in different modes.

[0020] To summarize the present disclosure, certain aspects, advantages, and novel features of the innovation are described herein. It should be understood that not all of these advantages may be achieved in accordance with any particular embodiment. Thus, the innovation may be embodied or implemented in a manner that realizes or optimizes one or a group of the advantages taught herein, without necessarily realizing other advantages taught or suggested herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Embodiments of the present disclosure will be described by way of non-limiting examples with reference to the accompanying drawings.

[0022] Figure 1 is a schematic diagram of a radio frequency system having a phased antenna array according to an embodiment.

[0023] Figure 2 is a graph showing the relationship between power added efficiency (PAE) and output power of a Doherty power amplifier at different voltage standing wave ratios (VSWRs) compared to a normalized ideal class B power amplifier.

[0024] Figure 3A is a schematic diagram of a multi-mode power amplifier circuit according to an embodiment.

[0025] Figure 3B is according to an embodiment Figure 3A schematic diagram of an example input matching circuit of a multi-mode power amplifier circuit.

[0026] Figure 3C is according to an embodiment Figure 3A schematic diagram of an example linearization and adaptive biasing circuit of a multi-mode power amplifier circuit.

[0027] Figure 3D is according to an embodiment Figure 3A schematic diagram of an example hybrid combiner of a multi-mode power amplifier circuit.

[0028] Figure 3E is according to an embodiment Figure 3A schematic diagram of an example switchable termination impedance circuit of a multi-mode power amplifier circuit.

[0029] Figure 4Schematic diagram of a multi - mode power amplifier circuit with power detection and control circuitry according to an embodiment.

[0030] Figure 5 Is a Smith chart related to power amplifier load impedances with different VSWRs, showing different operating modes of the multi - mode power amplifier within different VSWR ranges.

[0031] Figure 6A Schematic diagram of a power amplifier system with an antenna array performing beam scanning according to an embodiment. Figure 6B Table summarizing example control bits for beam positions according to an embodiment.

[0032] Figure 7 Is according to an embodiment Figure 3A Schematic diagram of the power amplifier circuit in Doherty mode.

[0033] Figure 8A Is related to Figure 7 Smith chart corresponding to the power amplifier circuit. Figure 8B Is Figure 7 Graph of the gain of the power amplifier circuit versus output power. Figure 8C Is Figure 7 Graph of the PAE of the power amplifier circuit versus output power.

[0034] Figure 9A Is according to an embodiment Figure 3A Schematic diagram of the power amplifier circuit in segmented mode. Figure 9B Is Figure 9A Graph of the bias voltage of the power amplifier section of the power amplifier circuit versus output power. [[ID=2 Is ​ Graph of the RF power of the power amplifier section of the power amplifier circuit versus output power.

[0035] ​ Is related to ​ Smith chart corresponding to the power amplifier circuit. ​ Is ​ Graph of the gain of the power amplifier circuit versus output power. ​ Is ​ Graph of the PAE of the power amplifier circuit versus output power.

[0036] ​ Is according to an embodiment ​ Schematic diagram of the power amplifier circuit in balanced mode.

[0037] ​ Is related to ​ Smith chart corresponding to the power amplifier circuit.​ is ​ a graph showing the relationship between the gain and the output power of a power amplifier circuit. ​ is ​ a graph showing the relationship between the PAE and the output power of a power amplifier circuit.

[0038] ​ is ​ a graph showing the relationship between the gain and the output power of a power amplifier circuit in Doherty mode, segmented mode, and balanced mode. ​ is ​ a graph showing the relationship between the PAE and the output power of a power amplifier circuit in Doherty mode, segmented mode, and balanced mode. DETAILED DESCRIPTION

[0039] The following detailed description of certain embodiments presents various descriptions of the specific embodiments. However, the innovations described herein can be embodied in many different ways, for example, as defined and covered by the claims. In this specification, reference is made to the accompanying drawings, in which like reference numerals may represent like or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Further, it should be understood that some embodiments may include more elements and / or subsets of the elements shown in the drawings. Additionally, some embodiments may incorporate any suitable combination of features from two or more of the drawings.

[0040] Power amplifiers are an important part of wireless transmitters. Power amplifiers can make significant contributions to overall system efficiency, linearity, and / or output power. In certain applications, a power amplifier can drive an individual antenna element of a phased antenna array.

[0041] High back-off efficiency can be achieved using various power amplifier (PA) architectures, such as Doherty, outphasing PA, or segmented PA. Modern communication systems require these efficient designs to reduce system power consumption, reduce cooling costs, and / or save battery life. Such power amplifier architectures can employ load modulation techniques to improve the back-off efficiency of the power amplifier. These power amplifier architectures can be designed and / or optimized to operate at a specific optimum load impedance (usually 50 ohms).

[0042] Due to antenna element coupling causing the power amplifier load impedance to deviate from the optimum value, voltage standing wave ratio (VSWR) variations may occur. Such VSWR variations can significantly degrade the performance of the power amplifier in a power amplifier system. For example, without compensation, VSWR variations can reduce one or more of efficiency, linearity, or output power. PAs employing load modulation techniques are more sensitive to load impedance variations than other PAs.

[0043] The present disclosure provides technical solutions for improving the performance of a power amplifier system when the load impedance changes. For example, the present disclosure provides technical solutions for improving the VSWR change sensitivity and achieving high efficiency by operating a multi-mode power amplifier circuit in different modes for different VSWR ranges and / or different beam positions. Such a multi-mode power amplifier circuit can be implemented in a millimeter wave (mmWave) beamformer for fifth generation (5G) and / or sixth generation (6G) wireless communication technologies.

[0044] Aspects of the present disclosure relate to a multi-mode power amplifier circuit, in which the power amplifier operates in different modes for different load impedances. The multi-mode power amplifier circuit can operate in different modes for different VSWR variations and / or different beam angles related to beam control. For multiple-input multiple-output (MIMO) and massive MIMO systems, the multi-mode PA can be used to improve the PA's sensitivity to VSWR variations, where the VSWR of the PA may vary due to limited isolation between adjacent channels within the MIMO system. The multi-mode power amplifier circuit can include a power amplifier core, an output combiner (e.g., a hybrid combiner), and an adjustable termination circuit. The output combiner can combine the output signals from the power amplifier core. The adjustable termination circuit can provide different terminations for the output combiner for different operating modes. The different operating modes can include a segmented power amplifier mode and at least one other operating mode. The at least one other operating mode can include a Doherty mode and / or a balanced mode, and / or at least one of class A mode, class B mode, class AB mode, class C mode, or class F mode PA. The multi-mode power amplifier circuit can adjust one or more of the power amplifier bias signal, the adaptive bias signal, the input matching network, or the output matching network.

[0045] A multi-core power amplifier can achieve high efficiency and linearity. An exemplary multi-core power amplifier is disclosed in U.S. Patent Publication No. 2022 / 0094306, the entire content and all purposes of which are incorporated herein by reference. For example, the multi-core power amplifier can be implemented in 5G and / or sixth generation (6G) phased array antenna systems and applications. Through the technical solutions disclosed herein, high efficiency and low VSWR sensitivity in such systems and applications can be achieved.

[0046] The power amplifier can drive an antenna array for beamforming applications. For example, such a power amplifier can be included in a cellular base station, an access point, a repeater, a relay, another network node, a router, a user equipment, etc. An example radio frequency system having an antenna array and a power amplifier will be discussed with reference to ​ an antenna array and a power amplifier will be discussed.

[0047] ​FIG. 0 is a schematic diagram of a radio frequency system 10 having a phased antenna array 12 according to an embodiment. In some applications, the radio frequency system 10 may be included in a network node, such as a cellular base station. The phased antenna array 12 includes an array of antenna elements 14. The radio frequency system 10 includes a plurality of processing channels, each processing channel associated with a respective antenna element 14. Each processing channel may include a transmit path 15 and a receive path 16. Switches 17A and 17B may selectively electrically couple the transmit path 15 or the receive path 16 to the antenna element 14 and a transceiver ( ​ not shown). Each transmit path 15 includes a power amplifier 18. The radio frequency system 10 may use the antenna elements 14 to perform beam scanning.

[0048] The antenna element 14 is driven by the power amplifier 18 in the transmit path 15. In some applications, the power amplifier 18 may include a multi-mode power amplifier circuit according to any suitable principles and advantages disclosed herein. When the radio frequency system 10 preforms beam scanning, the impedance of the antenna element 14 may vary. This impedance variation may be due to coupling with other antenna elements 14 in the phased antenna array 12. A power detection circuit 19 for the transmit path may detect an indication of reflected power, such as VSWR. This indication of reflected power may indicate the impedance of the antenna element 14. The power detection circuit 19 may include a radio frequency coupler and a power detector.

[0049] In ​ the radio frequency system 10, even for a well-designed relatively low-coupling antenna array, there may be a VSWR variation of 2:1 or 3:1. At small beam scanning angles, the VSWR variation of the antenna impedance can reach 2:1. At larger beam scanning angles, the VSWR variation can reach 3:1 or even 4:1. The VSWR variation caused by antenna element coupling causes the power amplifier load impedance (ZL) to deviate from its optimum value. This can significantly reduce one or more of the power amplifier's efficiency, output power, gain, and linearity. As described above, a high back-off efficiency power amplifier employing load modulation techniques, such as a Doherty power amplifier, is more sensitive to load impedance variations than some other power amplifiers.

[0050] ​ FIG. 14 shows a graph of power added efficiency (PAE) versus output power of a Doherty power amplifier for different VSWR variations, compared to a normalized ideal class B power amplifier. ​It is shown that for a Doherty power amplifier with an optimal load impedance of 50 ohms, the PAE at 6 dB back-off is more than 2.1 times that of an ideal class B power amplifier. However, under a VSWR variation of 2:1, the PAE of the Doherty power amplifier at 6 dB back-off drops to more than 1.2 times that of the ideal class B power amplifier. In the case of a 4:1 VSWR variation, the 6 dB back-off PAE of the Doherty power amplifier is 0.8 times less efficient than that of the ideal class B power amplifier. ​ The graph in shows that the Doherty power amplifier has an ideal PAE when the load impedance is equal to or close to the optimal load impedance.

[0051] ​ FIG. is a schematic diagram of a multimode power amplifier circuit 30 according to an embodiment. The multimode power amplifier circuit 30 may be included in a power amplifier system that also includes an antenna. Such a power amplifier system may be referred to as a multimode power amplifier system. The multimode power amplifier circuit 30 supports multiple operating modes across one or more of beam scanning, load impedance variation, or load VSWR variation. In certain applications, the multiple modes may include at least three modes. The multiple modes may include any suitable modes, including but not limited to Doherty mode, segmented mode, and balanced mode. To operate the multimode power amplifier circuit 30 in different modes, the terminal impedance and the power amplifier bias may be adjusted. Additionally, the impedance of one or more matching circuits may be adjusted for different modes.

[0052] In some embodiments, the multi-mode power amplifier circuit 30 can operate in three modes: Doherty mode, segmented mode, and balanced mode. The Doherty mode can be used for hole-side operation and / or typical load impedance environments. In the Doherty mode, the multi-mode power amplifier circuit 30 can support high power amplifier output power Pout and optimal back-off efficiency operation. The Doherty mode can be used for a first range of VSWR variations. For example, the Doherty mode can be used for VSWR variations up to 1.2:1. The Doherty mode can be used for a second range of VSWR variations, where the second range is higher than the first range and lower than a third range of the balanced mode. The segmented mode can be used for relatively small beam scan angles and / or moderate load impedance variations, such as variations up to 2:1 VSWR. The segmented mode can be used for larger load impedance variations than the Doherty mode operation. In the segmented mode, the multi-mode power amplifier circuit 30 can achieve the target power amplifier output power Pout with at least moderate efficiency operation. The multi-mode power amplifier circuit 30 in the segmented mode can achieve better efficiency, output power at power amplifier saturation (Psat), and 1 dB compression point (P1dB) than the Doherty mode under 2:1 VSWR variations. The balanced mode can involve adaptive power amplifier biasing for relatively large beam scan angles and / or relatively large load impedance variations, such as VSWR variations greater than 2:1. In the balanced mode, the multi-mode power amplifier circuit 30 can achieve near-target Psat, near-target P1dB, and PAE better than the Doherty mode or the segmented mode under high VSWR variations (such as VSWR variations greater than 2:1).

[0053] As shown, the multi-mode power amplifier circuit 30 includes a hybrid input splitter 31, a first power amplifier section 32-1, a second power amplifier section 32-2, a hybrid output combiner 37, and an adjustable termination impedance circuit 38. The hybrid input splitter 31 is a hybrid coupler. The hybrid input splitter 31 is an example of an input splitter that can split an RF input signal into signal components for the first power amplifier section 32-1 and the second power amplifier section 32-2. The hybrid input splitter 31 can provide two separated RF signals with a certain degree of phase shift relative to each other. For example, the hybrid input splitter 31 can split and provide two separated RF signals, and the relative phase of these two signals is in the range of 60 degrees to 130 degrees. In some applications, the hybrid input splitter 31 can split and provide two split RF signals with a relative phase of 90 degrees. The input signal of the second power amplifier section 32-2 can be phase-shifted 90 degrees relative to the input signal of the first power amplifier section 32-1. The hybrid input splitter 31 can divide the power of the RF input signal to determine the relative amplitude of the input signal of the first power amplifier section 32-1 and the input signal of the second power amplifier section 32-2.

[0054] As​ As shown, the first power amplifier section 32-1 includes a first input matching network 33-1 connected to the hybrid input splitter 31, a first power amplifier core 34-1, a first adaptive bias and linearization circuit 35-1 for generating a bias signal for the first power amplifier core 34-1, and a first output matching network 36-1. The second power amplifier section 32-2 includes a second input matching network 33-2 connected to the hybrid input splitter 31, a second power amplifier core 34-2, a second adaptive bias and linearization circuit 35-2 for generating a bias signal for the second power amplifier core 34-1, and a second output matching network 36-2.

[0055] The radio frequency (RF) input signal at the input node input can be separated by the hybrid input splitter 31 into a first signal for the first power amplifier section 32-1 and a second signal for the second power amplifier section 32-2. The first input matching network 33-1 can perform input matching for the first power amplifier core 34-1. The second input matching network 33-2 can perform input matching for the second power amplifier core 342. Both the first input matching network 33-1 and the second input matching network 33-2 can be programmable. Each of the first input matching network 33-1 and the second input matching network 33-2 can include controllable (e.g., switchable) passive components. The first input matching network 33-1 and / or the second input matching network 33-2 can be adjusted based on an indication of reflected power change or load VSWR change. The impedance of the input matching networks 33-1 and 33-2 can affect and / or control the power distribution ratio between the RF input signals provided to the power amplifier cores 34-1 and 34-2. The input matching networks 33-1 and / or 33-2 can be controlled to provide a phase shift between the input signals of the first power amplifier core 34-1 and the second power amplifier core 34-2, so as to increase and / or maximize the combined output signal after the hybrid output combiner 37.

[0056] The first signal can be amplified by the first power amplifier core 34-1. Similarly, the second signal can be amplified by the second power amplifier core 34-2. The power amplifier cores 34-1 and 34-2 can have any suitable power amplifier topology. The power amplifier cores 34-1 and 34-2 can include any suitable power amplifier transistors, such as but not limited to field effect transistors (FETs) (e.g., metal oxide semiconductor FETs (MOSFETs), p-type FETs (PFETs), n-type FETs (NFETs), or pseudomorphic high electron mobility transistors (pHEMTs)) and / or bipolar transistors. In some applications, the first power amplifier core 34-1 can have a different number of power amplifier transistors and / or power amplifier transistor area / size than the second power amplifier core 34-2. The supply voltage of the first power amplifier core 34-1 can be different from the supply voltage of the second power amplifier core 34-2.

[0057] The first adaptive bias and linearization circuit 35-1 provides a first bias signal to the input of the first power amplifier core 34-1. The first bias signal can be adjusted for different operating modes of the first power amplifier core 34-1. The first adaptive bias and linearization circuit 35-1 can adaptively adjust the first bias signal during the operating mode. The second adaptive bias and linearization circuit 35-2 provides a second bias signal to the input of the second power amplifier core 34-2. The second bias signal can be adjusted for different operating modes of the second power amplifier core 34-2. The second adaptive bias and linearization circuit 35-2 can adaptively adjust the second bias signal during the operating mode.

[0058] The first output matching network 36-1 can perform output matching on the first power amplifier core 34-1. The second output matching network 36-2 can perform output matching on the second power amplifier core 34-2. The first output matching network 36-1 and / or the second output matching network 36-2 can be programmable. The output matching networks 36-1 and / or 36-2 can be adjusted for different operating modes of the multimode power amplifier circuit 30. In some applications, each of the output matching networks 36-1 and 36-2 can include one or more switches for adjusting the output matching impedance for different operating modes. For example, the output matching networks 36-1 and / or 36-2 can include one or more shunt capacitors, each shunt capacitor in series with a corresponding switch.

[0059] The output signals from the output matching networks 36-1 and 36-2 can be combined with a hybrid output combiner 37 to produce a combined power amplifier output signal. The hybrid output combiner 37 is an example of an output combiner that can combine RF signals from the first power amplifier core 34-1 and the second power amplifier core 34-2. The hybrid output combiner 37 can phase-shift one of the output signals by a certain amount relative to the other signal. This can cancel out the phase shift of the hybrid input splitter 31. The hybrid output combiner 37 can phase-shift one of the output signals by an amount within the range of 60 degrees to 130 degrees relative to the other output signal. In some applications, the hybrid output combiner 37 can phase-shift one of the output signals by 90 degrees relative to the other output signal. Through the phase shift of the hybrid output combiner 37, the radio frequency signals from different power amplifier cores 34-1 and 34-2 can be in phase with each other. The adjustable termination impedance circuit 38 can adjust the termination impedance at the ports of the hybrid output combiner 38. The adjustable termination impedance circuit 38 can provide different terminations for different operating modes.

[0060] ​ is a schematic diagram of an example input matching network 33 according to an embodiment. The example input matching network 33 can implement ​ the first input matching network 33-1 and / or the second input matching network 31-2 of the multi-mode power amplifier circuit 30. The input matching network 33 can be in different states in different power amplifier segments 32-1 and 32-2. The input matching network 33 can be used to control and / or adjust the power distribution ratio between the power amplifier cores 34-1 and 34-2 in the multi-mode power amplifier circuit 30.

[0061] As ​ shown, the input matching network 33 can include a capacitor Cin1_1 and one or more switched capacitors Cin_n connected in series with corresponding switches 41. Each switched capacitor of the input matching circuit 33 can be electrically coupled or isolated from a node (e.g., the output of the hybrid input splitter 31 or the input of the power amplifier core) using the corresponding switch 41. Programmability can be implemented in the matching network 33 using one or more digital control bits. One or more digital control bits can select which switched capacitors to switch. The input matching network 33 can be used to control and / or adjust the power distribution ratio between the power amplifier cores 34-1 and 34-2 in the multi-mode power amplifier circuit 30. Any other suitable adjustable input matching network can be implemented alternatively or additionally.

[0062] ​ is according to an embodiment ​ of the example linearization and adaptive biasing circuit 35 of the multi-mode power amplifier circuit 30. The linearization and adaptive biasing circuit 35 is ​An example of the first linearization and adaptive bias circuit 35-1. The linearization and adaptive bias circuit 35 can alternatively or additionally be implemented ​ as the second linearization and adaptive bias circuit 35-2. The linearization and adaptive bias circuit 35 can operate as described in U.S. Patent Publication No. 2022 / 0094306, the entire content and all purposes of which are incorporated herein by reference. The linearization and adaptive bias circuit 35 can generate an adaptive power amplifier bias signal that varies according to the input power. The adaptive power amplifier bias signal can be a voltage or a current. The linearization and adaptive bias circuit 35 can also generate a non-DC signal component to eliminate the non-linearity of the power amplifier, thereby improving the overall linearity. Such a non-DC signal component has a non-zero frequency. The linearization and adaptive bias circuit 35 can generate a bias signal for the power amplifier core in a segmented mode, and the bias signal includes a DC bias component and at least one non-DC radio frequency tone. This can improve the overall linearity. Based on an indication of the reflected power change, the linearization and adaptive bias circuit 35 can adjust the amplitude of the DC bias component and the amplitude of the non-DC radio frequency tone.

[0063] As shown in the figure, the linearization and adaptive bias circuit 35 includes a bias circuit 42, a linearization circuit 43, and a linearization circuit coupling circuit 44. The linearization and adaptive bias circuit 35 includes a feedback path that couples the output of the linearization coupling circuit 44 to the input of the bias circuit 42, thereby forming a bias loop. The linearization circuit 43 includes adjustable resistors 45-1 and 45-2. The adjustable resistors 45-1 and / or 45-2 can be programmed to adjust the linearization circuit 43. In some cases, the adjustable resistors 45-1 and / or 45-2 can be replaced by current sources. The coupling circuit includes adjustable resistors 46-1 and / or 46-2, which can be programmed to adjust the coupling circuit. The adjustable current source 47 can generate a signal for the bias circuit 42.

[0064] ​ is an example of a hybrid combiner 37A and 37B that can be implemented in the ​ multimode power amplifier circuit 30 according to an embodiment. ​ The hybrid combiner 37 can be implemented by the hybrid combiner 37A or the hybrid combiner 37B. ​The hybrid output combiner 37 can be implemented by any suitable 90-degree hybrid combiner or any other suitable passive combiner that combines at least two signals with unequal phases. For example, a hybrid combiner 37A with lumped inductors and capacitors can be implemented. As another example, a hybrid combiner 38B with coupled transmission lines can be implemented. Any other suitable hybrid combiner for coupling signals with a 90-degree phase difference can be used for the hybrid combiner 37. For example, the hybrid combiner can include a Wilkinson combiner with a quarter-wavelength transmission line at one of the two input terminals. In certain applications, the hybrid combiner can achieve a phase shift of approximately 90 degrees. In some applications, the hybrid combiner can achieve a phase shift in the range of 60 degrees to 130 degrees and achieve suitable performance. ​ The hybrid input splitter 31 can be implemented with a structure similar to any hybrid combiner disclosed herein and is arranged to split an input radio frequency signal. Such a hybrid combiner can be set as a splitter instead of a combiner, for example, as ​ shown.

[0065] ​ is according to an embodiment of ​ Schematic diagram of an example adjustable termination impedance circuit 38 of the multimode power amplifier circuit 30. The adjustable termination impedance circuit 38 can provide ​ multiple different termination impedances to the isolation port of the hybrid output combiner 37. ​ The isolation port of the hybrid output combiner 37 can be referred to as a termination port. The adjustable termination impedance circuit 38 can provide different terminations for different operating modes of the multimode power amplifier circuit 30. In different states, the adjustable termination impedance circuit 38 can select one or more termination impedances to provide to ​ the port of the output hybrid combiner 37.

[0066] The adjustable termination impedance circuit 38 can provide various different termination impedances, such as but not limited to a short-circuit impedance (low impedance), an open-circuit impedance (high impedance), one or more resistive impedances, such as a resistive impedance in the range of 25 ohms to 100 ohms, one or more capacitive impedances, a combination of one or more resistive impedances and one or more capacitive impedances, etc. One or more termination impedances can be selected for each operating mode based on the power amplifier mode control signal PA mode control. As ​As shown, switches 48-1, 48-2, 48-3, and 48-4 can each select their respective terminal impedances. For example, switch 48-1 can select a capacitive terminal impedance C_term, switch 48-2 can select a short-circuit terminal impedance, switch 48-3 can select a first resistive terminal impedance R_term1, and switch 48-4 can select a second resistive end impedance R_term2. Any other suitable terminal impedance and / or method of adjusting the terminal impedance can be implemented alternatively or additionally.

[0067] ​ is a schematic diagram of a multi-mode power amplifier circuit 50 having a power detection and control circuit. The multi-mode power amplifier circuit 50 can detect an indication of VSWR and set an operating mode based on the representation of the VSWR. The multi-mode power amplifier circuit 50 includes ​ a circuit of the multi-mode power amplification circuit 30 and a circuit for detecting the VSWR and controlling the operating mode of the multi-mode power amplifier circuit 30. As shown, the multi-mode power amplifier circuit 50 includes a radio frequency coupler 52, a VSWR detector 54, and a control circuit 56.

[0068] The radio frequency coupler 52 can couple a portion of the radio frequency power propagating between the hybrid output combiner 37 and the antenna (or other power amplifier load). A portion of the radio frequency power can be provided to the VSWR detector 54. The VSWR detector 54 can detect an indication of the power amplifier load impedance, such as an impedance value or an indication of an impedance area associated with a set of impedance values.

[0069] The control circuit 56 can receive an output signal from the VSWR detector 54. The control circuit 56 can set the operating mode of the power amplifier circuit 50 based on the indication of the power amplifier load impedance from the VSWR detector 54. Each impedance region can correspond to a set of power amplifier control bits to set the power amplifier operating mode corresponding to the detected VSWR ratio region.

[0070] ​ is a Smith chart related to power amplifier load impedances having different VSWRs, showing different operating modes of the power amplifier circuit 50 in different VSWR ranges. Inside the inner circle of the Smith chart with a VSWR of 1.2 ​ the power amplifier circuit 50 can operate in Doherty mode. Thus, the Doherty mode can be used for VSWRs in the range of 1 to 1.2. ​The VSWR of the next circle away from the center point is 2. The power amplifier circuit 50 can operate in a segmented mode in the region between the inner circle and the next outer circle to obtain the VSWR. Thus, the segmented mode can be used for VSWR in the range of 1.2 to 2. Outside the circle with a VSWR of 2, the power amplifier circuit 50 can operate in a balanced mode. The power amplifier circuit 50 can operate in a balanced mode with a VSWR of 2 to 4.

[0071] Reference ​ , the set of power amplifier control bits for each operating mode can be stored in any suitable memory, such as a look-up table (LUT), non-volatile memory, or any other suitable storage unit. Such a memory can be included in the control circuit 56. Table 1 below summarizes example control bits for different operating modes corresponding to different detected VSWR impedances. The detected VSWR in Table 1 corresponds to an indication of the power amplifier load impedance from the VSWR detector 54. The PA1 control bits in Table 1 can include input matching control bits for the first input matching network 33-1, linearization bias and / or control bits for the first linearization and adaptive bias circuit 35-1, and bias bits for the first power amplifier core 34-1. In some cases, the PA 1 control bits can include one or more control bits for the first output matching network 36-1. The PA 2 control bits in Table 1 can include input matching control bits for the second input matching network 33-2, linearization bias and / or control bits for the second linearization and adaptive bias circuit 35-2, and bias bits for the second power amplifier core 34-2. In some cases, the PA 2 control bits can include one or more control bits for the second output matching network 36-2. The termination control in Table 1 can select a termination for the tunable termination impedance circuit 38. The control circuit 56 can set the operating mode of the power amplifier circuit 50 for a stand-alone power amplifier and / or a power amplifier in a beamforming system.

[0072]

[0073] Table 1

[0074] ​ is a schematic diagram of a power amplifier system 60 having a phased antenna array 12 that performs beam scanning according to an embodiment. The power amplifier system 60 includes antennas 14A to 14N and a plurality of processing channels 62A, 62B, 62N, each processing channel including a respective power amplifier 18A, 18B, 18N that drives a respective antenna 14A, 14B, 14N. Each power amplifier 18A, 18B, 18N can include ​Power amplifier circuit 30. The power amplifier system 60 can be used for beamforming. In the power amplifier system 60, the operation mode can be set based on the beam angle. In a beamforming system (e.g., having ≥5x5 antenna elements), most (e.g., ≥80%) of the channels 62A to 62N can have a power amplifier VSWR variation that is the same as or substantially the same as the beam scan.

[0075] ​ Is a table summarizing example control bits for beam positions according to an embodiment. The control bits in this table can be used to control the power amplifier circuits of a relatively large array. The control bits can be applied to all the power amplifiers of the array driving the antenna array. The control bits can be applied to any suitable subset of the power amplifiers of the array.

[0076] In ​ For the beam positions with azimuth and elevation angles for each beam position, power amplifier parameters are provided. The control bit PA1 can control the settings of the first power amplifier section 32-1, the control bit PA2 can control the settings of the second power amplifier section 32-2, and the terminal control can set ​ The state of the adjustable terminal impedance circuit 38 of. The control bits corresponding to the beam positions can be stored in any suitable memory, such as a LUT, non-volatile memory, or any other suitable storage unit. In some applications, the control bits can be applied during an initialization sequence.

[0077] For example, for the aperture side "main" beam with azimuth and elevation angles both being 0 and a relatively small beam angle, the Doherty power amplifier mode of operation can be enabled by applying the Doherty control bit.

[0078] For example, at a relatively large beam scan angle, in The range of, the segmented power amplifier mode of operation can be enabled by applying the segmented control bit.

[0079] For example, for a relatively large beam scan angle, The balanced power amplifier mode of operation can be enabled by applying the balanced control bit.

[0080] Reference will be made to ​ Discuss ​ The configuration and performance of the multimode power amplifier circuit 30 in different operating modes.

[0081] ​ Is according to an embodiment of ​Schematic diagram of the power amplifier circuit 30 in Doherty mode operation. The power amplifier circuit 30 can be used as a Doherty power amplifier at and / or near the optimum load conditions, where high back-off PAE can be achieved. In Doherty mode, the adjustable termination impedance circuit 38 is in a state that provides a quarter-wavelength transmission line behavior between the outputs of the first power amplifier core 34-1 and the second power amplifier core 34-2. This can provide load modulation at the load of the first power amplifier core 34-1 such that: (1) at low input power, the second power amplifier core 34-2 is turned off and the first power amplifier core 34-1 is loaded with the optimum (or near optimum) PAE load impedance; (2) at higher input power, the second power amplifier core 34-2 starts conducting, where the hybrid output combiner 37 is arranged to provide load modulation at the load of the first power amplifier core 34-1, where the load impedance at the first power amplifier core 34-1 moves from the optimum efficiency region to the optimum power impedance, and the load impedance of the second power amplifier core 34-2 moves towards the optimum power impedance; and (3) the hybrid output combiner 37 combines the output power Pout1 from the first power amplifier core 34-1 and the output power from the second power amplifier core 34-2 by canceling the phase difference of the output powers from the first power amplifier core 34-1 and the second power amplifier core 34-2 to obtain the maximum (or near maximum) combined output power Pout. In some cases, the adjustable termination impedance circuit 38 can provide a short circuit termination for the Doherty mode. In some other cases, the adjustable termination impedance circuit 38 can provide a capacitor termination for the Doherty mode.

[0082] The bias signal bias 1 for the first power amplifier core 34-1 can bias the first power amplifier core 34-1 for class A, class B, or class AB operation in Doherty mode. The bias signal bias 1 can be a bias voltage or a bias current. The bias signal bias 2 for the second power amplifier core 34-2 can bias the class B or class C operation in the second power amplifier core 34-2, where the second power amplifier core 34-1 is turned off at low input power and turned on at higher input power. The bias signal bias 2 can be a bias voltage or a bias current.

[0083] In Doherty mode, input matching control bits for the first input matching network 33-1 and input matching control bits for the second input matching network 33-2 can be set to control the input power levels at the inputs of each power amplifier core 34-1, 34-2, and to compensate for any phase mismatches between the power amplifier signals to ensure a total 90-degree phase shift between the output signals of the first power amplifier core 34-1 and the second power amplifier core 34%-2. This can achieve ideal PAE and combined output power Pout operation in Doherty mode.

[0084] The linearization bias and / or control bits for the first linearization and adaptive bias circuit 35-1 and the second linearization and adaptive bias circuit 35-2 can be set and / or optimized to achieve the desired AM-to-AM and AM-to-PM.

[0085] ​ is the Smith chart corresponding to the power amplifier circuit 30 in Doherty mode.

[0086] ​ is a graph of the gain of the power amplifier circuit 30 versus the output power in Doherty mode. ​ is a graph of the PAE of the power amplifier circuit 30 versus the output power in Doherty mode. At ​ and 8C In the graphs of, the power amplifier circuit 30 in Doherty mode operates under different load conditions. Different load conditions include optimal load conditions with a load impedance of 50 ohms, a 2:1 load VSWR, and a 4:1 load VSWR.

[0087] The power amplifier circuit 30 in Doherty mode can achieve optimal performance under optimal load conditions, with a PAE of 36.5% at 6 dB O, a maximum Psat of 24.5 dBm, and good AM-to-AM flatness versus the output power Pout, which can result in good linearity and relatively easy digital predistortion (DPD). This PAE is more than twice that of an ideal class B power amplifier PAE.

[0088] In Doherty mode, for the power amplifier circuit 30 at a 2:1 load VSWR, the worst-case back-off PAE drops by about 1.5 times from the maximum value at the optimal load, while achieving a PAE of 24%. In addition, the Psat drops by 2 dB and the AM-to-AM flatness decreases, resulting in a 10-dB reduction in P1dB.

[0089] In Doherty mode, the power amplifier circuit 30 has the worst back-off PAE drop by a factor of 3 at a load VSWR of 4:1, with the best load achieving a PAE of 12%, which is lower than that of an ideal class-B power amplifier with the best load. In addition, Psat drops by 4.5 dB from its maximum value, and the AM-to-AM flatness is significantly reduced, resulting in a 15-dB reduction in P1dB.

[0090] ​ and 8C The graph of... shows that the power amplifier circuit 30 in Doherty mode has a relatively high VSWR sensitivity. Therefore, the power amplifier circuit 30 in Doherty mode can be suitable for optimal and near-optimal load operation. The power amplifier circuit 30 can operate in one or more different modes at higher VSWRs, such as VSWRs greater than or equal to 1.2:1 and / or greater than or equal to 2:1.

[0091] ​ is according to an embodiment ​ Schematic diagram of the power amplifier circuit 30 in segmented mode operation. The power amplifier circuit 30 can operate in segmented mode with VSWR variations in the range of 1.2:1 to 2:1 and achieve a moderate PAE at the average operating power. Compared with the Doherty mode, the second power amplifier core 34-2 has a non-zero bias for low input power in segmented mode. In segmented mode, the power amplifier circuit 30 operates differently from the Doherty mode and the balanced mode.

[0092] As ​ shown, the first bias voltage Vbias 1 of the first power amplifier 35-1 can be generated by the first adaptive bias and linearization circuit 35-1 with a moderate linearization device to generate a constant first bias voltage Vbias 1 relative to the input power in segmented mode. ​ It is also shown that the second bias voltage Vbias 2 of the second power amplifier core 34-2 can be generated from the second adaptive bias and linearization circuit 35-2 using highly non-linear devices to generate the shown slope of the second bias voltage Vbias 2 relative to the input power and eliminate the high non-linearity in the second power amplifier core 34-2 operating as a class-B core in segmented mode.

[0093] Refer to ​, in the segmented mode, the input matching networks 33-1 and 33-2 can be in a state of splitting the input power without losing 3 dB of gain in the second power amplifier core 34-2 "off-core". Because the turn-on voltage of the second power amplifier core 34-2 depends on its input power Pin and the second bias voltage Vbias 2 from the second adaptive bias and linearization circuit 35-2. The linearization circuits of the first adaptive bias and linearization circuit 35-1 and the second adaptive bias and non-linearization circuit 35-2 can be in a state of generating different bias signals at each power amplifier input, where each bias signal has a DC component that is a function of the input power of each power amplifier core and the RF component to eliminate the self-nonlinearity of the core within each power amplifier, thereby improving the overall linearity of each power amplifier.

[0094] In the segmented mode, the adjustable termination impedance circuit 38 can be in the following states: (1) together with the first output matching network 36-1, providing an optimal efficiency (or near-optimal efficiency) load to the first power amplifier core 34-1, and (2) together with the second output matching network 36-2, providing an optimal power load (or near-optimal power load) to the second power amplifier core 34-2 to achieve the maximum (or near-maximum) output power. The adjustable termination impedance circuit 38 can select the resistor termination R_term1 as the termination impedance of the hybrid output combiner 37 in the segmented mode, as shown in the figure. Alternatively or additionally, the adjustable termination impedance circuit 38 can select the capacitor C_term to provide the termination impedance for the hybrid output combiner 37 in the segmented mode. ​ The impedance of the selected resistor termination R_term1 may be higher than that of the resistor termination in the balanced mode (e.g., the resistor termination R_term2). For example, the resistor termination R_term1 can have a termination impedance of 100 ohms, and the resistor termination R_term2 in the balanced mode can have a terminal resistance of 50 ohms.

[0095] ​ is ​ a graph showing the relationship between the RF power and the output power of the power amplifier core of the power amplifier circuit. This graph shows the contribution of each power amplifier core to the total output power of the power amplifier circuit 30 for different RF power levels in the segmented mode.

[0096] ​ is a Smith chart corresponding to the power amplifier circuit 30 operating in the segmented mode.

[0097] ​ is a graph showing the relationship between the gain and the output power of the power amplifier circuit 30 in the segmented mode. ​: is a graph showing the relationship between the PAE and output power of the power amplifier circuit 30 in the segmented mode. ​ and 10C The graph in FIG. 1 shows the performance of the power amplifier circuit 30 in the segment mode under different load conditions.

[0098] Under the optimal load condition of 50 ohms, the power amplifier circuit 30 in the segment mode can achieve its peak performance at 6 dBO with a PAE of 33%, a maximum Psat of 24.5 dBm, and an ideal AM to AM flatness versus output power Pout, which results in good linearity and relatively easy DPD. This PAE is greater than 1.8 times the normalized ideal Class B power amplifier PAE.

[0099] At a 2:1 load VSWR in segmented mode, the worst-case back-off PAE dropped by approximately 1.15 times from its maximum value at optimal load, while achieving a PAE of 28%. Furthermore, Psat dropped by 1 dB, and AM-to-AM flatness still enabled good linearity and relatively easy DPD, resulting in a 1 dB reduction in P1dB. At a 4:1 load VSWR in segmented mode, the worst-case back-off PAE dropped by 2 times from its maximum value at optimal load, while achieving a PAE of 22%, which is comparable to an optimally loaded Class B power amplifier. Furthermore, Psat dropped by 3 dB from its maximum value, and AM-to-AM flatness decreased, resulting in a 10 dB reduction in P1dB.

[0100] ​ and 10C The graph shows that the power amplifier circuit 30 in segment mode has moderate VSWR sensitivity. The power amplifier circuit 30 in segment mode can be suitable for optimal load operation and 2:1 VSWR variation operation. The power amplifier circuit 30 can operate in segment mode with a VSWR variation of less than or equal to 2:1. In some applications, the power amplifier circuit 30 can operate in segment mode to achieve a VSWR variation in the range of 1.2:1 to 2:1.

[0101] ​ According to the embodiment ​ FIG3 is a schematic diagram of a power amplifier circuit 30 in balanced mode operation. For higher VSWR variations, such as VSWR fluctuations greater than 2:1, the power amplifier circuit 30 can operate in balanced mode. The power amplifier circuit 30 in balanced mode can achieve better PAE at average operating power than in Doherty mode or segmented mode.

[0102] When the hybrid input splitter 31 and the hybrid output combiner 37 are connected in a balanced configuration, by controlling the first power amplifier core 34-1 and the second power amplifier core 34-2 to operate identically (or substantially identically) to each other, the power amplifier circuit 30 can operate in a balanced mode. When there are changes in the load impedance and / or load VSWR at the output ports, the balanced operation can cause the reflected signals to be absorbed by the isolation port of the hybrid output combiner 37, which is terminated by a 50-ohm resistor. This can make the power amplifier circuit 30 in the balanced mode less sensitive to VSWR changes than other modes.

[0103] Generally, the efficiency of a balanced power amplifier circuit can follow the same efficiency behavior of the two separate power amplifier cores 34-1 and 34-2. Advantageously, using adaptive biasing for the power amplifier cores 34-1 and 34-2 can improve the PAE of the power amplifier circuit 30 in the balanced mode during back-off operation.

[0104] The bias voltages Vbias1 and Vbias2 of the power amplifier cores 34-1 and 34-2 can be the same or substantially the same. These bias voltages Vbias1 and Vbias2 can be generated by the respective adaptive biasing and linearization circuits 35-1 and 35-2, which can generate bias voltages that follow the input power to obtain an ideal back-off efficiency.

[0105] The input matching networks 33-1 and 33-2 can be controlled to be the same or substantially the same as each other. The input matching networks 33-1 and 33-2 can be in a state where they achieve the maximum or near-maximum input power Pin at each input of the power amplifier cores 34-1, 34-2.

[0106] As ​ shown in the Smith chart, the adjustable termination impedance circuit 38 can provide the termination impedance for the same or substantially the same load impedance at each power amplifier output. As ​ shown, the adjustable termination impedance circuit 38 can select the termination resistor R_term2 to operate in the balanced mode. The termination resistor R_term2 can have an impedance of 50 ohms. The adjustable termination impedance circuit 38 can select different termination impedances for each of the balanced mode, the segmented mode, and the Doherty mode.

[0107] The hybrid output combiner 37 can cancel the 90-degree phase shift between the output signals from the power amplifier cores 34-1 and 34-2 to operate in the balanced mode.

[0108] ​ is the Smith chart corresponding to the power amplifier circuit 30 in the balanced mode.

[0109] ​Yes ​ Graph of the relationship between the gain and output power of the power amplifier circuit ​ Yes ​ Graph of the relationship between the PAE and output power of the power amplifier circuit. In ​ and 12C The curve graphs show the performance of the power amplifier circuit 30 in the balanced mode under different load conditions

[0110] Under the optimal load condition with a load impedance of 50 ohms, the power amplifier circuit 30 in the balanced mode can achieve its peak performance at 6 dB O with a PAE of 27%, a maximum Psat of 24.5 dBm, and an ideal AM-to-AM flatness with respect to the output power Pout, which results in good linearity and relatively easy DPD

[0111] At a 2:1 load VSWR in the balanced mode, the worst-case back-off PAE drops by approximately 1.06 times from its maximum value at the best load, while achieving a PAE of 25.5%. In addition, the output power saturation Psat drops by 1 dB, and the AM-to-AM flatness can still achieve good linearity and relatively easy DPD, resulting in a 1 dB reduction in P1dB

[0112] At a 4:1 load VSWR in the balanced mode, the worst-case back-off PAE drops by 1.3 times from its maximum value at the best load, while achieving a PAE of 20.7%. In addition, Psat drops by 2 dB from its maximum value, and the AM-to-AM flatness is suitable for achieving good linearity and relatively easy DPD, resulting in a 3 dB reduction in P1dB

[0113] ​ and 12C The curve graphs show that the power amplifier circuit 30 in the balanced mode has low VSWR sensitivity. Relative to the presence of VSWR variations, the power amplifier circuit 30 in the balanced mode can have a relatively low PAE improvement to achieve optimal load operation. The power amplifier circuit 30 can be applicable to VSWR variation operations greater than 2:1. The power amplifier circuit 30 can operate in the balanced mode to achieve VSWR variations greater than 2:1

[0114] ​ Yes ​ Graph of the relationship between the gain and output power of the power amplifier circuit 30 in Doherty mode, segmented mode, and balanced mode ​ Yes ​ Graph of the relationship between the PAE and output power of the power amplifier circuit 30 in Doherty mode, segmented mode, and balanced mode ​ and 13BThe graph shows that the power amplifier circuit 30 can achieve better back-off PAE than class B power amplifiers in a 4:1 VSWR range, with an optimal load, lower Psat and P1dB VSWR drop, and AM-to-AM flatness to enable relatively easy DPD and good VSWR linearity.

[0115] Table 2 summarizes the performance of the power amplifier circuit 30 in different modes and the overall performance when operating in different modes.

[0116]

[0117] Table 2

[0118] The present invention discloses a power amplifier operating in multiple operating modes to obtain desirable performance with respect to load variations and / or VSWR variations. The power amplifier circuit may include two power amplifier cores. The power amplifier circuit may include programmable biasing, input matching, output matching, and adaptive biasing and linearization circuits associated with each power amplifier core. The output power of the power amplifier cores may be combined with a hybrid output combiner. The hybrid output combiner may provide a 90-degree phase shift for radio frequency signals received from one of the two power amplifier cores. The hybrid output combiner may have a port connected to an adjustable termination impedance circuit. The adjustable termination impedance circuit may provide different termination impedances for each operating mode.

[0119] The power amplifier circuit may operate in a first mode of efficient operation with a load-modulated power amplifier architecture. The power amplifier circuit may operate in the first mode under optimal load conditions or near-optimal load conditions. The first mode may be a Doherty mode. In the Doherty mode, the first power amplifier core may be biased to operate as a class AB or class B amplifier, and the second power amplifier core may also be biased to operate as a class B or class C amplifier. The adjustable termination impedance circuit may be in a state that provides quarter-wavelength transmission line behavior for the first mode. The adjustable termination impedance circuit may provide a short-circuit termination for the first mode.

[0120] The power amplifier circuit may operate in a second mode with a VSWR variation up to 2:1 to achieve a moderate PAE at an average operating power. The second mode may be a segmented mode. In the segmented mode, (i) the biasing of the first power amplifier core is different from that of the second power amplifier core, and (ii) both the first power amplifier core and the second power amplifier core are activated throughout the mode. In the second mode, the adjustable termination impedance circuit may be in a state different from that of the first mode. For example, the adjustable termination impedance circuit may provide a resistive termination in the second mode.

[0121] For VSWR variations greater than 2:1, the power amplifier circuit can operate in a third mode to achieve a better PAE at the average operating power under such VSWR variations than in the first and second modes. The third mode can be a balanced mode. In the balanced mode, the reflected signal can be absorbed by the ports of the hybrid output combiner connected to the adjustable termination impedance circuit. The adjustable termination impedance circuit can be in a state different from the second mode and the first mode in the third mode. In the third mode, the adjustable termination impedance circuit can provide a resistive termination impedance of 50 ohms.

[0122] In the above embodiments, devices, systems, and methods for a multi-mode power amplifier are described in connection with specific embodiments. However, it should be understood that the principles and advantages of the embodiments can be used in any other system, apparatus, or method that requires a power amplifier circuit according to any suitable principles and advantages disclosed herein. Additionally, any suitable principles and advantages disclosed herein can be implemented in systems and methods that include a power amplifier and transmit radio frequency signals through one or more antennas.

[0123] The principles and advantages described herein can be implemented in various devices. Examples of such devices can include, but are not limited to, communication infrastructures such as wireless communication infrastructures, consumer electronics products, components of consumer electronic devices, electronic test equipment, in-vehicle electronics products, industrial electronics products, etc. Electronic products can include, but are not limited to, base stations such as cellular base stations, access points, repeaters, repeaters, wireless communication devices, user equipment, mobile phones (e.g., smartphones), handheld computers, tablets, laptops, wearable computing devices, in-vehicle electronic systems, radios, wearable health monitoring devices, etc. Additionally, the devices can include unfinished products.

[0124] Unless the context clearly requires otherwise, throughout the specification and claims, words such as "comprising," "including," "containing," etc. shall be construed in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including, but not limited to." The term "coupled" or "connected" as commonly used herein generally refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Additionally, the terms "herein," "above," "below," and similar terms with similar meanings in this application shall refer to the entire application, rather than any specific part of this application. Where the context permits, words used in the detailed description in the singular or plural may also respectively include the plural or the singular. When referring to a list of two or more items, the word "or" is intended to cover all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list. All numerical values provided herein are intended to include similar values within the measurement error.

[0125] In addition, unless otherwise specifically stated or understood in the context in which it is used, conditional language used herein, such as "can", "may", "could", "for example", "such as", etc., generally intends to convey that certain embodiments include, while other embodiments do not include certain features, elements, and / or states.

[0126] The teachings of the invention provided herein can be applied to other systems and not necessarily to the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. The acts of the methods discussed herein can be performed in any suitable order. In addition, the acts of the methods discussed herein can be performed serially or in parallel as needed.

[0127] Although certain embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the disclosure. In fact, the novel methods and systems described herein can be embodied in various other forms. In addition, various omissions, substitutions, and changes can be made to the forms of the methods and systems described herein without departing from the spirit of the disclosure. The appended claims and their equivalents are intended to cover forms or modifications that fall within the scope and spirit of the disclosure. Accordingly, the scope of the invention is defined by reference to the claims.

Claims

1. A power amplifier system, comprising: A first power amplifier core configured to provide a first radio frequency signal; A second power amplifier core configured to provide a second radio frequency signal; An output combiner configured to receive the first radio frequency signal and the second radio frequency signal, the output combiner including an output port and an isolation port; And An adjustable termination impedance circuit electrically connected to the isolation port, the adjustable termination impedance circuit being configured to provide different terminations to the isolation port in different modes, the different modes including a segmented power amplifier mode.

2. The power amplifier system according to claim 1, wherein the different modes include a Doherty mode.

3. The power amplifier system according to claim 1, wherein the different modes include a balanced mode.

4. The power amplifier system according to claim 1, wherein the adjustable termination impedance circuit is configured to adjust the termination impedance at the isolation port based on an indication of a change in voltage standing wave ratio (VSWR).

5. The power amplifier system according to claim 1, wherein the different modes include three modes.

6. The power amplifier system according to claim 5, wherein the three modes include a Doherty mode, a segmented power amplifier mode, and a balanced mode.

7. The power amplifier system according to claim 5, wherein the power amplifier system is configured to operate in a Doherty mode in response to a change in voltage standing wave ratio (VSWR) within the range of the Doherty mode, configured to operate in a segmented power amplifier mode for a VSWR change greater than the Doherty mode and less than the balanced mode, and configured to operate in a balanced mode for a VSWR change greater than the segmented power amplifier mode.

8. The power amplifier system according to claim 1, wherein: In the segmented power amplifier mode, the bias of the first power amplifier core is different from the bias of the second power amplifier core; And Throughout the segmented power amplifier mode, both the first power amplifier core and the second power amplifier core are activated.

9. The power amplifier system according to claim 1, wherein: The adjustable termination impedance circuit is configured to provide a resistive termination in the segmented power amplifier mode; and The power amplifier system is configured to adaptively bias the second power amplifier core in the segmented power amplifier mode, and the bias signal for the second power amplifier core includes at least one first tone component having a non-zero frequency to cancel the non-linearity of the second power amplifier core in the segmented mode.

10. The power amplifier system according to claim 1, further comprising an antenna array, wherein the power amplifier system is configured to perform beam scanning using the antenna array, and wherein the adjustable termination impedance circuit is configured to adjust the termination impedance at the isolation port based on an indication of a beam angle.

11. The power amplifier system according to claim 10 further includes a second multi-core power amplifier operable in different modes, the second multi-core amplifier being configured to drive a second antenna of the antenna array, wherein the second multi-core power amplifier is configured to operate in the same mode as the first and second power amplifier cores.

12. The power amplifier system according to claim 1, wherein the output combiner is a hybrid combiner, and the hybrid combiner is configured to combine the second RF signal with a phase shift in the range of 60 degrees to 130 degrees relative to the first RF signal.

13. The power amplifier system according to claim 1 further includes a hybrid input splitter configured to shift the phase of the second RF signal by an angle in the range of 60 degrees to 130 degrees relative to the first RF signal.

14. The power amplifier system according to claim 1, wherein: the first power amplifier core is included in a first power amplifier segment, the first power amplifier segment further including a first input matching circuit connected to an input of the first power amplifier core and a first adaptive bias circuit connected to the first power amplifier core, and the first input matching circuit and the first adaptive bias circuit are adjustable in different modes; and the second power amplifier core is included in a second power amplifier segment, the second power amplifier segment further including a second input matching circuit connected to an input of the second power amplifier core and a second adaptive bias circuit connected to the second power amplifier core, and the second input matching circuit and the second adaptive bias circuit are adjustable in different modes.

15. The power amplifier system according to claim 14, wherein the first input matching circuit includes at least one controllable passive element, and the first input matching circuit is adjusted based on an indication of at least one of a reflected power change or a load voltage standing wave ratio (VSWR) change.

16. The power amplifier system according to claim 14, wherein both the first adaptive bias circuit and the second adaptive bias circuit are configured to generate respective bias signals, the bias signals including a direct current (DC) bias component and at least one non-DC RF tone, and wherein the amplitude of the DC bias component and the amplitude of the non-DC RF tone are adjusted based on an indication of a reflected power change.

17. A power amplifier system, comprising: a first power amplifier core configured to provide a first RF signal; a second power amplifier core configured to provide a second RF signal; a hybrid combiner configured to receive the first RF signal and the second RF signal, the hybrid combiner including an output port and an isolation port; and an adjustable termination impedance circuit electrically connected to the isolation port, the adjustable termination impedance circuit being configured to provide different terminations to the isolation port in at least three different modes of the power amplifier system.

18. The power amplifier system according to claim 17, wherein the three different modes include Doherty mode, balanced mode, and another mode.

19. The power amplifier system according to claim 17, wherein the power amplifier system is configured to operate in three different modes within different ranges of load voltage standing wave ratio variation.

20. A method for amplifying a multi-mode radio frequency signal, the method comprising: amplifying a radio frequency signal using a power amplifier circuit in a segmented mode, the segmented mode being different from Doherty mode and balanced mode, the power amplifier circuit including a first power amplifier core, a second power amplifier core, an output combiner configured to combine output signals from the first and second power amplifier cores, and an adjustable termination impedance circuit connected to a port of the output combiner; adjusting a termination impedance provided by the adjustable termination impedance circuit for a mode different from the segmented mode; and amplifying the radio frequency signal in different modes.

Images