Radio frequency channel frequency response test system and method, and storage medium

Abstract

The invention provides a radio frequency channel frequency response test system and method and a storage medium, the system comprises a vector signal source, an analog signal source, a to-be-tested piece, a digital processing module, a signal analysis device and an upper computer, the to-be-tested piece is a radio frequency signal processing board, is provided with a radio frequency transmit-receive channel and is connected with a radio frequency transceiver through a radio frequency link, and the digital processing module is connected with the signal analysis device. The vector signal source is used for providing a test radio frequency signal, the analog signal source is used for providing a synchronous clock signal for the system, and the digital processing module is connected with a to-be-tested piece through a digital interface, is used for transmitting baseband data and a control signal, and interacts with an upper computer through a communication interface; the signal analysis equipment performs amplitude-frequency response and phase-frequency response analysis on the received radio frequency signal, and the upper computer is used for generating a broadband multi-tone baseband signal, controlling a test process and displaying a test result; according to the system, the gain flatness and the linear phase deviation of the radio frequency channel can be accurately tested.

Description

Technical Field

[0001] This application relates to the technical field of radio frequency signal testing, and particularly to a radio frequency channel frequency response testing system, method, and storage medium. Background Art

[0002] With the rapid development of wireless communication, radar detection, and software-defined radio (SDR) technologies, highly integrated integrated radio frequency transceivers (such as AD9371, AD9361, LimeSDR, etc.) have been widely used in modern wireless systems. Different from traditional radio frequency channels, the core feature of such devices is to directly complete the conversion from digital baseband signals to radio frequency signals (Digital-to-RF), and integrate functional modules such as digital-to-analog conversion (DAC), analog-to-digital conversion (ADC), quadrature mixing, filtering, and gain control, significantly improving the system's integration, programmability, and broadband coverage capabilities. However, during the digital baseband to radio frequency conversion process, the frequency response characteristics of the radio frequency channel (including gain flatness and phase linearity) have a decisive impact on signal quality. Gain flatness (BW Flatness) reflects the gain consistency of the transceiver for different frequency signals within the operating bandwidth, directly affecting the equalization of the amplitude response and the dynamic range of the system; while the linear phase deviation (Deviation from Linear Phase) measures the linearity of the system's phase response and has a significant impact on the demodulation error (EVM) of high-order modulation signals (such as 64-QAM, 256-QAM).

[0003] Traditional radio frequency channel testing mainly relies on instruments such as vector network analyzers (VNA) to perform frequency response analysis through S-parameters (such as S21) of the end-to-end radio frequency link. However, testing integrated radio frequency transceivers faces unique challenges: ① Complexity of digital-to-analog domain conversion: Signals need to go through digital processing and frequency conversion before entering the radio frequency link, and testing needs to cover the interaction process between digital baseband and radio frequency analog signals simultaneously; ② System-level interference factors: Filter characteristics, gain control errors, phase noise of the local oscillator (LO) signal, etc. inside the transceiver will all introduce frequency response distortion, and system-level testing is required for comprehensive evaluation; ③ Limitations of traditional methods: S-parameter testing cannot directly reflect the conversion characteristics from digital baseband to radio frequency link, and new methods need to be developed specifically.

[0004] Due to the above technical difficulties, existing testing methods are difficult to accurately evaluate the frequency response performance of integrated radio frequency transceiver channels, resulting in difficulties in effectively optimizing their applications in high-precision scenarios such as wireless communication and radar. Therefore, there is an urgent need for an efficient testing solution that takes into account both the digital domain and the radio frequency domain and covers system-level interference factors to achieve accurate measurement of gain flatness and phase linearity. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the present application provides a radio frequency channel frequency response test system, method and storage medium to solve the above technical problems.

[0006] The present application provides a radio frequency channel frequency response test system, and the system includes: a vector signal source, whose radio frequency output end is connected to the radio frequency receiving end of the device under test through a radio frequency connector, and is used to provide a test radio frequency signal; an analog signal source, whose output end is connected to the digital processing module, and is used to provide a synchronous clock signal; a device under test, which is a radio frequency signal processing board and includes a radio frequency transceiver channel, and the radio frequency transceiver channel is connected to a radio frequency transceiver through a radio frequency link; a digital processing module, which is connected to the digital end of the device under test through a digital interface, and is used to send baseband data and control signals to the device under test; and is connected to the upper computer through a communication interface, and is used to cache the baseband data generated by the upper computer; a signal analysis device, which is respectively connected to the device under test and the vector signal source through the radio frequency transceiver, and is used to analyze the amplitude-frequency response and phase-frequency response of the received test radio frequency signal; an upper computer, which is connected to the device under test, and is used to send a digital broadband multi-tone baseband signal to the device under test, so that the device under test generates a radio frequency broadband multi-tone signal; and is further used to control the signal analysis device to perform a frequency response test on the radio frequency channel and display the test results.

[0007] In an embodiment of the present application, the digital processing module includes: a programmable logic device, which is used to implement baseband data transmission and radio frequency transceiver control; a memory, which is used to cache the baseband data generated by the upper computer; a clock chip, which receives the reference clock signal of the analog signal source, generates a synchronous clock signal and distributes it to the programmable logic device and the radio frequency transceiver.

[0008] In an embodiment of the present application, the radio frequency signal processing board includes: a radio frequency transceiver, which is used to implement the conversion between the baseband signal and the test radio frequency signal; a programmable logic device, which performs data interaction with the digital processing module through a preset communication protocol; a clock management unit, which receives the synchronous clock signal of the digital processing module and provides a radio frequency local oscillator synchronous signal for the radio frequency transceiver.

[0009] In an embodiment of the present application, the upper computer includes a graphical user module, and the graphical user module at least includes: a system configuration unit, which is used to set the bandwidth, local oscillator frequency and baseband data transmission parameters of the radio frequency transceiver; a signal generation unit, which is used to generate a multi-tone baseband signal covering the target bandwidth; an analysis and display unit, which is used to display the signal amplitude-frequency response and phase-frequency response test results.

[0010] The present application provides a method for testing the frequency response of a radio frequency channel. The method includes: a host computer generating a multi-tone baseband signal covering the target channel bandwidth; sending the multi-tone baseband signal to a radio frequency transceiver through a digital processing module and converting it into a test radio frequency signal for output to a signal analysis device; or, converting the multi-tone baseband signal into a test radio frequency signal through a vector signal source and inputting it into the radio frequency transceiver, and then transmitting the converted baseband data back to the digital processing module; performing amplitude-frequency response and phase-frequency response analysis on the test radio frequency signal or the baseband data to obtain an analysis result; and calculating the gain flatness and linear phase deviation of the target channel based on the analysis result.

[0011] In an embodiment of the present application, when testing the transmitting channel of a radio frequency signal processing board, the method includes: a host computer generating a multi-tone baseband signal covering the transmitting channel bandwidth and sending it to a radio frequency transceiver through a digital processing module; the radio frequency transceiver converting the baseband signal into a test radio frequency signal and outputting it to a signal analysis device; and the signal analysis device performing amplitude-frequency response and phase-frequency response analysis on the test radio frequency signal to calculate the gain flatness and linear phase deviation of the transmitting channel.

[0012] In an embodiment of the present application, when testing the receiving channel of a radio frequency signal processing board, the method includes: a vector signal source outputting a test radio frequency signal to a radio frequency transceiver based on a multi-tone baseband signal generated by a host computer; the radio frequency transceiver converting the test radio frequency signal into baseband data and transmitting it back to the digital processing module, so that the digital processing module caches the baseband data and uploads it to the host computer through a communication interface; and the host computer performing amplitude-frequency response and phase-frequency response analysis on the baseband data to calculate the gain flatness and linear phase deviation of the receiving channel.

[0013] In an embodiment of the present application, the frequency interval and coverage bandwidth of the multi-tone baseband signal are dynamically configured according to the transmitting or receiving channel bandwidth of the radio frequency transceiver.

[0014] In an embodiment of the present application, the amplitude-frequency response and phase-frequency response analysis are realized by extracting the frequency-domain power spectrum and phase spectrum.

[0015] The present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor of a computer, the computer is made to execute the method for testing the frequency response of a radio frequency channel as described above.

[0016] Advantages of the present application: In the radio frequency channel frequency response test system proposed in the present application, by introducing a combination of a vector signal source and a wideband multi-tone baseband signal, the entire operating frequency band of the device under test can be efficiently excited, enabling comprehensive testing of the amplitude-frequency response and phase-frequency response of the radio frequency transceiver channel, thereby improving the accuracy and integrity of the test. Secondly, adopting an architecture of collaborative control between the digital processing module and the host computer not only improves the real-time performance and flexibility of the system, but also realizes efficient caching and transmission of test data, enhancing the scalability and versatility of the system. In addition, through high-resolution frequency domain analysis of the received radio frequency signal by a signal analysis device, key performance indicators such as the gain flatness and linear phase deviation of the radio frequency channel can be accurately obtained, which is applicable to the research and development verification and batch detection of high-performance radio frequency devices. The analog signal source provides a unified synchronous clock signal for the system, ensuring the timing consistency of the operation between modules and further improving the stability and repeatability of the test results. Generally speaking, the solution proposed in the present application provides an accurate, stable and efficient radio frequency channel frequency response test system through the combination of a vector signal source and a wideband multi-tone baseband signal, collaborative control between the digital processing module and the host computer, and high-resolution frequency domain analysis.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Brief Description of the Drawings

[0018] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0019] Figure 1 is a block diagram of a radio frequency channel frequency response test system shown in an exemplary embodiment of the present application;

[0020] Figure 2 is a block diagram of an internal program module of an FPGA shown in an exemplary embodiment of the present application;

[0021] Figure 3 is a flowchart of the transmit channel test of a radio frequency channel frequency response test method shown in an exemplary embodiment of the present application;

[0022] Figure 4 is a flowchart of the receive channel test of a radio frequency channel frequency response test method shown in an exemplary embodiment of the present application;

[0023] Figure 5It is a schematic diagram of the spectrum of an ideal broadband multi-tone signal shown in an exemplary embodiment of the present application;

[0024] Figure 6 It is a test result graph of the in-band gain flatness of an integrated radio frequency transceiver shown in an exemplary embodiment of the present application;

[0025] Figure 7 It is a test result graph of the in-band linear phase deviation of an integrated radio frequency transceiver shown in an exemplary embodiment of the present application;

[0026] Figure 8 It shows a schematic diagram of the structure of a computer system of an electronic device suitable for implementing the embodiments of the present application. Detailed implementation manners

[0027] The following will describe the implementation manners of the present application with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for explaining the present application, rather than for limiting the protection scope of the present application.

[0028] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0029] In the following description, a large number of details are discussed to provide a more thorough explanation of the embodiments of the present application. However, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present application difficult to understand.

[0030] First of all, it should be noted that the IQ signal is a term used in a communication system to represent a complex baseband signal, where I represents the in-phase component and Q represents the quadrature component. Similarly, IQ data is discrete data used in a digital communication system to represent a complex baseband signal, where I represents the in-phase component and Q represents the quadrature component. In the specific implementation of the present application, its multi-tone baseband signal is mostly taken as an example of a multi-tone baseband IQ signal.

[0031] In addition, as can be seen from the aforementioned background art, the inventors have found through research that: with the development of wireless communication, radar detection, and software-defined radio (SDR) technologies, highly integrated radio frequency (RF) transceivers (such as AD9371, AD9361, LimeSDR, etc.) are different from traditional RF channels in that they directly perform the conversion from digital baseband signals to RF signals (Digital-to-RF). During the digital baseband to RF conversion process, the frequency response characteristics of the channel (including gain flatness and phase linearity) directly affect the quality of the RF signal. Gain flatness (BW Flatness) reflects the gain consistency of the transceiver for different frequency signals within the operating bandwidth, affecting the equalization of the amplitude response and the dynamic range of the system. The linear phase deviation (Deviation from Linear Phase) measures whether the phase response of the system is linear and has a significant impact on the demodulation error (EVM) of high-order modulation signals (such as 64-QAM, 256-QAM). Traditional RF channel testing mainly relies on instruments such as vector network analyzers (VNA) to perform frequency response testing on the end-to-end RF link. However, the testing method for integrated RF transceivers is different, and its main difficulties include: ① The signal enters the RF link after digital processing and frequency conversion, and the testing method needs to take into account the conversion process between the digital domain and the analog domain; ② Factors such as filters, gain control, and LO (local oscillator) errors inside the transceiver will affect the frequency response, and system-level testing is required; ③ Traditional S-parameter testing (such as S21) cannot be directly applied to the digital baseband to RF channel testing, and new testing methods need to be adopted.

[0032] Based on this, the present application provides a frequency response testing system for an RF channel, which includes: a digital processing module, an integrated RF transceiver module, a control terminal, an RF signal source, a clock signal source, and a signal analysis device.

[0033] Among them, the digital processing module is used for digital communication with the integrated RF transceiver, including the transceiver of baseband data, the configuration control of the RF transceiver, and the supply of a synchronous clock, and conducts data interaction with the control terminal; the integrated RF transceiver module is used for the transceiver of RF signals, its RF input end is connected to the RF signal source, its RF output end is connected to the signal analysis device, and its digital end is communicatively connected to the digital processing unit; the control terminal is used for testing system control and data processing and communicates with the digital processing unit; the RF signal source is used to provide a test RF signal to the integrated RF transceiver module; the clock signal source is used to provide a reference clock signal for the digital processing unit; the signal analysis device is used to analyze the RF signal output by the integrated RF transceiver module.

[0034] Figure 1 is a block diagram of the frequency response testing system for an RF channel shown in an exemplary embodiment of the present application.

[0035] AsFigure 1 As shown, in the embodiments of the present application, an FPGA digital processing board is used as the digital processing module, an integrated radio frequency transceiver board is used as the radio frequency signal processing board, and a signal analyzer is used as the specific signal analysis device.

[0036] Among them, the radio frequency output end of the vector signal source is connected to the radio frequency receiving end of the device under test through a radio frequency connector, and is used to provide a test radio frequency signal; the output end of the analog signal source is connected to the digital processing module, and is used to provide a synchronous clock signal; the radio frequency signal processing board (i.e., the device under test) includes a radio frequency transceiver channel, and the radio frequency transceiver channel is connected to the radio frequency transceiver through a radio frequency link; the digital processing module is connected to the digital end of the device under test through a digital interface, and is used to send baseband data and control signals to the device under test, and is connected to the upper computer through a communication interface, and is used to cache the baseband data generated by the upper computer; the signal analysis device is connected to the device under test and the vector signal source respectively through the radio frequency transceiver, and is used to analyze the amplitude-frequency response and phase-frequency response of the received test radio frequency signal; the upper computer is connected to the device under test, and is used to send a digital broadband multi-tone baseband signal to the device under test, so that the device under test generates a radio frequency broadband multi-tone signal; it is also used to control the signal analysis device to perform a frequency response test on the radio frequency channel and display the test results.

[0037] Generally speaking, the radio frequency channel frequency response test system proposed in the present application is based on the main test architecture of "FPGA digital processing board + integrated radio frequency transceiver board + upper computer", and realizes the test of channel gain flatness and phase linearity in the digital-to-radio frequency (Digital-to-RF) conversion process through the generation and analysis of vector signals in the digital domain and the analog domain; adopts the FPGA and vector signal analysis methods, does not require an expensive radio frequency network analyzer, and reduces the test cost compared with the traditional VNA test method for radio frequency channels; through the multi-tone signal test method, the gain flatness and linear phase deviation can be accurately measured at one time in a relatively wide frequency range, and the test efficiency is greatly improved compared with the traditional single-tone sweep test method.

[0038] Specifically, the FPGA digital processing board is used for digital communication with the integrated radio frequency transceiver board, including the reception and transmission of baseband data, the control of the radio frequency transceiver circuit, and the clock supply, and communicates with the upper computer; the integrated radio frequency transceiver board is used for the reception and transmission of radio frequency signals, its radio frequency receiving end receives the radio frequency signal provided by the vector signal source, its radio frequency output end is connected to the input end of the signal analyzer, and its digital end is connected to the FPGA digital processing board through an FMC connector; the upper computer is used for test system control and test data analysis, and communicates with the FPGA digital processing board; the vector signal source is used to provide radio frequency signals for the integrated radio frequency transceiver board; the analog signal source is used to provide clock signals for the FPGA digital processing board; the signal analyzer is used to analyze the radio frequency signals output by the integrated radio frequency transceiver board.

[0039] In one embodiment of the present application, the digital processing module includes: a programmable logic device for implementing baseband data transmission and radio frequency transceiver control; a memory for caching baseband data generated by the host computer; and a clock chip that receives a reference clock signal from an analog signal source, generates a synchronous clock signal, and distributes it to the programmable logic device and the radio frequency transceiver.

[0040] In a specific embodiment of the present application, the FPGA digital processing board acts as a master control unit in the test system and is responsible for three tasks: ① Interaction with the host computer, including parsing instructions issued by the host computer, storing baseband IQ data of the radio frequency transceiver TX channel issued by the host computer, and uploading baseband IQ data of the radio frequency transceiver RX channel to the host computer; ② Interaction with the integrated radio frequency transceiver, including initializing and configuring the radio frequency transceiver, function control, GPIO control, and baseband IQ data transmission based on the JESD204B interface; ③ Control of the test system clock, including control of the clock chip and control of the system clock.

[0041] In one embodiment of the present application, the programmable logic device of the FPGA includes: a baseband data transmission unit for performing bidirectional data transmission with the integrated radio frequency transceiver module through a preset serial communication protocol; a configuration control unit for initializing and configuring the integrated radio frequency transceiver module and performing function control through a serial interface; a clock control unit for receiving an external reference clock signal and generating a system clock signal and a synchronization signal to ensure timing synchronization between the digital processing module and the integrated radio frequency transceiver module; and a processing core for executing control instructions to implement function calls to the integrated radio frequency transceiver module.

[0042] Figure 2 It is a block diagram of the internal program module of the FPGA shown in an exemplary embodiment of the present application.

[0043] In a specific embodiment of the present application, the internal program module of the FPGA is as Figure 2As shown in the figure. The communication between the FPGA and the host computer is mainly through the USB Controller module, which: ① can control the AXI Controller module to dynamically configure the parameters of JESD204B RX, JESD204B TX, JESD204B PHY, and MMCM; ② can control the SPI / GPIO module to configure and control the radio frequency transceiver; ③ can upload / download the baseband IQ data in the DDR cache. The data interaction between the FPGA and the radio frequency transceiver is mainly through JESD204B RX, JESD204B TX, and JESD204B PHY. These three modules are used to receive and transmit the baseband IQ data with the radio frequency transceiver based on the JESD204B protocol. The FPGA can also control the HMC7044 clock chip on the FPGA digital processing board through the SPI / GPIO module, so that it outputs a global clk clock to the MMCM module to generate the core clock for JESD204B communication, outputs a ref clk clock to the JESD204B PHY module for the reference clock of the internal PLL of the digital transceiver, outputs a device clk clock to the integrated radio frequency transceiver for the reference clock of the internal PLL, and additionally outputs two sysref signals to JESD204B RX / JESD204B TX and the radio frequency transceiver respectively for the synchronization of JESD204B communication. In addition, an ARM processor is integrated inside the FPGA, which can directly call the API function library of the integrated radio frequency transceiver to control it.

[0044] In addition, in an embodiment of the present application, the integrated radio frequency transceiver adopts a zero-intermediate frequency architecture, with a receive bandwidth of 100 MHz. After the radio frequency signal is quadrature down-converted, filtered, and ADC sampled, the baseband IQ data is directly obtained. The IQ data rate is set to 122.88 Msps; the transmit bandwidth is 200 MHz. After the baseband IQ data is DAC-converted, filtered, and quadrature up-converted, the radio frequency signal is output. The IQ data rate is set to 245.76 Msps. The baseband IQ data is transmitted through the JESD204B interface. The serial transceiver is 4 channels respectively (RX / TX Lanes = 4), and the number of data converters is 4 respectively (M = 4). Therefore, the line rate at the TX end is 4915.2 Msps, and the line rate at the RX end is 2457.6 Msps.

[0045] In an embodiment of the present application, the control terminal includes a graphical user module, which at least includes a system configuration unit, a signal generation unit, and an analysis and display unit. The system configuration unit is used to set the bandwidth, local oscillator frequency, and baseband data transmission parameters of the radio frequency transceiver; the signal generation unit is used to generate a multi-tone baseband signal covering the target bandwidth; the analysis and display unit is used to display the test results of the signal amplitude-frequency response and phase-frequency response.

[0046] Specifically, the system configuration unit is used to set the operating parameters of the RF transceiver under test, including the operating bandwidth, local oscillator frequency, baseband data format, sampling rate, etc., and send the configuration information to the digital processing module through the communication interface, thereby controlling the operating state of the device under test. The signal generation unit provides an interface for generating multi-tone baseband signals. The user can set the number of multi-tone signals, frequency interval, phase characteristics, and coverage bandwidth. The system automatically generates the corresponding digital broadband multi-tone baseband signal according to the set parameters and transmits it to the host computer buffer. Then, the digital processing module reads and sends it to the device under test for RF conversion. The analysis and display unit receives the test result data from the signal analysis device, visualizes the amplitude-frequency response curve and phase-frequency response curve of the RF channel, supports the intuitive presentation of key indicators such as gain flatness and linear phase deviation, and provides a test report generation function.

[0047] It can be understood that during the test process, the host computer coordinates the operation process of the entire system through the graphical user module, realizing human-computer interaction and automated control in the whole process from parameter configuration, signal excitation to data analysis, significantly improving the test efficiency and operation convenience.

[0048] In a specific embodiment of the present application, the above-mentioned graphical user module is specifically a graphical user interface, and the graphical user interface specifically includes at least one of the following: a system configuration interface for configuring parameters of the digital processing unit and the integrated RF transceiver module, including clock frequency setting, RF transceiver bandwidth configuration, local oscillator frequency setting, and baseband data transmission protocol parameter adjustment; a waveform generation and analysis interface for generating broadband multi-tone baseband IQ signals within a preset bandwidth, where the multi-tone signals include multiple tones with equal amplitudes and randomly distributed phases, and performing real-time analysis of the amplitude-frequency response and phase-frequency response of the baseband or RF signals output by the integrated RF transceiver module; a device control interface for controlling the carrier frequency, output power of the RF signal source, and acquisition parameters of the signal analysis device; a data visualization interface for real-time displaying the time-domain waveform, frequency-domain spectrum of the baseband IQ signal of the integrated RF transceiver module, and test results; an automated test interface for automatically executing parameter configuration, data acquisition, and analysis through a preset test process script and generating a test report.

[0049] In a specific embodiment of the present application, the host computer has an integrated visualization interface, including a system clock configuration interface, an integrated radio frequency transceiver configuration interface, an RX IQ data display and analysis interface, a TX IQ data waveform generation interface, a parameter test interface, and a device program control interface. Among them, the clock configuration interface can configure the output clock of the HMC7044 to meet the requirements of the test system; the integrated radio frequency transceiver configuration interface can configure the bandwidth of the transceiver, the baseband IQ rate, the JESD204B line rate, GPIO, etc.; the RX IQ data display and analysis interface can display the time-domain and frequency-domain waveforms of the RX baseband IQ data in real time, and can dynamically set the sampling data length and channel gain control; the TX IQ data waveform generation interface can select the type, amplitude, and length of the generated waveform, and can display the time-domain and frequency-domain waveforms of the generated waveform; the parameter test interface can test and display the results of parameters such as the channel gain flatness and phase linearity of the radio frequency transceiver in real time; the device program control interface can program devices such as vector signal sources and signal analyzers.

[0050] In addition, the present application also proposes a method for testing the frequency response of a radio frequency channel. The method includes: the host computer generates a multi-tone baseband signal covering the target channel bandwidth; the multi-tone baseband signal is sent to the radio frequency transceiver through the digital processing module and converted into a test radio frequency signal for output to the signal analysis device; or, the multi-tone baseband signal is converted into a test radio frequency signal by the vector signal source and input to the radio frequency transceiver, and the converted baseband data is sent back to the digital processing module; the amplitude-frequency response and phase-frequency response of the test radio frequency signal or baseband data are analyzed to obtain the analysis result; based on the analysis result, the gain flatness and linear phase deviation of the target channel are calculated.

[0051] Among them, the generation parameters of the multi-tone baseband signal include the number of tones, the adjacent tone interval, and the coverage bandwidth. The parameters are configured according to the transmit or receive bandwidth of the integrated radio frequency transceiver module; the phase distribution of the multi-tone signal is random or preset; the amplitude-frequency response and phase-frequency response analysis extract the power spectral density and phase information of the signal through a preset frequency-domain analysis method and compare it with the ideal baseband signal to determine the gain flatness and linear phase deviation of the channel.

[0052] Based on the characteristics of the integrated radio frequency transceiver, the method for testing the frequency response of its radio frequency channel is specifically divided into a transmit channel and a receive channel, as follows:

[0053] In an embodiment of the present application, when testing the transmission channel of a radio frequency signal processing board, the method includes: the host computer generates a multi-tone baseband signal covering the bandwidth of the transmission channel and sends it to the radio frequency transceiver through the digital processing module; the radio frequency transceiver converts the baseband signal into a test radio frequency signal and outputs it to the signal analysis device; the signal analysis device analyzes the amplitude-frequency response and phase-frequency response of the test radio frequency signal to calculate the gain flatness and linear phase deviation of the transmission channel.

[0054] Figure 3 It is the flowchart of the transmission channel test in the radio frequency channel frequency response test method shown in an exemplary embodiment of the present application.

[0055] As Figure 3 shown, when testing the transmission channel of the integrated radio frequency transceiver, it specifically includes the following steps:

[0056] S11. Based on the above integrated radio frequency transceiver test system, the host computer generates an ideal digital broadband multi-tone baseband IQ signal with a certain data length and sends it to the FPGA digital processing board;

[0057] S12. The FPGA digital processing board stores the broadband multi-tone baseband IQ signal and cyclically sends it to the integrated radio frequency transceiver board through the JESD204B protocol;

[0058] S13. After receiving the broadband multi-tone baseband IQ signal, the integrated radio frequency transceiver board generates an analog baseband signal inside the integrated radio frequency transceiver, up-converts it with the local oscillator signal, and outputs a radio frequency broadband multi-tone signal through the transmission channel to the signal analyzer;

[0059] S14. The signal analyzer performs amplitude-frequency response analysis on the received radio frequency broadband multi-tone signal through vector signal analysis software to obtain the in-band gain flatness test result of the transmission channel of the integrated radio frequency transceiver;

[0060] S15. The signal analyzer performs phase-frequency response analysis on the received radio frequency broadband multi-tone signal through vector signal analysis software and compares it with the phase-frequency characteristics of the known generated ideal digital multi-tone broadband baseband to obtain the in-band linear phase deviation test result of the transmission channel of the integrated radio frequency transceiver.

[0061] Specifically, in step S11, a multi-tone baseband IQ signal required for testing is generated through the TX IQ data waveform generation interface of the host computer. The multi-tone baseband IQ signal covering the transmitter bandwidth can measure the frequency response characteristics of the transmit channel at one time. To improve the test accuracy, the baseband IQ signal uses an equal-amplitude multi-tone signal with 666 tones and an adjacent tone interval of 300 KHz. The sampling rate is 245.76 Msps, the IQ data length is 32768, the phase of each tone is random and known, and the entire multi-tone signal covers a bandwidth of approximately 200 MHz. The generation formula of the multi-tone signal is:

[0062]

[0063] where N represents the number of multi-tone signals; A represents the amplitude of each tone (equal); f k = f start + k·Δf, the frequency of the k-th tone, the starting frequency f start is set to a certain baseband frequency, and the tone interval is Δf; φ k represents that the phase of each tone is random, and φ k u(0, 2π) follows a uniform distribution; j is the imaginary unit.

[0064] It should be noted that the spectrum of the multi-tone signal generated based on Equation (1) is specifically as Figure 5 shown.

[0065] In step S12, the FPGA digital processing board is responsible for storing, managing, and circularly sending the broadband multi-tone baseband IQ signal to the integrated radio frequency transceiver board. The data is transmitted through the JESD204B high-speed serial interface to ensure high-speed and high-precision data communication. The FPGA uses DDR3 as a cache to store the received IQ data. The IQ signal is usually in a fixed-point format (16-bit I + 16-bit Q). As the data sender, the FPGA uses the SERDES IP to pack the IQ data into a JESD204B-compatible format and then transmits it to the integrated radio frequency transceiver. The data uses 8B / 10B encoding to ensure synchronous transmission and error detection capabilities.

[0066] In step S13, the integrated RF transceiver board receives the broadband multi-tone baseband IQ signal sent from the FPGA digital processing board, and through internal digital-to-analog conversion (DAC), local oscillator (LO) mixing, and RF signal amplification, finally generates an RF broadband multi-tone signal, which is output through the transmit channel (TX) to the signal analyzer for subsequent test and analysis. The LO frequency can be configured in the range of 300 MHz to 6 GHz, and a specific frequency point (such as 2.2 GHz) is selected according to the test requirements. The RF broadband multi-tone signal is output through the TX port (external SMA interface) of the RF transceiver. If the test frequency band is set to 2.2 GHz and the bandwidth is 200 MHz, the center frequency of the output signal is 2.2 GHz, and the signal bandwidth covers 2.1 GHz to 2.3 GHz. The RF signal is connected to the signal analyzer (such as Keysight PXA / N9040 or R&S FSW) through a coaxial cable for subsequent gain flatness and phase deviation tests.

[0067] In step S14, the signal analyzer performs an amplitude-frequency response analysis on the received RF broadband multi-tone signal through vector signal analysis (VSA) software to obtain the in-band gain flatness test result of the transmit channel (TX) of the integrated RF transceiver. The RF broadband multi-tone signal is converted into baseband IQ data after passing through the front-end signal conditioning, signal down-conversion, and sampling inside the signal analyzer. The amplitude-frequency response test principle is to calculate the amplitude-frequency characteristics of the signal through fast Fourier transform (FFT) based on the baseband IQ data to obtain the multi-tone spectrum, and then calculate the gain flatness of each tone according to the power spectral density.

[0068] In step S15, the signal analyzer performs a phase-frequency response analysis on the received RF broadband multi-tone signal through vector signal analysis (VSA) software and compares it with the known ideal baseband multi-tone signal to measure the in-band linear phase deviation of the transmit channel (TX) of the integrated RF transceiver. The phase-frequency response test principle is to perform fast Fourier transform (FFT) based on the baseband IQ data to extract the phase information of each tone. In the baseband signal generation stage (S11), the phase information of the ideal multi-tone baseband IQ signal is known. The phase information of each tone extracted by the signal analyzer is compared with the known phase information of the original signal to obtain the deviation between the actual phase response and the ideal phase response.

[0069] In another embodiment of the present application, the receiving channel of the radio frequency signal processing board is tested. The method includes: a vector signal source outputs a test radio frequency signal to a radio frequency transceiver based on a multi-tone baseband signal generated by a host computer; the radio frequency transceiver converts the test radio frequency signal into baseband data and sends it back to a digital processing module, so that the digital processing module caches the baseband data and uploads it to the host computer through a communication interface; the host computer analyzes the amplitude-frequency response and phase-frequency response of the baseband data to calculate the gain flatness and linear phase deviation of the receiving channel.

[0070] Figure 4 It is a flowchart of the receiving channel test of the radio frequency channel frequency response test method shown in an exemplary embodiment of the present application.

[0071] As Figure 4 shown, the testing of the receiving channel of the integrated radio frequency transceiver specifically includes the following steps:

[0072] S21, based on the above integrated radio frequency transceiver test system, the host computer generates an ideal digital broadband multi-tone baseband IQ signal with a certain data length, packs it into a specific format and imports it into the vector signal source for playback, and the output radio frequency broadband multi-tone signal is sent to the radio frequency input end of the integrated radio frequency transceiver board;

[0073] S22, after the integrated radio frequency transceiver board receives the radio frequency broadband multi-tone signal, it outputs broadband multi-tone baseband IQ data after internal down-conversion and sampling processing, and the multi-tone baseband IQ data is sent to the FPGA digital processing board through the JESD204B protocol;

[0074] S23, the FPGA digital processing board caches the multi-tone baseband IQ data and uploads it to the host computer;

[0075] S24, the host computer performs amplitude-frequency response analysis on the obtained multi-tone baseband IQ data through vector signal analysis software to obtain the in-band gain flatness test result of the integrated radio frequency transceiver receiving channel;

[0076] S25, the host computer performs phase-frequency response analysis on the obtained multi-tone baseband IQ data through vector signal analysis software, and compares it with the phase-frequency characteristics of the known generated ideal digital multi-tone baseband to obtain the in-band linear phase deviation test result of the integrated radio frequency transceiver receiving channel.

[0077] Specifically, in step S21, a multi-tone baseband IQ signal required for testing is generated through the waveform generation interface of the host computer. The multi-tone baseband IQ signal covering the receiver bandwidth can measure the frequency response characteristics of the receiving channel at one time. To improve the test accuracy, the baseband IQ signal uses an equal-amplitude multi-tone signal with 666 tones and an adjacent tone interval of 150 KHz, a sampling rate of 122.88 Msps, an IQ data length of 32768, the phase of each tone is random and known, and the entire multi-tone signal covers a bandwidth of approximately 100 MHz. An ideal broadband multi-tone baseband IQ signal is generated and packaged into a specific format and imported into a vector signal source (VSG, Vector Signal Generator), and then the vector signal source generates a radio frequency broadband multi-tone signal and sends it to the radio frequency input end of the integrated radio frequency transceiver (RF Transceiver) board. The carrier frequency range of the vector signal source can be set to 300 MHz to 6 GHz, for example, set to 2.2 GHz; the radio frequency output power is set, for example, -20 dBm to -15 dBm, to avoid saturation of the integrated transceiver RX channel.

[0078] In step S22, the integrated radio frequency transceiver receives the radio frequency broadband multi-tone signal sent by the vector signal source (VSG), and through its internal down-conversion and analog-to-digital conversion (ADC), converts the analog signal into digital baseband IQ data, and finally sends it to the FPGA digital processing board through the JESD204B interface for caching and subsequent analysis. If the signal center frequency is set to 2.2 GHz and the bandwidth is 100 MHz, the output baseband signal bandwidth covers -50 MHz to 50 MHz.

[0079] In step S23, the FPGA needs to cache and format the received IQ data and upload it to the host computer through a high-speed data interface (such as PCIe, Ethernet, UART, USB, etc.) for subsequent signal analysis. The data storage method uses a FIFO+DDR3 buffering mechanism to ensure that data acquisition and upload do not conflict, and the data format can be repackaged according to the requirements of the host computer.

[0080] In step S24, the goal is to analyze the gain flatness of the receiving channel, that is, to evaluate the gain response consistency of the integrated radio frequency transceiver receiving link for different frequency components. To analyze the gain of the signal in the frequency domain, it is necessary to perform an amplitude-frequency response analysis on the received baseband IQ signal. The amplitude-frequency response test principle is to calculate the amplitude-frequency characteristics of the signal based on the baseband IQ data through a fast Fourier transform (FFT) to obtain a multi-tone spectrum, and then calculate the gain flatness of each tone according to the power spectral density.

[0081] In step S25, the goal is to analyze the linear phase characteristics of the receiving channel, that is, to evaluate whether the phase response of the integrated RF transceiver receiving link to different frequency components is linear, and then calculate the linear phase deviation. To analyze the phase response of the signal in the frequency domain, it is necessary to perform a Phase-Frequency Response analysis on the received baseband IQ signal and compare it with a known ideal baseband multi-tone signal to measure the in-band linear phase deviation (Deviation from Linear Phase) of the integrated RF transceiver receiving channel (RX). The principle of the phase-frequency response test is based on performing a Fast Fourier Transform (FFT) on the baseband IQ data to extract the phase information of each tone. In the baseband signal generation stage (S11), the phase information of the ideal multi-tone baseband IQ signal is known. By comparing the phase information of each tone extracted by the signal analyzer with the known phase information of the original signal, the deviation between the actual phase response and the ideal phase response is obtained.

[0082] In a specific embodiment of the present application, the channel frequency response of the integrated RF transceiver was tested. The product manual of this transceiver shows that the in-band gain flatness of the transmit channel is ±0.5 dB, and the in-band linear phase deviation is ±5°; the in-band gain flatness of the receive channel is ±0.5 dB, and the in-band linear phase deviation is ±5°. After actual measurement, the indicators all meet the values in the product manual. Some test results are shown in Figure 6 、 Figure 7 as shown

[0083] In summary, the RF channel frequency response test system and method proposed in this application, through the test architecture of "FPGA digital processing board + integrated RF transceiver board + host computer", combined with digital baseband signal generation, vector signal analysis and automated data processing, realizes the efficient test of the gain flatness and phase linearity of the digital baseband to RF (Digital-to-RF) channel. Compared with the traditional RF network analyzer (VNA) test method, this application does not require expensive test equipment and can complete the frequency response test of the RF channel by using FPGA and vector signal analysis technology, thus greatly reducing the test cost. In addition, this application adopts the broadband multi-tone signal test method, which can accurately measure the gain flatness and linear phase deviation at one time within a wide frequency range. Compared with the traditional single-tone sweep test method, it not only improves the test efficiency, but also avoids the interpolation error between frequency points, making the measurement results more accurate and reliable. The test system of this application supports automated control and data analysis, and can be applied to product R & D, production testing and on-line detection, especially suitable for high-frequency broadband RF systems in the fields of wireless communication, radar, satellite communication and software radio (SDR). At the same time, this method is applicable to modern highly integrated RF transceivers, such as 5G communication systems, millimeter-wave communication devices, system-on-chip (SoC) RF modules, etc., and can meet the development needs of current and future wireless communication technologies. Generally speaking, the RF channel frequency response test system and method proposed in this application have significant advantages in terms of cost control, test efficiency, measurement accuracy and engineering applicability, and can provide an efficient, low-cost and high-precision test solution for the performance evaluation of integrated RF transceivers, and have broad application prospects in the fields of RF testing, wireless communication, integrated circuit design and production.

[0084] Figure 8 FIG. shows a schematic structural diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application. It should be noted that Figure 8 The computer system 800 of the electronic device shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0085] As Figure 8As shown, the computer system 800 includes a Central Processing Unit (CPU) 801, which can perform various appropriate actions and processes according to the program stored in the Read-Only Memory (ROM) 802 or the program loaded from the storage section 808 into the Random Access Memory (RAM) 803, such as executing the method described in the above embodiments. In the RAM 803, various programs and data required for system operation are also stored. The CPU 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An Input / Output (I / O) interface 805 is also connected to the bus 804.

[0086] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including, for example, a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read from it can be installed into the storage section 808 as needed.

[0087] Specifically, according to the embodiments of the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments of the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network via the communication section 809, and / or installed from the removable medium 811. When the computer program is executed by the Central Processing Unit (CPU) 801, various functions defined in the system of the present application are executed.

[0088] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted by any suitable medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0089] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the above module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0090] The units involved in the embodiments described in this application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not, in some cases, constitute a limitation on the units themselves.

[0091] Another aspect of this application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor of the computer, the computer is caused to execute the radio frequency channel frequency response test method as described above. The computer-readable storage medium can be included in the electronic device described in the above embodiments, or can exist alone without being assembled into the electronic device.

[0092] Another aspect of this application also provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the radio frequency channel frequency response test method provided in the above various embodiments.

[0093] The above embodiments only exemplarily illustrate the principles and effects of this application, rather than limiting this application. Any person familiar with this technology can make modifications or changes to the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in this application should still be covered by the claims of this application.

Claims

1. A radio frequency channel frequency response test system, characterized in that, The system includes: A vector signal source, whose RF output terminal is connected to the RF receiving terminal of the device under test through an RF connector, and is used to provide a test RF signal; An analog signal source, whose output terminal is connected to the digital processing module, and is used to provide a synchronous clock signal; A device under test, which is an RF signal processing board and includes an RF transceiver channel. The RF transceiver channel is connected to an RF transceiver through an RF link; A digital processing module, which is connected to the digital terminal of the device under test through a digital interface, and is used to send baseband data and control signals to the device under test; and is connected to a host computer through a communication interface, and is used to cache the baseband data generated by the host computer; A signal analysis device, which is respectively connected to the device under test and the vector signal source through the RF transceiver, and is used to perform amplitude-frequency response and phase-frequency response analysis on the received test RF signal; A host computer, which is connected to the device under test, and is used to send a digital broadband multi-tone baseband signal to the device under test so that the device under test generates an RF broadband multi-tone signal; and is also used to control the signal analysis device to perform a frequency response test on the RF channel and display the test results.

2. The radio frequency channel frequency response test system according to claim 1, characterized in that, The digital processing module includes: A programmable logic device, which is used to implement baseband data transmission and RF transceiver control; A memory, which is used to cache the baseband data generated by the host computer; A clock chip, which receives the reference clock signal of the analog signal source, generates a synchronous clock signal and distributes it to the programmable logic device and the RF transceiver.

3. The radio frequency channel frequency response test system according to claim 1, wherein The RF signal processing board includes: An RF transceiver, which is used to implement the conversion between the baseband signal and the test RF signal; A programmable logic device, which performs data interaction with the digital processing module through a preset communication protocol; A clock management unit, which receives the synchronous clock signal of the digital processing module and provides an RF local oscillator synchronous signal for the RF transceiver.

4. The radio frequency channel frequency response test system according to claim 1, characterized in that The host computer includes a graphical user module, and the graphical user module at least includes: A system configuration unit, which is used to set the bandwidth, local oscillator frequency and baseband data transmission parameters of the RF transceiver; A signal generation unit, which is used to generate a multi-tone baseband signal covering the target bandwidth; An analysis and display unit, which is used to display the amplitude-frequency response and phase-frequency response test results of the signal.

5. A method for testing the frequency response of a radio frequency channel, characterized in that, The method includes: The host computer generates a multi-tone baseband signal covering the target channel bandwidth; Sending the multi-tone baseband signal to the RF transceiver through the digital processing module and converting it into a test RF signal for output to the signal analysis device; or, converting the multi-tone baseband signal into a test RF signal through the vector signal source and inputting it into the RF transceiver, and then sending back the converted baseband data to the digital processing module; Performing amplitude-frequency response and phase-frequency response analysis on the test RF signal or the baseband data to obtain an analysis result; Calculating the gain flatness and linear phase deviation of the target channel based on the analysis result.

6. The radio frequency channel frequency response testing method according to claim 5, wherein Testing the transmission channel of the RF signal processing board, and the method includes: The host computer generates a multi-tone baseband signal covering the transmission channel bandwidth and sends it to the RF transceiver through the digital processing module; The RF transceiver converts the baseband signal into a test RF signal and outputs it to the signal analysis device; The signal analysis device analyzes the amplitude-frequency response and phase-frequency response of the test radio frequency signal to calculate the gain flatness and linear phase deviation of the transmit channel.

7. The radio frequency channel frequency response test method according to claim 5, characterized in that Testing the receive channel of the radio frequency signal processing board, the method includes: The vector signal source outputs a test radio frequency signal to the radio frequency transceiver based on the multi-tone baseband signal generated by the host computer; The radio frequency transceiver converts the test radio frequency signal into baseband data and transmits it back to the digital processing module, so that the digital processing module caches the baseband data and uploads it to the host computer through the communication interface; The host computer analyzes the amplitude-frequency response and phase-frequency response of the baseband data to calculate the gain flatness and linear phase deviation of the receive channel.

8. The radio frequency channel frequency response testing method according to any one of claims 5-7, characterized in that The frequency interval and coverage bandwidth of the multi-tone baseband signal are dynamically configured according to the transmit or receive channel bandwidth of the radio frequency transceiver.

9. The radio frequency channel frequency response testing method according to any one of claims 5-7, characterized in that The amplitude-frequency response and phase-frequency response analysis are realized by extracting the frequency domain power spectrum and phase spectrum.

10. A computer-readable storage medium, characterized in that, It stores a computer program, when the computer program is executed by the processor of the computer, it causes the computer to execute the radio frequency channel frequency response test method according to any one of claims 5 to 9.

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