Physical layer signal techniques to maintain DC line balance

Abstract

The invention relates to physical layer signal techniques to maintain DC line balance. In some embodiments, a communication device is provided that is configured to receive power and transmit data signals through a pair of differential conductors. A communication device includes circuitry configured to generate or receive a common mode voltage via a differential pair; and at least one of: a circuit configured to, in response to detecting an edge of the input digital signal via the input conductor, transmit a pair of output pulses based on the detected edge via the differential pair; or a circuit configured to detect an input of the pair of pulses via the differential pair and adjust a signal indicative of a logic value transmitted via the output conductor based on the input of the pair of pulses.

Description

Technical Field

[0001] This application generally relates to differential signaling, and more particularly but not limited to, differential signaling techniques for data-powered environments. Background Art

[0002] In differential signaling, the voltages of two conductors are compared to determine the logical value represented by the signal. Generally, a high voltage difference will represent a first logical value (such as 0), and a low voltage difference will represent a second logical value (such as 1). If the data line is used to transmit power to a load, the differential signal can be separated by a DC voltage offset. One problem with implementing differential signals coupled with DC power transmission is maintaining the concept of DC balance. If too many symbols of the same value are transmitted on the differential conductor pair, the voltage difference may be absorbed by the coupling circuit, and data may be corrupted or lost. This is a problem when differential signals are provided on the same pair of differential conductors used for power supply, because the coupling circuit includes capacitors for preventing direct current from reaching the transceiver and is more likely to filter out the overflow of matching logical values. Summary of the Invention

[0003] This summary is provided to introduce a series of concepts in a simplified form that will be further described in the detailed description below. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0004] In some embodiments, a method of receiving power and transmitting data signals through a differential conductor pair is provided. A common-mode voltage is generated or received through the differential pair. In response to detecting an edge of an input digital signal via an input conductor, a pair of pulses is transmitted via the differential pair based on the edge.

[0005] In some embodiments, a method of receiving power and data signals through a differential conductor pair is provided. A common-mode voltage is generated or received through the differential pair. A signal indicating a logical value is transmitted through an output conductor. A pair of pulses is detected through the differential pair, and the signal indicating the logical value is adjusted based on the pair of pulses.

[0006] In some embodiments, a communication device is provided that is configured to receive power and transmit data signals via a differential conductor pair. The communication device includes: a circuit configured to generate or receive a common-mode voltage via the differential pair; at least one of the following: a circuit configured to transmit an output pulse pair via the differential pair based on a detected edge in response to detecting an edge of an input digital signal via an input conductor; or a circuit configured to detect an input pulse pair via the differential pair and adjust a signal indicating a logical value transmitted through an output conductor based on the input pulse pair. Brief Description of the Drawings

[0007] When combined with the accompanying drawings, the above aspects of the present invention and many attendant advantages will be more readily understood by reference to the following detailed description, in which:

[0008] Figure 1 is a schematic diagram of a system according to various aspects of the present disclosure that uses pairs of pulses to maintain DC line balance during differential signaling in a data-powered environment.

[0009] Figure 2A and Figure 2B is a schematic diagram showing a non-limiting example embodiment of a communication device according to various aspects of the present disclosure.

[0010] Figure 3 is a signal diagram showing a non-limiting example embodiment of signaling according to various aspects of the present disclosure.

[0011] Figure 4 is a flowchart showing a non-limiting example embodiment of a method for receiving power and communication through a differential conductor pair according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0012] Previous attempts to solve the DC line balance problem typically used software to generate a specific data encoding before the physical layer to avoid runs of the same value greater than a given length. While these techniques can solve the DC line balance problem, they require adding additional software to the software stack to generate the encoding. Techniques for maintaining DC line balance within the physical layer circuit without using any specific encoding of the data in the software are preferred, especially in cases where power is added to the physical layer in a system where there is already a software stack without DC line balance encoding.

[0013] Although there have been some attempts to solve the DC line balance problem at the physical layer, these attempts have not been ideal. For example, on-off keying (OOK) can be used to signal digital values. However, OOK encoding is sensitive to noise near the carrier frequency and can cause pulse width distortion. Other methods require a clock for encoding within the transceiver. What is desired is a technique for differential signaling that solves the DC line balance problem at the physical layer without using a clock signal or synchronization between the transmitter and receiver to achieve successful communication.

[0014] In embodiments of the present disclosure, techniques are provided for differential signaling on a single pair of wired conductors that maintain DC line balance at the physical layer regardless of any data encoding. Edge-based dual-pulse reverse-polarity return-to-common-mode signaling techniques are used to achieve DC line balance without a clock or other encoding from outside the physical layer.

[0015] Figure 1FIG. 0 is a schematic diagram of a system according to various aspects of the present disclosure that uses pairs of pulses to maintain DC line balance during differential signaling in a data-powered environment. In system 100, a plurality of communication devices including a first communication device 102, a second communication device 104, and a third communication device 106 are shown coupled to a two-conductor bus 110. In some embodiments, the communication devices may communicate using half-duplex asynchronous techniques including, but not limited to, Universal Asynchronous Receiver / Transmitter (UART) techniques.

[0016] The two-conductor bus 110 can be any two conductors suitable for transmitting differential signals and power. As a non-limiting example, the two-conductor bus 110 can be two conductors in a twisted pair of conductors. As another non-limiting example, the two-conductor bus 110 can be two conductors of a ribbon cable. In other examples, any other type of conductor suitable for transmitting differential signals can be used, including, but not limited to, traces on a printed circuit board. The term "differential pair" can be used interchangeably with the term "two-conductor bus" herein because both terms describe a pair of conductors that can be used in part to carry differential signals. By implementing communication and power supply on two conductors instead of using a greater number of conductors, the number of conductors can be reduced because separate conductor pairs are typically used for communication and power supply.

[0017] As shown, system 100 further includes a power supply 108 coupled to the two-conductor bus 110. The power supply 108 can be any type of DC power supply and can provide any suitable DC voltage to the two-conductor bus 110, including, but not limited to, any voltage in the range of 5V - 24V. Although shown as a separate device in Figure 1 , in some embodiments, the power supply 108 can be incorporated into one of the communication devices in system 100. Additionally, although only a single power supply 108 is shown, in some embodiments, multiple power supplies 108 may be present within system 100 and these power supplies 108 are coupled to the two-conductor bus 110.

[0018] Although Figure 1 shows three communication devices, it will be appreciated that more or fewer communication devices may be present in system 100 and these communication devices are coupled to the two-conductor bus 110. For example, in some embodiments, the two-conductor bus 110 can directly connect the first communication device 102 to the second communication device 104 without connecting other communication devices to the two-conductor bus 110. As another example, in some embodiments, the two-conductor bus 110 can have more than three communication devices coupled thereto.

[0019] System 100 is shown and described as a general "communication device" to avoid obscuring the inventive aspects of the present disclosure. In some embodiments, the communication device may be coupled to a microcontroller, or coupled to / included in other types of devices that can communicate via a two-conductor bus 110. As a non-limiting example, System 100 may provide building automation functionality, where the communication device is coupled to or incorporated into devices including two or more of a controller device, a programmable logic controller (PLC) of an HVAC system or other physical plant machine, an environmental sensor, a security sensor, a building access control system device, or any other type of device. In other embodiments, System 100 may support factory automation or robotic applications. Building automation, factory automation, and robotics are only non-limiting examples, and in other embodiments, any other type of device that communicates via the two-conductor bus 110 may be used in System 100.

[0020] Figure 2A and Figure 2B is a schematic diagram showing non-limiting example embodiments of a communication device in accordance with various aspects of the present disclosure. The illustrated communication device 202 can be used to implement Figure 1 the first communication device 102, the second communication device 104, and / or the third communication device 106 in System 100 of

[0021] As Figure 2A shown, the communication device 202 is coupled to the first conductor 208 and the second conductor 210 of the two-conductor bus 110 at terminals labeled A and B, respectively. Although Figure 2A only a single communication device 202 is shown, it should be understood that, as Figure 1 shown, at least one other communication device 202 may be coupled to the first conductor 208 and the second conductor 210.

[0022] Each of the first conductor 208 and the second conductor 210 is coupled to the communication device 202 through a capacitor, and the first conductor 208 and the second conductor 210 are coupled together through a resistor between the capacitor and the communication device 202, which is common in a differential signal circuit. The capacitor is configured to block direct current from reaching terminals A and B, such that terminals A and B receive and / or transmit alternating current (AC) differential signals. In some embodiments, the circuitry for providing terminals A and B may include circuitry compatible with the RS-485 communication standard.

[0023] The portions of the first conductor 208 and the second conductor 210 that are further from the communication device 202 than the capacitor are also coupled to the communication device 202 through a rectifier circuit 206, an inductor, and a terminal labeled V raw This coupling provides direct current from the first conductor 208 and the second conductor 210 to V rawTerminal. The inductor blocks the AC signal from reaching V raw Terminal, and the rectifier circuit 206 allows DC power to be supplied to either the first conductor 208 or the second conductor 210. Any suitable circuit can be used for the rectifier circuit 206, including but not limited to a diode bridge. In some embodiments, the rectifier circuit 206 can be omitted, and one of the energized conductors of the differential pair can be coupled to V through an inductor raw Terminal.

[0024] As shown, the power supply 108 is also coupled to the two-conductor bus 110. Specifically, the power supply 108 is shown coupled to the first conductor 208, although by using the rectifier circuit 206, the power supply 108 can be coupled to the first conductor 208 or the second conductor 210 without affecting the functionality of the communication device 202. Similar to V raw Terminal, the power supply 108 is coupled to the first conductor 208 via an inductor to block the AC signal from reaching the power supply 108.

[0025] The communication device 202 includes circuitry for generating and / or receiving differential signals corresponding to the logical states indicated by digital signals received through digital signal terminals such as terminal DI and terminal RO. In some embodiments, a voltage close to the power supply voltage applied to terminal DI represents logic 1 / high logic value, while a voltage close to the ground voltage applied to terminal DI represents logic 0 / low logic value. Similarly, in some embodiments, a voltage received on terminal RO close to the power supply voltage is interpreted as logic 1 / high logic value, while a voltage received on terminal RO close to ground is understood as logic 0 / low logic value. These terminals can be connected to a computing device 204, such as a microcontroller, PLC, ASIC, or any other suitable device, for sending and receiving digital signals through one or more input / output conductors 212. The computing device 204 can be powered by the communication device 202 at the V raw Terminal and transmitted by the communication device 202 at the VCC_OUT terminal.

[0026] As shown, each terminal of the communication device 202 is directly coupled to its corresponding external wire. In some embodiments, such coupling can be achieved by direct wiring, such as traces on a printed circuit board or soldered wiring. In some embodiments, the coupling to one or more terminals can be achieved through detachable coupling hardware, including but not limited to modular connectors / plugs (e.g., RJ11, RJ45, or other types of modular connectors), coaxial power plugs / plugs, SAE connectors, USB plugs / plugs, or any other suitable type of detachable coupling.

[0027] Figure 2BAdditional components of the communication device 202 are shown. Differential terminals (Terminal A and Terminal B) are coupled to a high-voltage electrostatic discharge circuit (HV ESD 224) and an automatic gain control circuit 222, as is typical for differential signal communication. The automatic gain control circuit 222 is electrically coupled to a conversion circuit 220 and an encoding circuit 216 for obtaining and recovering received signals below an acceptable threshold. Logic value terminals (RO terminal and DI terminal) are electrically coupled to the encoding circuit 216. The TXEN (Transmit Enable) terminal is also electrically coupled to the encoding circuit 216 and can be used to change the half-duplex communication direction (e.g., a high voltage on TXEN places the transceiver in transmit mode, while a low voltage on TXEN places the transceiver in receive mode). In some embodiments, other circuits (e.g., DE / Driver Enable pins and REN / Receiver Enable pins) can be used to provide similar functionality. A low-dropout regulator circuit 218 can be included to regulate the voltage between the raw terminals and the VCC_OUT terminal.

[0028] As shown, the communication device 202 also includes a digital control circuit 214. The digital control circuit 214 provides functionality for controlling configurable aspects of the communication device 202. For example, the digital control circuit 214 can accept signals via the TPULSE terminal to allow configuration of a pair of pulse lengths 318, the SRA terminal allows configuration of the transmit signal transition rate, and the ENCODE_EN terminal allows configuration of the encoding scheme. The digital control circuit 214 can send signals via the FAULT terminal to indicate problems detected within the communication device 202.

[0029] If the communication device 202 acts as a transmitter, when a digital signal is received via the terminal DI, the circuitry of the communication device 202 generates a differential signal based on the received digital signal and sends it to the first conductor 208 and the second conductor 210. If the communication device 202 acts as a receiver, when differential signals are received via terminals A and B, the circuitry of the communication device 202 generates digital signals and sends them via the terminal RO. To maintain DC line balance, the differential signals are generated and received in the form of pulse pairs, where the differential voltage is offset both above and below the common-mode voltage before returning to the common-mode voltage. Since each high voltage difference is balanced by a low voltage difference, regardless of the pattern of the data, the DC line balance is maintained.

[0030] Figure 3 is a signal diagram showing a non-limiting example embodiment of signaling in accordance with various aspects of the present disclosure. In Figure 3 it, time moves from left to right, the thick solid lines represent signals, and various dashed lines demarcate various aspects of the signals, which will be described in further detail below.

[0031] Figure 3The top of [the figure] shows a digital signal 302 received at or transmitted by terminal DI and / or terminal RO. The digital signal 302 shows the indicated logical states and may or may not show the specific voltages applied to or detected at the terminals. The digital signal 302 alternates between a high logical value 306 (e.g., 1) and a low logical value 308 (e.g., 0). The digital signal 302 includes bits generated at a data rate, where the data interval length 310 specifies the amount of time between consecutive logical values. After an initial idle interval, the shown digital signal 302 includes a plurality of first data intervals 320 - 336 from a first data interval 320 to a ninth data interval 336.

[0032] It should be noted that edges occur in the digital signal 302 when the value transitions between the high logical value 306 and the low logical value 308, and vice versa. For example, there is an edge (a transition from the low logical value 308 to the high logical value 306) in the digital signal 302 between the first data interval 320 and the second data interval 322, and an edge (a transition from the high logical value 306 to the low logical value 308) between the second data interval 322 and the third data interval 324, but there is no edge between the third data interval 324 and the fourth data interval 326 because the logical value remains at the low logical value 308 in both data intervals.

[0033] Figure 3 The bottom of [the figure] shows a differential signal 304 corresponding to the digital signal 302. As shown, the differential signal 304 is horizontally aligned (i.e., in time) with the digital signal 302, although the vertical scales between the digital signal 302 and the differential signal 304 may be different. Compared to the common - mode voltage 314, the differential signal 304 shows a high voltage differential 312 and a low voltage differential 316, and the thick line indicates that the common - mode voltage 314, the high voltage differential value 312, or the low voltage differential value 316 is generated and / or detected at a given time point.

[0034] In the common - mode voltage 314, the voltages detected via terminal A on the first conductor 208 and via terminal B on the second conductor 210 match each other. At the high voltage differential 312, the voltage detected via terminal A is higher than the current detected via terminal B. At the low voltage differential 316, the voltage detected via terminal A is lower than the voltage detected via terminal B. Assigning the high voltage and the low voltage to terminal A and terminal B is only an example, and in some embodiments, the roles of these terminals can be reversed. In some embodiments, the difference between the high voltage differential 312 and the common - mode voltage 314 matches the difference between the low voltage differential 316 and the common - mode voltage 314 (i.e., is the same or within 25%).

[0035] Initially, the differential signal 304 is held at the common-mode voltage 314. In an embodiment of the present disclosure, when the circuitry of the communication device 202 detects an edge of the digital signal 302 (i.e., a transition from the high logic value 306 to the low logic value 308, or a transition from the low logic value 308 to the high logic value 306), the circuitry in the communication device 202 generates a pair of pulses representing the transition. The pair of pulses includes a transition from the common-mode voltage to one of the high-voltage differential 312 or the low-voltage differential 316, depending on the direction of the edge, and then transitions to the other of the high-voltage differential line 312 or the low-voltage differential 316 before returning to the common-mode voltage 314.

[0036] The order in which the differential signal 304 transitions to the high-voltage differential 312 and the low-voltage differential 316 indicates the direction of the transition. For example, in the first data interval 320, the edge in the digital signal 302 indicates a transition from the high logic value 306 to the low logic value 308. Thus, to indicate the transition from the high logic value 306 to the low logic value 308, the differential signal 304 transitions from the common-mode voltage 314 to the low-voltage differential 316 and then from the low-voltage differential 316 to the high-voltage differential 312 before returning to the common-mode voltage 314. As another example, in the second data interval 322, the edge in the digital signal 302 indicates a transition from the low logic value 308 to the high logic value 306. Thus, to indicate the transition from the low logic value 308 to the high logic value 306, the differential signal 304 transitions from the common-mode voltage 314 to the high-voltage differential 312 and then from the high-voltage differential value 312 to the low-voltage differential value 316 before returning to the common-mode voltage 314. These sequences are merely non-limiting examples, and in other embodiments, the reverse order of the transitions between the high-voltage differential 312 and the low-voltage differential 316 may be used.

[0037] In some embodiments, the generation of the pair of pulses is triggered by detecting an edge in the digital signal 302. This allows communication to be performed without clock synchronization (or another type of synchronization) between the digital signal 302 and the differential signal 304. As shown, since the third data interval 324 and the fourth data interval 326 include consecutive low logic values 308, there is no edge in the digital signal 302 between the third data interval 324 and the fourth data interval 326. Thus, no pair of pulses is transmitted in the fourth data interval 326. Similarly, since the seventh data interval 332 and the eighth data interval 334 include consecutive high logic values 306, there is no edge in the digital signal 302 between the seventh data interval 332 and the eighth data interval 334. Thus, no pair of pulses is transmitted in the eighth data interval 334.

[0038] In some embodiments, the amount of time for which each pair of pulses is generated is as shown by a pair of pulse lengths 318. During the pulse pair length 318, the amount of time for which the high voltage differential 312 is generated matches (i.e., is equal to or within 25% of) the amount of time for which the low voltage differential 316 is generated. By using a matching amount of time for the high voltage differential 312 and the low voltage differential 316, DC line balance is maintained.

[0039] In some embodiments, the pair of pulse lengths 318 is less than the data interval length 310. As a non-limiting example, the data interval length 310 may be 100 μs (one ten-thousandth of a second), while the pulse pair length 318 is 1 μs (one millionth of a second). By making the pair of pulse lengths 318 independent of the data interval length 310, the pair of pulse widths 318 can be adjusted to optimize the magnetism of the differential signal, which may be less at higher frequencies. In some embodiments, the pair of pulse lengths 318 may be adjustable or programmable within the communication device 202, for example by providing a signal to the digital control circuit 214.

[0040] Figure 4 is a flowchart showing a non-limiting example embodiment of a method for receiving power and communication via a differential conductor pair in accordance with various aspects of the present disclosure. The method 400 may be performed by a pair of communication devices 202, such as the first communication device 102 and the second communication device 104 shown and described above. In the method 400, differential signals representing transitions between logic values using paired pulses are used for communication via a two-conductor bus 110, which is also used to transmit direct current.

[0041] The method 400 proceeds from the start block to block 402, where the first communication device 102 and the second communication device 104 coupled to the differential pair receive power via the differential pair. As Figure 1 and Figure 2A shown, the power supply 108 may supply power to the differential pair, and each communication device 202 may receive an AC signal from the direct current via an inductor. The power may in turn be provided by one or more of the communication devices 202 to a computing device 204 coupled thereto, which communicates digital signals with the communication device 202, or may be provided by one or more communication devices 202 to some other device.

[0042] At block 404, the first communication device 102 generates a common mode voltage. Although this common mode voltage is established between terminals A and B, this voltage does not reach the first conductor 208 and the second conductor 210 via the capacitor, although the differential signal does pass through the capacitor. At block 406, the second communication device 104 receives the differential AC signal and re-establishes the common mode voltage between terminals A and B (i.e., after the series capacitor). At Figure 3In the figure, the common-mode voltage is shown as common-mode voltage 314. In some embodiments, the common-mode voltage established across terminals A and B of the first communication device 102 may be different from the common-mode voltage formed across terminals A and B of the second communication device 104, while in other embodiments these common-mode voltages may be the same.

[0043] In step 408, the second communication device 104 transmits a signal representing a logic value via its output conductor. The output conductor may be an RO terminal or another terminal through which a signal indicating a logic value can be transmitted. In some embodiments, the second communication device 104 transmits a signal indicating a default logic value until it receives a pair of pulses indicating a change in the logic value. In some embodiments, instead of transmitting a default logic value, the second communication device 104 may not transmit any signal indicating a logic value until it receives the first pair of pulses.

[0044] In step 410, the first communication device 102 detects the edge of the input digital signal via its input conductor. The input conductor may be a DI terminal or another terminal through which a signal indicating a logic value can be received. In some embodiments, the edge may be detected by sensing a change in level from a level indicating a first logic value to a level indicating a second logic value.

[0045] In block 412, the first communication device 102 transmits a pair of pulses based on the edge via the differential pair. The first communication device 102 transmits the pair of pulses by changing the voltages applied to terminals A and B, thereby applying the pair of pulses to the differential pair. In some embodiments, changing the voltages applied to terminals A and B may include reducing the current applied to terminal B by an amount that matches (e.g., is equal to or within 10% of) the amount by which the voltage applied to terminal A is increased, and vice versa, thereby creating a "differential" signal between the first conductor 208 and the second conductor 210.

[0046] In some embodiments, the first communication device 102 determines whether to transmit the high-voltage differential 312 or the low-voltage differential 316 first based on the logic value indicated after the edge. For example, in Figure 3 the illustrated embodiment, if the logic value indicated after the edge is the low logic value 308, the low-voltage differential 316 will be transmitted before the high-voltage differential 312. Similarly, if the logic value indicated after the edge is the high logic value 306, the high-voltage differential 312 will be transmitted before the low-voltage differential 316. As Figure 3As shown, the first communication device 102 transmits a pulse pair within the time amount indicated by the pulse pair length 318, which can be configurable, and during the pulse pair length 318, the transmission time amounts of the high voltage differential 312 and the low voltage differential 316 are matched. After transmitting the pulse pair, the first communication device 102 returns to transmitting a common mode voltage to the differential pair.

[0047] At block 414, the second communication device 104 detects the pair of pulses via the differential pair. In some embodiments, the second communication device 104 detects the pair of pulses by detecting that the differential voltage between the first conductor 208 and the second conductor 210 (as received at terminals A and B) has deviated from the common mode voltage 314.

[0048] At block 416, the second communication device 104 adjusts a signal indicating a logical value based on the pair of pulses. In some embodiments, the adjusted signal may be transmitted in a manner similar to that described above with respect to block 408. In some embodiments, the second communication device 104 may determine whether the pair of pulses indicates a high logical value 306 or a low logical value 308 by determining whether the high voltage differential 312 or the low voltage differential 316 is received first.

[0049] In some embodiments, the second communication device 104 may compare the logical value indicated by the pair of pulses with the logical value currently indicated by the output signal from the second communication device 104, and if the logical value indicated by the pair of pulses is the same as the logical value currently indicated by the output signal, the signal indicating that logical value may be avoided from being adjusted. Otherwise, if the logical value indicated by the pair of pulses is different from the logical value currently indicated by the output signal from the second communication device 104, the second communication device 104 may adjust the output signal to the logical value represented by the pair of pulses instead. For example, if the signal output by the second communication device 104 currently indicates a low logical value 308 and the pair of pulses indicates a high logical value 306 by having the high voltage differential 312 precede the low voltage differential 316, the second communication device 104 may adjust the signal it outputs to indicate the high logical value 308 instead of the low logical value 306.

[0050] Method 400 then proceeds to decision block 418 where it is determined whether method 400 should continue. Generally, method 400 can continue as long as power is supplied to the two-conductor bus 110 or as long as the operator desires. If it is determined that method 400 should continue, the result of decision box 418 is yes and method 400 returns to block 410 to wait for a subsequent edge of an incoming digital signal. Otherwise, if it is determined that method 400 should end, the result of decision box 418 is no and method 400 proceeds to an end box and terminates. It will be noted that by looping back to block 410 and waiting for a subsequent edge of the input digital signal, method 400 will loop at a frequency approximately equal to the length of the data interval 310.

[0051] Although exemplary embodiments have been described, it should be understood that various changes can be made therein without departing from the spirit and scope of the invention.

[0052] Embodiment

[0053] The following numbered paragraphs include various non-limiting examples of embodiments of the present disclosure.

[0054] Embodiment 1. A method of receiving power and transmitting data signals through a differential conductor pair, the method comprising: generating or receiving a common-mode voltage through the differential pair; and transmitting a pair of pulses based on the edge via the differential pair in response to detecting an edge of an input digital signal via an input conductor.

[0055] Embodiment 2. The method according to Embodiment 1, wherein transmitting the pair of pulses comprises generating a high voltage difference compared to the common-mode voltage and generating a low voltage difference compared to the common-mode voltage before returning to generating the common-mode voltage.

[0056] Embodiment 3. The method according to Embodiment 2, wherein the difference between the high voltage difference and the common-mode voltage matches the difference between the low voltage difference and the common-mode voltage.

[0057] Embodiment 4. The method according to any one of Embodiments 2 or 3, wherein the amount of time for generating the high voltage difference matches the amount of time for generating the low voltage difference.

[0058] Example 5. The method according to any one of Examples 2-4 further includes determining whether the edge of the input digital signal indicates a transition from a first logic state to a second logic state or a transition from the second logic state to the first logic state; wherein in response to determining that the edge of the input digital signal indicates a transition from the first logic state to the second logic state, transmitting the pair of pulses includes generating the high voltage difference before generating the low voltage difference; and wherein in response to determining that the edge of the input digital signal indicates a transition from the second logic state to the first logic state, transmitting the pair of pulses includes generating the low voltage difference before generating the high voltage difference.

[0059] Example 6. The method according to any one of Examples 1-5, wherein the amount of time used to generate the output pulse pair is less than the data rate of the input digital signal.

[0060] Example 7. The method according to any one of Examples 1-6 further includes receiving power via the differential pair.

[0061] Example 8. A method of receiving power and data signals via a differential conductor pair, the method comprising:

[0062] generating or receiving a common mode voltage via the differential pair;

[0063] transmitting a signal indicating a logic value via an output conductor; and

[0064] detecting a pair of pulses via the differential pair; and

[0065] adjusting the signal indicating the logic value based on the pair of pulses.

[0066] Example 9. The method according to Example 8, wherein detecting the pair of pulses includes detecting a high voltage difference compared to the common mode voltage and detecting a low voltage difference compared to the common mode voltage before detecting a return to the common mode voltage.

[0067] Example 10. The method according to Example 9, wherein the difference between the high voltage difference and the common mode voltage matches the difference between the low voltage difference and the common mode voltage.

[0068] Example 11. The method according to Example 9 or 10, wherein the amount of time for detecting the high voltage difference matches the amount of time for detecting the low voltage difference.

[0069] Example 12. A method according to any one of Examples 8-11, wherein adjusting the signal indicating the logical value based on the pair of pulses includes: determining whether the pair of pulses indicates the logical value or indicates a different logical value; and in response to determining that the pair of pulses indicates a different logical value, transmitting a signal indicating a different logical value via an output conductor.

[0070] Embodiment 13. The method of any one of embodiments 8-12, wherein an amount of time during which the pair of pulses is detected is less than a data rate of a logic value transmitted via the output conductor.

[0071] Embodiment 14. The method of any one of embodiments 8-13, further comprising receiving power via the differential pair.

[0072] Embodiment 15. A communication device configured to receive power and transmit data signals via a differential conductor pair, the communication device comprising: a circuit configured to generate or receive a common-mode voltage via the differential pair; and at least one of the following: a circuit configured to transmit an output pulse pair based on the detected edge via the differential pair in response to detecting an edge of an input digital signal via the input conductor; or a circuit configured to detect an input pulse pair via the differential pair and adjust a signal indicating a logical value transmitted via the output conductor based on the input pulse pair.

[0073] Embodiment 16. The communication device of embodiment 15, wherein transmitting the pair of output pulses comprises generating a high voltage difference compared to the common mode voltage and generating a low voltage difference compared to the common mode voltage before returning to generating the common mode voltage.

[0074] Embodiment 17. The communication device of Embodiment 15 or 16, wherein detecting the pair of input pulses comprises detecting a high voltage difference from the common mode voltage and detecting a low voltage difference from the common mode voltage before detecting a return to the common mode voltage.

[0075] Embodiment 18. The communication device of any one of Embodiments 15-17, further comprising circuitry configured to receive power via the differential pair.

[0076] Embodiment 19. The communication device of embodiment 18, further comprising circuitry for separating the power from the input pulse pair or the output pulse pair.

[0077] Embodiment 20. The communication device of Embodiment 18 or 19, wherein the circuit configured to receive power via the differential pair comprises a rectifier circuit.

Claims

1. A method for receiving power and transmitting data signals through a differential conductor pair, the method comprising: generating or receiving a common-mode voltage through the differential pair; and in response to detecting an edge of an input digital signal via an input conductor, transmitting a pair of pulses based on the edge via the differential pair.

2. The method according to claim 1, wherein transmitting the pair of pulses comprises generating a high voltage difference compared to the common-mode voltage and a low voltage difference compared to the common-mode voltage before returning to generating the common-mode voltage.

3. The method according to claim 2, wherein the difference between the high voltage difference and the common-mode voltage matches the difference between the low voltage difference and the common-mode voltage.

4. The method according to claim 2, wherein the amount of time for generating the high voltage difference matches the amount of time for generating the low voltage difference.

5. The method according to claim 2, further comprising determining whether the edge of the input digital signal indicates a transition from a first logic state to a second logic state or a transition from the second logic state to the first logic state; wherein in response to determining that the edge of the input digital signal indicates a transition from the first logic state to the second logic state, transmitting the pair of pulses comprises generating the high voltage difference before generating the low voltage difference; and wherein in response to determining that the edge of the input digital signal indicates a transition from the second logic state to the first logic state, transmitting the pair of pulses comprises generating the low voltage difference before generating the high voltage difference.

6. The method according to claim 1, wherein the amount of time for generating the output pulse pair is less than the data rate of the input digital signal.

7. The method according to claim 1, further comprising receiving power via the differential pair.

8. A method for receiving power and data signals through a differential conductor pair, the method comprising: generating or receiving a common-mode voltage through the differential pair; transmitting a signal indicating a logical value via an output conductor; and detecting a pair of pulses via the differential pair; and adjusting the signal indicating the logical value based on the pair of pulses.

9. The method according to claim 8, wherein detecting the pair of pulses comprises detecting a high voltage difference compared to the common-mode voltage and a low voltage difference compared to the common-mode voltage before detecting a return to the common-mode voltage.

10. The method according to claim 9, wherein the difference between the high voltage difference and the common-mode voltage matches the difference between the low voltage difference and the common-mode voltage.

11. The method according to claim 9, wherein the amount of time for detecting the high voltage difference matches the amount of time for detecting the low voltage difference.

12. The method according to claim 8, wherein adjusting the signal indicating the logical value based on the pair of pulses comprises: determining whether the pair of pulses indicates the logical value or a different logical value; and in response to determining that the pair of pulses indicates a different logical value, transmitting a signal indicating a different logical value via the output conductor.

13. The method according to claim 8, wherein the amount of time the pair of pulses is detected is less than the data rate of the logic value transmitted via the output conductor.

14. The method according to claim 8, further comprising receiving power via the differential pair.

15. A communication device configured to receive power and transmit data signals via a differential conductor pair, the communication device comprising: a circuit configured to generate or receive a common-mode voltage via the differential pair; and at least one of the following: a circuit configured to transmit a pair of output pulses via the differential pair based on a detected edge in response to detecting an edge of an input digital signal via an input conductor; or a circuit configured to detect a pair of input pulses via the differential pair and adjust a signal indicative of a logic value transmitted via an output conductor based on the pair of input pulses.

16. The communication device according to claim 15, wherein transmitting the pair of output pulses includes generating a high voltage difference compared to the common-mode voltage and generating a low voltage difference compared to the common-mode voltage before returning to generating the common-mode voltage.

17. The communication device according to claim 15, wherein detecting the pair of input pulses includes detecting a high voltage difference compared to the common-mode voltage and detecting a low voltage difference compared to the common-mode voltage before detecting a return to the common-mode voltage.

18. The communication device according to claim 15, further comprising a circuit configured to receive power via the differential pair.

19. The communication device according to claim 18, further comprising a circuit for separating the power from the pair of input pulses or the pair of output pulses.

20. The communication device according to claim 18, wherein the circuit configured to receive power via the differential pair includes a rectifier circuit.

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