Communication system, communication method, electronic device, storage medium, and program product

Abstract

The present application discloses a communication system, a communication method, an electronic device, a storage medium, and a program product, which relate to the field of communication technology. A storage element is provided between a slave device and a master device, and the storage element can be used to cache data frames from the slave device. The essence of the system is to construct an intermediate buffer mechanism so that the data frames of the slave device can be written into the storage element corresponding to the slave device in advance, so that the master device can read them at any time according to the communication needs. By adopting the technical solution provided by the present application, the master device can read the required data frames on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, failure or communication congestion of the slave device, thereby achieving the effect of improving the communication efficiency of the communication system. It is particularly suitable for application scenarios with high real-time requirements.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and in particular to a communication system, a communication method, an electronic device, a storage medium, and a program product. Background Art

[0002] In application scenarios such as industrial control networks, smart home systems, and sensor networks, it is often necessary to set up a master device to communicate with multiple slave devices simultaneously to achieve efficient data collection, control command issuance, and system collaboration.

[0003] In related technologies, a master device is directly connected to multiple slave devices, communicating with each of them through polling. With this communication method, the master device must access each slave device in a fixed order. If a slave device responds slowly due to complex data processing, a fault, or communication congestion, the polling wait time for subsequent devices will increase significantly, resulting in low communication efficiency. This communication method is difficult to meet in applications with high real-time requirements. Summary of the Invention

[0004] The present application provides a communication system, a communication method, an electronic device, a storage medium, and a program product to at least solve the problem of low communication efficiency in related technologies.

[0005] The present application provides a communication system, the communication system comprising a plurality of slave devices, a plurality of storage elements, and a master device; the plurality of slave devices and the plurality of storage elements correspond one to one; the slave device comprises a first serial port, the storage element comprises a second serial port and a third serial port; the master device comprises a fourth serial port;

[0006] For any of the slave devices, the first serial port of the slave device is connected to the second serial port of the storage element corresponding to the slave device;

[0007] For any of the storage elements, the third serial port of the storage element is connected to the fourth serial port of the host device.

[0008] The present application also provides a communication method, which is applied to any one of the communication systems provided in the present application, and the communication method includes:

[0009] The storage element receives and buffers the data frame from the slave device;

[0010] In response to an access instruction to the slave device, the storage element outputs the buffered data frame from the slave device to the master device.

[0011] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned communication methods when executing the computer program.

[0012] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned communication methods are implemented.

[0013] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above communication methods when executed by a processor.

[0014] Through this application, since a storage element is set between the slave device and the master device, the storage element can be used to cache the data frames from the slave device. In essence, it builds an intermediate buffer mechanism so that the data frames of the slave device can be written to the storage element corresponding to the slave device in advance, so that the master device can read them at any time according to communication needs. Using the technical solution provided by this application, the master device can read the required data frames on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, failure or communication blockage of the slave device, and achieve the beneficial effect of improving the communication efficiency of the communication system. It is particularly suitable for application scenarios with high real-time requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A structural block diagram of a communication system provided in an embodiment of the present application;

[0017] Figure 2 A structural block diagram of another communication system provided in an embodiment of the present application;

[0018] Figure 3 A flow chart of a communication method provided in an embodiment of the present application;

[0019] Figure 4 A working principle diagram of a storage element provided in an embodiment of the present application;

[0020] Figure 5 A working principle diagram of another storage element provided in an embodiment of the present application;

[0021] Figure 6A working principle diagram of another storage element provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of a data frame format provided in an embodiment of the present application;

[0023] Figure 8 A schematic diagram of a data set obtained according to an embodiment of the present application;

[0024] Figure 9 A structural block diagram of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0027] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] An embodiment of the present application provides a communication system, which includes multiple slave devices, multiple storage elements and a master device; the multiple slave devices and the multiple storage elements correspond one to one; the slave device includes a first serial port, the storage element includes a second serial port and a third serial port; the master device includes a fourth serial port; for any slave device, the first serial port of the slave device is connected to the second serial port of the storage element corresponding to the slave device; for any storage element, the third serial port of the storage element is connected to the fourth serial port of the master device.

[0029] Figure 1 This is a structural block diagram of a communication system provided in an embodiment of the present application. For example, see Figure 1 The communication system includes four slave devices (respectively slave device 1 to slave device 4), four storage elements (respectively storage element 1 to storage element 4) and one master device.

[0030] For example, see Figure 1 Taking the master device accessing slave device 1 as an example, before receiving the access instruction to slave device 1, the data frame from slave device 1 is cached in advance to storage element 1. After receiving the access instruction to slave device 1, storage element 1 sends the data frame from slave device 1 cached in its internal memory to the master device.

[0031] The technical solution provided by this application, by setting a storage element between the slave device and the master device, can use this storage element to cache the data frames from the slave device. In essence, it builds an intermediate buffer mechanism so that the data frames of the slave device can be written to the storage element corresponding to the slave device in advance, so that the master device can read them at any time according to communication needs. Using the technical solution provided by this application, the master device can read the required data frames on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, failure or communication congestion of the slave device, and can improve the communication efficiency of the communication system. It is particularly suitable for application scenarios with high real-time requirements.

[0032] Furthermore, the communication system can also be arranged to include a first logic control element, a second logic control element and a master control element; the first logic control element includes multiple first signal transmission channels, and the two ends of any first signal transmission channel are respectively connected to the first serial port of the slave device and the second serial port of the storage element with a corresponding relationship; the second logic control element includes multiple second signal transmission channels, and one end of any second signal transmission channel is connected to the third serial port of the storage element, and the other end is connected to the fourth serial port of the master device; different second signal transmission channels are connected to different storage elements; the master control element is connected to the first logic control element and the second logic control element.

[0033] For example, see Figure 2 This communication system includes four slave devices (slave 1 through slave 4) and four storage elements (storage element 1 through storage element 4). The first logic control element includes four first signal transmission channels: a first signal transmission channel between slave 1 and storage element 1, a first signal transmission channel between slave 2 and storage element 2, a first signal transmission channel between slave 3 and storage element 3, and a first signal transmission channel between slave 4 and storage element 4. Under the control of a first state adjustment signal, the first logic control element can adjust the on / off state of each first signal transmission channel to keep some or all of the first signal transmission channels in an on state. Slave devices and storage elements connected by an on-state first signal transmission channel can exchange data.

[0034] The second logic control element includes four second signal transmission channels: a second signal transmission channel between storage element 1 and the master device, a second signal transmission channel between storage element 2 and the master device, a second signal transmission channel between storage element 3 and the master device, and a second signal transmission channel between storage element 4 and the master device. Under the control of a second state adjustment signal, the second logic control element can adjust the on / off state of each second signal transmission channel in turn, allowing the master device to exchange data with each storage element in turn.

[0035] By adding a first logic control element, a second logic control element, and a master control element to the communication system, data exchange between a master device and some or all of multiple slave devices can be achieved by adjusting the on / off states of the first signal transmission channel and the second signal transmission channel according to communication needs. This adjustment process eliminates the need for manual adjustment of the connection relationship between the slave devices and the master device.

[0036] Furthermore, the communication system may be configured to further include a first processor; the first processor is connected to the master control element.

[0037] Furthermore, the master control element may be connected to at least one storage element.

[0038] Figure 3 This is a flow chart of a communication method provided in an embodiment of the present application. Figure 3 , the communication method comprises:

[0039] S110 : The storage element receives and buffers a data frame from a slave device.

[0040] S120 , in response to an access instruction to the slave device, the storage element outputs the buffered data frame from the slave device to the master device.

[0041] For example, see Figure 1 Taking the master device accessing slave device 1 as an example, before receiving the access instruction to slave device 1, the data frame from slave device 1 is cached in advance to storage element 1. After receiving the access instruction to slave device 1, storage element 1 sends the data frame from slave device 1 cached in its internal memory to the master device.

[0042] The technical solution provided by this application, by setting a storage element between the slave device and the master device and using this storage element to cache the data frames from the slave device, essentially builds an intermediate buffer mechanism that enables the data frames of the slave device to be written to the corresponding storage element of the slave device in advance, so that the master device can read them at any time according to communication needs. Using the technical solution provided by this application, the master device can read the required data frames on demand without waiting for the real-time response of the slave device. Therefore, it can avoid the problem of low communication efficiency caused by complex data processing, failure or communication congestion of the slave device, and can improve the communication efficiency of the communication system. It is particularly suitable for application scenarios with high real-time requirements.

[0043] Based on the above technical solution, optionally, the method may also include: a storage element receives and caches data frames from a master device; the data frames from the master device have corresponding slave devices; and the storage element outputs the data frames from the master device to the corresponding slave devices.

[0044] For example, assume that the master device needs to send data frame 2 to slave device 1. Figure 1 , storage element 1 receives and buffers data frame 2 from the master device, and subsequently storage element 1 outputs data frame 2 from the master device to slave device 1.

[0045] With the above setting method, the master device can complete the data frame transmission operation without waiting for the real-time response of the slave device. In the future, the data frame from the master device is considered to be transmitted after it is written into the storage element, thereby freeing up the communication resources of the master device and improving its concurrent processing capability.

[0046] Based on the above technical solutions, optionally, the communication system further includes a first logic control element, a second logic control element, and a master control element; the first logic control element includes multiple first signal transmission channels, with the two ends of any first signal transmission channel respectively connected to a corresponding slave device and storage element; the second logic control element includes multiple second signal transmission channels, with one end of any second signal transmission channel connected to a storage element and the other end connected to a master device; different second signal transmission channels are connected to different storage elements; and the master control element is connected to the first logic control element and the second logic control element. The method further includes: the master control element sending a first state adjustment signal to the first logic control element and sending a second state adjustment signal to the second logic control element; the first logic control element adjusting the on / off state of the first signal transmission channel based on the first state adjustment signal so that the slave device and the storage element connected to the first signal transmission channel in the on state can achieve data exchange; and the second logic control element adjusting the on / off state of the second signal transmission channel based on the second state adjustment signal so that the master device and the storage element can achieve data exchange.

[0047] For example, see Figure 2 This communication system includes four slave devices (slave 1 through slave 4) and four storage elements (storage element 1 through storage element 4). The first logic control element includes four first signal transmission channels: a first signal transmission channel between slave 1 and storage element 1, a first signal transmission channel between slave 2 and storage element 2, a first signal transmission channel between slave 3 and storage element 3, and a first signal transmission channel between slave 4 and storage element 4. Under the control of a first state adjustment signal, the first logic control element can adjust the on / off state of each first signal transmission channel to keep some or all of the first signal transmission channels in an on state. Slave devices and storage elements connected by an on-state first signal transmission channel can exchange data.

[0048] The second logic control element includes four second signal transmission channels: a second signal transmission channel between storage element 1 and the master device, a second signal transmission channel between storage element 2 and the master device, a second signal transmission channel between storage element 3 and the master device, and a second signal transmission channel between storage element 4 and the master device. Under the control of a second state adjustment signal, the second logic control element can adjust the on / off state of each second signal transmission channel in turn, allowing the master device to exchange data with each storage element in turn.

[0049] By adding a first logic control element, a second logic control element, and a master control element to the communication system, data exchange between a master device and some or all of multiple slave devices can be achieved by adjusting the on / off states of the first signal transmission channel and the second signal transmission channel according to communication needs. This adjustment process eliminates the need for manual adjustment of the connection relationship between the slave devices and the master device.

[0050] Based on the above technical solutions, optionally, the storage element includes multiple first storage units and multiple second storage units; the multiple first storage units are arranged in a first order to form a first storage sequence; the multiple second storage units are arranged in a second order to form a second storage sequence; the storage element caches data frames from the slave device and outputs the data frames from the slave device to the master device, including: the first storage sequence caches the data frames from the slave device in a first-in-first-out manner, and outputs the data frames to the master device; the storage element caches the data frames from the master device and outputs the data frames from the master device to the master device, including: the second storage sequence caches the data frames from the master device in a first-in-first-out manner, and outputs the data frames to the slave device.

[0051] For example, see Figure 4The storage element includes three first storage cells (respectively, first storage cells 1-3) and three second storage cells (respectively, second storage cells 1-3). The three first storage cells are arranged in a first order to form a first storage sequence. In the first storage sequence, first storage cell 1 is the first storage cell in the first storage sequence, and therefore, first storage cell 1 is the first storage cell at the beginning of the sequence. First storage cell 3 is the last storage cell in the first storage sequence, and therefore, first storage cell 3 is the first storage cell at the end of the sequence. When storing a data frame in the first storage sequence, the data frame is stored in the first storage cell at the end of the sequence (i.e., first storage cell 3). When reading a data frame from the first storage sequence, the data frame is read from the first storage cell at the beginning of the sequence (i.e., first storage cell 1).

[0052] Similarly, the three second storage units are arranged in a second order to form a second storage sequence. In the second storage sequence, second storage unit 1 is the first storage unit in the second storage sequence, and therefore, second storage unit 1 is the second storage unit at the beginning of the sequence. Second storage unit 3 is the last storage unit in the second storage sequence, and therefore, second storage unit 3 is the second storage unit at the end of the sequence. When storing a data frame in the second storage sequence, the data frame is stored in the second storage unit at the end of the sequence (i.e., second storage unit 3). When reading a data frame from the second storage sequence, the data frame is read from the second storage unit at the beginning of the sequence (i.e., second storage unit 1).

[0053] Furthermore, the first storage sequence caches data frames from the slave device, including: when the first storage unit at the end of the sequence does not include the data frame, the storage element receives the data frame from the slave device and stores the received data frame in the first storage unit at the end of the sequence; the second storage sequence caches data frames from the master device, including: when the second storage unit at the end of the sequence does not include the data frame, the storage element receives the data frame from the master device and stores the received data frame in the second storage unit at the end of the sequence.

[0054] For example, see Figure 2 , the storage element 1 is connected to the slave device 1 through the first signal transmission channel, and is connected to the master device through the second signal transmission channel. Figure 4 , in the storage element 1, the first storage unit 3 is the first storage unit at the end of the sequence. When the storage element 1 detects that the first storage unit 3 does not include the data frame, the storage element 1 receives the data frame 13 from the slave device 1 and stores the received data frame 13 in the first storage unit at the end of the sequence. The result after storing the data frame 13 is as follows Figure 5 shown.

[0055] Similarly, see Figure 4, the second storage unit 3 is the second storage unit at the end of the sequence. When the storage element 1 detects that the second storage unit 3 does not include a data frame, the storage element 1 receives the data frame 23 from the master device and stores the received data frame 23 in the second storage unit at the end of the sequence. The result after storing the data frame 13 is as follows Figure 5 shown.

[0056] By arranging to obtain and cache data frames from the slave device when the first storage unit at the end of the sequence does not include data frames, and to obtain and cache data frames from the master device when the second storage unit at the end of the sequence does not include data frames, this method can effectively avoid the occurrence of adverse conditions such as data loss caused by overflow of data frames in the first storage unit or data frames being overwritten.

[0057] Furthermore, the first storage sequence outputs the cached data frames to the master device, including: outputting the data frames in the first storage unit at the beginning of the sequence to the master device; the storage element sequentially shifting the data frames stored in the remaining first storage units in the first storage sequence, except for the first first storage unit, to the previous first storage unit; and clearing the data frames in the first storage unit at the end of the sequence. The second storage sequence outputs the cached data frames to the slave device, including: outputting the data frames in the second storage unit at the beginning of the sequence to the slave device; the storage element sequentially shifting the data frames stored in the remaining second storage units in the second storage sequence, except for the first second storage unit, to the previous second storage unit, and clearing the data frames in the second storage unit at the end of the sequence.

[0058] For example, see Figure 5 , the first storage unit 1 is the first storage unit at the beginning of the sequence. After the master device reads the data frame 11 in the first storage unit 1, the data frame 12 in the first storage unit 2 is moved to the first storage unit 1, so that in the first storage unit 1, the data frame 12 covers the data frame 11. The data frame 13 in the first storage unit 3 is moved to the first storage unit 2, so that in the second storage unit 2, the data frame 13 covers the data frame 12. The data frame 13 in the second storage unit 3 is cleared, so that the first storage unit 3 does not include the data frame after the clearing. Finally, the first storage sequence is obtained as follows Figure 6 In this way, the first storage sequence can cache the data frames from the slave device in a first-in-first-out manner and output the data frames to the master device.

[0059] Similarly, see Figure 5, the second storage unit 1 is the second storage unit at the beginning of the sequence. After the master device reads the data frame 21 in the second storage unit 1, the data frame 22 in the second storage unit 2 is moved to the second storage unit 1, so that in the second storage unit 1, the data frame 22 covers the data frame 21. The data frame 23 in the second storage unit 3 is moved to the second storage unit 2, so that in the second storage unit 2, the data frame 23 covers the data frame 22. The data frame 23 in the second storage unit 3 is cleared so that the second storage unit 3 does not include the data frame. Finally, the second storage sequence is obtained as follows Figure 6 In this way, the second storage sequence can cache the data frames from the master device in a first-in-first-out manner and output the data frames to the slave device.

[0060] Based on the above technical solutions, the method may optionally further include: when each first storage unit in the first storage sequence contains data frames, the storage element sends a first full-load signal to the first logic control element; after receiving the first full-load signal, the first logic control element sends a first pause signal to the slave device; and after receiving the first pause signal, the slave device pauses sending data to the storage element. The purpose of this configuration is to, when each first storage unit in the first storage sequence contains data frames, use the first full-load signal to restrict the slave device from sending data frames to the first storage sequence, thereby effectively avoiding data loss caused by the inability to write new data frames or data loss caused by new data frames overwriting data frames that have not been read by the master device.

[0061] Similarly, when each second storage unit in the second storage sequence contains data frames, the storage element sends a second full-load signal to the second logic control element. Upon receiving the second full-load signal, the second logic control element sends a second pause signal to the master device. Upon receiving the second pause signal, the master device pauses sending data to the storage element. This configuration is intended to limit the master device from sending data frames to the second storage sequence by using the second full-load signal when each second storage unit in the second storage sequence contains data frames. This effectively avoids data loss caused by the inability to write new data frames or by new data frames overwriting data frames that have not been read by the slave device.

[0062] Furthermore, a configuration can be provided in which, when the first storage unit at the end of the sequence does not include a data frame, the storage element receives a data frame from the slave device, including: when the first storage unit at the end of the sequence does not include a data frame, the storage element sends a first no-load signal to the first logic control element; after receiving the first no-load signal, the first logic control element sends a first resume signal to the slave device; after receiving the first resume signal, the slave device sends a data frame to the storage element; and the storage element receives the data frame from the slave device. The essence of this configuration is that, when the slave device suspends sending data frames to the storage element, the first no-load signal is used to control the slave device to resume sending data frames to the storage element. This configuration method can fully utilize the data storage space of the storage element, reduce idle resources caused by insufficient storage space, and further improve communication efficiency.

[0063] Similarly, when the second storage unit at the end of the sequence does not contain a data frame, the storage element receives a data frame from the master device, including: when the second storage unit at the end of the sequence does not contain a data frame, the storage element sends a second no-load signal to the second logic control element; after receiving the second no-load signal, the second logic control element sends a second resume signal to the master device; after receiving the second resume signal, the master device sends a data frame to the storage element; and the storage element receives the data frame from the master device. The essence of this configuration is that when the master device suspends sending data frames to the storage element, the second no-load signal is used to control the master device to resume sending data frames to the storage element. This configuration method can fully utilize the data storage space of the storage element, reduce idle resources caused by insufficient storage space, and further improve communication efficiency.

[0064] On the basis of the above-mentioned technical solutions, optionally, the slave device and the storage element exchange data at a first baud rate; the storage element and the master device exchange data at a second baud rate; when the number of the first signal transmission channels in the on state is N, the second baud rate is greater than or equal to N times the first baud rate. For example, if the number of the first signal transmission channels in the on state is 4, assuming that the data transmission rate between the slave device and the storage element is the first baud rate F, and the data transmission rate between the storage element and the master device is the second baud rate, the second baud rate is greater than or equal to 4F. In practice, since the data flow sent by the slave device to the master device is much greater than the instruction flow sent by the master device to the slave device, the essence of such a setting is to limit the rate at which the master device reads the cached data frames in the storage element to N times or more of the rate at which the storage element writes the cached data frames from the slave device. In this way, the storage element can transfer data frames normally, avoiding the accumulation of data frames caused by the storage element not being able to forward data frames in time, resulting in data transmission delays.

[0065] This application does not limit the specific format of the data frame. In practical applications, the data frame can be set to include a start bit, data bits, a check bit, and an end bit. The start bit, data bits, check bit, and end bit are arranged in a fourth preset order. For example, see Figure 7 In the data frame, the fourth preset sequence is the start bit, data bit, check bit and end bit.

[0066] Based on the above technical solutions, the method may optionally further include: the master device processing data frames received through each second signal transmission channel to obtain multiple data groups; wherein each data group includes multiple data frames, and different data frames come from different second signal transmission channels; and parsing the data groups in sequence.

[0067] For example, see Figure 8 , slave device 1 sequentially sends data frames 1-1, 1-2, and so on to the master device. Slave device 2 sequentially sends data frames 2-1, 2-2, and so on to the master device. Slave device 3 sequentially sends data frames 3-1, 3-2, and so on to the master device. Slave device 4 sequentially sends data frames 4-1, 4-2, and so on to the master device. The data frame sequence received by the master device is data frame 1-1, data frame 2-1, data frame 3-1, data frame 4-1, data frame 1-2, data frame 2-2, data frame 3-2, and data frame 4-2. Processing this data frame sequence yields two data groups, of which data frame 1-1, data frame 2-1, data frame 3-1, and data frame 4-1 constitute one data group. Data frame 1-2, data frame 2-2, data frame 3-2, and data frame 4-2 constitute another data group. The different data frames in any data group originate from different second signal transmission channels, and the number of data frames originating from any one second signal transmission channel is one. In practice, data frames sent by slave devices may be temporally or logically related. Parsing by data group, rather than by data frame, helps the master device determine the global state of the system.

[0068] Furthermore, the method may also include: in the process of data interaction between the slave device and the storage element connected by the first signal transmission channel in the on state, when a data frame fails to be received through a certain first signal transmission channel in the on state, a replacement signal is stored in the storage element corresponding to the first signal transmission channel. The function of the replacement signal is to write a replacement signal with a preset format or identifier to the corresponding storage element when the first signal transmission channel fails to receive the data frame due to communication anomalies, slave device failure or data frame loss, so as to prevent data parsing errors or system anomalies caused by empty frames. In addition, when the master device reads the replacement signal, it can identify that the data frame corresponding to the replacement signal has not been received normally, thereby triggering operations such as fault alarm, thereby improving the maintainability of the system.

[0069] On the basis of the above technical solution, optionally, the communication system also includes a first processor, the first processor is connected to the master control element, the master control element sends a first state adjustment signal to the first logic control element, and sends a second state adjustment signal to the second logic control element, including: the first processor sends a first control signal to the master control element; the master control element responds to the first control signal, sends the first state adjustment signal to the first logic control element, and sends the second state adjustment signal to the second logic control element.

[0070] For example, see Figure 2 The first processor is associated with a control program, which allows a user to control the first processor to send a first control signal to the master control element. This first control signal may, for example, indicate which slave device or slaves the master device needs to establish a communication link with. Based on the first control signal, the master control element sends a first state adjustment signal to the first logic control element. The first state adjustment signal may, for example, reflect the target state of each first signal transmission channel. The target state of a first signal transmission channel is the state to which the first signal transmission channel is to be adjusted, which may specifically be an on state or an off state. Based on the first control signal, the master control element sends a second state adjustment signal to the second logic control element. The second state adjustment signal may, for example, reflect the target state of each second signal transmission channel. The target state of a second signal transmission channel is the state to which the second signal transmission channel is to be adjusted, which may specifically be an on state or an off state. Subsequently, the first logic control element adjusts the state of each first signal transmission channel within it to the target state based on the first state adjustment signal, and the second logic control element adjusts the state of each second signal transmission channel within it to the target state based on the second state adjustment signal.

[0071] Furthermore, in the communication system, the master control element is connected to at least one storage element; the master control element sends a first state adjustment signal to the first logic control element and sends a second state adjustment signal to the second logic control element, including: the master device sends a second control signal to the second logic control element; the second logic control element forwards the second control signal to the storage element; the storage element forwards the second control signal to the master control element; the master control element responds to the second control signal, sends the first state adjustment signal to the first logic control element, and sends the second state adjustment signal to the second logic control element.

[0072] For example, see Figure 2 The user can directly operate the master device to send a second control signal to the second logic control element. The second control signal may, for example, indicate which slave device or slaves the master device wishes to establish a communication link with. The second control signal is then transmitted to the master control element via the storage element. Based on the second control signal, the master control element sends a first state adjustment signal to the first logic control element.

[0073] This application provides two control signal transmission paths for the master control element: the first is for the first processor to directly send a first control signal to the master control element; the second is for the master device to send a second control signal, which is then transmitted to the master control element via a second logic control element and a storage element. These two control signal transmission paths can meet different user needs.

[0074] In practice, the technical method provided in this application can be applied to the server. Figure 9 A schematic diagram of applying the technical method provided by this application to a server. Figure 9 The server includes a BMC (Baseboard Management Controller), a CPLD (Complex Programmable Logic Device), a CPU (Central Processing Unit), and a UART CON (Universal Asynchronous Receiver-Transmitter Connector).

[0075] The BMC is an embedded controller independent of the main CPU, used for remote management of servers and other devices, monitoring hardware status (such as temperature and voltage), and providing fault alarms. A CPLD is an integrated circuit that can be programmed to implement logic circuit functions and is commonly used in digital circuit design for logic control and interface expansion. The CPU is the core computing unit of the server, responsible for executing instructions and processing data, and is the "brain" of the system.

[0076] In the server, the CPLD includes UART Control Logic, UART Switch Logic0, UART Switch Logic1, FIFO0, FIFO1, FIFO2, and FIFO3. UART Control Logic is the master control element, UART Switch Logic0 is the first logic control element, and UART Switch Logic1 is the second logic control element. FIFO0, FIFO1, FIFO2, and FIFO3 represent four storage elements, respectively. UART Switch Logic connects to four slave devices via the UART3 through UART6 buses. Slave devices can be, for example, OCP (Open Compute Project) network cards or SmartNICs. UART CON is used to connect to a master device, which can be, for example, an external device (i.e., a device connected to the server but not part of it, such as a computer connected to the server to monitor its operating status).

[0077] Specifically, UART Switch Logic0 is connected to the serial port design inside the server and is responsible for selecting the UART channel to FIFO. UART Switch Logic1 is connected to the server's external UART CONN and is responsible for selecting the FIFO to UART_PLD signal and informing the user through RTS_PLD whether data can be received normally.

[0078] Each FIFO has two internal storage arrays (specifically, registers). The first array buffers data frames from slave devices connected to the UART bus, while the second array stores data frames from master devices connected to UARTCONN. Each FIFO communicates with UART Switch Logic0 via virtual signals VUART0-3 and informs UART Switch Logic0 whether the first array is full via virtual signals VRTS0-3. The FIFO communicates with UART Switch Logic1 via virtual signals VUART4-7 and informs UART Switch Logic0 whether the second array is full via virtual signals VRTS4-7. UART Control Logic is connected to UART Switch Logic0 and UART Switch Logic1, respectively, to control the UART selection logic. UART Control Logic also monitors serial port communication data in FIFO0 to identify serial port switching commands issued by the user.

[0079] The UART Control Logic configures UART Switch Logic0-1 based on user needs to select different UART slave devices and connect them to the corresponding FIFOs. For example, if the user wants an external device to communicate with UART3-UART6 simultaneously, UARTSwitch Logic0-1 will select UART3 to FIFO0, UART4 to FIFO1, UART5 to FIFO2, and UART6 to FIFO3. During communication, UART3-UART6 store data frames in the corresponding FIFOs at baud rate F1, while the external device exchanges data frames with FIFO0-3 via the UART_PLD signal at baud rate F2. Here, F2 ≥ 4·F1.

[0080] The following uses UART3 and FIFO0 as an example to illustrate the process of reading and writing data:

[0081] See also Figure 9 and Figure 4When a slave device connected to URAT3 sends data frame 13, data frame 13 is transmitted via the UART3 bus, through UART Switch Logic0, and to FIFO0. FIFO0 stores data frame 13 in first storage unit 3, located at the end of FIFO0's first storage sequence. When all first storage units in FIFO0's first storage sequence contain data frames, FIFO0 notifies UART Switch Logic0 via the VTRS0 signal (i.e., the first full signal). UART Switch Logic0 then transmits a first pause signal (specifically, a software flow control signal) to notify the corresponding slave device to pause data frame transmission.

[0082] See also Figure 9 and Figure 5 , UART Switch Logic1 will read the data frame 11 in the first storage unit 1 in the first storage sequence of each FIFO in turn, and send the data frame 11 to the external device through UART_PLD in sequence. After UART Switch Logic1 reads the data frame 11, FIFO0 will control the data frame 12 and data frame 13 to perform shift processing. Figure 6 After the shift process, the first storage unit at the end of the first storage sequence contains no data frame. FIFO0 notifies UART Switch Logic0 via the VTRS0 signal (i.e., the first no-load signal). UART Switch Logic0 then sends a first resume signal (specifically, a software flow control signal) to notify the corresponding slave device to resume data transmission.

[0083] Continue to see Figure 9 and Figure 5 When the master device sends data frame 23, UART Switch Logic1 stores data frame 23 in FIFO0 via VUART4. When all second storage units in the second storage sequence of FIFO0 are filled with data frames, FIFO0 notifies UART Switch Logic1 via the VTRS4 signal (i.e., the second full signal). UART Switch Logic1 then sends a second pause signal (specifically, a software flow control signal) to notify the external device to pause data frame transmission. UART Switch Logic0 reads data frame 21 from FIFO0 via VUART0 and forwards it to UART3. After reading data frame 21, FIFO0 controls the shifting of data frames 22 and 23. See [Refer to the following text]. Figure 6After the shift processing, there is no data frame in the second storage unit 3. FIFO0 will inform UART Switch Logic 1 through the VTRS4 signal (i.e., the second no-load signal). UART Switch Logic 1 will send a second resume signal (specifically, it can be a software flow control signal or an RTS_PLD entity signal) to inform the external device to continue sending data frames.

[0084] Continue to see Figure 9 In this server, the CPU is connected to the BMC via the eSPI bus. The BMC parses the system serial port data on the eSPI bus and transmits it to the CPLD via the SYS_UART line. Simultaneously, the BMC transmits its own serial port data to the CPLD via the BMC_UART line. External devices connected to the UART CON can obtain both the system serial port data and the BMC's own serial port data through the CPLD.

[0085] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0086] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above communication method embodiments.

[0087] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above-mentioned XX method embodiments when run.

[0088] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0089] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above communication method embodiments are implemented.

[0090] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned communication method embodiments are implemented.

[0091] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] The above is a detailed introduction to a communication system, communication method, electronic device, storage medium, and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A communication system, characterized in that: The communication system includes a plurality of slave devices, a plurality of storage elements, and a master device; the plurality of slave devices and the plurality of storage elements correspond one to one; the slave device includes a first serial port, the storage element includes a second serial port and a third serial port; the master device includes a fourth serial port; For any of the slave devices, the first serial port of the slave device is connected to the second serial port of the storage element corresponding to the slave device; For any of the storage elements, the third serial port of the storage element is connected to the fourth serial port of the host device; The communication system further includes a first logic control element, a second logic control element, and a master control element; The first logic control element includes a plurality of first signal transmission channels, and two ends of any first signal transmission channel are respectively connected to the first serial port of the slave device and the second serial port of the storage element having a corresponding relationship; The second logic control element includes a plurality of second signal transmission channels, one end of each of the second signal transmission channels is connected to the third serial port of the storage element, and the other end is connected to the fourth serial port of the master device; Different second signal transmission channels are connected to different storage elements; The master control element is connected to the first logic control element and the second logic control element.

2. The communication system according to claim 1, wherein: The communication system further includes a first processor; the first processor is connected to the master control component.

3. The communication system according to claim 1, wherein: The master control component is connected to at least one of the storage components.

4. A communication method, characterized in that: The communication method is applied to the communication system according to any one of claims 1 to 3, and the communication method includes: The storage element receives and buffers the data frame from the slave device; In response to an access instruction to the slave device, the storage element outputs the buffered data frame from the slave device to the master device; The communication system further includes a first logic control element, a second logic control element, and a master control element; the first logic control element includes a plurality of first signal transmission channels, and the two ends of any first signal transmission channel are respectively connected to the corresponding slave device and the storage element; the second logic control element includes a plurality of second signal transmission channels, and one end of any second signal transmission channel is connected to the storage element and the other end is connected to the master device; different second signal transmission channels are connected to different storage elements; the master control element is connected to the first logic control element and the second logic control element, and the method further includes: The master control element sends a first state adjustment signal to the first logic control element and sends a second state adjustment signal to the second logic control element; The first logic control element adjusts the on / off state of the first signal transmission channel based on the first state adjustment signal, so that the slave device connected to the first signal transmission channel in the on state and the storage element can achieve data exchange; The second logic control element adjusts the on / off state of the second signal transmission channel based on the second state adjustment signal, so as to enable data exchange between the host device and the storage element.

5. The method according to claim 4, characterized in that The method further comprises: The storage element receives and buffers the data frame from the master device; the data frame from the master device has the slave device corresponding thereto; The storage element outputs the data frame from the master device to the corresponding slave device.

6. The method according to claim 5, characterized in that The storage element includes a plurality of first storage units and a plurality of second storage units; the plurality of first storage units are arranged in a first order to form a first storage sequence; the plurality of second storage units are arranged in a second order to form a second storage sequence; The storage element buffers the data frames from the slave device and outputs the data frames from the slave device to the master device, comprising: the first storage sequence buffers the data frames from the slave device in a first-in-first-out manner and outputs the data frames to the master device; The storage element caches the data frames from the master device and outputs the data frames from the master device to the slave device, including: the second storage sequence caches the data frames from the master device in a first-in-first-out manner and outputs the data frames to the slave device.

7. The method according to claim 6, characterized in that The first storage sequence buffers the data frame from the slave device, comprising: when the first storage unit at the end of the sequence does not include the data frame, the storage element receives the data frame from the slave device and stores the received data frame in the first storage unit at the end of the sequence; The second storage sequence caches the data frame from the master device, including: when the second storage unit at the end of the sequence does not include the data frame, the storage element receives the data frame from the master device and stores the received data frame in the second storage unit at the end of the sequence.

8. The method according to claim 7, characterized in that The first storage sequence outputs the buffered data frames to the master device, including: outputting the data frame in the first storage unit at the beginning of the sequence to the master device, the storage element sequentially moving the data frames stored in the remaining first storage units in the first storage sequence except the first storage unit at the beginning to the previous first storage unit, and clearing the data frames in the first storage unit at the end of the sequence; The second storage sequence outputs the cached data frames to the slave device, including: outputting the data frames in the second storage unit at the beginning of the sequence to the slave device, the storage element moving the data frames stored in the remaining second storage units in the second storage sequence except the second storage unit at the beginning of the sequence forward to the previous second storage unit, and clearing the data frames in the second storage unit at the end of the sequence.

9. The method according to claim 8, characterized in that The method further comprises: In a case where each of the first storage units in the first storage sequence includes a data frame, the storage element sends a first full-load signal to the first logic control element; after receiving the first full-load signal, the first logic control element sends a first pause signal to the slave device; after receiving the first pause signal, the slave device pauses sending data to the storage element; When each of the second storage units in the second storage sequence includes a data frame, the storage element sends a second full load signal to the second logic control element; after receiving the second full load signal, the second logic control element sends a second pause signal to the master device, and after receiving the second pause signal, the master device pauses sending data to the storage element.

10. The method according to claim 9, characterized in that When the first storage unit at the end of the sequence does not include a data frame, the storage element receives the data frame from the slave device, comprising: when the first storage unit at the end of the sequence does not include a data frame, the storage element sends a first no-load signal to the first logic control element; after receiving the first no-load signal, the first logic control element sends a first recovery signal to the slave device; after receiving the first recovery signal, the slave device sends a data frame to the storage element; and the storage element receives the data frame from the slave device; When the second storage unit at the end of the sequence does not include a data frame, the storage element receives the data frame from the master device, including: when the second storage unit at the end of the sequence does not include a data frame, the storage element sends a second no-load signal to the second logic control element; after receiving the second no-load signal, the second logic control element sends a second recovery signal to the master device; after receiving the second recovery signal, the master device sends the data frame to the storage element; and the storage element receives the data frame from the master device.

11. The method according to claim 5, characterized in that The communication system further includes a first processor connected to the master control element, wherein the master control element sends a first state adjustment signal to the first logic control element and sends a second state adjustment signal to the second logic control element, including: The first processor sends a first control signal to the master control element; In response to the first control signal, the master control element sends a first state adjustment signal to the first logic control element and sends a second state adjustment signal to the second logic control element.

12. The method according to claim 5, characterized in that The master control element is connected to at least one of the storage elements; The master control element sends a first state adjustment signal to the first logic control element and sends a second state adjustment signal to the second logic control element, including: The master device sends a second control signal to the second logic control element; The second logic control element forwards the second control signal to the storage element; The storage element forwards the second control signal to the master control element; In response to the second control signal, the master control element sends a first state adjustment signal to the first logic control element and sends a second state adjustment signal to the second logic control element.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the communication method according to any one of claims 4 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the communication method according to any one of claims 4 to 12 when executed by a processor.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the communication method according to any one of claims 4 to 12 are implemented.

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