Centralized video splicing processor to achieve vertical synchronization method, system and device

Abstract

The present invention belongs to the field of video processing, and specifically relates to a method, system and device for realizing vertical synchronization of a centralized video splicing processor, and aims to solve the problem of misalignment and tearing of upper and lower adjacent displays when multiple LCD displays are spliced ​​together to output the same picture using a splicing processor. The present invention comprises: determining the relative position of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen; calculating the output delay line number of the lower display relative to the upper display based on the number of vertical resolution lines of the display; when the splicing processor outputs image data, the output lines of all displays below the first line are subjected to frame delay control based on the number of delay lines until the output of the entire frame image is completed. The present invention ensures visually continuous, seamless and synchronous image display, and completely eliminates vertical misalignment and tearing.

Description

Technical Field

[0001] The present invention belongs to the field of video processing, and in particular relates to a method, system and device for realizing vertical synchronization of a centralized video splicing processor. Background Art

[0002] When using a splicing controller to process an input video signal and display it in a tiled manner on multiple LCD screens of the same model, due to the LCD screen refresh mechanism, when the video image moves quickly left and right, the upper and lower adjacent LCD displays are prone to image misalignment, tearing, and other phenomena. Most LCD displays on the market use a line-by-line refresh mode, refreshing the image display from left to right and from top to bottom; after the field synchronization signal arrives, the frame image is refreshed, and after the line synchronization signal arrives (often aligned with the field synchronization signal), the line image data is displayed dot by dot according to the data enable signal. When the enable signal ends, the line data ends, and the next line synchronization signal arrives, repeating the process until the entire frame image ends and the field synchronization signal arrives to refresh the next frame image.

[0003] This image display method will cause different pixels of the same image to be displayed non-simultaneously. When displayed on one display, the human eye cannot see this problem. However, when a splicing controller is used to display the same image on multiple LCD displays, the upper and lower adjacent displays will be processed according to the same frame, and each display will refresh each line at the same time. However, the correct logic is that the first line of the lower display will not be refreshed until the last line of the upper display is refreshed. Therefore, it will cause misalignment and tearing of the upper and lower adjacent images.

[0004] Based on this, the present invention proposes a method, system and device for implementing vertical synchronization of a centralized video splicing processor. Summary of the Invention

[0005] In order to solve the above-mentioned problem in the prior art, that is, when a splicing processor is used to splice multiple LCD displays to output the same image, the upper and lower adjacent displays are misaligned and torn, the present invention provides a method, system and device for realizing vertical synchronization using a centralized video splicing processor.

[0006] A first aspect of the present invention provides a method for implementing vertical synchronization in a centralized video splicing processor, the method comprising:

[0007] Determine the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen;

[0008] Based on the number of vertical resolution lines of the display, calculate the number of output delay lines of the lower display relative to the upper display;

[0009] When outputting image data, the splicing processor performs frame delay control on the output rows of all displays below the first row based on the number of delayed rows until the output of the entire frame of image is completed.

[0010] Furthermore, the display in the first row is used as the reference display. When the reference display outputs the first row of the Nth frame, the display below sequentially outputs the ((k-1)×H+1)th row of the (N-(k-1))th frame.

[0011] Where H is the number of vertical resolution rows of a single display, k is the number of rows of displays in the spliced ​​large screen, and k ≥ 1.

[0012] Furthermore, at least (D+1) frames of image data are cached in the image buffer, where D is the maximum number of rows of the display in the spliced ​​large screen;

[0013] The frame pointer is dynamically adjusted according to the position of the display: the top display reads the current frame data; for the k-th row display, the output starts from the ((k-1)×H+1)-th row of the (N-(k-1)) frame.

[0014] Furthermore, the number of vertical resolution lines is dynamically configured according to actual display parameters, and the method includes:

[0015] Automatically detect the display's EDID information and parse it; or

[0016] Determined by the display parameter configuration preset by the user.

[0017] Furthermore, the relative positions of upper and lower adjacent displays are obtained through topological information pre-configured in the splicing system.

[0018] Furthermore, the topology information pre-configured by the splicing system is obtained, and the specific method is as follows:

[0019] Two-dimensional row and column coordinates of the display are established, and the relative position relationship between upper and lower adjacent displays is determined based on the two-dimensional row and column coordinates.

[0020] Furthermore, the image buffer adopts a circular storage mechanism. When a new frame image is input, the oldest frame data in the cache is overwritten, and each display synchronously updates the read frame number according to the position relationship.

[0021] In a second aspect of the present invention, a centralized video splicing processor is provided to implement a vertical synchronization system. The system comprises:

[0022] A position acquisition module configured to determine the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen;

[0023] a delay line number calculation module configured to calculate the output delay line number of the lower display relative to the upper display based on the vertical resolution line number of the display;

[0024] The delay module is configured to perform frame delay control on the output rows of all displays below the first row based on the number of delay rows when the splicing processor outputs image data until the output of the entire frame of image is completed.

[0025] According to a third aspect of the present invention, an electronic device is provided, comprising:

[0026] at least one processor; and

[0027] a memory communicatively connected to at least one of the processors; wherein,

[0028] The memory stores instructions that can be executed by the processor, and the instructions are used to be executed by the processor to implement a method for implementing vertical synchronization of a centralized video splicing processor.

[0029] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement a vertical synchronization method for a centralized video splicing processor.

[0030] Beneficial effects of the present invention:

[0031] By precisely calculating the number of delayed lines of the lower display relative to the upper display and actively applying frame delay control, this method fundamentally solves the problem of asynchronous refresh timing at the connection point of adjacent screen images (the bottom and top lines) caused by the LCD's line-by-line refresh characteristics.

[0032] This ensures that the time when the first line of image on the lower display starts to refresh is accurately aligned with the time when the last line of image on the upper display has just finished refreshing, ensuring visually continuous, seamless, and synchronized image display, and completely eliminating vertical misalignment and tearing.

[0033] Different from expensive hardware solutions that rely on external synchronization signal generators (such as Genlock) or special displays that support synchronization input and output, the present invention completely realizes synchronization in the internal logic of the centralized video splicing processor.

[0034] The core mechanism is to use the stitching processor to control the output image data stream and achieve the required frame delay by managing the time of reading and writing operations of different channel image data in different storage areas (buffers).

[0035] This implementation significantly reduces the requirements and costs for external hardware of the splicing system and improves the versatility and deployability of the solution.

[0036] The core of the present invention lies in the read and write scheduling strategy for the existing video data buffer. It does not require the addition of an additional full-frame buffer or complex cache hardware for each display (except for the necessary buffer structure of the splicing controller itself).

[0037] The delay required for synchronization is calculated based on the known display line resolution, and the data output timing is precisely controlled by an internal clock / counter, eliminating the need for an external precise clock source. This "soft synchronization" method maximizes the use of the existing memory and control resources of the splicing processor, achieving complex vertical synchronization functions with minimal additional overhead.

[0038] This invention completely solves the problem of screen tearing and significantly improves the integrity, continuity, and visual comfort of large-screen spliced ​​displays. It provides users with a seamless, stable, high-quality spliced ​​image experience and is particularly suitable for applications requiring high-precision visual presentation, such as command and dispatch centers, large-scale exhibitions, and high-end conference rooms.

[0039] This method performs calculations based on the physical position (topology) of the displays and the known number of resolution rows. Theoretically, it can be applied to any number of LCD displays with any resolution combination (row alignment). Configuration is relatively simple; simply set the positional relationship and resolution parameters of each display in the splicing processor to automatically calculate delays and synchronize them. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0041] Figure 1 Schematic diagram of a spliced ​​large screen in the first embodiment of the present invention;

[0042] Figure 2 Schematic diagram of splicing large-screen display input sources in the first embodiment of the present invention;

[0043] Figure 3 is a schematic diagram of image misalignment displayed on each display in the first embodiment of the present invention;

[0044] Figure 4 Schematic diagram of the image caching mechanism in the first embodiment of the present invention. DETAILED DESCRIPTION

[0045] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are intended only to illustrate the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0046] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] The present invention provides a method for realizing vertical synchronization of a centralized video splicing processor, the method comprising:

[0048] Step S10, determining the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen;

[0049] Step S20, calculating the output delay line number of the lower display relative to the upper display based on the vertical resolution line number of the display;

[0050] Step S30 , when outputting image data, the splicing processor performs frame delay control on the output rows of all displays below the first row based on the number of delayed rows until the output of the entire frame of image is completed.

[0051] like Figure 1 and Figure 2 As shown, taking a 1920×1080 display as an example, display A to display I are all displays with a resolution of 1920×1080, together forming a 3×3 spliced ​​large screen, the output resolution of the spliced ​​large screen is 5760×3240, and display A, display B and display C are three sub-screens adjacent to each other in a row on the left side of the spliced ​​large screen;

[0052] The image display is refreshed from left to right and from top to bottom.

[0053] Since n outputs are scanned out simultaneously, such as Figure 3 As shown:

[0054] Monitors A, B, and C all output images at the same time, representing the same frame. However, due to the image refresh method, monitors A, B, and C all output new images simultaneously on the same row. While the top of monitor B displays the new image, the bottom of monitor A continues to display the original image. Similarly, while the top of monitor C displays the new image, the bottom of monitor B continues to display the original image, resulting in image misalignment.

[0055] Figure 2 In the image, vertical diagonal lines are used to represent the image moving from left to right. Each frame moves 3 points to the right, which becomes a misalignment phenomenon when displayed on the monitor. Since the image movement is continuous, the image misalignment cannot be seen on the same monitor.

[0056] Since it takes one frame for the new image on the display to refresh to the bottom, the bottom of display A and the top of display B, as well as the bottom of display B and the top of display C will appear misaligned. If our image is a common 60-frame image, then the misaligned image time is about 1 / 60 s.

[0057] The dislocation effect is as shown in the left image below. The ideal display effect should be as follows Figure 2 As shown in the image on the right, there is no image misalignment or tearing.

[0058] When outputting images in a progressive scanning mode, if vertical synchronization processing is not performed, when display A scans the first line of video data, displays B and C will also scan the first line. If the image is static, the misalignment and tearing of the image are not very obvious. However, when the image moves, the misalignment and tearing of the upper and lower adjacent displays are very obvious. According to the overall image processing logic, display A should scan the last line of data before starting to scan the first line of data of display B; display B should scan the last line of data before starting to scan the first line of data of display C. The main idea of ​​the present invention is to delay the display of the corresponding number of lines on the lower display according to the positional relationship of the displays, and calculate the number of lines required for delay based on displays with different resolutions, so that the image can achieve the purpose of vertical synchronization visually.

[0059] In order to more clearly illustrate the method for realizing vertical synchronization of a centralized video splicing processor of the present invention, the following is combined with Figure 1 Each step in the embodiment of the present invention is described in detail as follows:

[0060] Step S10, determining the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen;

[0061] In this embodiment, the relative positions of upper and lower adjacent displays are obtained through topological information pre-configured in the splicing system. Specifically, two-dimensional row and column coordinates of the displays are established, and the relative position relationship of the upper and lower adjacent displays is determined based on the two-dimensional row and column coordinates.

[0062] Specifically, during the system initialization phase, the centralized video splicing processor establishes a two-dimensional row and column coordinate model of all displays using preset splicing topology configuration information.

[0063] like Figure 1 As shown, each display is assigned a unique coordinate identifier (such as display A is located at (1, 1), display B is located at (2, 1), and display C is located at (3, 1)). This coordinate system directly maps the physical position relationship, where increasing row numbers represent the vertical downward adjacent relationship (for example, row number 2 of display B (2, 1) is greater than row number 1 of display A (1, 1), so B is directly below A).

[0064] The processor automatically determines the relationship between upper and lower neighbors based on two-dimensional coordinates: for any display, the display corresponding to the row coordinate minus 1 is the upper neighbor, and the display corresponding to the row coordinate plus 1 is the lower neighbor. Taking display B (2, 1) as an example, the system outputs its upper neighbor as display A (Δrow = -1) at coordinates (1, 1) and its lower neighbor as display C (Δrow = +1) at coordinates (3, 1). This relationship is directly used in subsequent delay calculations.

[0065] Step S20, calculating the output delay line number of the lower display relative to the upper display based on the vertical resolution line number of the display;

[0066] In this embodiment, the number of delayed rows is calculated as follows:

[0067] The number of delay lines is directly based on the vertical resolution lines of the display. Based on the vertical position of the display in the spliced ​​large screen (with the top display as the reference layer), the number of delay lines of the lower display relative to the reference layer is calculated according to the formula:

[0068] Delay line number = vertical resolution × position line number difference;

[0069] The position row number difference is the number of rows between the display for which the delay row number is currently to be calculated and the top display.

[0070] by Figure 1 Take the 3×3 splicing screen (vertical resolution 1080 lines) as an example:

[0071] Reference layer (display A): Position row number difference x = 0 → Delay row number = 1080 × 0 = 0 rows (no delay required);

[0072] Lower display B: located directly below display A (x=1) → delayed lines = 1080 × 1 = 1080 lines;

[0073] Bottom display C: Located directly below B (x=2) → Delay lines = 1080×2=2160 lines.

[0074] Step S30 , when outputting image data, the splicing processor performs frame delay control on the output rows of all displays below the first row based on the number of delayed rows until the output of the entire frame of image is completed.

[0075] In this embodiment, the display in the first row is used as the reference display. When the reference display outputs the first row of the Nth frame, the lower display sequentially outputs the ((k-1)×H+1)th row of the (N-(k-1))th frame.

[0076] Where H is the number of vertical resolution rows of a single display, k is the number of rows of displays in the spliced ​​large screen, and k ≥ 1.

[0077] Specifically, when the reference display (the 1st row display) outputs the 1st row of the Nth frame, the kth row display (k≥2) vertically below it synchronously outputs the ((k-1)×H+1)th row of the (N-(k-1))th frame.

[0078] Parameter initialization: Get the vertical resolution H of all displays (via EDID or pre-configuration); determine the k value based on the preset two-dimensional coordinates (e.g., A→k=1, B→k=2, C→k=3);

[0079] Real-time output control:

[0080] When the reference display (k=1) outputs the first line of the current frame N:

[0081] The lower display B (k=2) immediately outputs the (H+1)th line of the previous frame (N-1);

[0082] The bottom display C (k=3) immediately outputs the (2H+1)th row of the previous two frames (N-2);

[0083] Loop mechanism:

[0084] After each frame scan is completed, the frame number N increases, and all displays re-match the output frame number according to the k value (for example, when N→N+1, B outputs the (H+1)th line of frame N, and C outputs the (2H+1)th line of frame N-1).

[0085] When display A scans line 1 of frame N, display B scans line 1080×1+1 of frame N-1, and display C scans line 1080×2+1 of frame N-2, and so on until the entire image is scanned. If more displays are present, the calculation process repeats. When the display resolution is 3840×2160, the 1080 in the above calculation needs to be replaced with the actual display vertical resolution of 2160. This scanning process repeats until display A scans line 1 of frame N, display B scans line 1081 of frame N-1, and display C scans line 2161 of frame N-2. The output delay between the upper and lower displays is 1080 lines, which is the vertical resolution of the display. Different output delays occur depending on the output resolution.

[0086] The number of vertical resolution lines is dynamically configured according to actual display parameters, and the method includes:

[0087] Automatically detect the display's EDID information and parse it; or determine it through user-preset display parameter configuration.

[0088] In this embodiment, at least (D+1) frames of image data are cached in the image buffer, where D is the maximum number of rows of the display in the spliced ​​large screen;

[0089] The frame pointer is dynamically adjusted according to the position of the display: the top display reads the current frame data; for the k-th row display, the output starts from the ((k-1)×H+1)-th row of the (N-(k-1)) frame.

[0090] The image buffer adopts a circular storage mechanism. When a new frame image is input, the oldest frame data in the cache is overwritten, and each display synchronously updates the read frame number according to the position relationship.

[0091] like Figure 4 As shown, the board used by the splicing processor in the present invention has a processing logic that stores the layer data of the output image in a fixed storage space on the board. Each output channel is accessed by the output card from a fixed position in the corresponding storage space and output to the screen. Several frames of images are cached in the image buffer. Data is accessed from corresponding positions of different frames according to different positions of the display. When display A outputs the first line of the nth frame, display B outputs the 1080×1+1th line of the n-1th frame, and display C outputs the 1080×2+1th line of the n-2th frame, until the image scan of this frame is completed, and the process is repeated; when display A outputs the first line of the n+1th frame, display B outputs the 1080×1+1th line of the nth frame, and display C outputs the 1080×2+1th line of the n-1th frame.

[0092] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art will understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0093] A second embodiment of the present invention provides a centralized video splicing processor to implement vertical synchronization system, based on a centralized video splicing processor to implement vertical synchronization method, the system includes:

[0094] A position acquisition module configured to determine the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen;

[0095] a delay line number calculation module configured to calculate the output delay line number of the lower display relative to the upper display based on the vertical resolution line number of the display;

[0096] The delay module is configured to, when the splicing processor outputs image data, perform frame delay control on the output rows of all displays below the first row based on the number of delayed rows until the entire frame of image output is completed. Those skilled in the art will clearly understand that for ease and brevity of description, the specific operating process and related description of the system described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0097] It should be noted that the above embodiment provides a centralized video splicing processor to implement a vertical synchronization system, which is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps and are not regarded as improper limitations on the present invention.

[0098] An electronic device according to a third embodiment of the present invention includes:

[0099] at least one processor; and

[0100] a memory communicatively connected to at least one of the processors; wherein,

[0101] The memory stores instructions that can be executed by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned method for implementing vertical synchronization using a centralized video splicing processor.

[0102] A fourth embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned method for implementing vertical synchronization using a centralized video splicing processor.

[0103] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes and related instructions of the storage device and processing device described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0104] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. In order to clearly illustrate the interchangeability of electronic hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0105] The terms "first", "second", etc. are used to distinguish similar objects, rather than to describe or indicate a particular order or sequence.

[0106] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0107] Thus far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present invention.

Claims

1. A method for realizing vertical synchronization of a centralized video splicing processor, characterized in that: The method includes: Determine the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen; Based on the number of vertical resolution lines of the display, calculate the number of output delay lines of the lower display relative to the upper display; When outputting image data, the splicing processor performs frame delay control on the output rows of all displays below the first row based on the number of delayed rows until the output of the entire frame of image is completed; The display in the first row is used as the reference display. When the reference display outputs the first row of the Nth frame, the display below it sequentially outputs the ((k-1)×H+1)th row of the (N-(k-1))th frame. Where H is the number of vertical resolution rows of a single display, k is the number of rows of displays in the spliced ​​large screen, and k ≥ 1.

2. The method for implementing vertical synchronization of a centralized video splicing processor according to claim 1, wherein: Cache at least (D+1) frames of image data in the image buffer, where D is the maximum number of rows of displays in the spliced ​​large screen; The frame pointer is dynamically adjusted according to the position of the display: the top display reads the current frame data; for the k-th row display, the output starts from the ((k-1)×H+1)-th row of the (N-(k-1)) frame.

3. The method for implementing vertical synchronization of a centralized video splicing processor according to claim 1, characterized in that: The number of vertical resolution lines is dynamically configured according to actual display parameters, and the method includes: Automatically detect the display's EDID information and parse it; or Determined by the display parameter configuration preset by the user.

4. The method for implementing vertical synchronization of a centralized video splicing processor according to claim 1, wherein: The relative positions of upper and lower adjacent displays are obtained through the topology information pre-configured in the splicing system.

5. The method for realizing vertical synchronization of a centralized video splicing processor according to claim 4, characterized in that: The topology information pre-configured by the splicing system is obtained by: Two-dimensional row and column coordinates of the display are established, and the relative position relationship between upper and lower adjacent displays is determined based on the two-dimensional row and column coordinates.

6. A method for implementing vertical synchronization of a centralized video splicing processor according to claim 2, characterized in that: The image buffer adopts a circular storage mechanism. When a new frame image is input, the oldest frame data in the cache is overwritten, and each display synchronously updates the read frame number according to the position relationship.

7. A centralized video splicing processor realizes vertical synchronization system, based on a centralized video splicing processor realizes vertical synchronization method according to any one of claims 1 to 6, characterized in that: The system includes: A position acquisition module configured to determine the relative positions of upper and lower adjacent displays based on the physical position relationship of each display in the spliced ​​large screen; a delay line number calculation module configured to calculate the output delay line number of the lower display relative to the upper display based on the vertical resolution line number of the display; The delay module is configured to perform frame delay control on the output rows of all displays below the first row based on the number of delay rows when the splicing processor outputs image data until the output of the entire frame of image is completed.

8. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to at least one of the processors; wherein, The memory stores instructions that can be executed by the processor, and the instructions are used to be executed by the processor to implement the vertical synchronization method of a centralized video splicing processor as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the method for implementing vertical synchronization by a centralized video splicing processor according to any one of claims 1 to 6.

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