Optical interconnect cable assembly, communication system, server and link power consumption control method

Abstract

The present application discloses an optical interconnection cable assembly, a communication system, a server, and a link power consumption control method, which relate to the fields of computer systems and information interaction technology. The present application discloses an optical interconnection cable assembly, a communication system, a server, and a link power consumption control method. The present application relates to the fields of computer systems and information interaction technology, and includes an optical interconnection cable assembly. A first cable subassembly controls a first processor and a first optical interconnection device to enter or exit a low power consumption mode, and a second processor controls a second processor and a second optical interconnection device to enter or exit a low power consumption mode. The present application solves the technical problem that related technologies do not allow optical cables or optical modules to enter a low power consumption mode, and that they operate in a standard mode for a long time, resulting in high power consumption of the entire link. The present application achieves the technical effect of reducing the energy consumption of the entire optical interconnection link.

Description

Technical Field

[0001] The present application relates to the field of computer systems and information interaction technology, and in particular to an optical interconnection cable assembly, a communication system, a server, and a link power consumption control method. Background Art

[0002] As the speed of the PCIe (Peripheral Component Interconnect Express) protocol continues to increase, optical interconnect technology, due to its low transmission loss, has been introduced into PCIe link systems. While optical cables can extend transmission distances, as active devices, they consume high power, and large-scale use increases costs and energy consumption.

[0003] While the PCIe protocol includes an electrical idle state to reduce power consumption in electrical links, this mechanism doesn't fully account for the characteristics of optical interconnects. Consequently, there's a response delay when optical modules wake up from low-power modes. Initiating link training before the optical modules have fully recovered and stabilized can prevent the link rate and bit width from recovering, leading to signal distortion and bit errors. Consequently, current PCIe optical interconnect systems typically don't allow entry into low-power modes, resulting in higher overall power consumption. Summary of the Invention

[0004] The present application provides an optical interconnect cable assembly, a communication system, a server, and a link power consumption control method, in order to at least solve the technical problem that the related technology does not allow the optical cable or optical module to enter the low power consumption mode, and works in the standard mode for a long time, resulting in high power consumption of the entire link.

[0005] The present application provides an optical interconnection cable assembly, comprising: a first cable subassembly and a second cable subassembly; the first cable subassembly comprises a first processor and a first optical interconnection device, and the first processor and the first optical interconnection device allow entering or exiting a low power consumption mode; the second cable subassembly comprises a second processor and a second optical interconnection device, and the second processor and the second optical interconnection device allow entering or exiting a low power consumption mode.

[0006] The present application also provides an optical interconnection communication system, comprising: the above-mentioned optical interconnection cable assembly; and a transmitting end and a receiving end arranged at both ends of the optical interconnection cable assembly.

[0007] The present application also provides an optical interconnection communication system, comprising: a plurality of the above-mentioned optical interconnection cable assemblies; at least one transmitting end and at least one receiving end, wherein the at least one transmitting end and the at least one receiving end are respectively connected to one end of different optical interconnection cable assemblies; and a switch, the switch being connected to the other ends of different optical interconnection cable assemblies.

[0008] An embodiment of the present application also provides a server, comprising any of the above-mentioned optical interconnection communication systems.

[0009] An embodiment of the present application also provides a method for controlling power consumption of an optical interconnection link, which is applied to the first processor of the first cable subassembly in the above-mentioned optical interconnection cable assembly. The method includes: identifying whether the first electrical signal from the transmitting end carries an entry identifier for an electrical idle state; if the first electrical signal carries an entry identifier for an electrical idle state, controlling the devices in the first cable subassembly to enter a low power consumption mode according to a pre-set target entry sequence.

[0010] An embodiment of the present application also provides a method for controlling power consumption of an optical interconnection link, which is applied to the second processor of the second cable sub-assembly in the above-mentioned optical interconnection cable assembly, and the method includes: obtaining a first electrical signal from a transmitting end; identifying whether the first electrical signal carries an entry identifier for an electrical idle state; if the first electrical signal carries an entry identifier for an electrical idle state, controlling the devices in the second cable sub-assembly to enter a low power consumption mode according to a pre-set target entry sequence.

[0011] An embodiment of the present application also provides a method for controlling power consumption of an optical interconnection link, which is applied to the first processor of the first cable subassembly in the above-mentioned optical interconnection cable assembly. The method includes: identifying whether the first electrical signal from the transmitting end carries an exit mark of the electrical idle state; if the first electrical signal carries an exit mark of the electrical idle state, controlling the devices in the first cable subassembly to exit the low power consumption mode according to a pre-set target exit sequence.

[0012] An embodiment of the present application also provides a method for controlling power consumption of an optical interconnection link, which is applied to the second processor in the above-mentioned optical interconnection cable assembly, and the method includes: obtaining a first electrical signal from a transmitting end; identifying whether the first electrical signal from the transmitting end carries an exit mark for an electrical idle state; if the first electrical signal carries an exit mark for an electrical idle state, controlling the devices in the second cable subassembly to exit a low power consumption mode according to a pre-set target exit sequence.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned optical interconnection link power consumption control methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for controlling power consumption of optical interconnection links are implemented.

[0015] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned optical interconnection link power consumption control methods when executed by a processor.

[0016] Through the present application, since the first cable subassembly in the optical interconnection cable assembly can be used to control the first processor and the first optical interconnection device to enter or exit the low power consumption mode, and the second processor can control the second processor and the second optical interconnection device to enter or exit the low power consumption mode, low power consumption control of the optical interconnection link can be achieved. Therefore, the technical problem that the relevant technology does not allow the optical cable or optical module to enter the low power consumption mode and works in the standard mode for a long time, resulting in high power consumption of the entire link, can be solved, thereby achieving the technical effect of reducing the energy consumption of the entire optical interconnection link. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic structural diagram of an optical interconnect cable assembly provided in an embodiment of the present application;

[0019] Figure 2 This is a flowchart of the target entry sequence when entering the low power consumption mode according to an embodiment of the present application;

[0020] Figure 3 This is a flowchart of the target exit sequence when exiting the low power consumption mode according to an embodiment of the present application;

[0021] Figure 4 A schematic diagram of a non-target entry sequence flow chart provided for one embodiment of the present application;

[0022] Figure 5 A schematic diagram of a non-target exit sequence flow chart provided for one embodiment of the present application;

[0023] Figure 6 A schematic diagram of a non-target exit sequence flow chart provided for another embodiment of the present application;

[0024] Figure 7 A schematic diagram of the structure of an optical interconnection communication system provided in an embodiment of the present application;

[0025] Figure 8 A schematic diagram of the structure of another optical interconnection communication system provided in an embodiment of the present application;

[0026] Figure 9 A schematic diagram showing the components of the transmitting side of a low-power PCIe optical interconnect link provided by one embodiment of the present application;

[0027] Figure 10 A schematic diagram of a process for implementing low power consumption control on the transmitting side of a low power PCIe optical interconnect link according to one embodiment of the present application;

[0028] Figure 11 A schematic diagram illustrating the receiving side of a low-power PCIe optical interconnect link provided by one embodiment of the present application;

[0029] Figure 12 A schematic diagram of a process for implementing low power consumption control on the receiving side of a low power PCIe optical interconnect link according to one embodiment of the present application;

[0030] Figure 13 A schematic structural diagram of a low-power PCIe optical interconnect cable assembly provided in one embodiment of the present application;

[0031] Figure 14 A schematic diagram of a control flow for a low-power PCIe optical interconnect cable assembly to enter a low-power state according to one embodiment of the present application;

[0032] Figure 15 A schematic diagram of a control flow for a low-power PCIe optical interconnect cable assembly to exit a low-power state, provided in one embodiment of the present application;

[0033] Figure 16 A schematic diagram of the structure of an optical interconnection system provided in one embodiment of the present application;

[0034] Figure 17 A schematic diagram of another optical interconnection system structure provided in one embodiment of the present application;

[0035] Figure 18 A schematic flow chart of a method for controlling power consumption of an optical interconnect link applied to a first processor according to an embodiment of the present application;

[0036] Figure 19 A schematic flow chart of a method for controlling power consumption of an optical interconnect link applied to a second processor according to an embodiment of the present application;

[0037] Figure 20 A schematic flow chart of a method for controlling power consumption of an optical interconnect link applied to a first processor according to an embodiment of the present application;

[0038] Figure 21 A schematic flow chart of a method for controlling power consumption of an optical interconnect link applied to a second processor according to an embodiment of the present application;

[0039] Figure 22 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0042] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0043] Figure 1 A schematic structural diagram of an optical interconnect cable assembly provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the optical interconnection cable assembly 10 specifically includes: a first cable subassembly 101 , a second cable subassembly 102 , a first processor 103 , a first optical interconnection device 104 , a second processor 105 and a second optical interconnection device 106 .

[0044] Among them, the first cable subassembly 101 includes a first processor 103 and a first optical interconnect device 104, and the first processor 103 and the first optical interconnect device 104 allow entering or exiting the low power consumption mode; the second cable subassembly 102 includes a second processor 105 and a second optical interconnect device 106, and the second processor 105 and the second optical interconnect device 106 allow entering or exiting the low power consumption mode.

[0045] Among them, the first processor 103 is used to relay and recover PCIe protocol signals, and can be a PCIeRetimer chip, or a PCIeSwitch chip with the same support for PCIe protocol signals, etc. The second processor 105 has the same function as the first processor 103 and is usually the same type of chip as the first optical interconnect device 104 in the optical interconnect link. The PCIe protocol signal includes an EIOS (Electrical Idle Ordered Set) sequence and an EIEOS (Electrical Idle Exit Ordered Set) sequence. The EIOS sequence is used to indicate that the link enters the electrical idle state, and the EIEOS is used to indicate that the link exits the electrical idle state. The electrical idle state is a low-power state in the PCIe protocol. In this state, the link temporarily stops data transmission to reduce energy consumption.

[0046] It can be understood that the first cable sub-assembly 101 of the embodiment of the present application includes a first processor 103 and a first optical interconnect device 104, and the first processor 103 relays and recovers the PCIe protocol signal, thereby allowing the first processor 103 and the first optical interconnect device 104 to enter or exit the low power consumption mode; similarly, the second cable sub-assembly 102 includes a second processor 105 and a second optical interconnect device 106, and the second processor 105 relays and recovers the PCIe protocol signal, thereby allowing the second processor 105 and the second optical interconnect device 106 to enter or exit the low power consumption mode, thereby realizing low power consumption control of the optical interconnection link.

[0047] In an embodiment of the present application, the first optical interconnect device 104 includes a first optical transmitter and a first optical receiver, the second optical interconnect device 106 includes a second optical transmitter and a second optical receiver, the first processor 103 is pre-set with a target control sequence, and the first processor 103, the first optical transmitter and the first optical receiver enter or exit the low power consumption mode according to the target control sequence, and the second processor 105 is pre-set with a target control sequence, and the second processor 105, the second optical transmitter and the second optical receiver enter or exit the low power consumption mode according to the target control sequence.

[0048] Among them, the function of the first optical transmitter and the second optical transmitter is to convert electrical signals into optical signals for transmission through the optical cable; the function of the first optical receiver and the second optical receiver is to convert the optical signals received from the optical cable back into electrical signals; the first optical transmitter, the second optical transmitter and the first optical receiver, the second optical receiver can be used to send and receive EIOS sequences and EIEOS sequences.

[0049] It can be understood that the first optical interconnect device 104 of the embodiment of the present application includes a first optical transmitter and a first optical receiver, and the second optical interconnect device 106 includes a second optical transmitter and a second optical receiver, which are used to transmit and receive optical signals, respectively, and complete the conversion into electrical signals; the first processor 103 and the second processor 105 each preset a target control sequence, so that the first processor 103 and its associated first optical transmitter and first optical receiver can enter or exit the low power mode in an orderly manner according to the target control sequence, and the second processor 105 and its associated second optical transmitter and second optical receiver also perform corresponding low power mode switching according to the target control sequence, thereby ensuring that each component can efficiently enter or exit the low power mode without affecting the stability of data transmission, thereby realizing energy consumption management.

[0050] In an embodiment of the present application, the target control sequence includes a target entry sequence and / or a target exit sequence, wherein the target entry sequence includes: controlling the first optical receiver, the second optical transmitter, the second optical receiver, the second processor 105, the first optical transmitter and the first processor 103 to enter the low power consumption mode in sequence; and / or, the target exit sequence includes: controlling the first optical transmitter, the second optical receiver, the first optical receiver, the second optical transmitter, the first processor 103 and the second processor 105 to exit the low power consumption mode in sequence. It can be understood that when the embodiment of the present application needs to enter or exit the low power mode, it is necessary to follow the target control sequence. When entering the low power mode, the target entry sequence is to control the first optical receiver, the second optical transmitter, the second optical receiver, the second processor 105, the first optical transmitter and the first processor 103 to enter the low power mode in sequence; when exiting the low power mode, the target exit sequence is to control the first optical transmitter, the second optical receiver, the first optical receiver, the second optical transmitter, the first processor 103 and the second processor 105 to exit the low power mode in sequence. Through the target control sequence, the low power control of the optical interconnection link can be achieved stably and efficiently, preventing high delays or errors when entering or exiting the low power mode.

[0051] Specifically, Figure 2 This is a flowchart of the target entry sequence when entering the low power consumption mode according to the embodiment of the present application. Figure 2 As shown, the target entry sequence specifically includes the following steps:

[0052] Step S101: The first optical receiver enters a low power consumption mode.

[0053] The first optical receiver is first turned off under the control of the first processor 103 .

[0054] Step S102: The second optical transmitter enters a low power consumption mode.

[0055] The second optical transmitter is controlled to shut down by the second processor. The first optical receiver and the second optical transmitter are primarily responsible for transmitting PCIe protocol signals from the receiving device to the transmitting device. When the transmitting device enters the electrical idle state, it no longer receives data from the receiving device. Therefore, the first optical receiver and the second optical transmitter, which are responsible for transmitting PCIe protocol signals from the receiving device to the transmitting device, can be shut down first.

[0056] Step S103: The second optical receiver enters a low power consumption mode.

[0057] Step S104: The second processor 105 enters a low power consumption mode.

[0058] Steps S103 and S104 are executed successively, and the second optical receiver and the second processor 105 enter the low power consumption mode successively. The two are mainly for receiving and transmitting the electrical idle state to the receiving end device. After completing the reception and forwarding of the EIOS sequence, they can enter the low power consumption mode.

[0059] Step S105: The first optical transmitter enters a low power consumption mode.

[0060] Step S106: The first processor 103 enters a low power consumption mode.

[0061] Steps S105 and S106 are executed successively, and the first optical transmitter and the first processor 103 enter the low power consumption mode successively. Both of them can enter the low power consumption mode only after they can complete all forwarding tasks of the EIOS sequence sent by the transmitting end device.

[0062] Figure 3 This is a flowchart of the target exit sequence when exiting the low power consumption mode according to the embodiment of the present application. Figure 3 As shown, the target exit sequence specifically includes the following steps:

[0063] Step S201: The first optical transmitter exits the low power consumption mode.

[0064] The first optical transmitter is first controlled by the first processor 103 to exit the low power consumption mode.

[0065] Step S202: The second optical receiver exits the low power consumption mode.

[0066] The signal is transmitted to the second processor 105 so that the processor controls the second optical receiver to exit the low power consumption mode.

[0067] Step S203: The first optical receiver exits the low power consumption mode.

[0068] Step S204: The second optical transmitter exits the low power consumption mode.

[0069] Steps S203 and S204 are executed. After t0, the first optical receiver and the second optical transmitter return to normal working state and begin to formally forward the EIEOS sequence, so that the entire PCIe optical interconnect link exits the electrical idle state. t0 is set according to actual needs and is not specifically limited here.

[0070] Step S205: The first processor 103 exits the low power consumption mode.

[0071] Step S206: The second processor 105 exits the low power consumption mode.

[0072] After steps S201-S204, the first optical transmitter, the second optical transmitter and the first optical receiver, the second optical receiver all exit the low power consumption mode and return to normal state. Then, steps S105 and S106 are executed successively to make the first optical transmitter and the first processor 103 exit the low power consumption mode successively.

[0073] Since the entire PCIe optical interconnection link cannot transmit data normally when the first optical transmitter, the second optical transmitter and the first optical receiver, the second optical receiver have not recovered to normal working conditions, the first processor 103 and the second processor 105 do not need to completely exit low power consumption at this stage. Therefore, in order to avoid the first processor 103 and the second processor 105 entering normal working conditions too early and causing energy consumption, the first processor 103 and the second processor 105 are the last to exit when exiting low power consumption mode.

[0074] It should be noted that the embodiment of the present application needs to enter or exit the low power consumption mode in accordance with the target control sequence. If the low power consumption mode is not entered or exited in accordance with the target control sequence, it may cause delays, increase power consumption, and even generate errors, leading to link errors, link interruptions and other problems, affecting normal operation.

[0075] Specifically, the following further describes the problems that may result from not following the target control sequence to enter or exit the low power mode through some incorrect embodiments. Figure 4 This is a non-target entry sequence flow chart. If the low power mode is not entered according to the target control sequence, but according to Figure 4 Follow the steps shown below:

[0076] Step S301: The first optical receiver enters a low power consumption mode.

[0077] Step S302: The second optical transmitter enters a low power consumption mode.

[0078] Steps S301 and S302 are executed in sequence. When the PCIe optical interconnect link begins to enter the low power consumption mode, the first optical receiver is first controlled to be turned off by the first processor 103, and then the second optical transmitter at the receiving end is controlled to be turned off by the second processor 105. These two components are mainly responsible for transmitting PCIe protocol signals from the receiving end device to the transmitting end device. When the transmitting end begins to enter the electrical idle state, it will no longer receive data from the receiving end and the transmitting end. Therefore, the first optical receiver and the second optical transmitter, which are responsible for transmitting PCIe protocol signals from the receiving end device to the transmitting end device, can be turned off first. Steps S301 and S302 follow the target control order.

[0079] Step S303: The first optical transmitter enters a low power consumption mode.

[0080] When the first optical transmitter enters a low power consumption state, the transmitting end cannot send an EIOS sequence to the receiving end.

[0081] Step S304: The second optical receiver enters a low power consumption mode.

[0082] Step S305: The second processor 105 enters a low power consumption mode.

[0083] Step S306: The first processor 103 enters a low power consumption mode.

[0084] Because the first optical transmitter enters a low-power state, the transmitter cannot send an EIOS sequence to the receiver. The receiver, including second processor 105, can only assume, according to the PCIe protocol, that the link has entered an idle state if it has not received any valid data signals for a specified time (e.g., more than 128 μs in the L0 state). Second processor 105 must control the second optical receiver to enter a low-power state before entering a low-power state. First processor 103 also enters a low-power state after completing all forwarding tasks for the EIOS sequence sent by the transmitter.

[0085] Although the entire link can also enter the low power state after the first optical transmitter and the second optical receiver enter the link idle state in a different order, the receiver enters the electrical idle state each time. Figure 2 The sequences shown will all have a certain delay and generate a certain amount of additional power consumption.

[0086] Figure 5 and Figure 6 This is a non-target exit sequence flow chart. In some embodiments of the present application, if the embodiment of the present application exits the low power mode not according to the target control sequence, but according to Figure 5 Follow the steps shown below:

[0087] Step S401: The first processor 103 exits the low power consumption mode.

[0088] Step S402: The first optical transmitter exits the low power consumption mode.

[0089] Step S403: The second optical receiver exits the low power consumption mode.

[0090] Step S404: The first optical receiver exits the low power consumption mode.

[0091] Step S405: The second optical transmitter exits the low power consumption mode.

[0092] Step S406: The second processor 105 exits the low power consumption mode.

[0093] According to the above steps, if the first processor 103 exits the electrical idle state first, and the order of exiting the other components remains unchanged, the first processor 103 forwards the EIEOS sequence, but the first optical transmitter and the second optical receiver have not yet entered the normal working state, then the EIEOS sequence cannot be smoothly forwarded to the second processor 105. After completing the forwarding of the EIEOS sequence, the first processor 103 will not confirm the receiving end and link status according to the protocol and will start to transmit data signals. At this time, the second processor 105 will not be able to correctly receive the data signal or will receive an erroneous data signal, resulting in a bit error and a link error.

[0094] In some embodiments of the present application, if the embodiment of the present application exits the low power consumption mode not according to the target control sequence, but according to Figure 6 Follow the steps shown below:

[0095] Step S501: The first processor 103 exits the low power consumption mode.

[0096] Step S502: The first optical transmitter exits the low power consumption mode.

[0097] Step S503: The second optical receiver exits the low power consumption mode.

[0098] Step S504: The first optical receiver exits the low power consumption mode.

[0099] Step S505: The second optical transmitter exits the low power consumption mode.

[0100] Step S506: The second processor 105 exits the low power consumption mode.

[0101] If the first processor 103, the first optical transmitter, the second optical receiver, and the second processor 105 exit the electrical idle state in sequence, the order in which the remaining components exit remains unchanged. When the first processor 103 forwards a high-speed data signal, the high-speed data signal can reach the second processor 105 and be forwarded to the back-end PCIe chip because the first optical transmitter on the transmitting end and the second optical receiver on the receiving end are already functioning normally. Because PCIe uses an ACK / NAK flow control mechanism (ACK (Acknowledgment) / NAK (Negative Acknowledgment), which is primarily used at the data link layer of the PCIe link to confirm successful data packet reception or report errors during data packet transmission), the second processor 105 needs to forward the ACK / NAK message from the data link layer of the backend PCIe chip upon receiving the high-speed data signal forwarded by the first processor 103. At this time, the first optical receiver and the second optical transmitter may not have fully exited the low-power state and entered the normal operating state (usually taking 1-5 seconds). Therefore, the ACK / NACK message may not successfully reach the first processor 103, triggering a retransmission mechanism. The ACK / NAK message from the data link layer of the backend PCIe chip of the second processor 105 will be retransmitted after tens to hundreds of nanoseconds. However, the retransmission interval is much shorter than the recovery time of the first optical receiver and the second optical transmitter (usually taking 1-5 seconds). Therefore, the second processor 105 may still not receive the ACK / NAK message, which may result in a link error or link interruption, potentially interrupting the application process and affecting the normal operation of the system.

[0102] According to the optical interconnection cable assembly proposed in the embodiment of the present application, the first cable sub-assembly controls the first processor and the first optical interconnection device to enter or exit the low power consumption mode according to the target control sequence, and the second processor controls the second processor and the second optical interconnection device to enter or exit the low power consumption mode according to the target control sequence. This can stably implement low power consumption control of the optical interconnection link, thereby achieving the technical effect of reducing the energy consumption of the entire optical interconnection link.

[0103] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0104] The embodiment of the present application also provides an optical interconnection communication system, such as Figure 7 As shown, the optical interconnection communication system 20 includes: the above-mentioned optical interconnection cable assembly 10 , and a transmitting end 601 and a receiving end 602 provided at both ends of the optical interconnection cable assembly 10 .

[0105] Among them, the sending end 601 is used to generate PCIe signals transmitted in the link, and is usually a device or chip such as a CPU (Central Processing Unit) that can serve as the root node in the PCIe architecture; the root node is the starting point of the entire PCIe hierarchy, responsible for initializing the PCIe link, managing the address space, and serving as a bridge for communication between the host and PCIe devices; the receiving end 602 is usually the Target (target node, a device that serves as the data receiver / responder) end in the PCIe system, including but not limited to GPU (Graphics Processing Unit, graphics processor), SSD (Solid State Drive, solid-state drive) and other devices.

[0106] It can be understood that the embodiment of the present application includes an optical interconnect cable assembly 10, which has a transmitting end 601 and a receiving end 602 at both ends. The transmitting end 601 is usually a device or chip such as a CPU that plays the role of a root node in the PCIe structure, and is used to generate PCIe signals transmitted in the link; the receiving end 602 is usually a device such as a GPU, SSD, etc., which serves as the target node in the PCIe structure, that is, the data receiver and responder. This structure can achieve efficient and reliable PCIe signal transmission and processing.

[0107] According to the optical interconnection communication system proposed in the embodiment of the present application, signal transmission between the transmitting end and the receiving end can be realized through the optical interconnection cable assembly therein, and the technical effect of stably realizing connection and transmitting PCIe protocol optical signals can be achieved.

[0108] The embodiment of the present application also provides an optical interconnection communication system, such as Figure 8 As shown, the optical interconnection communication system 30 includes: a plurality of the above-mentioned optical interconnection cable assemblies 10; at least one transmitting end 601 and at least one receiving end 602, wherein the at least one transmitting end 601 and the at least one receiving end 602 are respectively connected to one end of different optical interconnection cable assemblies 10; and a switch 603, which is connected to the other end of different optical interconnection cable assemblies 10.

[0109] The switch 603 is responsible for the forwarding function in the electrical idle state.

[0110] It can be understood that the embodiment of the present application includes multiple optical interconnect cable assemblies 10 described above, at least one transmitting end 601 and at least one receiving end 602. Each transmitting end 601 and receiving end 602 are respectively connected to one end of a different optical interconnect cable assembly 10, and the other ends of these optical interconnect cable assemblies 10 are connected to a switch 603. The switch 603 is responsible for the forwarding function in the electrical idle state. For example, when only two optical interconnect cable assemblies 10, one transmitting end 601 and one receiving end 602 are included, when the transmitting end 601 serves as the root node, the port of the switch 603 connected to the optical interconnect cable assembly 10 of the transmitting end 601 acts as the receiving end of the switch 603, and the port of the optical interconnect cable assembly 10 connected to the receiving end 602 acts as the transmitting end of the switch 603. In this configuration, the two ports of the switch 603 can work together, so that the optical interconnect cable assemblies 10 of the transmitting end 601 and the receiving end 602 can smoothly enter the low power consumption mode, thereby achieving efficient energy-saving management of the system, while ensuring the stability of data transmission, and effectively reducing the energy consumption of the entire system.

[0111] According to the optical interconnection communication system proposed in the embodiment of the present application, signal transmission between multiple transmitting ends and receiving ends can be realized through a switch, and multiple optical interconnection cable assemblies can be controlled to smoothly enter a low-power mode, thereby realizing efficient energy-saving management of the system, while ensuring the stability of data transmission, and effectively reducing the energy consumption of the entire system.

[0112] The optical interconnection communication system is further described below through a specific embodiment.

[0113] Figure 9 The schematic diagram of the transmitting side of a low-power PCIe optical interconnect link provided in this embodiment includes a transmitter 601, a first processor 103, and a first optical interconnect device 104. The transmitter 601 is used to generate PCIe signals transmitted in the link. It is typically a device or chip such as a CPU that can serve as a root node in the PCIe architecture. It can determine whether the PCIe link of the corresponding port should enter or exit the electrical idle state based on the computing task. The first processor 103 is used to relay and recover PCIe protocol signals sent by the transmitter 601. Typically, PCIe protocol signals sent by the transmitter 601 are attenuated during transmission to the first optical transmitter 104 and do not meet the PCIe protocol specification. Therefore, the first processor 103 is typically added to the link to recover PCIe protocol signals. The first processor 103 is typically a PCIe retimer chip. The first optical transmitter 104 is used to convert PCIe electrical signals transmitted from the first processor 103 into PCIe optical signals, and to convert PCIe optical signals received from the other end into PCIe electrical signals for transmission to the first processor 103.

[0114] for Figure 9 The schematic diagram of the low-power PCIe optical interconnect link transmission side is shown in FIG. The control process for achieving low power consumption is as follows: Figure 10 As shown, the following steps are included:

[0115] Step 1.1: When the link starts to enter the electrical idle state, the transmitter 601 sends the EIOS sequence;

[0116] Step 1.2: After receiving the EIOS sequence, the first processor 103 sends the EIOS sequence to the first optical interconnect device 104, and controls the first optical receiver of the first optical interconnect device 104 to enter a shutdown state;

[0117] Step 1.3: After the first processor 103 completes sending the EIOS sequence downstream, it simultaneously sends an LP (Low-Power mode) instruction to reduce the power consumption of the first optical transmitter of the first optical interconnect device 104, so that the power consumption of the first optical transmitter enters the low power consumption mode;

[0118] Step 1.4: The first processor 103 then enters an electrical idle state, and at this time, the transmitting side of the PCIe optical interconnection link enters a low power consumption mode.

[0119] Specifically, in step 1.2, the receiving end of the first optical interconnect device 104 enters a completely power-off shutdown state, which is the most energy-efficient state; and in step 1.3, the transmitting end of the first optical interconnect device 104 needs to quickly recover to a normal working state when the subsequent link exits the electrical idle state, so the low-power mode entered is a sleep state; in addition to being a PCIeRetimer chip, the first processor 103 can also be a chip such as a PCIeSwitch that has the same support for PCIe protocol signals.

[0120] Figure 11 The working principle and composition diagram of the receiving side of the low-power PCIe optical interconnect link provided in this embodiment are as follows: Figure 11 As shown, the receiving side of the low-power PCIe optical interconnection link includes: a receiving end 602, a second processor 105 and a second optical interconnection device 106. The receiving end 602 is usually a target node in the PCIe system, including but not limited to GPU, SSD solid state drive and other devices, which can be connected to Figure 9Data is transmitted between the transmitting end 601 and the transmitting end 601, and the transmitting end 601 enters the electrical idle state after receiving the EIOS sequence sent by the first processor 103; the second processor 105 has the same function as the first processor 103, and is used to relay and recover the PCIe protocol signal sent by the transmitting end 601; the second optical interconnect device 106 has the same function as the first optical interconnect device 104, and is used to convert the PCIe electrical signal transmitted from the second processor 105 into a PCIe optical signal and convert the PCIe optical signal input from the opposite end into a PCIe electrical signal and transmit it to the second processor 105.

[0121] for Figure 11 The process of achieving low power consumption control at the receiving end of the low power PCIe optical interconnect link is as shown in FIG. Figure 12 As shown, the specific steps include:

[0122] Step 2.1: After receiving the EIOS sequence sent from the upstream, the second processor 105 transmits the EIOS sequence to the receiving end 602 and controls the second transmitter of the second optical interconnect device 106 to enter the off state.

[0123] Step 2.2: After receiving the EIOS sequence, the receiving end 602 enters the electrical idle state;

[0124] Step 2.3: The second processor 105 directly enters the electrical idle state, and at the same time reduces the power consumption of the second receiver controlling the second optical interconnection device 106, so that the second receiver enters the low power consumption mode.

[0125] Specifically, in step 2.1, the second transmitter of the second optical interconnect device 106 enters a completely powered-off state, which is the most energy-efficient state; and in step 2.3, the second receiver of the second optical interconnect device 106 needs to quickly recover to a normal working state when the subsequent link exits the electrical idle state, so the low-power mode entered is a sleep state; in addition to being a PCIeRetimer chip, the second processor 105 can also be a chip such as a PCIeSwitch that supports the same PCIe protocol signal. Usually, in the PCIe optical interconnect link, the second processor 105 and the first processor 103 are chips of the same type.

[0126] Figure 13 This embodiment provides a low-power PCIe optical interconnect cable assembly that can implement the above-mentioned low-power control method for PCIe optical interconnect links.

[0127] like Figure 13As shown, the optical interconnect cable assembly mainly includes a first cable subassembly 101, a second cable subassembly 102, and optical fibers 1 and 2. The first cable subassembly 101 is mainly composed of a first processor 103 and a first optical interconnect device 104, which includes a first optical transmitter and a first optical receiver. The second cable subassembly 102 is mainly composed of a second processor 105 and a second optical interconnect device 106, which includes a second optical transmitter and a second optical receiver. The first cable subassembly 101 and the second cable subassembly 102 are used to connect PCIe devices on both sides, implement optical-to-electrical conversion of PCIe protocol signals, and control the link to enter and exit a low-power state based on the link operating conditions to achieve optimal energy consumption. Optical fibers 1 and 2 are mainly used to connect the cable connectors at both ends to transmit PCIe protocol optical signals.

[0128] for Figure 13 The control process of the low-power PCIe optical interconnect cable assembly entering the low-power state is shown as follows Figure 14 As shown, the specific steps include:

[0129] Step 3.1: The optical interconnection link is in normal working state for transmitting data signals;

[0130] Step 3.2: The first processor 103 in the first cable subassembly 101 detects whether the first high-speed electrical signal contains an EIOS sequence indicating an electrical idle state. If no EIOS sequence is detected, the link is determined to be in a normal working state as in step 3.1. If an EIOS sequence is detected, the process proceeds to step 3.3.

[0131] Step 3.3: The first processor 103 transmits the EIOS sequence to the first optical transmitter, and controls the first optical receiver to enter the off state through the second control electrical signal;

[0132] Step 3.4: The EIOS sequence is converted into a first optical signal by the first optical transmitter and then transmitted to the second optical receiver in the second cable subassembly 102 through the optical fiber 1;

[0133] Step 3.5: The second optical receiver converts the EIOS sequence into an electrical signal and transmits it to the second processor 105. After detecting the EIOS sequence, the second processor 105 transmits the EIOS sequence to the connected device via the first high-speed electrical signal.

[0134] Step 3.6: The second processor 105 controls the second optical transmitter to enter the off state and the second optical receiver to enter the sleep state through the third control electrical signal, and then the second processor 105 enters the electrical idle state;

[0135] Step 3.7: The first processor 103 detects whether the first high-speed electrical signal 233 contains an EIOS sequence indicating entering the electrical idle state. If the EIOS sequence is still detected, the process proceeds to step 3.4, where the EIOS electrical signal is converted into an optical signal and transmitted to the second optical receiver at the other end.

[0136] Step 3.8: If the EIOS sequence is not detected, the upstream PCIe device has entered the electrical idle state. The first processor 103 controls the first optical transmitter to enter the sleep state through the first control electrical signal. Then, the first processor 103 enters the electrical idle low power state.

[0137] Specifically, the EIOS sequence detection is performed in both step 3.2 and step 3.7. The detection in step 3.2 is to start the execution of the low power control method, and the detection in step 3.7 is to avoid the EIOS sequence transmitted to the second optical interconnect device 106 for the first time from being incorrectly received and recognized. In the PCIe protocol, the upstream PCIe device will also send multiple EIOS sequences when entering the electrical idle state, so Figure 13 The low-power control scheme employed by the device shown in the figure also requires that multiple EIOS sequences be transmitted to the peer end. Furthermore, the first optical transmitter in the first cable subassembly 101 and the second optical receiver in the second cable subassembly 102 enter a dormant state, maintaining low-power operation to facilitate rapid response when the subsequent PCIe optical interconnect link exits the electrical idle state. The upstream device connected to the first cable subassembly 101, which sends the EIOS sequence for entering the electrical idle state, is defined as the root node in the PCIe architecture. When exiting the electrical idle state, it is also controlled by the root node. Therefore, it is only necessary to ensure that the first optical transmitter in the first cable subassembly 101 and the second optical receiver in the second cable subassembly 102 enter a dormant state from which they can be quickly awakened. The first optical receiver in the first cable subassembly 101 and the second optical transmitter in the second cable subassembly 102 enter a nearly power-free shutdown state to minimize energy consumption.

[0138] for Figure 13 The control flow chart of the low-power PCIe optical interconnect cable assembly exiting the low-power state is shown in FIG. Figure 15 As shown, the specific steps include:

[0139] Step 4.1: The transmitting end of the optical interconnection link begins to exit the electrical idle state;

[0140] Step 4.2: The first processor 103 in the first cable subassembly 101 receives a first high-speed electrical signal sent by an uplink device;

[0141] Step 4.3: Check whether the first high-speed electrical signal contains an EIEOS sequence that exits the electrical idle state. If not, return to step 4.2 and proceed to the normal electrical signal reception state. If an EIEOS sequence is detected, proceed to step 4.4.

[0142] Step 4.4: The first processor 103 controls the first optical transmitter to exit the sleep state through the first control electrical signal, controls the first optical receiver to start powering on and resume normal operation, and starts timing t1;

[0143] Step 4.5: After exiting the dormant state, the first optical transmitter transmits a first low-frequency sequence to the second optical receiver in the second cable subassembly 102 via a first optical signal;

[0144] Step 4.6: The second optical receiver transmits the low-frequency sequence signal indicating that the second cable subassembly 102 needs to exit the sleep state to the second processor 105 through the fourth control electrical signal;

[0145] Step 4.7: The second processor 105 controls the optical receiver to exit the sleep state through the fourth control electrical signal, and controls the second optical transmitter to power on and resume normal working state through the third control electrical signal;

[0146] Step 4.8: After the second optical transmitter is powered on and restored to normal working state, it transmits a second low-frequency sequence to the first optical receiver in the first cable subassembly 101 via a second optical signal. The first optical receiver transmits the sequence indicating that the optical assembly has returned to normal working state to the first processor 103 via a second control electrical signal.

[0147] Step 4.9: When the time t1 reaches the recovery time t0 of the optoelectronic device in the cable assembly from the off state to the normal working state, the first processor 103 officially exits the electrical idle state and starts sending the EIEOS sequence to the first optical transmitter;

[0148] S410: The first optical transmitter converts the EIEOS sequence electrical signal into an optical signal and transmits the optical signal to the second processor 105. After receiving the EIEOS sequence, the second processor 105 transmits the EIEOS sequence to the connected device and exits the electrical idle state.

[0149] S411: The second processor 105 sends out an EIE sequence and an FTS sequence in succession, which are converted into optical signals by the second optical transmitter and then transmitted to the first processor 103 in the first cable subassembly 101 to start link training and restore to a normal communication state.

[0150] Specifically, the low-frequency sequence for exiting the sleep state mentioned in steps 4.5 and 4.8 is usually a low-level or high-level signal with a low frequency (which can be considered as a Hz-level signal), which can be correctly transmitted and identified when the optical interconnect component is in the sleep state; further, the recovery time t0 required for the optoelectronic device to go from the off state to the normal working state is not a fixed value. Different types of optical and electrical devices have their own startup time t0, which is usually in the range of hundreds of milliseconds to seconds. This value can be written into the EEPROM (Electrically Erasable Programmable Read-Only Memory) inside the PCIeRetimer chip; further, the optoelectronic devices are divided into optical receiving end devices and optical transmitting end devices, each of which has its own startup time. The startup time t0 used for control here is the larger value of the startup time of the optical transmitting component and the optical receiving component.

[0151] Applying the above low-power PCIe optical interconnect cable assembly to the optical interconnect system can produce the following Figure 16 A PCIe optical interconnect system using a low power consumption control method and a cable assembly is shown. Figure 16 As shown, the system includes: a first server device 30, a second server device 31, and a PCIe optical interconnect cable assembly 10 for connecting the two server devices. A first cable subassembly 101 in the optical interconnect cable assembly 10 is connected to a transmitter 601 in the first server device 30 and can transmit PCIe protocol electrical signals. A second cable subassembly 102 in the optical interconnect cable assembly 10 is connected to a receiver 602 in the second server device 31 and can transmit PCIe protocol electrical signals. The first and second cable subassemblies 101, 102 are connected via optical fibers and transmit PCIe protocol optical signals.

[0152] Figure 16 When the system enters the link idle state, the transmitting end 601 in the first server device 30 sends the EIOS sequence to the PCIe optical interconnect cable assembly 10 through the electrical link, and then executes Figure 14 The control process of low- to medium-power PCIe optical interconnect cable assembly entering a low-power state, wherein the entire PCIe optical interconnect link and the corresponding ports of the link's transmitter 601 and receiver 602 enter a low-power mode; Figure 16 When the system exits the link idle state, the transmitting end 601 in the first server device 30 sends the EIEOS sequence to the PCIe optical interconnect cable assembly 10 through the first electrical link 302, and then executes Figure 15The control process for the medium and low power PCIe optical interconnect cable assembly to exit the low power state enables all chips and components of the entire interconnection link from the transmitting end 601 in the first server device 30 to the receiving end 602 in the second server device 31 to exit the low power mode and return to normal working state.

[0153] Figure 17 A schematic diagram of another PCIe optical interconnect system to which the low-power control method and cable assembly provided herein can be applied includes: a switch device 32, a first server device 30, a second server device 31, and two optical interconnect cable assemblies 10 for connecting the two server devices to the PCIe switch device. The cable subassemblies at both ends of the optical interconnect cable assembly 10 respectively connect the transmitting end 601 and the receiving end 602 in the server device to the switch 603 in the switch device 32, thereby transmitting PCIe protocol electrical signals. In other words, the transmitting end 601 and the receiving end 602 achieve interconnected communication through the switch 603 and the two optical interconnect cable assemblies 10.

[0154] Figure 17 In the system shown, the switch 603 is responsible for the forwarding function in the electrical idle state. When the sending end 601 is the root node, the port of the switch 603 connected to the optical interconnection cable assembly 10 is the receiving end of the switch 603, and the port of the optical interconnection cable assembly 10 connected to the receiving end 602 is the sending end of the switch 603. The two ports of the switch 603 can cooperate to independently complete the entry of the two optical interconnection cable assemblies 10 into low power consumption mode.

[0155] An embodiment of the present application further provides a server comprising any of the above-mentioned optical interconnection communication systems.

[0156] Figure 18 A flow chart of a method for controlling power consumption of an optical interconnection link provided in an embodiment of the present application is provided. The method is applied to the first processor of the first cable subassembly in the above-mentioned optical interconnection cable assembly, such as Figure 18 As shown, the method includes the following steps:

[0157] In step S701, it is identified whether the first electrical signal from the transmitting end carries an entry flag of the electrical idle state.

[0158] The entry identifier of the electrical idle state is the EIOS sequence, and the EIOS sequence is used to indicate that the link enters the electrical idle state.

[0159] It can be understood that the first processor of the embodiment of the present application first needs to identify whether there is an entry mark of the electrical idle state, that is, the EIOS sequence, in the first electrical signal sent by the sending end. If so, it confirms that the link is about to enter the low power consumption mode and prepares to execute the corresponding low power consumption control steps described below.

[0160] In step S702, if the first electrical signal carries an entry flag for the electrical idle state, the components in the first cable subassembly are controlled to enter a low power consumption mode according to a preset target entry sequence.

[0161] It can be understood that when the embodiment of the present application recognizes that the first electrical signal carries an identifier for entering the electrical idle state, it shuts down or reduces the working state of each component in sequence and in an orderly manner according to the target entry order, and controls each device in the first cable sub-assembly to enter the low power consumption mode, thereby ensuring that the entire link can enter the low power consumption mode smoothly and efficiently.

[0162] In an embodiment of the present application, the first processor interacts with the first optical transmitter of the first optical interconnect device through a first control signal, and the first processor interacts with the first optical receiver of the first optical interconnect device through a second control signal, and controls the devices in the first cable subassembly to enter a low power consumption mode according to a target entry sequence, including: controlling the first optical receiver to enter a low power consumption mode according to the second control signal; controlling the first optical transmitter to send a first optical signal carrying an entry identifier to the second cable subassembly according to the first control signal, wherein the devices in the second cable subassembly enter a low power consumption mode according to the target entry sequence; if the first electrical signal carrying the entry identifier is not identified, controlling the first optical transmitter to enter a low power consumption mode according to the first control signal, and after both the first optical receiver and the first optical transmitter enter the low power consumption mode, controlling the first processor to enter a low power consumption mode.

[0163] The first control signal and the second control signal are both electrical signals, and the first processor and the first optical transmitter and the first optical receiver of the first optical interconnect device communicate with each other through electrical signals.

[0164] It can be understood that in the process of controlling each device to enter the low power mode in the embodiment of the present application, if the first processor recognizes the first electrical signal carrying the entry identifier, the first optical receiver is caused to enter the low power mode through the second control signal; then, the first control signal is used to allow the first optical transmitter to send the first optical signal with the entry identifier (EIOS sequence) of the electrical idle state to the second cable sub-assembly, so that the devices in the second cable sub-assembly can receive the signal and enter the low power mode in the target order; if the first electrical signal carrying the entry identifier is not recognized, the first optical transmitter is directly controlled to enter the low power mode through the first control signal. Finally, after the first optical receiver and the first optical transmitter both enter the low power mode, the first processor is controlled to enter the low power mode, thereby ensuring that the corresponding components can enter the low power state in an orderly and efficient manner.

[0165] In the embodiment of the present application, the low power consumption mode of the first optical receiver is an off state, the low power consumption mode of the first optical transmitter is a sleep state, and the low power consumption mode of the first processor is an electrical idle state.

[0166] Among them, the off state is a state of complete power off or almost no power consumption, which can maximize energy saving. When the link enters the electrical idle state, it is no longer necessary to receive any data, so the low power mode of the first optical receiver can be the off state; the sleep state is a low-power standby state that allows the device to reduce energy consumption when not sending data while maintaining the ability to respond quickly. The first optical transmitter consumes less energy in this state while still being able to respond quickly and return to normal working state; the first processor stops processing and transmitting data in the electrical idle state and enters the energy-saving mode, but still maintains minimum functions so that it can detect the reactivation signal and quickly resume normal working state.

[0167] It can be understood that the first optical receiver of the embodiment of the present application will be completely shut down when entering the low-power mode to achieve maximum energy saving; the first optical transmitter will enter a sleep state, in which the transmitter can still quickly return to a normal working state, thereby reducing energy consumption when no data is sent; the first processor will enter an electrical idle state, stop data processing and transmission, but still retain basic functions to facilitate rapid resumption of operation, thereby ensuring that the system can maintain the ability to respond quickly and resume normal operation while ensuring efficient energy saving.

[0168] According to the optical interconnection link power consumption control method applied to the first processor of the first cable sub-assembly in the above-mentioned optical interconnection cable assembly provided in an embodiment of the present application, it is possible to control the first processor and the first optical interconnection device to enter a low power consumption mode through the first cable sub-assembly, and transmit a signal for entering the low power consumption mode to the second cable sub-assembly, thereby ensuring that each component enters the low power consumption mode in an orderly manner. At the same time, it is ensured that the system can maintain the ability to respond quickly and resume normal operation while ensuring high efficiency and energy saving, thereby achieving the technical effect of reducing the energy consumption of the entire optical interconnection link.

[0169] The description of the features in the embodiment corresponding to the optical interconnection link power consumption control method applied to the first processor of the first cable subassembly in the above-mentioned optical interconnection cable assembly can be found in the relevant description of the embodiment corresponding to the optical interconnection communication system, and will not be repeated here.

[0170] Figure 19 A flow chart of a method for controlling power consumption of an optical interconnection link provided in an embodiment of the present application is provided. The method is applied to the second processor of the second cable subassembly in the above-mentioned optical interconnection cable assembly, such as Figure 19 As shown, the method includes the following steps:

[0171] In step S801, a first electrical signal from a transmitting end is acquired.

[0172] The first electrical signal is obtained by restoring the received first optical signal to the first electrical signal through the second optical receiver of the second optical interconnection device.

[0173] It can be understood that the embodiment of the present application receives the first optical signal emitted by the first optical transmitter of the transmitting end through the second optical receiver in the second optical interconnect device, wherein the first optical signal is converted from the first electrical signal sent by the transmitting end, and the second optical receiver restores the first optical signal to the first electrical signal after receiving the first optical signal, so that the receiving end can correctly obtain and process the first electrical signal emitted by the transmitting end, ensuring that data can be transmitted efficiently and accurately between the transmitting end and the receiving end.

[0174] In step S802, it is identified whether the first electrical signal carries an entry flag of the electrical idle state.

[0175] It can be understood that after obtaining the first electrical signal, the second processor of the embodiment of the present application identifies whether there is an entry mark of the electrical idle state, that is, the EIOS sequence, in the first electrical signal. If so, it confirms that the link is about to enter the low power consumption mode and prepares to execute the corresponding low power consumption control steps described below.

[0176] In step S803, if the first electrical signal carries an entry flag for the electrical idle state, the components in the second cable subassembly are controlled to enter a low power consumption mode according to a preset target entry sequence.

[0177] It can be understood that when the embodiment of the present application recognizes that the first electrical signal carries an indication of entering an electrical idle state, it shuts down or reduces the working state of each component in an orderly manner according to the target entry order, and controls each device in the second cable sub-assembly to enter a low power consumption mode, thereby ensuring that the entire link can enter the low power consumption mode smoothly and efficiently.

[0178] In an embodiment of the present application, the second processor interacts with the second optical transmitter of the second optical interconnect device through a third control signal, and the second processor interacts with the second optical receiver of the second optical interconnect device through a fourth control signal, and controls the devices in the second cable subassembly to enter a low power mode according to a target entry sequence, including: responding to the fourth control signal, determining that the first optical transmitter of the first optical interconnect device enters a low power mode, and then controlling the second optical transmitter to enter a low power mode according to the third control signal; controlling the second optical receiver to enter a low power mode according to the fourth control signal; and controlling the second processor to enter a low power mode after both the second optical transmitter and the second optical receiver enter a low power mode.

[0179] The third control signal and the fourth control signal are both electrical signals, and the second processor and the second optical transmitter and the second optical receiver of the second optical interconnect device communicate with each other through electrical signals.

[0180] It can be understood that the second processor of the embodiment of the present application communicates with the second optical transmitter through the third control signal and communicates with the second optical receiver through the fourth control signal to achieve control of each device in the second cable sub-assembly to enter the low power mode according to a predetermined target entry sequence. Specifically, the second processor first confirms through the fourth control signal that the first optical transmitter of the first optical interconnect device has entered the low power mode, and then uses the third control signal to control the second optical transmitter to enter the low power mode. Subsequently, the fourth control signal is used to control the second optical receiver to enter the low power mode. When it is confirmed that the second optical transmitter and the second optical receiver have successfully entered the low power mode, the second processor finally enters the low power mode, thereby ensuring that the entire system can enter the low power state in an orderly and efficient manner.

[0181] In the embodiment of the present application, the low power consumption mode of the second optical receiver is a sleep state, the low power consumption mode of the second optical transmitter is an off state, and the low power consumption mode of the second processor is an electrical idle state.

[0182] It can be understood that the second optical receiver in the embodiment of the present application is in a dormant state in the low power consumption mode, which enables the second optical receiver to be in a low energy consumption state while maintaining the ability to quickly recover to a normal working state; the second optical transmitter is completely shut down in the low power consumption mode to achieve maximum energy saving effect; the second processor enters an electrical idle state in the low power consumption mode, suspending data processing and transmission, but still retaining basic functions to facilitate rapid recovery of the working state, thereby ensuring that the system has the ability to respond quickly and resume normal operation while achieving efficient energy saving.

[0183] According to the optical interconnection link power consumption control method applied to the second processor of the second cable subassembly in the above-mentioned optical interconnection cable assembly provided in an embodiment of the present application, it is possible to control the second processor and the second optical interconnection device to enter a low power consumption mode through the second cable subassembly, thereby ensuring that each component enters the low power consumption mode in an orderly manner. At the same time, it is ensured that the system can maintain the ability to respond quickly and resume normal operation while ensuring high efficiency and energy saving, thereby achieving the technical effect of reducing the energy consumption of the entire optical interconnection link.

[0184] The description of the features in the embodiment corresponding to the optical interconnection link power consumption control method of the second processor of the second cable subassembly in the above-mentioned optical interconnection cable assembly can be found in the relevant description of the embodiment corresponding to the optical interconnection communication system, and will not be repeated here.

[0185] Figure 20A flow chart of a method for controlling power consumption of an optical interconnection link provided in an embodiment of the present application is provided. The method is applied to the first processor of the first cable subassembly in the above-mentioned optical interconnection cable assembly, such as Figure 20 As shown, the method includes the following steps:

[0186] In step S901, it is identified whether the first electrical signal from the sending end carries an exit flag of the electrical idle state.

[0187] The exit identifier of the electrical idle state is the EIEOS sequence, and the EIEOS sequence is used to indicate that the link exits the electrical idle state.

[0188] It can be understood that the first processor of the embodiment of the present application first needs to identify whether there is an exit mark of the electrical idle state, that is, the EIEOS sequence, in the first electrical signal sent by the sending end. If so, it confirms that the link needs to exit the low power mode and prepares to execute the following corresponding exit low power control steps.

[0189] In step S902, if the first electrical signal carries an exit flag for the electrical idle state, the components in the first cable subassembly are controlled to exit the low power consumption mode according to a preset target exit sequence.

[0190] It can be understood that when the embodiment of the present application recognizes that the first electrical signal carries an identifier for exiting the electrical idle state, it wakes up the working state of each component in sequence and in an orderly manner according to the target exit order, and controls each device in the first cable sub-assembly to exit the low power mode, thereby ensuring that the entire link can exit the low power mode smoothly and efficiently.

[0191] In an embodiment of the present application, a first processor interacts with a first optical transmitter of a first optical interconnect device through a first control signal, and a first processor interacts with a first optical receiver of the first optical interconnect device through a second control signal, and controls the devices in the first cable subassembly to exit a low power mode according to a target exit sequence, including: controlling the first optical transmitter to exit the low power mode according to the first control signal; controlling the first optical transmitter to send a first optical signal carrying a first wake-up signal to the second cable subassembly according to the first control signal, wherein the devices in the second cable subassembly exit the low power mode according to the target exit sequence; responding to the received second wake-up signal, determining that the second optical receiver exits the low power mode, and then controlling the first optical receiver to exit the low power mode according to the second control signal; responding to the received second wake-up signal, determining that the second optical transmitter and the second optical receiver exit the low power mode, and then controlling the first processor to exit the low power mode; controlling the first optical transmitter to send a first optical signal carrying an exit identifier to the second cable subassembly according to the first control signal, wherein the second processor in the second cable subassembly exits the low power mode.

[0192] Among them, the first wake-up signal is a low-frequency sequence signal, which is emitted by the first optical transmitter and transmitted to the second cable sub-assembly through the optical fiber to notify the device in the second cable sub-assembly to start exiting the low-power mode; the second wake-up signal is also a low-frequency sequence signal, which is emitted by the first optical transmitter in the second cable sub-assembly and transmitted back to the first processor to confirm that the second optical receiver has exited the low-power mode; the low-frequency sequence signal is a low-level or high-level signal with a low frequency, which can be correctly transmitted and identified when the optical interconnect device is in low-power mode.

[0193] It can be understood that the first processor of the embodiment of the present application interacts with the first optical transmitter through the first control signal, and interacts with the first optical receiver through the second control signal, so as to control the devices in the first cable subassembly to exit the low power mode according to the target exit sequence. The specific steps are as follows: First, according to the first control signal, the first processor controls the first optical transmitter to exit the low power mode, and sends a first wake-up signal to the second cable subassembly, prompting the devices in the second cable subassembly to exit the low power mode according to the target exit sequence. After the devices in the second cable subassembly exit the low power mode according to the target exit sequence, the second wake-up signal will be sent to the second cable subassembly. When the second cable subassembly receives the first control signal, the first processor controls the first optical transmitter to exit the low power mode, and sends a first wake-up signal to the second cable subassembly. After receiving the second wake-up signal from the second cable subassembly and confirming that the second optical receiver has exited the low power mode, the first processor controls the first optical receiver to exit the low power mode according to the second control signal. Subsequently, after confirming that both the second optical transmitter and the second optical receiver have exited the low power mode, the first processor also exits the low power mode. Finally, the first processor controls the first optical transmitter to send a first optical signal carrying an exit identifier, i.e., an EIEOS sequence, to the second cable subassembly through the first control signal, ensuring that the second processor in the second cable subassembly also exits the low power mode. Through this process, it can be ensured that the entire system can exit the low power state in an orderly and efficient manner.

[0194] In the embodiment of the present application, the signal frequencies of the first wake-up signal and the second wake-up signal are lower than a preset frequency.

[0195] Among them, the preset frequency is a pre-set frequency threshold, which is usually a lower frequency value, such as the Hz level, to ensure that the first wake-up signal and the second wake-up signal can be correctly transmitted and identified when the optical interconnect device is in low power consumption mode. It is set according to actual needs and is not specifically limited here.

[0196] In an embodiment of the present application, before controlling the first processor to exit the low power mode, the method further includes: when controlling the first optical receiver to exit the low power mode according to the second control signal, recording the exit time, and if the actual time difference between the exit time and the current time is greater than a preset time difference, determining that the first optical receiver has returned to a normal state from the off state, and then controlling the first processor to exit the low power mode. The preset time difference is the maximum time required for the first transmitter and the first receiver to each start up.

[0197] It can be understood that before controlling the first processor to exit the low power mode, the embodiment of the present application needs to first use the second control signal to make the first optical receiver exit the low power mode and record the exit time. If the actual time from the exit time to the current time is greater than the preset time, that is, the maximum time required for the first optical transmitter and the first optical receiver to start up respectively, it can be confirmed that the first optical receiver has fully recovered to normal working state. Only then is the first processor allowed to exit the low power mode. In this way, it is ensured that the components have sufficient recovery time, thereby ensuring that the entire system can smoothly and reliably resume normal operation from low power mode.

[0198] In an embodiment of the present application, after controlling the devices in the first cable sub-assembly to exit the low power consumption mode according to the target exit sequence, it also includes: responding to the received second control signal, determining that the optical interconnection link enters the link training state; and performing link training on the optical interconnection link until the current state of the link is in the link preparation state.

[0199] The link training state refers to an intermediate step in the optical interconnect link's recovery from low-power mode to normal operating state. In this state, the devices at both ends of the link perform a series of tests and adjustments to ensure that the link can correctly and stably transmit data. The second control signal includes an EIE (Electrical Idle Exit Sequence) sequence and an FTS (Fast Training Sequence) sequence successively issued by the second processor. The first processor receives the second control signal and identifies these sequences, determining that the second processor has exited the electrical idle state and that the optical interconnect link has entered the link training state. The link preparation state refers to the final state after successful link training. In this state, the link is ready for normal communication and can begin transmitting data.

[0200] It can be understood that after the embodiment of the present application controls the devices in the first cable sub-assembly to exit the low power mode according to the target exit sequence, it responds to the received second control signal, identifies the EIE sequence and FTS sequence therein, and determines that the optical interconnection link has entered the link training state; then, link training is performed on the optical interconnection link to ensure that the devices at both ends of the link can transmit data correctly and stably, until the current state of the link reaches the link preparation state, indicating that the link training is successfully completed, the link is ready for normal communication and can start transmitting data. Through link training, the reliability and stability of data transmission are ensured after the system recovers from low power mode to normal working state.

[0201] According to the optical interconnection link power consumption control method provided in an embodiment of the present application and applied to the first processor of the first cable sub-assembly in the above-mentioned optical interconnection cable assembly, it is possible to control the first processor and the first optical interconnection device to exit the low power consumption mode through the first cable sub-assembly, and transmit a signal to exit the low power consumption mode to the second cable sub-assembly, thereby ensuring that the entire system exits the low power consumption mode in an orderly manner, and through link training, ensuring the reliability and stability of data transmission after the system recovers from the low power consumption mode to the normal working state.

[0202] The description of the features in the embodiment corresponding to the optical interconnection link power consumption control method applied to the first processor of the first cable subassembly in the above-mentioned optical interconnection cable assembly can be found in the relevant description of the embodiment corresponding to the optical interconnection communication system, and will not be repeated here.

[0203] Figure 21 A flow chart of a method for controlling power consumption of an optical interconnection link provided in an embodiment of the present application is provided. The method is applied to the second processor of the second cable subassembly in the above-mentioned optical interconnection cable assembly, such as Figure 21 As shown, the method includes the following steps:

[0204] In step S1001, a first electrical signal from a transmitting end is acquired.

[0205] It can be understood that the embodiment of the present application receives the first optical signal emitted by the first optical transmitter of the transmitting end through the second optical receiver in the second optical interconnect device, wherein the first optical signal is converted from the first electrical signal sent by the transmitting end, and the second optical receiver restores the first optical signal to the first electrical signal after receiving the first optical signal, so that the receiving end can correctly obtain and process the first electrical signal emitted by the transmitting end, ensuring that data can be transmitted efficiently and accurately between the transmitting end and the receiving end.

[0206] In step S1002, it is identified whether the first electrical signal from the sending end carries an exit flag of the electrical idle state.

[0207] It can be understood that after obtaining the first electrical signal, the second processor of the embodiment of the present application identifies whether there is an exit mark of the electrical idle state, that is, the EIEOS sequence, in the first electrical signal. If so, it confirms that the link is about to exit the low power mode and prepares to execute the following corresponding control steps for exiting the low power mode.

[0208] In step S1003, if the first electrical signal carries an exit flag for the electrical idle state, the components in the second cable subassembly are controlled to exit the low power consumption mode according to a preset target exit sequence.

[0209] It can be understood that when the embodiment of the present application recognizes that the first electrical signal carries an identifier for exiting the electrical idle state, it wakes up the working state of each component in sequence and in an orderly manner according to the target exit order, and controls each device in the second cable sub-assembly to exit the low power mode, thereby ensuring that the entire link can exit the low power mode smoothly and efficiently.

[0210] In an embodiment of the present application, the second processor interacts with the second optical transmitter through a third control signal, and the second processor interacts with the second optical receiver through a fourth control signal, and controls the devices in the second cable subassembly to exit the low power mode according to the target exit sequence, including: responding to the received first wake-up signal, determining that the first optical transmitter in the first cable subassembly exits the low power mode, and then controlling the second optical receiver to exit the low power mode according to the fourth control signal; responding to the received first wake-up signal, determining that the receiver in the first cable subassembly exits the low power mode, and then controlling the second optical transmitter to exit the low power mode according to the third control signal; controlling the second optical transmitter according to the third control signal to send a second wake-up signal to the first cable subassembly, wherein the first processor in the first cable subassembly exits the low power mode; responding to the received fourth control signal, determining the exit identifier carried by the first electrical signal, and exiting the low power mode after identifying the exit identifier.

[0211] It can be understood that the second processor of the embodiment of the present application interacts with the second optical transmitter and the second optical receiver through the third control signal and the fourth control signal respectively, and controls the devices in the second cable sub-assembly to exit the low power mode according to a predetermined target exit sequence. Specifically, when the second processor receives the first wake-up signal and confirms that the first optical transmitter in the first cable sub-assembly has exited the low power mode, the fourth control signal is used to make the second optical receiver exit the low power mode; then, after confirming that the first optical receiver in the first cable sub-assembly has also exited the low power mode, the third control signal is used to make the second optical transmitter exit the low power mode; then, the second optical transmitter sends a second wake-up signal to the first cable sub-assembly, prompting the first processor to exit the low power mode; finally, after receiving the fourth control signal and identifying the exit mark carried by the first electrical signal, namely the EIEOS sequence, the second processor also exits the low power mode, thereby achieving orderly recovery of the entire system to normal working state, ensuring that the system can efficiently resume normal operation from low power mode while ensuring data transmission continuity and stability.

[0212] In an embodiment of the present application, before controlling the second processor to exit the low power consumption mode, it also includes: when controlling the second optical emitter to exit the low power consumption mode according to the third control signal, recording the exit time, if the actual time length between the exit time and the current time is greater than the preset time length, it is determined that the second optical emitter has recovered from the off state to the normal state, and then controlling the second processor to exit the low power consumption mode.

[0213] It can be understood that, in the embodiment of the present application, before controlling the second processor to exit the low power mode, it is necessary to use a third control signal to make the second optical transmitter exit the low power mode and record the exit time. If the actual time from the exit time to the current time is greater than the preset time, that is, the maximum time required for the second optical transmitter and the second optical receiver to start up respectively, it can be confirmed that the second optical transmitter has fully recovered to the normal working state, and only then is the second processor allowed to exit the low power mode. This method ensures that the components have sufficient time to complete the transition from low power mode to normal working state, thereby avoiding data transmission errors or other problems caused by premature exit from low power mode, and ensuring the stability and reliability of the system.

[0214] According to the optical interconnection link power consumption control method applied to the second processor of the second cable sub-assembly in the above-mentioned optical interconnection cable assembly provided in an embodiment of the present application, it is possible to control the second processor and the second optical interconnection device to exit the low power consumption mode through the second cable sub-assembly, and transmit a signal to exit the low power consumption mode to the first cable sub-assembly, thereby ensuring that the entire system exits the low power consumption mode in an orderly manner, and through link training, ensuring the reliability and stability of data transmission after the system recovers from the low power consumption mode to the normal working state.

[0215] The description of the features in the embodiment corresponding to the optical interconnection link power consumption control method of the second processor of the second cable subassembly in the above-mentioned optical interconnection cable assembly can be found in the relevant description of the embodiment corresponding to the optical interconnection communication system, and will not be repeated here.

[0216] The embodiment of the present application also provides an electronic device, such as Figure 22 As shown, the electronic device includes a memory 1101 and a processor 1102. The memory 1101 stores a computer program, and the processor 1102 is configured to run the computer program to execute the steps in any of the above-mentioned optical interconnection link power consumption control method embodiments.

[0217] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned optical interconnection link power consumption control method embodiments when running.

[0218] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0219] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned optical interconnection link power consumption control method embodiments are implemented.

[0220] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned optical interconnection link power consumption control method embodiments are implemented.

[0221] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0222] The above is a detailed introduction to an optical interconnect cable assembly, communication system, server and link power consumption control method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. An optical interconnect cable assembly, characterized in that: include: a first cable subassembly and a second cable subassembly; The first cable subassembly includes a first processor and a first optical interconnect device, wherein the first processor and the first optical interconnect device allow entry into or exit from a low power consumption mode; the second cable subassembly includes a second processor and a second optical interconnect device, wherein the second processor and the second optical interconnect device allow entry into or exit from the low power consumption mode; The first optical interconnect device includes a first optical transmitter and a first optical receiver, the second optical interconnect device includes a second optical transmitter and a second optical receiver, the first processor is pre-set with a target control sequence, and the first processor, the first optical transmitter and the first optical receiver enter or exit the low power consumption mode according to the target control sequence, and the second processor is pre-set with a target control sequence, and the second processor, the second optical transmitter and the second optical receiver enter or exit the low power consumption mode according to the target control sequence.

2. The optical interconnect cable assembly according to claim 1, wherein: The target control sequence includes a target entry sequence and / or a target exit sequence, and the target entry sequence includes: controlling the first optical receiver, the second optical transmitter, the second optical receiver, the second processor, the first optical transmitter, and the first processor to enter the low power consumption mode in sequence; And / or, the target exit sequence includes: controlling the first optical transmitter, the second optical receiver, the first optical receiver, the second optical transmitter, the first processor and the second processor to exit the low power consumption mode in sequence.

3. An optical interconnection communication system, characterized in that: include: The optical interconnect cable assembly according to any one of claims 1 to 2; The transmitting end and the receiving end are arranged at both ends of the optical interconnection cable assembly.

4. An optical interconnection communication system, characterized in that: include: A plurality of optical interconnect cable assemblies according to any one of claims 1 to 2; at least one transmitting end and at least one receiving end, wherein the at least one transmitting end and the at least one receiving end are respectively connected to one end of different optical interconnect cable assemblies; A switch is connected to the other end of the different optical interconnection cable assemblies.

5. A server, characterized in that: Includes the optical interconnection communication system according to claim 3 or 4.

6. A method for controlling power consumption of an optical interconnection link, characterized in that: The method is applied to a first processor of a first cable subassembly in an optical interconnect cable assembly according to any one of claims 1 to 2, the method comprising: Identifying whether the first electrical signal from the transmitting end carries an entry flag for an electrical idle state; If the first electrical signal carries an entry flag for the electrical idle state, the components in the first cable subassembly are controlled to enter a low power consumption mode according to a preset target entry sequence.

7. The method for controlling power consumption of an optical interconnection link according to claim 6, wherein: The first processor interacts with the first optical transmitter of the first optical interconnect device through a first control signal, and the first processor interacts with the first optical receiver of the first optical interconnect device through a second control signal, and controlling the devices in the first cable subassembly to enter the low power consumption mode according to the target entry sequence includes: controlling the first optical receiver to enter a low power consumption mode according to the second control signal; controlling the first optical transmitter to transmit the first optical signal carrying the entry identifier to the second cable subassembly according to the first control signal, wherein the components in the second cable subassembly enter a low power consumption mode according to the target entry sequence; If the first electrical signal carrying the entry identifier is not recognized, the first optical transmitter is controlled to enter the low power consumption mode according to the first control signal, and after both the first optical receiver and the first optical transmitter enter the low power consumption mode, the first processor is controlled to enter the low power consumption mode.

8. The method for controlling power consumption of an optical interconnection link according to claim 7, wherein: The low power consumption mode of the first optical receiver is an off state, the low power consumption mode of the first optical transmitter is a sleep state, and the low power consumption mode of the first processor is an electrical idle state.

9. A method for controlling power consumption of an optical interconnection link, characterized in that: The method is applied to the second processor of the second cable subassembly in the optical interconnect cable assembly according to any one of claims 1 to 2, and the method comprises: Acquire a first electrical signal from a transmitting end; identifying whether the first electrical signal carries an entry flag for an electrical idle state; If the first electrical signal carries an entry flag for the electrical idle state, the components in the second cable subassembly are controlled to enter a low power consumption mode according to the preset target entry sequence.

10. The optical interconnection link power consumption control method according to claim 9, characterized in that: The second processor interacts with the second optical transmitter of the second optical interconnect device through a third control signal, and the second processor interacts with the second optical receiver of the second optical interconnect device through a fourth control signal. Controlling the devices in the second cable subassembly to enter the low power consumption mode according to the target entry sequence includes: In response to the fourth control signal, after determining that the first optical transmitter of the first optical interconnect device enters the low power consumption mode, controlling the second optical transmitter to enter the low power consumption mode according to the third control signal; controlling the second optical receiver to enter a low power consumption mode according to the fourth control signal; After both the second optical transmitter and the second optical receiver enter the low power consumption mode, the second processor is controlled to enter the low power consumption mode.

11. The optical interconnection link power consumption control method according to claim 10, characterized in that: The low power consumption mode of the second optical receiver is a sleep state, the low power consumption mode of the second optical transmitter is an off state, and the low power consumption mode of the second processor is an electrical idle state.

12. A method for controlling power consumption of an optical interconnection link, characterized in that: The method is applied to a first processor of a first cable subassembly in an optical interconnect cable assembly according to any one of claims 1 to 2, the method comprising: Identifying whether the first electrical signal from the transmitting end carries an exit flag for an electrical idle state; If the first electrical signal carries an exit flag for the electrical idle state, the components in the first cable subassembly are controlled to exit the low power consumption mode according to a preset target exit sequence.

13. The optical interconnection link power consumption control method according to claim 12, characterized in that: The first processor interacts with the first optical transmitter of the first optical interconnect device through a first control signal, and the first processor interacts with the first optical receiver of the first optical interconnect device through a second control signal. The controlling the devices in the first cable subassembly to exit the low power consumption mode according to the target exit sequence includes: controlling the first optical transmitter to exit the low power consumption mode according to the first control signal; controlling the first optical transmitter according to the first control signal to send a first optical signal carrying a first wake-up signal to the second cable subassembly, wherein the components in the second cable subassembly exit the low power consumption mode according to the target exit sequence; In response to the received second wake-up signal, after determining that the second optical receiver exits the low power consumption mode, controlling the first optical receiver to exit the low power consumption mode according to the second control signal; In response to the received second wake-up signal, after determining that the second optical transmitter and the second optical receiver have exited the low power consumption mode, controlling the first processor to exit the low power consumption mode; The first optical transmitter is controlled according to the first control signal to send a first optical signal carrying the exit identifier to the second cable subassembly, wherein the second processor in the second cable subassembly exits the low power consumption mode.

14. The method for controlling power consumption of an optical interconnection link according to claim 13, wherein: The signal frequencies of the first wake-up signal and the second wake-up signal are lower than a preset frequency.

15. The method for controlling power consumption of an optical interconnection link according to claim 13, wherein: After controlling the components in the first cable subassembly to exit the low power consumption mode according to the target exit sequence, the method further includes: In response to the received second control signal, determining that the optical interconnection link enters a link training state; Link training is performed on the optical interconnection link until the current state of the link is in a link preparation state.

16. A method for controlling power consumption of an optical interconnection link, characterized in that: The method is applied to the second processor in the optical interconnect cable assembly according to any one of claims 1 to 2, and the method comprises: Acquire a first electrical signal from a transmitting end; Identifying whether the first electrical signal from the transmitting end carries an exit flag for an electrical idle state; If the first electrical signal carries an exit flag for the electrical idle state, the components in the second cable subassembly are controlled to exit the low power consumption mode according to a preset target exit sequence.

17. The method for controlling power consumption of an optical interconnection link according to claim 16, wherein: The second processor interacts with the second optical transmitter via a third control signal, and the second processor interacts with the second optical receiver via a fourth control signal. The controlling the components in the second cable subassembly to exit the low power consumption mode according to the target exit sequence includes: In response to the received first wake-up signal, after determining that the first optical transmitter in the first cable subassembly exits the low power consumption mode, controlling the second optical receiver to exit the low power consumption mode according to the fourth control signal; In response to the received first wake-up signal, after determining that the receiver in the first cable subassembly exits the low power consumption mode, controlling the second optical transmitter to exit the low power consumption mode according to the third control signal; controlling the second optical transmitter according to the third control signal to send a second wake-up signal to the first cable subassembly, wherein the first processor in the first cable subassembly exits the low power consumption mode; In response to the received fourth control signal, an exit identifier carried by the first electrical signal is determined, and the low power consumption mode is exited after the exit identifier is identified.

18. An electronic device, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the optical interconnection link power consumption control method according to any one of claims 6 to 17 when executing the computer program.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the optical interconnection link power consumption control method according to any one of claims 6 to 17 are implemented.

20. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the optical interconnection link power consumption control method according to any one of claims 6 to 17 are implemented.

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