Communication system and method

Abstract

The embodiment of the invention discloses a communication system and a communication method, relates to the technical field of communication, and is used for improving the network interface specification of a WLAN (Wireless Local Area Network) communication system. The communication system comprises N SOCs, each SOC comprises a network port, an ETH, a communication interface and a memory, the N SOCs comprise a first SOC and a second SOC, and a first communication path exists between the communication interface of the first SOC and the communication interface of the second SOC. The ETH of the first SOC is used for sending the first network port data to the memory of the first SOC and sending the first network port data to the memory of the second SOC through the first communication path; the communication interface of the first SOC is used for receiving second network port data sent by the ETH of the second SOC through the first communication path and sending the second network port data to the memory of the first SOC; the EHT of the first SOC is also used for reading the first target data in the memory of the first SOC. The first network port data is data in a first message, the first message is a message received by a network port of the first SOC, and the first target data comprises the first network port data and / or second network port data.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communication technologies, and in particular, to a communication system and method. Background Art

[0002] A wireless local area network (WLAN) refers to a network system that interconnects computer devices using wireless communication technologies to enable mutual communication and resource sharing.

[0003] WLAN is currently widely used in home gateways and enterprise networks. The currently operating WLAN has reached a certain scale. In outdoor areas, WLAN can provide WLAN network services for mobile phones supporting the WLAN function or tablet computers supporting the WLAN.

[0004] With the rapid development of technology, the network transmission speed has also increased. Therefore, it is necessary to improve the network interface specifications of the WLAN communication system so that the network interfaces of the WLAN communication system can adapt to the increasingly high network transmission speed. Summary of the Invention

[0005] The embodiments of the present application provide a communication system and a communication method for improving the network interface specifications of a WLAN communication system. To achieve the above objective, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, the embodiments of the present application provide a communication system. The communication system includes: N system on chips (SOCs), where an SOC includes a network interface, an ethernet process system (ETH), a communication interface, and a memory. The N SOCs include a first SOC and a second SOC, and there is a first communication path between the communication interfaces of the first SOC and the second SOC. The ETH of the first SOC is configured to send first network interface data to the memory of the first SOC and send the first network interface data to the memory of the second SOC through the first communication path; the communication interface of the first SOC is configured to receive second network interface data sent by the ETH of the second SOC through the first communication path and send the second network interface data to the memory of the first SOC; the ETH of the first SOC is further configured to read first target data in the memory of the first SOC. Wherein, the first network interface data is the data in a first packet, the first packet is a packet received by the network interface of the first SOC, the second network interface data is the data in a second packet, the second packet is a packet received by the network interface of the second SOC, and the first target data includes the first network interface data and / or the second network interface data.

[0007] It can be seen that, on the one hand, compared with the ETH of the SOC in the WLAN communication system in the related art, which can only write the data of the network interface of this SOC into the memory of this SOC, the ETH of the SOC in the communication system provided by the embodiments of the present application can not only write the data of the network interface of this SOC into the memory of this SOC, but also write the data of the network interface of this SOC into the memory of other SOCs through the first communication path. On the other hand, compared with the ETH of the SOC in the WLAN communication system in the related art, which can only read the data of the network interface of this SOC from the memory of this SOC, the ETH of the SOC in the communication system provided by the embodiments of the present application can not only read the data of the network interface of this SOC from the memory of this SOC, but also read the data of the network interface of other SOCs from the memory of this SOC. Thus, one SOC in the WLAN communication system can read and write the data of N SOC network interfaces, thereby improving the network interface specification of the WLAN system.

[0008] In a possible implementation manner, the above SOC further includes a medium access control system (MAC), a physical layer system (PHY), and an airport process system (AIR).

[0009] In a possible implementation manner, the MAC of the first SOC is configured to read first target data in the memory of the first SOC and send the first target data to the PHY of the first SOC.

[0010] In a possible implementation manner, the PHY of the first SOC is configured to send the first target data to the AIR of the first SOC.

[0011] It can be seen that, compared with the air interface in the WLAN communication system in the related art, which can only send the data of the network interface of this SOC, the air interface of the SOC in the communication system provided by the embodiments of the present application can not only send the data of the network interface of this SOC, but also send the data of the network interface of other SOCs. Thus, one air interface can send the data entering from multiple network interfaces, thereby improving the air interface specification of the WLAN system.

[0012] In a possible implementation manner, the PHY of the first SOC is configured to send first air interface data to the MAC of the first SOC, where the first air interface data is the data in a third message, and the third message is the message received by the AIR of the first SOC.

[0013] In a possible implementation, the MAC of the first SOC is used to send the first radio interface data to the memory of the first SOC and send the first radio interface data to the memory of the second SOC through the first communication path.

[0014] In a possible implementation, the communication interface of the first SOC is further used to receive the second radio interface data sent by the MAC of the second SOC through the first communication path and send the second radio interface data to the memory of the first SOC. The second radio interface data is the data in the fourth message, and the fourth message is the message received by the AIR of the second SOC.

[0015] In a possible implementation, the MAC of the first SOC is further used to read the second target data in the memory of the first SOC, and the second target data includes the first radio interface data and / or the second radio interface data.

[0016] It can be seen that, on the one hand, compared with the MAC of the SOC in the WLAN communication system in the related art that can only write the radio interface data of its own SOC into the memory of its own SOC, the MAC of the SOC in the communication system provided by the embodiment of the present application can both write the radio interface data of its own SOC into the memory of its own SOC and write the radio interface data of its own SOC into the memory of other SOCs through the first communication path. On the other hand, compared with the MAC of the SOC in the WLAN communication system in the related art that can only read the radio interface data of its own SOC from the memory of its own SOC, the MAC of the SOC in the communication system provided by the embodiment of the present application can both read the radio interface data of its own SOC from the memory of its own SOC and read the radio interface data of other SOCs from the memory of its own SOC. Thus, one SOC in the WLAN communication system can read and write the radio interface data of N SOCs, thereby improving the radio interface specification of the WLAN system.

[0017] In a possible implementation, the ETH of the first SOC is further used to read the second target data in the memory of the first SOC and send the second target data to the network interface of the first SOC.

[0018] It can be seen that, compared with the network interface of the WLAN communication system in the related art that can only send the radio interface data of its own SOC, the network interface of the SOC in the communication system provided by the embodiment of the present application can both send the radio interface data of its own SOC and send the radio interface data of other SOCs. Thus, one network interface can send the data entering from multiple radio interfaces, thereby improving the network interface specification of the WLAN system.

[0019] In a possible implementation, the SOC further includes a processor.

[0020] In a possible implementation, the processor of the first SOC is configured to send first processor data to the processor of the second SOC via the first communication path.

[0021] In a possible implementation, the communication interface of the first SOC is further configured to receive second processor data sent by the processor of the second SOC via the first communication path, and send the second processor data to the processor of the first SOC.

[0022] In a possible implementation, the processor of the first SOC is configured to send a first processor message to the processor of the second SOC via the first communication path.

[0023] In a possible implementation, the communication interface of the first SOC is further configured to receive a second processor message sent by the processor of the second SOC via the first communication path, and send the second processor message to the processor of the first SOC.

[0024] Compared with the related art where communication between the processor of an SOC in a WLAN communication system and the processor of another SOC in the WLAN communication system needs to be through a network interface or an air interface, and the processors of multiple SOCs communicating through a network interface or an air interface will appear as multiple wireless access points (Access Point, AP) externally, in the embodiments of the present application, the processor of an SOC in the WLAN communication system and the processor of another SOC in the WLAN communication system can communicate through the first communication path without going through a network interface or an air interface, and the processors of multiple SOCs communicating through the first communication path will appear as one AP externally.

[0025] In a possible implementation, the processor of the first SOC is configured to send first processor data to the memory of the second SOC via the first communication path, and send a first message to the processor of the second SOC via the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0026] In a possible implementation, the communication interface of the first SOC is further configured to receive second processor data and a second message sent by the processor of the second SOC via the first communication path, send the second processor data to the memory of the first SOC, and send the second message to the processor of the first SOC, where the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0027] It can be seen that, compared with the processor of the SOC in the related art WLAN communication system that can only write data into the memory of the SOC itself, the processor of the SOC in the WLAN communication system provided by the embodiments of the present application can not only write data into the memory of the SOC itself, but also write data into the memory of other SOCs through the first communication path, thereby improving the processor data transmission specification of the WLAN system.

[0028] In a possible implementation manner, the above SOC further includes direct memory access (DMA).

[0029] In a possible implementation manner, the processor of the first SOC is configured to send first processor data to the memory of the first SOC, and send a third message to the DMA of the first SOC, where the third message is used to indicate sending the first processor data to the memory of the second SOC.

[0030] In a possible implementation manner, the DMA of the first SOC is configured to read the first processor data in the memory of the first SOC, and send the first processor data to the memory of the second SOC through the first communication path.

[0031] It can be seen that, compared with the DMA of the SOC in the related art WLAN communication system that can only write data into the memory of the SOC itself, the DMA of the SOC in the WLAN communication system provided by the embodiments of the present application can not only write data into the memory of the SOC itself, but also write data into the memory of other SOCs through the first communication path, thereby improving the DMA data transmission specification of the WLAN system.

[0032] In a possible implementation manner, the DMA of the first SOC is further configured to send a first message to the processor of the second SOC through the first communication path, where the first message is used to represent that the first processor data has been written into the memory of the second SOC.

[0033] In a possible implementation manner, the DMA of the first SOC is further configured to send a first message to the processor of the first SOC.

[0034] In a possible implementation manner, the DMA of the second SOC is further configured to send a second message to the processor of the first SOC through the first communication path, where the second message is used to represent that the second processor data has been written into the memory of the first SOC.

[0035] In a possible implementation manner, the DMA of the second SOC is further configured to send a second message to the processor of the second SOC.

[0036] In a possible implementation, the processor of the first SOC is further configured to send a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0037] In a possible implementation, the communication interface of the SOC is further configured to determine target information of the input source according to the priority of the input source of the SOC, where the input source includes ETH and / or DMA, and the target information includes at least one of a data input limit amount, a data input interval, a single data input limit amount, or a data input number limit amount.

[0038] It can be seen that there may be multiple data input sources in the communication interface of the WLAN communication system provided by the embodiments of the present application. Therefore, by setting priorities for multiple data input sources, the smoothness of high-priority traffic can be ensured when the transmission bandwidth of the communication interface is limited.

[0039] In a possible implementation, the communication system further includes M Baseband chips, where a Baseband chip includes a MAC, a PHY, an AIR, and a communication interface, the M Baseband chips include a first Baseband chip, and there is a second communication path between the communication interface of the first SOC and the communication interface of the first Baseband chip.

[0040] In a possible implementation, the MAC of the first Baseband chip is configured to read first target data in the memory of the first SOC through the second communication path and send the first target data to the PHY of the first Baseband chip.

[0041] In a possible implementation, the PHY of the first Baseband chip is configured to send the first target data to the AIR of the first Baseband chip.

[0042] It can be seen that, compared with the prior art where the air interface of the Baseband chip in the WLAN communication system can only send the network interface data of the SOC connected thereto, the air interface of the Baseband chip in the communication system provided by the embodiments of the present application can send both the network interface data of the SOC connected thereto and the network interface data of other SOCs. Thus, one air interface can send data entering from multiple network interfaces, thereby improving the air interface specification of the WLAN system.

[0043] Second aspect, an embodiment of the present application provides a communication method, which is applied to a communication system. The communication system includes N SOCs. Each SOC includes a network interface, ETH, a communication interface, and a memory. The N SOCs include a first SOC and a second SOC. There is a first communication path between the communication interface of the first SOC and the communication interface of the second SOC. The method includes: the ETH of the first SOC sends first network interface data to the memory of the first SOC, where the first network interface data is the data in a first message, and the first message is the message received by the network interface of the first SOC; the ETH of the first SOC sends the first network interface data to the memory of the second SOC through the first communication path; the communication interface of the first SOC receives second network interface data sent by the ETH of the second SOC through the first communication path, where the second network interface data is the data in a second message, and the second message is the message received by the network interface of the second SOC; the communication interface of the first SOC sends the second network interface data to the memory of the first SOC; the ETH of the first SOC reads first target data in the memory of the first SOC, where the first target data includes the first network interface data and / or the second network interface data.

[0044] In a possible implementation manner, each SOC further includes a MAC, a PHY, and an AIR.

[0045] In a possible implementation manner, the method further includes: the MAC of the first SOC reads the first target data in the memory of the first SOC; the MAC of the first SOC sends the first target data to the PHY of the first SOC; the PHY of the first SOC sends the first target data to the AIR of the first SOC.

[0046] In a possible implementation, the above method further includes: the PHY of the first SOC sends first air interface data to the MAC of the first SOC, where the first air interface data is the data in the third packet, and the third packet is the packet received by the AIR of the first SOC; the MAC of the first SOC sends the first air interface data to the memory of the first SOC; the MAC of the first SOC sends the first air interface data to the memory of the second SOC through the first communication path; the communication interface of the first SOC receives second air interface data sent by the MAC of the second SOC through the first communication path, where the second air interface data is the data in the fourth packet, and the fourth packet is the packet received by the AIR of the second SOC; the communication interface of the first SOC sends the second air interface data to the memory of the first SOC; the MAC of the first SOC reads second target data in the memory of the first SOC, and the second target data includes the first air interface data and / or the second air interface data.

[0047] In a possible implementation, the above method further includes: the memory of the first SOC sends the second target data to the ETH of the first SOC; the ETH of the first SOC sends the second target data to the network interface of the first SOC.

[0048] In a possible implementation, the above SOC further includes a processor.

[0049] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor data to the processor of the second SOC through the first communication path; the communication interface of the first SOC receives second processor data sent by the processor of the second SOC through the first communication path; the communication interface of the first SOC receives and sends the second processor data to the processor of the first SOC.

[0050] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor messages to the processor of the second SOC through the first communication path; the communication interface of the first SOC receives second processor messages sent by the processor of the second SOC through the first communication path; the communication interface of the first SOC receives and sends the second processor messages to the processor of the first SOC.

[0051] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor data to the memory of the second SOC through the first communication path; the processor of the first SOC sends a first message to the processor of the second SOC through the first communication path, and the first message is used to indicate that the first processor data has been written into the memory of the second SOC; the communication interface of the first SOC receives second processor data and a second message sent by the processor of the second SOC through the first communication path; the communication interface of the first SOC sends the second processor data to the memory of the first SOC; the communication interface of the first SOC sends the second message to the processor of the first SOC, and the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0052] In a possible implementation, the above SOC further includes a processor and a DMA.

[0053] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor data to the memory of the first SOC; the processor of the first SOC sends a third message to the DMA of the first SOC, and the third message is used to instruct to send the first processor data to the memory of the second SOC; the DMA of the first SOC reads the first processor data in the memory of the first SOC; the DMA of the first SOC sends the first processor data to the memory of the second SOC through the first communication path.

[0054] In a possible implementation, the above method further includes: the DMA of the first SOC sends a first message to the processor of the second SOC through the first communication path, and the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0055] In a possible implementation, the above method further includes: the DMA of the first SOC sends a first message to the processor of the first SOC.

[0056] In a possible implementation, the above method further includes: the DMA of the second SOC sends a second message to the processor of the first SOC through the first communication path, and the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0057] In a possible implementation, the above method further includes: the DMA of the second SOC sends a second message to the processor of the second SOC.

[0058] In a possible implementation, the above method further includes: the processor of the first SOC sends a first message to the processor of the second SOC through the first communication path, and the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0059] In a possible implementation, the above method further includes: the communication interface of the first SOC determines the target information of the input source according to the priority of the input source of the SOC, the input source includes ETH and / or DMA, and the target information includes at least one of a data input limit amount, a data input interval, a single data input limit amount, or a data input number limit amount.

[0060] In a possible implementation, the above communication system further includes a plurality of baseband chips, the baseband chips include MAC, PHY, AIR, and a communication interface, the plurality of baseband chips include a first baseband chip, and there is a second communication path between the communication interface of the first SOC and the communication interface of the first baseband chip.

[0061] In a possible implementation, the above method further includes: the MAC of the first baseband chip reads the first target data in the memory of the first SOC through the second communication path; the MAC of the first baseband chip sends the first target data to the PHY of the first baseband chip; the PHY of the first baseband chip sends the first target data to the AIR of the first baseband chip.

[0062] In a third aspect, an embodiment of the present application further provides a communication device, which includes: at least one processor, and when the at least one processor executes program code or instructions, the method described in the second aspect or any possible implementation manner thereof is implemented.

[0063] Optionally, the communication device may further include at least one memory, and the at least one memory is used to store the program code or instructions.

[0064] In a fourth aspect, an embodiment of the present application further provides a chip, which includes: an input interface, an output interface, and at least one processor. Optionally, the chip may further include a memory. The at least one processor is used to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method described in the second aspect or any possible implementation manner thereof.

[0065] Optionally, the above chip may also be an integrated circuit.

[0066] Fifth aspect, embodiments of the present application further provide a computer-readable storage medium for storing a computer program, where the computer program includes a method for implementing the method described in the second aspect or any possible implementation manner thereof above.

[0067] Sixth aspect, embodiments of the present application further provide a computer program product including instructions, which, when running on a computer, enable the computer to implement the method described in the second aspect or any possible implementation manner thereof above.

[0068] Seventh aspect, embodiments of the present application further provide a communication device, which includes the communication system described in the first aspect or any possible implementation manner thereof.

[0069] The communication system, computer storage medium, computer program product, and chip provided in this embodiment are all used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the communication system provided above, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0071] Figure 1 It is a schematic structural diagram of a communication system provided by an embodiment of the present application;

[0072] Figure 2 It is a schematic structural diagram of an SOC provided by an embodiment of the present application;

[0073] Figure 3 It is a schematic structural diagram of another SOC provided by an embodiment of the present application;

[0074] Figure 4 It is a schematic structural diagram of another communication system provided by an embodiment of the present application;

[0075] Figure 5 It is a schematic structural diagram of yet another SOC provided by an embodiment of the present application;

[0076] Figure 6 It is a schematic structural diagram of yet another SOC provided by an embodiment of the present application;

[0077] Figure 7 It is a schematic structural diagram of yet another communication system provided by an embodiment of the present application;

[0078] Figure 8Another schematic structural diagram of the SOC provided by the embodiment of the present application;

[0079] Figure 9 Another schematic structural diagram of the communication system provided by the embodiment of the present application;

[0080] Figure 10 Another schematic structural diagram of the SOC provided by the embodiment of the present application;

[0081] Figure 11 Another schematic structural diagram of the communication system provided by the embodiment of the present application;

[0082] Figure 12 Another schematic structural diagram of the SOC provided by the embodiment of the present application;

[0083] Figure 13 Another schematic structural diagram of the communication system provided by the embodiment of the present application;

[0084] Figure 14 A schematic structural diagram of a baseband chip provided by the embodiment of the present application;

[0085] Figure 15 Another schematic structural diagram of a baseband chip provided by the embodiment of the present application;

[0086] Figure 16 Another schematic structural diagram of the communication system provided by the embodiment of the present application;

[0087] Figure 17 Another schematic structural diagram of the SOC provided by the embodiment of the present application;

[0088] Figure 18 Another schematic structural diagram of the communication system provided by the embodiment of the present application;

[0089] Figure 19 Another schematic structural diagram of the communication system provided by the embodiment of the present application;

[0090] Figure 20 Another schematic structural diagram of the communication system provided by the embodiment of the present application. Detailed implementation manners

[0091] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the embodiments of the present application.

[0092] As used herein, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0093] In the description of the embodiments of the present application, terms such as "first" and "second" in the specification and drawings are used to distinguish different objects or different treatments of the same object, rather than to describe a specific order of the objects.

[0094] In addition, the terms "comprising" and "having" and any variations thereof mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include other unlisted steps or units, or may optionally further include other steps or units inherent to these processes, methods, products, or devices.

[0095] It should be noted that in the description of the embodiments of the present application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the embodiments of the present application should not be construed as being more preferred or more advantageous than other embodiments or design solutions. Rather, the use of words such as "exemplarily" or "for example" is intended to present relevant concepts in a specific manner.

[0096] WLAN refers to a network system that uses wireless communication technology to interconnect computer devices and enables mutual communication and resource sharing.

[0097] WLAN is currently widely used in home gateways and enterprise networks. The currently operating WLAN has reached a certain scale. In outdoor areas, WLAN can provide WLAN network services for mobile phones supporting the WLAN function or tablet computers supporting the WLAN.

[0098] With the rapid development of technology, the network transmission speed has also increased accordingly. Therefore, it is necessary to improve the network interface specifications of the WLAN communication system so that the network interface of the WLAN communication system can adapt to the increasingly high network transmission speed.

[0099] Therefore, the embodiments of the present application provide a communication system for improving the network interface specifications of the WLAN communication system.

[0100] Figure 1 A schematic diagram of a possible and non-limiting above-mentioned communication system is shown. As Figure 1 shown, the communication system 100 includes N SOCs 200.

[0101] Wherein, N is a positive integer greater than 1. For example, N can be 2, 3, 4, 5, 6, 7, 8, 9, 10 or other positive integers.

[0102] Exemplarily, the above communication system 100 can be a WLAN communication system.

[0103] Combined with Figure 1 , such as Figure 2 As shown, the above SOC 200 includes a network interface 201, ETH 202, a communication interface 203, and a memory 204.

[0104] Exemplarily, the above network interface 201 can be an optical fiber network interface, a registered jack 45 (RJ45), or other network interfaces.

[0105] Exemplarily, the above communication interface 203 can be a peripheral component interconnect express (PCIE), a universal serial bus (USB), a high definition multimedia interface (HDMI), a display port (DP), or other communication interfaces.

[0106] Exemplarily, the above memory 204 can be a double data rate synchronous dynamic random access memory (DDRC) (such as DDR3, DDR4, DDR5, etc.), a low power DDR (LPDDR) (such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, etc.), a graphics DDR (GDDR) (such as GDDR5, GDDR5X, or GDDR6), a synchronous dynamic random access memory (SDRAM), a high bandwidth memory (HBM), or other memories.

[0107] Combined with Figure 2 , such as Figure 3 As shown, in addition to being integrated inside the SOC 200, the memory 204 of the SOC 200 can also be provided outside the SOC 200 as an independent device.

[0108] Combined with Figure 1 , such as Figure 4As shown, the N SOCs 200 of the communication system 100 include a first SOC and a second SOC, and there is a first communication path between the communication interface of the first SOC and the communication interface of the second SOC.

[0109] In a possible implementation, the ETH of the first SOC is used to send first network interface data to the memory of the first SOC and send the first network interface data to the memory of the second SOC through the first communication path.

[0110] Wherein, the first network interface data is the data in the first packet, and the first packet is the packet received by the network interface of the first SOC.

[0111] Exemplarily, as Figure 4 shown, the ETH of the first SOC can determine whether the first packet belongs to the local air interface or the air interface of other chips according to the packet information in the first packet. When the first packet belongs to the local air interface, the ETH of the first SOC can send the first network interface data to the memory of the first SOC through path 1-2.

[0112] Another exemplarily, as Figure 4 shown, the ETH of the first SOC can determine whether the first packet belongs to the local air interface or the air interface of other chips according to the packet information in the first packet. When the first packet belongs to the air interface of other chips, the ETH of the first SOC can send the first network interface data to the memory of the second SOC through path 1-3, the first communication path and path 2-4.

[0113] In a possible implementation, the packet information includes other information such as MAC address, Internet Protocol (IP) address, port, or control and provisioning of wireless access points protocol specification (CAPWAP) header.

[0114] In a possible implementation, the communication interface of the first SOC is used to receive the second network interface data sent by the ETH of the second SOC through the first communication path and send the second network interface data to the memory of the first SOC.

[0115] Wherein, the second network interface data is the data in the second packet, and the second packet is the packet received by the network interface of the second SOC.

[0116] Exemplarily, as Figure 4As shown, the ETH of the second SOC can send the second network interface data to the memory of the second SOC through path 2-2.

[0117] Exemplarily, as Figure 4 shown, the ETH of the second SOC can send the second network interface data to the memory of the first SOC through path 2-3, the first communication path, and path 1-4.

[0118] In a possible implementation, the ETH of the first SOC is further used to read first target data in the memory of the first SOC.

[0119] Wherein, the first target data includes the first network interface data and / or the second network interface data.

[0120] Exemplarily, as Figure 4 shown, the ETH of the first SOC can read the first target data in the memory of the first SOC through path 1-2.

[0121] In a possible implementation, the ETH of the second SOC is used to read first target data in the memory of the second SOC.

[0122] Exemplarily, as Figure 4 shown, the ETH of the second SOC can read the first target data in the memory of the second SOC through path 2-2.

[0123] It can be seen that, on the one hand, compared with the ETH of the SOC in the related WLAN communication system that can only write the data of its own SOC network interface into the memory of its own SOC, the ETH of the SOC in the communication system provided by the embodiments of the present application can not only write the data of its own SOC network interface into the memory of its own SOC, but also write the data of its own SOC network interface into the memory of other SOCs through the first communication path. On the other hand, compared with the ETH of the SOC in the related WLAN communication system that can only read the data of its own SOC network interface from the memory of its own SOC, the ETH of the SOC in the communication system provided by the embodiments of the present application can not only read the data of its own SOC network interface from the memory of its own SOC, but also read the data of other SOC network interfaces from the memory of its own SOC. Thus, one SOC in the WLAN communication system can read and write the data of N SOC network interfaces, thereby improving the network interface specification of the WLAN system.

[0124] Combined with Figure 2 as Figure 5 shown, the above SOC 200 may further include MAC 205, PHY206, and AIR 207.

[0125] Combined with Figure 5 as Figure 6As shown, in addition to being integrated inside the SOC 200, the AIR 207 of the SOC 200 can also be provided as an independent device outside the SOC 200.

[0126] In one possible implementation, the MAC of the first SOC is used to read the above-mentioned first target data in the memory of the first SOC.

[0127] Exemplarily, as Figure 7 shown, the MAC of the first SOC can read the first target data in the memory of the first SOC through path 1-5.

[0128] In one possible implementation, the MAC of the second SOC is used to read the above-mentioned first target data in the memory of the second SOC.

[0129] Exemplarily, as Figure 7 shown, the MAC of the second SOC can read the first target data in the memory of the second SOC through path 2-5.

[0130] In one possible implementation, the MAC of the above-mentioned first SOC is used to send the above-mentioned first target data to the PHY of the above-mentioned first SOC.

[0131] Exemplarily, as Figure 7 shown, the MAC of the first SOC can send the above-mentioned first target data to the PHY of the above-mentioned first SOC through path 1-6.

[0132] In one possible implementation, the MAC of the above-mentioned second SOC is used to send the above-mentioned first target data to the PHY of the above-mentioned second SOC.

[0133] Exemplarily, as Figure 7 shown, the MAC of the second SOC can send the above-mentioned first target data to the PHY of the above-mentioned second SOC through path 2-6.

[0134] In one possible implementation, the PHY of the above-mentioned first SOC is used to send the above-mentioned first target data to the AIR of the above-mentioned first SOC.

[0135] Exemplarily, as Figure 7 shown, the PHY of the first SOC can send the above-mentioned first target data to the AIR of the above-mentioned first SOC through path 1-7.

[0136] In one possible implementation, the PHY of the above-mentioned second SOC is used to send the above-mentioned first target data to the AIR of the above-mentioned second SOC.

[0137] Exemplarily, as Figure 7As shown, the PHY of the second SOC can send the above-mentioned first target data to the AIR of the above-mentioned second SOC through path 2-7.

[0138] It can be seen that compared with the fact that the air interface of the WLAN communication system in the related art can only send the data of the network interface of this SOC, the air interface of the SOC in the communication system provided by the embodiments of the present application can send both the data of the network interface of this SOC and the data of the network interfaces of other SOCs. Thus, one air interface can send the data entering from multiple network interfaces, thereby improving the specification of the air interface of the WLAN system.

[0139] In a possible implementation manner, the PHY of the above-mentioned first SOC is used to send first air interface data to the MAC of the above-mentioned first SOC.

[0140] Wherein, the above-mentioned first air interface data is the data in the third message, and the third message is the message received by the AIR of the above-mentioned first SOC.

[0141] Exemplarily, as Figure 7 shown, the PHY of the first SOC can send the first air interface data to the MAC of the above-mentioned first SOC through path 1-6.

[0142] In a possible implementation manner, the PHY of the above-mentioned second SOC is used to send second air interface data to the MAC of the above-mentioned second SOC.

[0143] Wherein, the above-mentioned second air interface data is the data in the fourth message, and the fourth message is the message received by the AIR of the above-mentioned second SOC. [[ID=2I]]

[0144] Exemplarily, as Figure 7 shown, the PHY of the second SOC can send the second air interface data to the MAC of the above-mentioned second SOC through path 2-6.

[0145] In a possible implementation manner, the MAC of the above-mentioned first SOC is used to send the above-mentioned first air interface data to the memory of the above-mentioned first SOC and send the above-mentioned first air interface data to the memory of the above-mentioned second SOC through the above-mentioned first communication path. <>

[0146] Exemplarily, as Figure 7 shown, the MAC of the first SOC can determine whether the first air interface data is sent through this network interface or through the network interfaces of other chips through message information or task descriptors. In the case where the first air interface data is sent through this network interface, the MAC of the first SOC can send the above-mentioned first air interface data to the memory of the above-mentioned first SOC through path 1-5.

[0147] Another exemplarily, as Figure 7As shown, the MAC of the first SOC can determine whether the first radio access data is sent through this network interface or through the network interfaces of other chips based on the packet information or the task descriptor. In the case where the first radio access data is sent through the network interfaces of other chips, the MAC of the first SOC can send the first radio access data to the memory of the second SOC through Path 1-8, the first communication path, and Path 2-4.

[0148] The above task descriptor can be obtained in any way that those skilled in the art can think of, and the embodiments of the present application do not limit this. For example, the processor can first send a task descriptor to the hardware. The descriptor contains the packet address and some other information. The hardware knows how to send the subsequent data, whether to read the packet content locally or across chips, by identifying this information.

[0149] In a possible implementation, the communication interface of the first SOC is further configured to receive the second radio access data sent by the MAC of the second SOC through the first communication path, and send the second radio access data to the memory of the first SOC.

[0150] Among them, the second radio access data is the data in the fourth packet, and the fourth packet is the packet received by the AIR of the second SOC.

[0151] Exemplarily, as Figure 7 shown, the MAC of the second SOC can send the second radio access data to the memory of the second SOC through Path 2-5.

[0152] Another example, as Figure 7 shown, the MAC of the second SOC can send the second radio access data to the memory of the first SOC through Path 2-8, the first communication path, and Path 1-4.

[0153] In a possible implementation, the MAC of the first SOC is further configured to read the second target data in the memory of the first SOC, where the second target data includes the first radio access data and / or the second radio access data.

[0154] Exemplarily, as Figure 7 shown, the MAC of the first SOC can read the second target data in the memory of the first SOC through Path 1-5.

[0155] In a possible implementation, the MAC of the second SOC is configured to read the second target data in the memory of the second SOC.

[0156] Exemplarily, as Figure 7 shown, the MAC of the second SOC can read the second target data in the memory of the second SOC through Path 2-5.

[0157] It can be seen that, on the one hand, compared with the MAC of the SOC in the WLAN communication system in the related art that can only write the data of the air interface of this SOC into the memory of this SOC, the MAC of the SOC in the communication system provided by the embodiments of the present application can not only write the data of the air interface of this SOC into the memory of this SOC, but also write the data of the air interface of this SOC into the memory of other SOCs through the first communication path. On the other hand, compared with the MAC of the SOC in the WLAN communication system in the related art that can only read the data of the air interface of this SOC from the memory of this SOC, the MAC of the SOC in the communication system provided by the embodiments of the present application can not only read the data of the air interface of this SOC from the memory of this SOC, but also read the data of the air interface of other SOCs from the memory of this SOC. Thus, one SOC in the WLAN communication system can read and write the data of the air interfaces of N SOCs, thereby improving the air interface specification of the WLAN system.

[0158] In a possible implementation manner, the ETH of the first SOC is further configured to read second target data in the memory of the first SOC.

[0159] Exemplarily, as Figure 7 shown, the ETH of the first SOC can read the second target data in the memory of the first SOC through path 1-2.

[0160] In a possible implementation manner, the ETH of the second SOC is further configured to read second target data in the memory of the second SOC.

[0161] Exemplarily, as Figure 7 shown, the ETH of the second SOC can read the second target data in the memory of the second SOC through path 2-2.

[0162] In a possible implementation manner, the ETH of the first SOC is further configured to send the second target data to the network interface of the first SOC.

[0163] Exemplarily, as Figure 7 shown, the ETH of the first SOC can send the second target data to the network interface of the first SOC through path 1-1.

[0164] In a possible implementation manner, the ETH of the second SOC is further configured to send the second target data to the network interface of the second SOC.

[0165] Exemplarily, as Figure 7 shown, the ETH of the second SOC can send the second target data to the network interface of the second SOC through path 2-1.

[0166] It can be seen that, compared with the network interface of the WLAN communication system in the related art, which can only send the data of the air interface of this SOC, the network interface of the SOC in the communication system provided by the embodiments of the present application can not only send the data of the air interface of this SOC, but also send the data of the air interface of other SOCs. Thus, a network interface can send the data entering from multiple air interfaces, thereby improving the network interface specification of the WLAN system.

[0167] Combined with Figure 2 , such as Figure 8 shown, the SOC may further include a processor 208.

[0168] Exemplarily, the above-mentioned processor may be a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a video codec, a digital signal processor (DSP), a baseband processor, a neural-network processing unit (NPU), or other processors.

[0169] In a possible implementation manner, the processor of the first SOC is used to send first processor data to the processor of the second SOC through the first communication path.

[0170] Exemplarily, as Figure 9 shown, the processor of the first SOC can send the first processor data to the processor of the second SOC through path 1-9, the first communication path, and path 2-9.

[0171] In a possible implementation manner, the communication interface of the first SOC is further used to receive the second processor data sent by the processor of the second SOC through the first communication path, and send the second processor data to the processor of the first SOC.

[0172] Exemplarily, as Figure 9 shown, the processor of the second SOC can send the first processor data to the processor of the first SOC through path 2-9, the first communication path, and path 1-9.

[0173] Compared with the related art in which communication between the processor of the SOC in the WLAN communication system and the processors of other SOCs in the WLAN communication system needs to be through a network port or an air port, and the processors of multiple SOCs communicating through the network port or the air port will appear to the outside as multiple APs, the processor of the SOC in the WLAN communication system provided in the embodiment of the present application can communicate with the processors of other SOCs in the WLAN communication system through a first communication path, without going through a network port or an air port, and the processors of multiple SOCs communicating through the first communication path will appear to the outside as one AP.

[0174] In a possible implementation, the processor of the first SOC is configured to send a first processor message to the memory of the second SOC through the first communication path.

[0175] For example, Figure 9 As shown, the processor of the first SOC can send a first processor message to the processor of the second SOC through the path 1-9, the first communication path and the path 2-9.

[0176] In a possible implementation, the communication interface of the first SOC is further configured to receive a second processor message sent by the processor of the second SOC through the first communication path, and to send the second processor message to the processor of the first SOC.

[0177] For example, Figure 9 As shown, the processor of the second SOC can send a first processor message to the processor of the first SOC through the path 2-9, the first communication path and the path 1-9.

[0178] In a possible implementation, the processor of the first SOC is configured to send first processor data to the memory of the second SOC through the first communication path, and to send a first message to the processor of the second SOC through the first communication path.

[0179] The first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0180] For example, Figure 9 As shown, the processor of the first SOC can send the first processor data to the memory of the second SOC through the path 1-9, the first communication path and the path 2-4, and send the first message to the processor of the second SOC through the path 1-9, the first communication path and the path 2-9.

[0181] In a possible implementation, the communication interface of the first SOC is further configured to receive the second processor data and the second message sent by the processor of the second SOC through the first communication path, send the second processor data to the memory of the first SOC, and send the second message to the processor of the first SOC.

[0182] Wherein, the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0183] Exemplarily, as Figure 9 shown, the processor of the second SOC can send the second processor data to the memory of the first SOC through path 2-9, the first communication path, and path 1-4, and send the first message to the processor of the first SOC through path 2-9, the first communication path, and path 1-9.

[0184] It can be seen that compared with the related art where the processor of the SOC in the WLAN communication system can only write data into the memory of its own SOC, the processor of the SOC in the WLAN communication system provided by the embodiments of the present application can not only write data into the memory of its own SOC, but also write data into the memory of other SOCs through the first communication path, thereby improving the processor data transmission specification of the WLAN system.

[0185] Combined with Figure 8 , as Figure 10 shown, the SOC may further include DMA209.

[0186] In a possible implementation, the processor of the first SOC is configured to send the first processor data to the memory of the first SOC, and send a third message to the DMA of the first SOC.

[0187] Wherein, the third message is used to instruct to send the first processor data to the memory of the second SOC.

[0188] Exemplarily, as Figure 11 shown, the processor of the first SOC can send the first processor data to the memory of the first SOC through path 1-10, and add a task (addjob) to send the third message to the DMA of the first SOC through path 1-11

[0189] In a possible implementation, the third message may include a source address, a destination address, a length, a message content, or other information.

[0190] In a possible implementation, the processor of the second SOC is configured to send the second processor data to the memory of the second SOC, and send a fourth message to the DMA of the second SOC.

[0191] Among them, the above fourth message is used to indicate sending the above second processor data to the memory of the first SOC.

[0192] Exemplarily, as Figure 11 shown, the processor of the second SOC can send the second processor data to the memory of the second SOC through path 2-10, and send the fourth message to the DMA of the second SOC through path 2-11.

[0193] In a possible implementation manner, the above fourth message may include a source address, a destination address, a length, a message content, or other information.

[0194] In a possible implementation manner, the DMA of the above first SOC is used to read the first processor data in the memory of the first SOC.

[0195] Exemplarily, as Figure 11 shown, the DMA of the first SOC can read the first processor data in the memory of the first SOC through path 1-12.

[0196] In a possible implementation manner, the DMA of the above second SOC is used to read the second processor data in the memory of the second SOC.

[0197] Exemplarily, as Figure 11 shown, the DMA of the second SOC can read the second processor data in the memory of the second SOC through path 2-12.

[0198] In a possible implementation manner, the DMA of the above first SOC is used to send the above first processor data to the memory of the second SOC through the above first communication path.

[0199] Exemplarily, as Figure 11 shown, the DMA of the first SOC can send the above first processor data to the memory of the second SOC through path 1-13, the first communication path, and path 2-4.

[0200] In a possible implementation manner, the DMA of the above second SOC is used to send the above second processor data to the memory of the first SOC through the above first communication path.

[0201] Exemplarily, as Figure 11 shown, the DMA of the second SOC can send the above second processor data to the memory of the first SOC through path 2-13, the first communication path, and path 1-4.

[0202] In a possible implementation, the DMA of the first SOC is further configured to send a first message to the processor of the first SOC.

[0203] Exemplarily, as Figure 11 shown, the DMA of the first SOC can send the first message to the processor of the first SOC through path 1-11.

[0204] In a possible implementation, the DMA of the first SOC is further configured to send a first message to the processor of the second SOC through a first communication path.

[0205] Exemplarily, as Figure 11 shown, the DMA of the first SOC can send the first message to the processor of the second SOC through path 1-13, the first communication path, and path 2-9.

[0206] Wherein, the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0207] In a possible implementation, the DMA of the second SOC is further configured to send a second message to the processor of the second SOC.

[0208] Exemplarily, as Figure 11 shown, the DMA of the second SOC can send the second message to the processor of the second SOC through path 2-11.

[0209] In a possible implementation, the DMA of the second SOC is further configured to send a second message to the processor of the first SOC through a first communication path.

[0210] Exemplarily, as Figure 11 shown, the DMA of the second SOC can send the second message to the processor of the first SOC through path 2-13, the first communication path, and path 1-9.

[0211] Wherein, the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0212] In a possible implementation, the DMA or the processor of the SOC is further configured to apply for a cache (reqbuffer).

[0213] Exemplarily, the DMA or the processor of the first SOC can apply for a cache from the cache management unit (buffer manage) in the memory of the second SOC.

[0214] Another exemplarily, the DMA or the processor of the second SOC can apply for a cache from the cache management unit in the memory of the first SOC.

[0215] In a possible implementation, the DMA or processor of the SOC is also used to release the cache.

[0216] Exemplarily, the DMA or processor of the first SOC may release the first processor cached in the memory of the first SOC when the above-mentioned first processor data has been written into the memory of the second SOC.

[0217] Exemplarily again, the DMA or processor of the second SOC may release the second processor cached in the memory of the second SOC when the above-mentioned second processor data has been written into the memory of the first SOC.

[0218] In a possible implementation, the DMA or processor of the SOC is also used to ensure the order of data reading and writing and / or the order of data messages.

[0219] Exemplarily, the DMA or processor of the SOC may ensure the order of reading and writing of the first network port data, the second network port data, the first air interface data, the second air interface data, the first processor data, or the second processor data.

[0220] Combined Figure 2 , as Figure 12 shown, the SOC 200 may include a network port 201, an ETH 202, a communication interface 203, a memory 204, a MAC 205, a PHY 206, an AIR 207, a processor 208, and a DMA 209.

[0221] In a possible implementation, the communication interface of the above SOC is also used to determine the target information of the input source according to the priority of the input source of the SOC.

[0222] Wherein, the input source includes ETH and / or DMA, and the target information includes at least one of a data input limit amount, a data input interval, a single data input limit amount, or a data input number limit amount.

[0223] The data input limit amount is the maximum data input amount within a preset time. For example, the maximum data input amount per second.

[0224] Exemplarily, the transmission capacity of the communication interface of the SOC is 12 gigabits per second (Gbps). The communication interface of the SOC has two input sources, ETH and DMA. ETH has a high priority, and the traffic of ETH is 10 Gbps. DMA has a low priority, and the traffic of DMA is 10 Gbps. Since the sum of the two is greater than the transmission capacity of the communication interface, which is 12 Gbps, the traffic of the low-priority DMA can be controlled to 2 Gbps so that the sum of the two is less than or equal to the transmission capacity of the communication interface, which is 12 Gbps.

[0225] Exemplarily, the communication interface of the SOC can determine the data input interval of the input source according to the priority of the input source. For example, the minimum interval time between two data inputs of each input source can be set to 0.4 microseconds (us).

[0226] Exemplarily, the communication interface of the SOC can determine the single - data input limit amount and the data input number limit amount of the input source according to the priority of the input source. For example, the number of data packets sent simultaneously can be set to 2, that is, at most 2 data packets can be sent simultaneously. After the response RESP1 corresponding to data packet 1 returns, data packet 3 can be sent. The maximum amount of data carried by each data packet is 64 bytes (Byte).

[0227] Combined with Figure 1 , as Figure 13 shown, the communication system 100 may further include M baseband chips 300.

[0228] Wherein, M is a positive integer greater than 0. For example, M can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or other positive integers.

[0229] In a possible implementation, M may be equal to N.

[0230] Combined with Figure 13 , as Figure 14 shown, the above - mentioned baseband chip 300 includes a MAC 301, a PHY 302, an AIR 303 and a communication interface 304.

[0231] Combined with Figure 14 , as Figure 15 shown, in addition to being integrated inside the baseband chip 300, the AIR 303 of the baseband chip 300 can also be set outside the baseband chip 300 as an independent device.

[0232] Combined with Figure 1 and Figure 13 , as Figure 16 shown, the M baseband chips 300 of the communication system 100 include a first baseband chip. There is a second communication path between the communication interface of the first SOC and the communication interface of the first baseband chip.

[0233] In a possible implementation, the MAC of the first baseband chip is used to read the first target data in the memory of the first SOC through the above - mentioned second communication path.

[0234] Exemplarily, as Figure 16 shown, the MAC of the first baseband chip can read the first target data in the memory of the first SOC through path 1 - 4 and the second communication path.

[0235] In a possible implementation, the MAC of the first baseband chip is used to send the first target data to the PHY of the first baseband chip.

[0236] Exemplarily, as Figure 16 shown, the MAC of the first baseband chip can send the first target data to the PHY of the first baseband chip through path 3-2.

[0237] In a possible implementation, the PHY of the first baseband chip is used to send the first target data to the AIR of the first baseband chip.

[0238] Exemplarily, as Figure 16 shown, the PHY of the first baseband chip can send the first target data to the AIR of the first baseband chip through path 3-3.

[0239] It can be seen that, compared with the prior art where the air interface of the baseband chip in the WLAN communication system can only send the network interface data of the SOC connected thereto, the air interface of the baseband chip in the communication system provided by the embodiments of the present application can not only send the network interface data of the SOC connected thereto, but also send the network interface data of other SOCs. Thus, one air interface can send the data entering from multiple network interfaces, thereby improving the air interface specification of the WLAN system.

[0240] Combined with Figure 2 , as Figure 17 shown, the communication interface 203 may include K communication sub-interfaces. Different communication sub-interfaces of the SOC can be connected to different devices.

[0241] Wherein, K is a positive integer greater than 0. For example, K may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or other positive integers.

[0242] Exemplarily, as Figure 18 shown, there is a first communication path between the communication sub-interface 1 of the first SOC and the communication sub-interface 1 of the second SOC. There is a second communication path between the communication sub-interface K of the first SOC and the communication interface of the first baseband chip.

[0243] It should be noted that the above embodiments are described by taking one second SOC included in N SOCs as an example, but do not limit that only one second SOC can be included in N SOCs. Multiple second SOCs may also be included in N SOCs. For example, 1, 2, 3, 4, 5, 6, ……, N-3, N-2, N-1 second SOCs may be included in N SOCs. Correspondingly, there may be a first communication path between the communication interface of the first SOC and the communication interfaces of 1, 2, 3, 4, 5, 6, ……, N-3, N-2, N-1 second SOCs.

[0244] Exemplarily, as Figure 19 shown, there is a first communication path between the communication sub-interface 1 of the first SOC and the communication sub-interface 1 of the second SOC 1, and there is a first communication path between the communication sub-interface 2 of the first SOC and the communication sub-interface 2 of the second SOC 2.

[0245] It should be noted that in the case where the N SOCs include multiple second SOCs, there may also be a first communication path between the communication interfaces of the multiple SOCs.

[0246] As Figure 20 shown, there is a first communication path between the communication sub-interface 2 of the second SOC 1 and the communication sub-interface 1 of the second SOC 2.

[0247] An embodiment of the present application provides a communication method applied to the above communication system. The method includes:

[0248] S401. The ETH of the first SOC sends first network interface data to the memory of the first SOC,

[0249] wherein, the first network interface data is the data in the first packet, and the first packet is the packet received by the network interface of the first SOC.

[0250] S402. The ETH of the first SOC sends the first network interface data to the memory of the second SOC through the first communication path.

[0251] S403. The communication interface of the first SOC receives the second network interface data sent by the ETH of the second SOC through the first communication path.

[0252] wherein, the second network interface data is the data in the second packet, and the second packet is the packet received by the network interface of the second SOC.

[0253] S404. The communication interface of the first SOC sends the second network interface data to the memory of the first SOC.

[0254] S405. The ETH of the first SOC reads the first target data in the memory of the first SOC.

[0255] wherein, the first target data includes the first network interface data and / or the second network interface data.

[0256] In a possible implementation manner, the method further includes: the MAC of the first SOC reads the first target data in the memory of the first SOC; the MAC of the first SOC sends the first target data to the PHY of the first SOC; the PHY of the first SOC sends the first target data to the AIR of the first SOC.

[0257] In a possible implementation, the above method further includes: the PHY of the first SOC sends first air interface data to the MAC of the first SOC, where the first air interface data is the data in the third message, and the third message is the message received by the AIR of the first SOC; the MAC of the first SOC sends the first air interface data to the memory of the first SOC; the MAC of the first SOC sends the first air interface data to the memory of the second SOC through the first communication path; the communication interface of the first SOC receives second air interface data sent by the MAC of the second SOC through the first communication path, where the second air interface data is the data in the fourth message, and the fourth message is the message received by the AIR of the second SOC; the communication interface of the first SOC sends the second air interface data to the memory of the first SOC; the MAC of the first SOC reads second target data in the memory of the first SOC, and the second target data includes the first air interface data and / or the second air interface data.

[0258] In a possible implementation, the above method further includes: the ETH of the first SOC reads second target data in the memory of the first SOC; the ETH of the first SOC sends the second target data to the network interface of the first SOC.

[0259] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor data to the processor of the second SOC through the first communication path; the communication interface of the first SOC receives second processor data sent by the processor of the second SOC through the first communication path; the communication interface of the first SOC sends the second processor data to the processor of the first SOC.

[0260] In a possible implementation, the above method further includes: the processor of the first SOC sends a first processor message to the processor of the second SOC through the first communication path; the communication interface of the first SOC receives a second processor message sent by the processor of the second SOC through the first communication path; the communication interface of the first SOC sends the second processor message to the processor of the first SOC.

[0261] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor data to the memory of the second SOC through the first communication path; the processor of the first SOC sends a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC; the communication interface of the first SOC receives second processor data and a second message sent by the processor of the second SOC through the first communication path; the communication interface of the first SOC sends the second processor data to the memory of the first SOC; the communication interface of the first SOC sends the second message to the processor of the first SOC, where the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0262] In a possible implementation, the above method further includes: the processor of the first SOC sends first processor data to the memory of the first SOC; the processor of the first SOC sends a third message to the DMA of the first SOC, where the third message is used to instruct to send the first processor data to the memory of the second SOC; the DMA of the first SOC reads the first processor data in the memory of the first SOC; the DMA of the first SOC sends the first processor data to the memory of the second SOC through the first communication path.

[0263] In a possible implementation, the above method further includes: the DMA of the first SOC sends a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0264] In a possible implementation, the above method further includes: the DMA of the first SOC sends a first message to the processor of the first SOC.

[0265] In a possible implementation, the above method further includes: the DMA of the second SOC sends a second message to the processor of the first SOC through the first communication path, where the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

[0266] In a possible implementation, the above method further includes: the DMA of the second SOC sends a second message to the processor of the second SOC.

[0267] In a possible implementation, the above method further includes: the processor of the first SOC sends a first message to the processor of the first SOC through the first communication path, and the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

[0268] In a possible implementation, the above method further includes: the communication interface of the first SOC determines the target information of the input source according to the priority of the input source of the SOC, the input source includes ETH and / or DMA, and the target information includes at least one of a data input limit amount, a data input interval, a single data input limit amount, or a data input number limit amount.

[0269] In a possible implementation, the above method further includes: the memory of the first SOC sends the first target data to the MAC of the first baseband chip through the second communication path; the MAC of the first baseband chip sends the first target data to the PHY of the first baseband chip; the PHY of the first baseband chip sends the first target data to the AIR of the first baseband chip.

[0270] An embodiment of the present application further provides a communication device, which includes: at least one processor, and when the at least one processor executes program code or instructions, the method described in any of the above possible implementations is implemented.

[0271] Optionally, the communication device may further include at least one memory, and the at least one memory is used to store the program code or instructions.

[0272] An embodiment of the present application further provides a chip, which includes: an input interface, an output interface, and at least one processor. Optionally, the chip may further include a memory. The at least one processor is used to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method described in any of the above possible implementations.

[0273] Optionally, the above chip may also be an integrated circuit.

[0274] An embodiment of the present application further provides a computer storage medium, in which computer instructions are stored, and when the computer instructions run on a communication device, the communication device is enabled to execute the above related method steps to implement the communication method in the above embodiment.

[0275] An embodiment of the present application further provides a computer program product, and when the computer program product runs on a computer, the computer is enabled to execute the above related steps to implement the communication method in the above embodiment.

[0276] The embodiments of the present application also provide a communication device, which may specifically be a chip, an integrated circuit, a component or a module. Specifically, the device may include a processor connected to a memory for storing instructions, or the device includes at least one processor for obtaining instructions from an external memory. When the device runs, the processor may execute the instructions to cause the chip to execute the communication methods in the above method embodiments.

[0277] It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the above processes do not mean the order of execution is prior or subsequent. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0278] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0279] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0280] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be in an electrical, mechanical or other form.

[0281] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units. They may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0282] In addition, in each embodiment of the present application, each functional unit may be integrated into one processing unit, may exist physically alone for each unit, or two or more units may be integrated into one unit.

[0283] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the above methods in each embodiment of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0284] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A communication system, characterized in that, Including: N system-on-chip (SOC) integrated circuits, where each SOC includes a network interface, an Ethernet forwarding processing system (ETH), a communication interface, and a memory. The N SOCs include a first SOC and a second SOC, and there is a first communication path between the communication interfaces of the first SOC and the second SOC; The ETH of the first SOC is used to send first network interface data to the memory of the first SOC and send the first network interface data to the memory of the second SOC through the first communication path. The first network interface data is the data in a first packet, and the first packet is a packet received by the network interface of the first SOC; The communication interface of the first SOC is used to receive second network interface data sent by the ETH of the second SOC through the first communication path and send the second network interface data to the memory of the first SOC. The second network interface data is the data in a second packet, and the second packet is a packet received by the network interface of the second SOC; The ETH of the first SOC is further used to read first target data in the memory of the first SOC, where the first target data includes the first network interface data and / or the second network interface data.

2. The communication system according to claim 1, wherein The SOC further includes a media access control (MAC) layer system, a physical layer system (PHY), and an air interface processing system (AIR); The MAC of the first SOC is used to read the first target data in the memory of the first SOC and send the first target data to the PHY of the first SOC; The PHY of the first SOC is used to send the first target data to the AIR of the first SOC.

3. The communication system according to claim 1 or 2, characterized in that, The SOC further includes a MAC, a PHY, and an AIR; The PHY of the first SOC is used to send first air interface data to the MAC of the first SOC. The first air interface data is the data in a third packet, and the third packet is a packet received by the AIR of the first SOC; The MAC of the first SOC is used to send the first air interface data to the memory of the first SOC and send the first air interface data to the memory of the second SOC through the first communication path; The communication interface of the first SOC is further used to receive second air interface data sent by the MAC of the second SOC through the first communication path and send the second air interface data to the memory of the first SOC. The second air interface data is the data in a fourth packet, and the fourth packet is a packet received by the AIR of the second SOC; The MAC of the first SOC is further used to read second target data in the memory of the first SOC, where the second target data includes the first air interface data and / or the second air interface data.

4. The communication system according to claim 3, characterized in that, The ETH of the first SOC is further used to read the second target data in the memory of the first SOC and send the second target data to the network interface of the first SOC.

5. The communication system according to any one of claims 1 to 4, characterized in that The SOC further includes a processor; The processor of the first SOC is used to send first processor data to the processor of the second SOC through the first communication path; The communication interface of the first SOC is further configured to receive second processor data sent by the processor of the second SOC through the first communication path, and send the second processor data to the processor of the first SOC.

6. The communication system according to any one of claims 1 to 5, characterized in that, The SOC further includes a processor; The processor of the first SOC is configured to send first processor data to the memory of the second SOC through the first communication path, and send a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC; The communication interface of the first SOC is further configured to receive second processor data and a second message sent by the processor of the second SOC through the first communication path, send the second processor data to the memory of the first SOC, and send the second message to the processor of the first SOC, where the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

7. The communication system according to any one of claims 1 to 6, characterized in that, The SOC further includes a processor and a direct memory access (DMA); The processor of the first SOC is configured to send first processor data to the memory of the first SOC, and send a third message to the DMA of the first SOC, where the third message is used to instruct to send the first processor data to the memory of the second SOC; The DMA of the first SOC is configured to read the first processor data in the memory of the first SOC, and send the first processor data to the memory of the second SOC through the first communication path.

8. The communication system according to claim 7, characterized in that, The DMA of the first SOC is further configured to send a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

9. The communication system according to claim 7 or 8, characterized in that, The processor of the first SOC is further configured to send a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

10. The communication system according to any one of claims 1 to 9, characterized in that, The communication interface of the SOC is further configured to determine target information of the input source according to the priority of the input source of the SOC, where the input source includes ETH and / or DMA, and the target information includes at least one of a data input limit amount, a data input interval, a single data input limit amount, or a data input number limit amount.

11. The communication system according to any one of claims 1 to 10, characterized in that, The communication system further includes M baseband chips, where each baseband chip includes a MAC, a PHY, an AIR, and a communication interface. The M baseband chips include a first baseband chip, and there is a second communication path between the communication interface of the first SOC and the communication interface of the first baseband chip; The MAC of the first baseband chip is configured to read the first target data in the memory of the first SOC through the second communication path, and send the first target data to the PHY of the first baseband chip; The PHY of the first baseband chip is configured to send the first target data to the AIR of the first baseband chip.

12. A communication method, characterized in that, Applied to a communication system, the communication system includes N SOCs. Each SOC includes a network port, ETH, a communication interface, and a memory. The N SOCs include a first SOC and a second SOC. There is a first communication path between the communication interface of the first SOC and the communication interface of the second SOC. The method includes: The ETH of the first SOC sends first network port data to the memory of the first SOC. The first network port data is the data in a first message, and the first message is the message received by the network port of the first SOC. The ETH of the first SOC sends the first network port data to the memory of the second SOC through the first communication path. The communication interface of the first SOC receives second network port data sent by the ETH of the second SOC through the first communication path. The second network port data is the data in a second message, and the second message is the message received by the network port of the second SOC. The communication interface of the first SOC sends the second network port data to the memory of the first SOC. The ETH of the first SOC reads first target data in the memory of the first SOC. The first target data includes the first network port data and / or the second network port data.

13. The method according to claim 12, wherein The SOC further includes a MAC, a PHY, and an AIR. The method further includes: The MAC of the first SOC reads the first target data in the memory of the first SOC. The MAC of the first SOC sends the first target data to the PHY of the first SOC. The PHY of the first SOC sends the first target data to the AIR of the first SOC.

14. The method according to claim 12 or 13, characterized in that, The SOC further includes a MAC, a PHY, and an AIR. The method further includes: The PHY of the first SOC sends first air interface data to the MAC of the first SOC. The first air interface data is the data in a third message, and the third message is the message received by the AIR of the first SOC. The MAC of the first SOC sends the first air interface data to the memory of the first SOC. The MAC of the first SOC sends the first air interface data to the memory of the second SOC through the first communication path. The communication interface of the first SOC receives second air interface data sent by the MAC of the second SOC through the first communication path. The second air interface data is the data in a fourth message, and the fourth message is the message received by the AIR of the second SOC. The communication interface of the first SOC sends the second air interface data to the memory of the first SOC. The MAC of the first SOC reads second target data in the memory of the first SOC. The second target data includes the first air interface data and / or the second air interface data.

15. The method according to claim 14, wherein The method further includes: The ETH of the first SOC reads the second target data in the memory of the first SOC. The ETH of the first SOC sends the second target data to the network port of the first SOC.

16. The method according to any one of claims 12 to 15, characterized in that, The SOC further includes a processor. The method further includes: The processor of the first SOC sends first processor data to the processor of the second SOC through the first communication path; The communication interface of the first SOC receives second processor data sent by the processor of the second SOC through the first communication path; The communication interface of the first SOC receives the sending of the second processor data to the processor of the first SOC.

17. The method according to any one of claims 12 to 16, characterized in that The SOC further includes a processor, and the method further includes: The processor of the first SOC sends first processor data to the memory of the second SOC through the first communication path; The processor of the first SOC sends a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC; The communication interface of the first SOC receives second processor data and a second message sent by the processor of the second SOC through the first communication path; The communication interface of the first SOC sends the second processor data to the memory of the first SOC; The communication interface of the first SOC sends the second message to the processor of the first SOC, where the second message is used to indicate that the second processor data has been written into the memory of the first SOC.

18. The method according to any one of claims 12 to 17, characterized in that The SOC further includes a processor and a DMA, and the method further includes: The processor of the first SOC sends first processor data to the memory of the first SOC; The processor of the first SOC sends a third message to the DMA of the first SOC, where the third message is used to instruct to send the first processor data to the memory of the second SOC; The DMA of the first SOC reads the first processor data in the memory of the first SOC; The DMA of the first SOC sends the first processor data to the memory of the second SOC through the first communication path.

19. The method according to claim 18, wherein The method further includes: The DMA of the first SOC sends a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

20. The method according to claim 18 or 19, characterized in that, The method further includes: The processor of the first SOC sends a first message to the processor of the second SOC through the first communication path, where the first message is used to indicate that the first processor data has been written into the memory of the second SOC.

21. The method according to any one of claims 12 to 20, characterized in that, The method further includes: The communication interface of the SOC determines target information of the input source according to the priority of the input source of the SOC, the input source includes ETH and / or DMA, and the target information includes at least one of a data input limit amount, a data input interval, a single data input limit amount, or a data input number limit amount.

22. The method according to any one of claims 12 to 21, characterized in that, The communication system further includes M baseband chips, the baseband chips include a MAC, a PHY, an AIR, and a communication interface, the M baseband chips include a first baseband chip, and there is a second communication path between the communication interface of the first SOC and the communication interface of the first baseband chip, and the method further includes: The MAC of the first baseband chip reads the first target data in the memory of the first SOC through the second communication path; The MAC of the first baseband chip sends the first target data to the PHY of the first baseband chip; The PHY of the first baseband chip sends the first target data to the AIR of the first baseband chip.

23. A communication device, characterized in that, The device includes the communication system according to any one of claims 1 to 11.

24. A communication device, characterized in that, Comprising at least one processor and an interface circuit, the at least one processor and the interface circuit are coupled, and the at least one processor executes a program or instructions stored in a memory to enable the communication device to implement the method according to any one of claims 12 to 22.

25. A computer-readable storage medium for storing a computer program, characterized in that, The computer program includes instructions for implementing the method according to any one of claims 12 to 22.

26. A computer program product comprising instructions, characterized in that, When the instructions run on a computer or a processor, the computer or the processor implements the method according to any one of claims 12 to 22.

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