5G TDD synchronization method and device for repeater

Abstract

The invention provides a 5G TDD synchronization method and device for a repeater, which is low in implementation cost, high in precision and long in synchronization retention time, and comprises the following steps: recording high and low level time lengths in an input radio frequency signal through a counter, and finding out a frame header position; after the frame header is found, when the counter finding the position of the frame header counts the period length of one half frame from the position of the frame header every time, a pulse signal marking the frame header is output, and a radio frequency switch signal is output according to time slot information, so that synchronization with a current network signal is realized; when the counter finding the frame header position continuously counts to a set overflow threshold value, subtracting the period length of one half frame from the count value, so that the counter is always aligned with the frame header position, recording the synchronization times, and calibrating the frame header position by adopting a ping-pong method when the synchronization times are less than or equal to a set value; when the synchronization times are greater than a set value and less than a set maximum value, calibrating the frame header position according to the effective edge change; and when the synchronization times reach the maximum value, the frame header position is searched again.

Description

Technical Field

[0001] The present invention relates to the field of 5G communication technologies, and particularly to a TDD synchronization method for 5G. Background Art

[0002] The development of 5G technology plays an important role in various fields such as intelligent transportation, aerospace, telemedicine, and virtual VR game experiences. The communication methods of 5G technology can be divided into FDD (Frequency Division Duplexing) and TDD (Time Division Duplexing). In the FDD method, the uplink and downlink frequencies are different and no scheduling is required. The uplink and downlink frequencies of TDD are the same, and unified scheduling and allocation by the base station are required. TDD synchronization technology is a synchronization method to avoid the inability of the user terminal to synchronize with the base station or a large error, resulting in communication errors or even interference with the base station.

[0003] Currently, the synchronization technology of 4G is relatively mature, and the existing TDD synchronization technologies of 5G mainly include: (1) The TDD synchronization method of 5G technology selects the digital signal processing chip deframing method; (2) Adopt the TDD baseband synchronization module method; (3) Satellite synchronization in 5G technology to obtain a precise clock synchronization method; (4) The edge change calibration method of envelope detection, as disclosed in the patent with the publication number CN119095145A. Among them, the costs of method (1), method (2), and method (3) are relatively high, the algorithms are complex, and the synchronization holding time in method (4) is relatively short. Summary of the Invention

[0004] To solve the deficiencies of the prior art, the present invention provides a 5G TDD synchronization method and device for a repeater, which have low implementation cost, high precision, and long synchronization holding time.

[0005] The technical solution is as follows: A 5G TDD synchronization method for a repeater, characterized by comprising the following steps:

[0006] Step 1: Count the low and high level durations in the input radio frequency signal through a counter, match the obtained low and high level durations with the theoretical uplink signal and downlink signal durations in the time slot information of the input signal, and find the frame head position;

[0007] Step 2: After finding the frame head, when the counter that finds the frame head position counts full a half-frame cycle length each time from the frame head position, output a pulse signal marking the frame head and output a radio frequency switch signal according to the time slot information to achieve synchronization with the in-network signal;

[0008] Step 3: When the counter that finds the frame header position continues to count up to the set overflow threshold, subtract the cycle length of one and a half frames from the count value of the counter that finds the frame header position, so that the counter that finds the frame header position is always aligned with the frame header position. Record the number of synchronization times. When the number of synchronization times is less than or equal to the set value, use the ping-pong method to calibrate the frame header position; when the number of synchronization times is greater than the set value and less than the set maximum number of synchronization times, calibrate the frame header position according to the valid edge change at any moment of the downlink signal in the detected input signal; when the number of synchronization times reaches the set maximum value, return to Step 1 to find the frame header position again.

[0009] Further, Step 1 is specifically executed as follows: Turn on the downlink RF switch, identify the edge change of the input signal, enable the first counter to start counting at the edge change point from high level to low level, enable the second counter to start counting at the edge change point from low level to high level, and read the value of the counter at each change point, so as to obtain the recorded low-level duration and high-level duration, and compare them with the theoretical durations of the uplink and downlink in the time slot information until the obtained durations meet the theoretical durations of each uplink and downlink within one and a half frame periods in the time slot information. According to the theoretical frame header position in the time slot information, determine the count value corresponding to the frame header position of the input signal in the second counter and use it as the frame header position for synchronization.

[0010] Further, in Step 3, let m be the overflow threshold, m satisfies T < m < Cmax, T is the cycle of one and a half frames, Cmax is the maximum counting time of the counter, set n as the set value of the number of synchronization times, set the maximum value of the number of synchronization times as max, and set the theoretical error generated by the clock of the counter within the period T of the input signal as a.

[0011] When the number of synchronization times is greater than or equal to 0 and less than or equal to n, whenever the second counter counts to m, use the ping-pong method to calibrate the frame header position;

[0012] When the number of synchronization times is greater than n and less than max, calibrate the frame header position according to the valid edge change at any moment of the downlink signal in the detected input signal;

[0013] When the number of synchronization times is max times, when the second counter counts to m, the current value of the second counter is expressed as T2 = T 当前 -T, return to Step 1 to find the frame header again, and set the number of synchronization times to 0.

[0014] Further, in Step 3, the method of using the ping-pong method to calibrate the frame header position is specifically executed as follows:

[0015] If the number of synchronization times is an odd number from 0 to n, whenever the second counter counts to m, calibrate the current value of the second counter to T2 = T 当前 -T + a + 1, and increment the number of synchronization times by 1;

[0016] When the number of synchronization times is an even number from 0 to n times, whenever the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 -T + a - 1, and the number of synchronization times is incremented by 1.

[0017] Further, in step 3, the position of the frame header is calibrated according to the valid edge change at any moment of the downlink signal in the detected input signal, and the specific implementation is as follows:

[0018] Let the value of the second counter when the valid edge change is detected be Temp1. According to the time slot information, the symbol duration is t_sy. Let x be the integer obtained by taking the integer part of the quotient of Temp1 divided by t_sy, and let y be the remainder of Temp1 divided by t_sy.

[0019] When condition 1 is satisfied: if y is greater than t_sy - t2, the distance cTemp between the current signal valid edge change position and the theoretical frame header position is:

[0020] cTemp = (x + 1) * t_sy;

[0021] When condition 2 is satisfied: if y is less than t2, the distance cTemp between the current signal valid edge change position and the theoretical frame header position is:

[0022] cTemp = x * t_sy;

[0023] If y does not satisfy condition 1 or condition 2, exit the current process and increment the number of synchronization times by one;

[0024] If either condition 1 or condition 2 is satisfied, update cTemp to the current count value of the second counter, set the number of synchronization times to 0, and enter the ping-pong method calibration.

[0025] Among them, cTemp is the distance between the current signal valid edge change position and the theoretical frame header position calculated according to the edge change combined with the time slot information. t2 is the maximum relative symbol deviation, t2 is not greater than n * a, n is the set value of the number of synchronization times, and a is the theoretical error generated by the clock of the counter within the period T of the input signal.

[0026] A computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the 5G TDD synchronization method for a repeater as described above.

[0027] A computer-readable storage medium stores a program, and when the program is executed by a processor, it implements the 5G TDD synchronization method for a repeater as described above.

[0028] A computer program product includes a computer program / instructions which, when executed by a processor, implement the steps of the above method.

[0029] The 5G TDD synchronization method for a repeater according to the present invention is improved based on envelope detection and is a software-based synchronization solution. Compared with complex hardware synchronization solutions, it can reduce the difficulty of development and implementation. The synchronization based on software in the present invention can reduce the hardware cost, reduce the dependence on expensive digital signal processing chips, baseband synchronization modules or satellite synchronization devices, and improve the competitiveness of products in cost-sensitive markets. The method combines ping-pong calibration and edge change calibration. Long-term synchronization is achieved through ping-pong calibration, and calibration accuracy is ensured through edge change calibration. The two work together to extend the synchronization time, and the synchronization accuracy can be controlled by adjusting parameters to meet the requirements for synchronization accuracy in different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of steps in an embodiment;

[0031] Figure 2 It shows the time slot waveform diagram of the signal of a 3.5 GHz, 5 ms double-cycle frame structure;

[0032] Figure 3 It is a flowchart of finding the frame header position of a 5 ms double cycle in an embodiment;

[0033] Figure 4 It shows the signal timing diagram of the signal of a 3.5 GHz, 5 ms double-cycle frame structure;

[0034] Figure 5 It is the internal structure diagram of a computer device in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] See Figure 1 , a 5G TDD synchronization method and device for a repeater according to the present invention include the following steps:

[0036] Step 1: Count the durations of low and high levels in the input radio frequency signal through a counter, match the obtained durations of low and high levels with the theoretical durations of uplink and downlink signals in the time slot information of the input signal, and find the frame header position;

[0037] Step 2: After finding the frame header, when the counter that finds the frame header position counts full a half-frame cycle length each time from the frame header position, output a pulse signal marking the frame header and output a radio frequency switch signal according to the time slot information to achieve synchronization with the in-network signal;

[0038] Step 3: When the counter that finds the frame header position continues to count up to the set overflow threshold, subtract the cycle length of one and a half frames from the count value of the counter that finds the frame header position, so that the counter that finds the frame header position is always aligned with the frame header position. Record the number of synchronization times. When the number of synchronization times is less than or equal to the set value, use the ping-pong method to calibrate the frame header position; when the number of synchronization times is greater than the set value and less than the set maximum number of synchronization times, calibrate the frame header position according to the valid edge change at any moment of the downlink signal in the detected input signal; when the number of synchronization times reaches the set maximum value, return to Step 1 to find the frame header position again.

[0039] Specifically, in Step 1 of an embodiment of the present invention, according to the time slot information of the input signal, find the frame header position, and the specific implementation is as follows: Turn on the downlink RF switch, identify the edge change of the input signal, enable the first counter to start counting at the edge change point from high level to low level, enable the second counter to start counting at the edge change point from low level to high level, and read the value of the counter at each change point, so as to obtain the recorded low-level duration and high-level duration, and compare them with the theoretical durations of the uplink and downlink in the time slot information until the obtained durations meet the theoretical durations of each uplink and downlink within one and a half frame periods in the time slot information. According to the theoretical frame header position in the time slot information, determine the count value corresponding to the frame header position of the input signal in the second counter and use it as the frame header position for synchronization with the existing network.

[0040] In Step 2 of the embodiment, when the counter that finds the frame header position counts full of the cycle length of one and a half frames each time from the frame header position, output a trig pulse signal to mark the frame header, and then output an RF switch signal according to the trig pulse signal and the uplink and downlink signal durations in the configuration information to achieve synchronization with the existing network signal;

[0041] In Step 3 of the embodiment, each time the count of the second counter that finds the frame header position reaches the overflow threshold, subtract the period T from the count value of the second counter. Let m be the overflow threshold, then m satisfies T < m < Cmax, where T is the cycle of one and a half frames and Cmax is the maximum counting time of the counter, so that the second counter that finds the frame header position continues to count.

[0042] In Step 3 of the embodiment, in order to synchronize for a longer time, record the number of synchronization times each time the overflow threshold is reached.

[0043] Set n as the set number, set the maximum value of the number of synchronization times as max, and set the theoretical error generated by the clock of the counter within the period T of the input signal as a.

[0044] When the number of synchronization times is greater than or equal to 0 and less than or equal to n, each time the second counter counts to m, use the ping-pong method to calibrate the frame header position;

[0045] When the number of synchronization times is greater than n and less than max, calibrate the frame header position according to the valid edge change at any moment of the downlink signal in the detected input signal;

[0046] When the number of synchronization times reaches max, when the second counter counts to m, the current value of the second counter is expressed as T2 = T 当前 -T, return to step 1 to search for the frame header again, and set the number of synchronization times to 0.

[0047] In step 3 of the embodiment, the ping-pong method is used to calibrate the frame header position as follows:

[0048] If the number of synchronization times is an odd number from 0 to n, whenever the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 -T + a + 1, and increment the number of synchronization times by 1;

[0049] If the number of synchronization times is an even number from 0 to n, whenever the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 -T + a - 1, and increment the number of synchronization times by 1.

[0050] In step 3 of the embodiment, calibrate the frame header position according to the valid edge change at any moment of the downlink signal in the detected input signal, as follows:

[0051] Let the value of the second counter when the valid edge change is detected be Temp1, obtain the symbol duration t_sy according to the time slot information, let x be the integer obtained by taking the integer part of the quotient of Temp1 divided by t_sy, and let y be the remainder of Temp1 divided by t_sy.

[0052] When condition 1 is satisfied: if y is greater than t_sy - t2, the distance cTemp from the current signal valid edge change position to the theoretical frame header position is:

[0053] cTemp = (x + 1) * t_sy;

[0054] When condition 2 is satisfied: if y is less than t2, the distance cTemp from the current signal valid edge change position to the theoretical frame header position is:

[0055] cTemp = x * t_sy;

[0056] If y does not satisfy any of condition 1 and condition 2, exit the current calibration and increment the number of synchronization times by one;

[0057] Among them, cTemp is the distance from the current signal valid edge change position to the theoretical frame header position calculated according to the edge change and time slot information, t2 is the maximum relative symbol deviation, t2 is not greater than n * a, n is the set value of the number of synchronization times, and a is the error corresponding to the period T;

[0058] If any one of Condition 1 or Condition 2 is satisfied, update cTemp to the current count value of the second counter, set the synchronization count to 0, and enter the ping-pong method calibration.

[0059] For a clearer illustration, in the embodiments, the 5G TDD synchronization method for a repeater of the present invention will be exemplified with a 3.5 GHz, 5 ms dual-period frame structure.

[0060] The process of finding the frame header position in Step 1 is specifically manifested as:

[0061] It can be known from the relevant literature of 3GPP that the time slot configuration of the 3.5 GHz, 5 ms dual-period frame structure signal is DDDSUDDSUU, the period T = 5 ms, the S time slot ratio is 10:2:2 (DDDDDDDDDDGGUU), the subcarrier spacing is 30 kHz, where D represents downlink, U represents uplink, S represents the special time slot ratio, G represents the guard interval, the occupancy duration of D in S is 0.5 ms * 10 / 14, the occupancy duration of U in S is 0.5 ms * 2 / 14, and the occupancy duration of G in S is 0.5 ms * 2 / 14. Figure 2 The time slot waveform diagram of the 3.5 GHz, 5 ms dual-period frame structure signal is shown. In the example, it is only for convenience of illustration and does not only apply to this frame structure.

[0062] Step 101: When the falling edge of the radio frequency input signal is recognized, the first counter starts counting. When the next rising edge comes, the second counter starts counting and reads the value c1 of the first counter. c1 needs to satisfy Condition 1; in Condition 1, c1 starts counting at the falling edge and reads at the rising edge, so it describes the low-level duration. The uplink period signal detected at the downlink signal end should be at a low level. For the 3.5 GHz, 5 ms dual-period frame structure signal, if the detected low level satisfies the total duration of the ninth and tenth time slots U (uplink time slots) in the time slot information, it can be considered that the rising edge position of the c1 reading of the first counter is presumably the frame header position. According to the time slot information, Condition 1 is: c1 satisfies being greater than the duration of two U time slots plus the duration of U in the S time slot, and c1 satisfies being at most no more than the duration of two U time slots plus the occupancy duration of U in the S time slot plus the occupancy duration of G in the S time slot; if Condition 1 is not satisfied, the first counter and the second counter are cleared, and wait for the next falling edge until a condition-satisfying edge change is found. If Condition 1 is satisfied, enter Step 102;

[0063] Step 102: The second counter continues to count, and the first counter is cleared. When the next falling edge arrives, the first counter starts counting again and reads the value c2 of the second counter. The value c2 must meet condition 2. The downlink time slot should detect a high-level signal during the downlink period at the downlink signal end. c2 is the count at the rising edge and the reading at the falling edge of the second counter, which describes the high-level duration. Therefore, c2 must meet condition 2. The counting method of condition 2 is the same as that of condition 1. For a 3.5 GHz, 5 ms dual-period frame structure signal, according to the time slot information, condition 2 is: c2 is greater than the duration of 3 D time slots plus the proportion of D in S, and c2 is at most the duration of 3 D time slots plus the proportion of D in S plus the proportion of G in S. If it does not meet the condition, the second counter and the first counter are cleared, and return to step 101.

[0064] For a 5 ms single-period frame structure, if the conditions of step 101 and step 102 are met and the waveform of a complete 5 ms cycle is detected, the frame header position can be confirmed according to the time slot information. For a 5 ms dual-period frame structure, if the conditions of step 101 and step 102 are met but a 5 ms cycle has not been completely detected, there may be detection errors. Therefore, to more accurately determine the frame header position, continuous detection is required until a 5 ms cycle is completed.

[0065] Step 103: The second counter continues to count, and the first counter also continues to count. When the next rising edge arrives, mark the value c3 of the second counter and read the value of the first counter. The value c4 of the first counter must meet condition 3. c4 starts counting at the falling edge and reads at the rising edge, so it describes the low-level duration. For a 3.5 GHz, 5 ms dual-period frame structure signal, condition 3 is: c4 is greater than the proportion of the 5th time slot U and the proportion of U in the 4th time slot S, and c4 is at most the proportion of the 5th time slot U, the proportion of U in the 4th time slot S, and the proportion of G in the 4th time slot S. If it does not meet the condition, c3 is assigned 0, the second counter and the first counter are cleared, and return to step 101. If c4 meets the condition, go to step 104.

[0066] Step 104: The second counter continues to count, and the first counter is cleared; when the next falling edge arrives, read the value c5 of the second counter, and condition 4 needs to be satisfied; c3 is the value recorded by the second counter at the second rising edge, and c5 is the value at the second falling edge after the second counter starts counting. Therefore, c5 - c3 describes the second high level, that is, the duration of the second downlink signal in a double period. According to the time slot information, for a 3.5 GHz, 5 ms double-period frame structure signal, condition 4 is: c5 - c3 is greater than the occupancy duration of D in the 6th time slot D, the 7th time slot D, and the 8th time slot S; c5 - c3 also satisfies not being greater than the occupancy duration of D in the 6th time slot D, the 7th time slot D, the 8th time slot S, and G in the 8th time slot S; if not satisfied, assign 0 to c3, clear the second counter, and return to step 101. If the condition is satisfied, go to step 2.

[0067] The flowchart for finding the frame header position can be seen in Figure 3 , Figure 3 where cnt1 represents the first counter in Figure 3 and cnt2 represents the second counter. The steps 101 to 104 given in the embodiment are the process of finding the frame header position. The conditions 1, 2, 3, and 4 involved in the steps are determined according to the time slot information. For time slots with a 5 ms double period like in the embodiment, a complete 5 ms cycle is required to accurately determine the frame header position. For 5 ms single-period time slots such as B39, B40, and N41, steps 103 and 104 can be saved, but the time slot information for each is different, and the conditions are adjusted corresponding to the time slot information. However, no matter how it changes, as long as it satisfies detecting a complete 5 ms signal cycle that matches the durations of the uplink signal and downlink signal in the theoretical time slot information, the frame header can be determined.

[0068] In step 1 of this embodiment, according to the time slot information of 3.5 GHz and 5 ms double period, it can be determined that in this embodiment, the frame header position is the position where the second counter starts counting. Since the counter cannot count indefinitely, theoretically, if the counter clock is 10 MHz, then one number represents 0.1 us. To record a 5 ms signal cycle, 50000 numbers are required, and to record 2 cycles, 2 * 50000 are required. And the maximum count of a counter is 65536. That is to say, if the clock is 10 MHz, the maximum that can be recorded is 6.5536 ms. If the counter clock is adjusted to 1 MHz, the maximum can be recorded as 65.536 ms, but one number is 1 us. Although the method of register splicing can also be used to increase the maximum count, it increases resource consumption and occupies a high level of processor resources. In this case, to improve accuracy, save processor resources, and reduce power consumption, a 10 MHz counter clock is used. In other embodiments, counters with other clock frequencies can also be used.

[0069] In step 2, when the counter that finds the header position counts up to the cycle length of one and a half frames each time from the header position, an output trig pulse signal for marking the header is generated, and then, according to the trig pulse signal and the uplink and downlink signal durations in the configuration information, a radio frequency switch signal is output to achieve synchronization with the in-network signal;

[0070] In step 3 of the embodiment, when the second counter that finds the header position continues to count and reaches the overflow threshold each time, the count value of the second counter is subtracted by the period T. Let m be the overflow threshold, then m satisfies T < m < Cmax, where T is the period of the input signal and Cmax is the maximum counting time of the counter, so that the second counter that finds the header position continues to count. In this embodiment, the adopted method is that when the second counter counts for more than one period of 5 ms but before overflowing at the maximum counting time of 6.5536 ms, the value of the second counter is subtracted by one period T, that is, 5 ms, so that the header position theoretically remains unchanged.

[0071] In the embodiment, taking the 3.5 GHz, 5 ms dual-period frame structure as an example, in step 3, n is set as the set number, m is set as the overflow threshold for the second counter to count, satisfying 5 ms < m < 6.5536 ms, and the error corresponding to the period T is set as a. For a clock of 10 MHz ± 20 ppm theoretically, the maximum value of the a value is 0.1 us;

[0072] When the synchronization times are greater than 0 and less than or equal to n, each time the second counter counts to m, the ping-pong method is used to calibrate the header position;

[0073] When the synchronization times are greater than n and less than max, the header position is calibrated according to the valid edge change at any moment of the downlink signal in the detected input signal;

[0074] When the synchronization times reach max times, when the second counter counts to m, the current value of the second counter is expressed as T2 = T 当前 -T, return to step 1 to search for the header again, and set the synchronization times to 0.

[0075] Among them, the specific implementation of calibrating the header position by the ping-pong method is as follows:

[0076] When the second counter counts to m, and the synchronization times are odd numbers from 0 to n, each time the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 -T + a + 1, and the synchronization times are incremented by 1;

[0077] When the second counter counts to m, and the synchronization times are even numbers from 0 to n, each time the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 -T + a - 1, and the synchronization times are incremented by 1;

[0078] By using the above-mentioned ping-pong method to calibrate the value of the second counter, long-term synchronization can be maintained. The deviation accuracy can be controlled by the set value of n. The larger the value of n, the longer the synchronization time, but the accuracy will decrease.

[0079] In step 3 of the embodiment, the frame header position is calibrated according to the valid edge change at any moment of the downlink signal in the detected input signal, and the specific implementation is as follows:

[0080] Let the value of the second counter when the valid edge change is detected be Temp1. According to the time slot information, the symbol duration is t_sy. Let x be the integer obtained by taking the integer part of the quotient of Temp1 divided by t_sy, and let y be the remainder of Temp1 divided by t_sy.

[0081] When condition 1 is satisfied: if y is greater than t_sy - t2, the distance cTemp from the current signal valid edge change position to the theoretical frame header position is:

[0082] cTemp = (x + 1) * t_sy;

[0083] When condition 2 is satisfied: if y is less than t2, the distance cTemp from the current signal valid edge change position to the theoretical frame header position is:

[0084] cTemp = x * t_sy;

[0085] If y does not satisfy condition 1 or condition 2, exit the current process and enter the ping-pong method calibration;

[0086] If either condition 1 or condition 2 is satisfied, update cTemp to the current count value of the second counter, set the synchronization count to 0, and enter the ping-pong method calibration.

[0087] Among them, cTemp is the distance from the current signal valid edge change position to the theoretical frame header position calculated according to the edge change and time slot information. t2 is the maximum relative symbol deviation, and t2 is not greater than n * a. n is the set value of the synchronization count, and a is the theoretical error generated by the counter clock within the period T of the input signal.

[0088] The detected signal edge change should be the edge change of the downlink signal, and either the rising edge or the falling edge can be used. To leave time for step 3 to execute normally, the value of the second counter is between 5 ms and m on the time axis; the maximum relative symbol deviation t2 needs to be less than half of the symbol error and greater than the error discarded by t_sy. Therefore, the maximum symbol deviation t2 can be set to the possible error caused by the previous n times of ping-pong method calibration. Taking the 3.5 GHz, 5 ms double-period frame structure as an example, the error a corresponding to the period of 5 ms is 0.1 us. When n is 30 times, the maximum symbol deviation t2 should not be greater than 3 us. If n is 15, the maximum symbol deviation t2 should not be greater than 1.5 us.

[0089] In the ping-pong calibration and edge change calibration in step 3, the value in the second counter is modified so that the value of the second counter will not overflow and always uses the frame header found in step 1 as a reference.

[0090] Figure 4 The signal timing diagram showing the case of a 5 ms double period is presented. Figure 4 In it, ① to ⑤ represent the process of finding the frame header; ⑥ represents the position where the downlink RF switch is turned on, meaning that the downlink RF signal of the next period is about to arrive, so the downlink RF switch needs to be turned on in advance; ⑦ represents that the downlink RF signal of the first half period has ended, so the downlink RF switch can be turned off; ⑧ represents that the downlink RF signal of the second half period is about to arrive, so the downlink RF switch needs to be turned on in advance; ⑨ represents that the downlink RF signal of the second half period has ended, so the downlink RF switch can be turned off; ⑩ represents the position where the next downlink RF switch is turned on, meaning that the downlink RF signal is about to arrive. ⑥ to ⑩ is a complete signal period (5 ms double period). To avoid timing errors, the downlink RF switch should be set high before the RF signal and set low after the RF signal.

[0091] In the current 5G TDD synchronization technology, the frame decoding method of the digital signal processing chip, the TDD baseband synchronization module method, and the satellite synchronization to obtain precise clock synchronization method are costly and not applicable to cost-sensitive scenarios such as repeater application scenarios in underground parking lots, elevator shafts, tunnels, etc. The method of the present invention reduces the hardware cost on the premise of ensuring the synchronization function. Compared with the existing costly synchronization technologies, it provides a new solution for the application of synchronization technology in more cost-sensitive fields and can broaden the market application scope.

[0092] The method of the present invention can also solve the problem that the existing envelope detection edge change calibration method has a short synchronization holding time and cannot meet the requirement of long-term stable synchronization in actual communication. This solution combines the ping-pong algorithm and the edge change calibration method. The ping-pong method delays the accumulation of clock drift through periodic positive and negative error compensation, effectively extending the synchronization time. The application of edge change calibration actively corrects the frame header offset before the ping-pong method fails, improving the system robustness, ensuring the continuous and stable synchronization of signals during the communication process, and also achieving a high synchronization accuracy, meeting the dual requirements for accuracy and cost.

[0093] The method of the present invention supports multiple time slot configurations, adapts to signals of different frequency bands, and the synchronization accuracy parameters can be dynamically adjusted to meet the accuracy and power consumption requirements of different scenarios. Moreover, it is not only applicable to 5G TDD synchronization but also can be applied to 4G TDD synchronization, with good versatility.

[0094] In an embodiment of the present invention, a computer device is further provided, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the 5G TDD synchronization method for a repeater as described above is implemented.

[0095] The computer device may be a terminal, and its internal structure diagram may be as Figure 4 shown. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected through a bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the 5G TDD synchronization method for a repeater is implemented. The display screen of the computer device may be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device may be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, a touchpad, or a mouse, etc.

[0096] The memory may be, but is not limited to, a random access memory (Random Access Memory, abbreviated as RAM), a read-only memory (Read Only Memory, abbreviated as ROM), a programmable read-only memory (Programmable Read-Only Memory, abbreviated as PROM), an erasable programmable read-only memory (Erasable Programmable Read-Only Memory, abbreviated as EPROM), an electrically erasable programmable read-only memory (Electric Erasable Programmable Read-Only Memory, abbreviated as EEPROM), etc. Among them, the memory is used to store a program, and after receiving an execution instruction, the processor executes the program.

[0097] The processor can be an integrated circuit chip with the ability to process signals. The above-mentioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc. The processor can also be other general-purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0098] Those skilled in the art can understand that Figure 4 the structure shown in [the figure] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0099] In an embodiment of the present invention, there is also provided a computer-readable storage medium, on which a program is stored, and characterized in that: when the program is executed by a processor, it implements the 5G TDD synchronization method for a repeater as described above.

[0100] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a computer device, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program code.

[0101] Embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, computer devices, or computer program products according to embodiments of the present invention. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing terminal devices to generate a machine, such that the instructions executed by the processors of the computer or other programmable data processing terminal devices generate a device for realizing the functions specified in the flowcharts and / or block diagrams.

[0102] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that realizes the functions specified in the flowchart.

[0103] In an embodiment of the present invention, there is also provided a computer program product, including a computer program / instructions, characterized in that when the computer program / instructions are executed by a processor, the steps of the above method are realized.

[0104] In actual application processes, the above computer program product includes, but is not limited to: smart phones, desktop computers, laptop computers, tablet computers, base stations, host computers, and server platforms, etc., and no specific limitations are made here.

[0105] The above has introduced in detail the application of the 5G TDD synchronization method, computer device, computer-readable storage medium, and computer program product provided by the present invention for a repeater. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A 5G TDD synchronization method and device for a repeater, characterized in that It includes the following steps: Step 1: Use a counter to count the durations of low and high levels in the input radio frequency signal, match the obtained durations of low and high levels with the theoretical durations of uplink and downlink signals in the time slot information of the input signal, and find the frame header position; Step 2: After finding the frame header, when the counter at the frame header position counts up to the cycle length of one and a half frames each time, output a pulse signal marking the frame header and output a radio frequency switch signal according to the time slot information to achieve synchronization with the in-network signal; Step 3: When the counter at the frame header position continues to count up to the set overflow threshold, subtract the cycle length of one and a half frames from the count value of the counter at the frame header position, so that the counter at the frame header position is always aligned with the frame header position, record the synchronization times. When the synchronization times are less than or equal to the set value, use the ping-pong method to calibrate the frame header position; when the synchronization times are greater than the set value and less than the maximum set synchronization times, calibrate the frame header position according to the valid edge change at any moment of the detected downlink signal in the input signal; when the synchronization times reach the maximum set value, return to Step 1 to find the frame header position again.

2. The 5G TDD synchronization method for a repeater according to claim 1, wherein Step 1 is specifically executed as follows: Turn on the downlink radio frequency switch, identify the edge change of the input signal, start counting with the first counter at the edge change point from high level to low level, start counting with the second counter at the edge change point from low level to high level, read the value of the counter at each change point, so as to obtain the recorded durations of low and high levels, and compare them with the theoretical durations of uplink and downlink in the time slot information until the obtained durations meet the theoretical durations of each uplink and downlink within one and a half frame periods in the time slot information. According to the theoretical frame header position in the time slot information, determine the count value corresponding to the frame header position of the input signal in the second counter and use it as the frame header position for synchronization.

3. A 5G TDD synchronization method for a repeater according to claim 2, characterized in that, In Step 3, let m be the overflow threshold, m satisfies T < m < Cmax, T is the cycle of one and a half frames, Cmax is the maximum counting time of the counter, set n as the set value of the synchronization times, set the maximum value of the synchronization times as max, and set the theoretical error generated by the clock of the counter within the period T of the input signal as a, When the synchronization times are greater than or equal to 0 and less than or equal to n, every time the second counter counts up to m, use the ping-pong method to calibrate the frame header position; When the synchronization times are greater than n and less than max, calibrate the frame header position according to the valid edge change at any moment of the detected downlink signal in the input signal; When the number of synchronization times reaches max, when the second counter counts to m, the current value of the second counter is expressed as T2 = T 当前 - T, return to step 1 to search for the frame header again, and set the number of synchronization times to 0.

4. A 5G TDD synchronization method for a repeater according to claim 3, characterized in that, In Step 3, the ping-pong method for calibrating the frame header position is specifically executed as follows: When the number of synchronization times is an odd number from 0 to n times, every time the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 - T + a + 1, and increment the number of synchronization times by 1; When the number of synchronization times is an even number from 0 to n times, every time the second counter counts to m, the current value of the second counter is calibrated to T2 = T 当前 - T + a - 1, and increment the number of synchronization times by 1.

5. A 5G TDD synchronization method for a repeater according to claim 3, characterized in that, In Step 3, calibrating the frame header position according to the valid edge change at any moment of the detected downlink signal in the input signal is specifically executed as follows: Let the value of the second counter when the valid edge change is detected be Temp1, obtain the symbol duration as t_sy according to the time slot information, let x be the integer obtained by taking the integer part of the quotient of Temp1 divided by t_sy, and let y be the remainder of Temp1 divided by t_sy, When the condition 1 is satisfied: If y is greater than t_sy - t2, the distance cTemp between the current signal valid edge change position and the theoretical frame header position is: cTemp = (x + 1) * t_sy; When condition 2 is satisfied: If y is less than t2, the distance cTemp from the position of the valid edge change of the current signal to the position of the theoretical frame header is: cTemp = x * t_sy; If y does not satisfy condition 1 or condition 2, exit the current process and increment the synchronization count by one; If either condition 1 or condition 2 is satisfied, update cTemp to the current count value of the second counter, set the synchronization count to 0, and enter ping-pong method calibration. Among them, cTemp is the distance from the position of the valid edge change of the current signal to the position of the theoretical frame header calculated according to the edge change combined with the time slot information, t2 is the maximum relative symbol deviation, t2 is not greater than n * a, n is the set value of the synchronization count, and a is the theoretical error generated by the clock of the counter within the period T of the input signal.

6. A computer device, including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements the 5G TDD synchronization method for a repeater as described in any one of claims 1 to 5.

7. A computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, it implements the 5G TDD synchronization method for a repeater as described in any one of claims 1 to 5.

8. A computer program product, including computer programs / instructions, and when the computer programs / instructions are executed by a processor, it implements the steps of the method as described in any one of claims 1 to 5.

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