A data link wireless communication timing synchronization method

Abstract

The present invention provides a data link wireless communication timing synchronization method, comprising the following steps: using multiple groups of PN sequences as the basis for synchronization timing, detecting the number of valid synchronization symbols, detecting the time-of-departure (TOD) following the PN sequence number, performing a CRC check on the information content, using RS encoding and decoding, and then performing 8-fold spread spectrum. The demodulator uses the correct position of the check as the basis for the synchronization timing time point, and determines the valid timing position based on the sequence numbers of different hops. The present invention has the following beneficial effects: reducing the synchronization signal-to-noise ratio to below 0dB, significantly reducing the false alarm probability and missed alarm probability, thereby improving frame synchronization performance; and enhancing the anti-interference capability in the time domain and frequency domain.

Description

Technical Field

[0001] The present invention belongs to the technical field of data link wireless communication, and in particular relates to a data link wireless communication timing synchronization method. Background Art

[0002] Wireless data links are used to transmit real-time data (such as voice, video, sensor data, or control commands) and are commonly used in the following scenarios: industrial automation: high-precision time synchronization (such as TSN time-sensitive networking); mobile communications (5G / 6G): high-speed mobility, millimeter-wave communications, and massive MIMO. In these applications, timing synchronization is essential for ensuring accurate signal demodulation at the receiver. Timing synchronization is the process of ensuring that all participating nodes (platforms, terminals, relay stations, etc.) in wireless data link systems (such as Link-16, TTNT, and the Industrial Internet of Things) have a highly consistent time reference. Its goal is to ensure that all nodes "know" that they should send or receive specific signals or data at the same time. The core goal is to eliminate or minimize time deviations between nodes caused by clock discrepancies and signal propagation delays. Failure to synchronize can result in the loss of entire frames. Inaccurate synchronization can lead to inter-symbol interference (ISI), increased bit error rate (BER), and even communication link disruption. In wireless communications, wireless signal interference and anti-interference have always been a contradictory relationship. Under such conditions, it is very important to be able to decode the synchronization information of wireless signals under interference. Therefore, multi-hop synchronization and multiple timing information per hop are effective ways to effectively resolve interference. Summary of the Invention

[0003] In view of this, the present invention aims to propose a data link wireless communication timing synchronization method to solve the problems of the prior art in that the false alarm probability and missed alarm probability are high when the signal-to-noise ratio is 0db, and the anti-interference ability in the time domain and frequency domain is weak.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] A data link wireless communication timing synchronization method comprises the following steps:

[0006] S1. Construct synchronization frame information;

[0007] S2. Send a frequency hopping synchronization frame information once, and then send another frequency hopping synchronization frame information;

[0008] S3, the synchronization frame information TOD check correct position as the basis for the synchronization timing time point, according to the sequence number of different jumps to determine the effective timing synchronization position;

[0009] In step S1, a synchronization frame is constructed, including:

[0010] S11, construct synchronization area;

[0011] S12, constructing a PN sequence area, the PN sequence area including multiple groups of PN sequences;

[0012] S13: Construct a TOD area, and perform CRC check, RS encoding, and 8x spread spectrum processing on the TOD area;

[0013] S14, constructing a free area, the free area including eight bytes of free bits;

[0014] In step S12, constructing a PN sequence area includes:

[0015] The PN sequence area includes four groups of 127-bit PN sequences. The four groups of PN sequences are composed of four groups of gold sequences. The gold sequences are obtained by modulo-2 addition of two m-sequence pairs. The four groups of gold sequences are obtained by modulo-2 addition of the same m-sequence pairs with different initial phases. The m-sequence level is 7 and the period is 127 bits.

[0016] Furthermore, in step S11, a synchronization area is constructed, including:

[0017] The synchronization area is an 8μs pilot synchronization area, of which 2μs is used for frequency switching and waiting for frequency switching to stabilize, and 6μs is used for demodulation system bit synchronization.

[0018] Furthermore, in step S122, four groups of PN sequences include:

[0019] localparam FRAME_head_m1 = 127'hPN1;

[0020] localparam FRAME_head_m2 = 127'hPN2;

[0021] localparam FRAME_head_m3 = 127'hPN3;

[0022] localparam FRAME_head_m4 = 127'hPN4.

[0023] Furthermore, in step S13, constructing a TOD area includes:

[0024] S131. Perform CRC check on TOD area information;

[0025] S132, performing RS encoding based on the TOD area information of step S131;

[0026] S133. Perform 8-fold spread spectrum based on the TOD area information in step S132.

[0027] Furthermore, in step S131, CRC check includes:

[0028] Perform CRC check on the three-byte frequency hopping sequence number, one-byte frequency hopping frequency mask, one-byte synchronization frame sequence number, and one-byte modulation information and rate information in the TOD area to generate a one-byte CRC check bit. The CRC check polynomial is: 8 + x 5 + x³ + x² + x + 1.

[0029] Furthermore, in step S132, RS encoding includes:

[0030] The three-byte frequency hopping sequence number, one-byte frequency hopping frequency mask, one-byte synchronization frame sequence number, one-byte modulation information and rate information, and one-byte CRC check bit of the TOD area are RS-encoded. The RS encoding uses the IP provided by Vivado to generate RS (112,56).

[0031] Furthermore, in step S133, the 8-fold spectrum spreading includes:

[0032] The RS (112, 56) is spread 8 times to form 896 bits of information data.

[0033] Furthermore, in step S2, the frequency hopping synchronization frame information is sent once, and then the frequency hopping synchronization frame information is sent another time, including:

[0034] The synchronization frame information of another frequency hopping uses the same PN sequence group as the previous frequency hopping. The difference from the TOD area of ​​the previous hop is that the frequency hopping sequence number is reduced by one compared with the previous hop, and the CRC check value and RS check are recalculated.

[0035] Furthermore, in step S3, determining a valid timing synchronization position includes:

[0036] S31, taking the end time point of the spread spectrum as the synchronization timing time point, and taking the end time point of the last hop spread spectrum as the effective timing synchronization position according to the sequence position of different hops;

[0037] S32. At the receiving and demodulating end, if the CRC check of the last hop is correct, it is used as the timing synchronization position. Otherwise, the other synchronization hops with correct CRC check are used as valid timing synchronization position identifiers, and corresponding delays are made according to the synchronization sequence number to obtain the final synchronization timing position.

[0038] Compared with the prior art, the data link wireless communication timing synchronization method described in the present invention has the following beneficial effects:

[0039] (1) Multiple groups of PN sequences are used as the basis for synchronization timing. When the number of valid synchronization symbols is detected, the TOD after the PN sequence number is detected. The TOD is 8 times or other multiple spread spectrum. RS encoding and decoding or other encoding and decoding methods are used to improve the signal-to-noise ratio. CRC check or cumulative check is performed on the information content to improve information security. The correct check position is used as the basis for the synchronization timing time point. The effective timing position is determined according to the sequence position of different hops.

[0040] (2) Reduce the false alarm probability and missed alarm probability when the signal-to-noise ratio is 0dB, thereby improving frame synchronization performance.

[0041] (3) Strengthen the anti-interference capability in time domain and frequency domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0043] Figure 1 This is a schematic diagram of a theoretical performance curve of frame synchronization with a length of 48 according to an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a synchronization frame structure definition according to an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of CRC generation logic according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of a theoretical performance curve for frame synchronization plus checksum of a sequence length of 127 according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0048] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0049] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0050] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0051] Glossary:

[0052] TOD (Time of Day) is a time synchronization technology based on the computer system clock. It synchronizes the computer system clock to the global standard time. This concept is borrowed here to transmit information in the frequency domain (hopping frequency) and time domain (hopping sequence number).

[0053] like Figures 1 to 4 As shown, a data link wireless communication timing synchronization method includes the following steps:

[0054] The following steps are involved:

[0055] S1. Construct synchronization frame information;

[0056] S2. Send a frequency hopping synchronization frame information once, and then send another frequency hopping synchronization frame information;

[0057] S3. The correct position of the synchronization frame information TOD check is used as the basis for the synchronization timing time point, and the effective timing synchronization position is determined according to the sequence position of different hops.

[0058] The specific implementation is as follows:

[0059] 1. Common synchronization timing method:

[0060] Conventional synchronization and timing technology involves the transmitter sending a PN sequence, which the receiver uses to perform channel correlation. Based on the correlation results, the receiver determines whether the received information is synchronized and generates subsequent receive timing information for the system. A PN sequence (pseudo-noise sequence) is a special binary sequence commonly used as a pseudo-random signal in communication systems. It is primarily used in spread spectrum communications, spread spectrum modulation, and wireless communication synchronization and encryption. PN sequence synchronization and timing are crucial aspects of its application, particularly ensuring that the receiver accurately synchronizes to the transmitter's signal to ensure accurate and reliable data transmission.

[0061] 1. Basic principles of PN sequence:

[0062] Definition: A PN sequence is generated using a specific feedback shift register. Its characteristic is that the autocorrelation function of the sequence is very large when the delay is zero, but very small at other delays. This property gives the PN sequence excellent autocorrelation and cross-correlation characteristics, making it ideal for use as a synchronization signal.

[0063] 2. PN sequence generation method:

[0064] Typically, a PN sequence can be generated using a linear feedback shift register (LFSR). The initial state of the LFSR and the feedback polynomial determine the specific form of the sequence.

[0065] For example, the feedback polynomial for a common 8-bit PN sequence can be

[0066] x^8 + x^4 + x^3 + x^2 + 1.

[0067] 3. Principle of synchronous timing:

[0068] In a communication system, the receiver needs to be accurately synchronized with the transmitter's signal in order to correctly decode the information. There are several main methods for PN sequence synchronization timing:

[0069] Correlation detection: The receiver correlates the received signal with a locally generated PN sequence. If the signal is well synchronized with the clock, the correlation value will be high, triggering the synchronization process.

[0070] A correlation detector is typically used to measure the correlation between the received signal and the locally generated sequence. When a sufficiently high correlation is detected, the correct synchronization point can be considered to have been found.

[0071] Phase-locked loop (PLL): A phase-locked loop (PLL) is used to track and lock the phase of the received signal. The PLL automatically adjusts the receiver's local clock frequency and phase to synchronize with the transmitter's clock. A PLL typically consists of a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). The phase detector compares the input signal's phase with that of a reference signal, and the loop filter adjusts the VCO's output to minimize phase error.

[0072] Timing Recovery: In some systems, it may also be necessary to accurately recover the signal's timing, that is, to determine the exact arrival time of each bit. This can be achieved by sampling the received signal and performing timing analysis. Timing recovery typically involves sampling the signal and detecting edges to accurately determine when each data bit begins and ends.

[0073] 4. Common synchronous timing technology implementation steps:

[0074] Generate local PN sequence: Generate the same PN sequence at the receiving end as that at the transmitting end.

[0075] Correlation operation: The received signal is correlated with the locally generated PN sequence.

[0076] Synchronization judgment: Determine whether synchronization is achieved based on the size of the correlation value.

[0077] PLL Adjustment: If more precise synchronization is required, the clock can be further adjusted using PLL technology.

[0078] Data decoding: Once synchronization is achieved, decoding of the data can begin.

[0079] Through the above method, the receiving end can accurately synchronize with the PN sequence of the transmitting end, thereby ensuring the accuracy and reliability of data transmission.

[0080] 2. Measurement of frame synchronization performance:

[0081] In a complex electromagnetic environment, a high signal-to-noise ratio working environment, and a low signal-to-noise ratio working environment, how to improve the reliability of synchronization, that is, to ensure a low synchronization false alarm probability and missed detection probability is the main issue considered by the present invention. The missed detection probability ( ) and false alarm probability ( ) are two important indicators for measuring frame synchronization performance.

[0082] 1. Calculation of missed detection probability:

[0083] Channel noise and interference can cause transmission errors in some code elements of the frame header synchronization code group in the information code stream, resulting in incorrect recognition by the frame header identifier. This can lead to the error of misidentifying the absence of synchronization codes when synchronization codes are present. The probability of this happening is called the missed detection probability, which is expressed as Taking a 7-bit synchronization code as an example, if the decision threshold is set to 6, when a single-bit synchronization code error occurs, the adder output is 5, which is less than the decision threshold and results in a missed detection. If the decision threshold is lowered to 4, no errors occur. Therefore, the missed detection probability is related to the decision threshold and, more specifically, the number of bits of synchronization code error tolerance.

[0084] set up is the probability of a code element error, is the number of synchronization code group symbols, is the maximum number of code elements allowed to have errors, then the probability of error-free transmission of synchronization code elements is , the probability of a 1-bit error is ,occur The probability of error is .because is the maximum number of code elements that can be erroneous, then the probability that the synchronization code identifier can correctly detect is , accordingly, the missed detection probability is

[0085] ;

[0086] in, for Winning The number of combinations of , where r is the value variable used to calculate the number of combinations, which has a similar physical meaning to m and indicates the situation where r errors occur.

[0087] For common modulations such as BPSK and QPSK, the theoretical bit error rate under different SNRs can be obtained as the probability of a code element error. , from which the theoretical missed detection probability can be calculated.

[0088] 2. Calculation of false alarm probability:

[0089] When receiving symbol data streams or when there is only noise without any signal, the identifier may mistakenly identify random code or other random interference as a synchronization code, thereby sending out an incorrect frame synchronization signal. The probability of being mistakenly judged as a valid synchronization is called the false alarm probability, which is expressed as express.

[0090] Similarly, assuming is the number of synchronization code group symbols, The maximum number of code elements that can cause errors. Since each code element in the information code stream is equal to "0" or "1", the probability of the code element entering the shift register is equal to The probability that all code elements are the same as the synchronization code is , there is a different probability of ,have The probability of a different bit is , then it is allowed to have The probability of an error within a bit is , that is, when allowing The false alarm probability in the case of bit synchronization code error is:

[0091] ;

[0092] The ideal situation is that both the false alarm probability and the missed detection probability of the correlation peak detection are small, so that a reliable judgment result can be obtained, but the false alarm probability and the missed detection probability cannot be reduced at the same time.

[0093] If a 7-bit synchronization code is used as the synchronization code group, assuming the symbol error rate is ,exist and The false detection probability and false alarm probability are:

[0094] ;

[0095] ;

[0096] and

[0097] ;

[0098] ;

[0099] If a 13-bit synchronization code is used, assuming the symbol error rate is ,exist and The false detection probability and false alarm probability are:

[0100] ;

[0101] ;

[0102] and

[0103] ;

[0104] ;

[0105] It can be seen from this that when the number of code elements is constant, the code element error rate remains unchanged, and the number of error code elements allowed is If the synchronization code length and the number of error symbols allowed are increased, the probability of missed detection decreases, but the probability of false alarm increases. Conversely, if the number of synchronization code bits is increased, the probability of false alarm decreases, but the probability of missed detection increases. Therefore, the choice of synchronization code length and the number of error symbols allowed requires a compromise between the probability of missed detection and the probability of false alarm.

[0106] like Figure 1 As shown in the figure Theoretical false alarm probability and missed detection probability of synchronization sequence, where the threshold is , which is the number of correct symbols. As can be seen from the figure, the false alarm probability and missed detection probability are related to the threshold selection: a higher threshold reduces the false alarm probability and increases the missed detection probability. The SNR also influences the missed detection probability: a lower SNR increases the missed detection probability. In practical applications, the threshold and synchronization code length should be selected based on the minimum operating SNR to ensure that the false alarm and missed detection probabilities meet system requirements.

[0107] Example 1:

[0108] The present invention sets the PN sequence to 128 bits. There are four types of PN sequences, which are composed of 128×4=512 bits. After the four groups of PN sequences, a TOD area is given. The data information content that constitutes the TOD is considered as 7 bytes, of which 6 bytes are the information itself and 1 byte is the information CRC check. These 7 bytes are spread 8 times and then encoded according to 1 / 2RS to form 7×8×8×2=896 bits of data that are sent to the channel.

[0109] In order to improve the system's anti-interference performance, after the above-mentioned hop information is sent, the information of another hop is given, the same PN sequence group is sampled, and the TOD content number is reduced by one to ensure that after the previous hop is interfered, the next hop can synchronize timing normally.

[0110] 1. Frame structure definition:

[0111] like Figure 2 As shown, at the beginning of the frame, an 8μs pilot synchronization area is provided, of which 2μs is used for frequency switching and waiting for frequency switching to stabilize, and 6μs is used for demodulation system bit synchronization;

[0112] Four 127-bit PN sequences are composed of four gold sequences. Each PN sequence is generated by performing modulo-2 addition on a preferred pair of m sequences to form a 127-bit PN sequence. In the present invention, the four PN sequences are generated by modulo-2 addition on the same preferred pair but different initial phases to obtain four gold sequences. This PN sequence can achieve good cross-correlation and autocorrelation characteristics.

[0113] TOD area: The original information includes the frequency hopping sequence number (3 bytes), the frequency hopping frequency mask (1 byte), the synchronization frame number, the modulation information and the rate information (2 bytes). The above 6 bytes of information are CRC checked (1 byte, TOD check). The 7 bytes of information combined with the check are RS-encoded (112, 56). The 112-bit original information is 56 bits, and the RS check bit is 56 bits. The 112-bit information is spread 8 times to form 896 bits of information.

[0114] Spare bits: To meet the 100µs per hop requirement, 64 spare bits are added to satisfy the time requirement.

[0115] 2. PN sequence:

[0116] Generated by m-sequence, 127-bit period m-sequence, level 7, its preferred pairs are: 203, 211, 217, 235, 277, 313, 325, 345, 367; two of these groups are used as the preferred pairs to generate four groups of PN sequences, the generated PN sequences are:

[0117] localparam FRAME_head_m1 = 127'hPN1;

[0118] localparam FRAME_head_m2 = 127'hPN2;

[0119] localparam FRAME_head_m3 = 127'hPN3;

[0120] localparam FRAME_head_m4 = 127'hPN4;

[0121] 4 groups of 127-bit PN sequences are formed;

[0122] 3.CRC check:

[0123] like Figure 3 As shown, the check polynomial is: x 8 + x 5 + x³ + x² + x + 1, g0 ~gn are 1 1 1 1 01 0 0 1, where "0" indicates disconnection and "1" indicates connection. M(x) is the input information sequence to be verified, CLK is the system operating clock, D represents a D flip-flop, Q1 ~ Qn are the output results of the D flip-flops, and the "⊕" symbol indicates that the two input signals are XORed and output to the next D flip-flop, and Qn outputs the result.

[0124] 4. RS codec:

[0125] RS encoding and decoding uses the IP provided by Vivado to generate RS (112, 56). This sequence has good error correction capabilities. After CRC check, the original information generates 7 bytes of data, totaling 56 bits. After RS ​​(112, 56) encoding, 112 bits of data are obtained.

[0126] 5.8 times spread spectrum:

[0127] The binary code 01110010 is used as the spreading code to perform 8-fold spreading on the TOD segment information. The 112-bit information is spread by 8 to generate 112 × 8 = 896 bits of data.

[0128] like Figure 4 The figure shows the effect simulation of the present invention. It is the false alarm probability and missed alarm probability curve output under different thresholds (i.e. matching values) when the length of the gold sequence is 127 for frame synchronization. The horizontal axis is the threshold and the vertical axis is the probability. At the same time, when the signal-to-noise ratio is between -10dB and 4dB, Figure 4 The first blue line on the left is the false alarm probability, and the other eight lines are the missed alarm probabilities.

[0129] The beneficial effects and advantages of the present invention are as follows:

[0130] (1) Multiple groups of PN sequences are used as the basis for synchronization timing. When the number of valid synchronization symbols is detected, the TOD after the PN sequence number is detected. The TOD is 8 times or other multiple spread spectrum. RS encoding and decoding or other encoding and decoding methods are used to improve the signal-to-noise ratio. CRC check or cumulative check is performed on the information content to improve information security. The correct check position is used as the basis for the synchronization timing time point. The effective timing position is determined according to the sequence position of different hops.

[0131] (2) Reduce the false alarm probability and missed alarm probability when the signal-to-noise ratio is 0dB, thereby improving frame synchronization performance.

[0132] (3) Strengthen the anti-interference capability in time domain and frequency domain.

[0133] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A data link wireless communication timing synchronization method, characterized in that: The following steps are involved: S1. Construct synchronization frame information; S2. Send a frequency hopping synchronization frame information once, and then send another frequency hopping synchronization frame information; S3, the synchronization frame information TOD check correct position as the basis for the synchronization timing time point, according to the sequence number of different jumps to determine the effective timing synchronization position; In step S1, a synchronization frame is constructed, including: S11, construct synchronization area; S12, constructing a PN sequence area, the PN sequence area including multiple groups of PN sequences; S13: Construct a TOD area, and perform CRC check, RS encoding, and 8x spread spectrum processing on the TOD area; S14, constructing a free area, the free area including eight bytes of free bits; In step S12, constructing a PN sequence area includes: The PN sequence area includes four groups of 127-bit PN sequences. The four groups of PN sequences are composed of four groups of gold sequences. The gold sequences are obtained by modulo-2 addition of two m-sequence pairs. The four groups of gold sequences are obtained by modulo-2 addition of the same m-sequence pairs with different initial phases. The m-sequence level is 7 and the period is 127 bits.

2. A data link wireless communication timing synchronization method according to claim 1, characterized in that: In step S11, a synchronization area is constructed, including: The synchronization area is an 8μs pilot synchronization area, of which 2μs is used for frequency switching and waiting for frequency switching to stabilize, and 6μs is used for demodulation system bit synchronization.

3. The data link wireless communication timing synchronization method according to claim 1, wherein: In step S122, four groups of PN sequences include: localparam FRAME_head_m1 = 127'hPN1; localparam FRAME_head_m2 = 127'hPN2; localparam FRAME_head_m3 = 127'hPN3; localparam FRAME_head_m4 = 127'hPN4.

4. The data link wireless communication timing synchronization method according to claim 1, wherein: In step S13, constructing a TOD area includes: S131. Perform CRC check on TOD area information; S132, performing RS encoding based on the TOD area information of step S131; S133. Perform 8-fold spread spectrum based on the TOD area information in step S132.

5. A data link wireless communication timing synchronization method according to claim 4, characterized in that: In step S131, CRC check includes: Perform CRC check on the three-byte frequency hopping sequence number, one-byte frequency hopping frequency mask, one-byte synchronization frame sequence number, and one-byte modulation information and rate information in the TOD area to generate a one-byte CRC check bit. The CRC check polynomial is: 8 + x 5 + x³+ x² + x + 1.

6. A data link wireless communication timing synchronization method according to claim 4, characterized in that: In step S132, RS encoding includes: The three-byte frequency hopping sequence number, one-byte frequency hopping frequency mask, one-byte synchronization frame sequence number, one-byte modulation information and rate information, and one-byte CRC check bit of the TOD area are RS-encoded. The RS encoding uses the IP provided by Vivado to generate RS (112,56).

7. A data link wireless communication timing synchronization method according to claim 4, characterized in that: In step S133, 8-fold spectrum spreading is performed, including: The RS (112, 56) is spread 8 times to form 896 bits of information data.

8. The data link wireless communication timing synchronization method according to claim 1, wherein: In step S2, a frequency hopping synchronization frame is sent once, and then another frequency hopping synchronization frame is sent, including: The synchronization frame information of another frequency hopping uses the same PN sequence group as the previous frequency hopping. The difference from the TOD area of ​​the previous hop is that the frequency hopping sequence number is reduced by one compared with the previous hop, and the CRC check value and RS check are recalculated.

9. The data link wireless communication timing synchronization method according to claim 1, characterized in that: In step S3, determining a valid timing synchronization position includes: S31, taking the end time point of the spread spectrum as the synchronization timing time point, and taking the end time point of the last hop spread spectrum as the effective timing synchronization position according to the sequence position of different hops; S32. At the receiving and demodulating end, if the CRC check of the last hop is correct, it is used as the timing synchronization position. Otherwise, the other synchronization hops with correct CRC check are used as valid timing synchronization position identifiers, and corresponding delays are made according to the synchronization sequence number to obtain the final synchronization timing position.

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