Semiconductor device and preparation method thereof, memory, chip and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, a memory, a chip and electronic equipment, relates to the technical field of semiconductors, and is used for improving the electrical difference between a memory array and a peripheral logic device. The semiconductor device includes a substrate, a first fin, a first gate, a second fin, a second gate, and a work function layer. The substrate comprises an N-type doped region and a P-type doped region. The first grid electrode is arranged on the first fin in a crossing mode, and the first fin and the first grid electrode are arranged on the N-type doped region of the substrate. The second grid electrode is arranged on the second fin in a crossing mode, and the second fin and the second grid electrode are arranged on the P-type doped region of the substrate. The first gate is connected with the second gate. The work function layer includes a first portion, a second portion, and a third portion. The first portion covers a top surface and a side surface of the first fin, the second portion covers a top surface and a side surface of the second fin, and the third portion is located between the first fin and the second fin. The work function of the third part is larger than that of the second part, and the work function of the second part is larger than that of the first part.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device, a method for manufacturing the same, a memory, a chip, and an electronic device. Background Art

[0002] A memory includes a storage array and peripheral logic devices located outside the storage array. For a cache memory, such as a static random access memory (SRAM), its information storage relies on control signals and digital signals transmitted by the peripheral logic devices and two nodes of an inverter in the storage array for storage.

[0003] An inverter is composed of a pull-down N-type transistor (PD) and a pull-up P-type transistor (PU) located on the same substrate. The gates of the PD transistor and the PU transistor are connected, and the thickness of the work function layer of the PD transistor is different from that of the PU transistor, resulting in a metal boundary effect at the junction of the PD transistor and the PU transistor. That is, there is a metal boundary effect in the storage array of the memory, while there is no metal boundary effect in the peripheral logic devices, which leads to an electrical difference between the peripheral logic devices and the storage array, affecting the reading and writing of the memory and causing a yield problem of the chip. Summary of the Invention

[0004] Embodiments of this application provide a semiconductor device, a method for manufacturing the same, a memory, a chip, and an electronic device, which are used to reduce the electrical difference between a storage array and peripheral logic devices.

[0005] To achieve the above object, this application adopts the following technical solutions:

[0006] In a first aspect of embodiments of this application, a semiconductor device is provided, including a substrate, a first fin, a first gate, a second fin, a second gate, and a work function layer. The substrate includes an N-type doped region and a P-type doped region. The first gate straddles the first fin, and both the first fin and the first gate are disposed on the N-type doped region of the substrate. The second gate straddles the second fin, and both the second fin and the second gate are disposed on the P-type doped region of the substrate. The first gate and the second gate are connected. The work function layer includes a first part, a second part, and a third part. The first part covers the top surface and two opposite side surfaces of the first fin, the second part covers the top surface and two opposite side surfaces of the second fin, and the third part is located between the first fin and the second fin and connects the first part and the second part. The work function of the third part is greater than that of the second part, and the work function of the second part is greater than that of the first part.

[0007] In the semiconductor device provided by the embodiment of the present application, the work function of the third part is greater than that of the second part, and the work function of the second part is greater than that of the first part. That is, the work function of the third part is the largest, and the third part is connected to the first part and the second part. The solution of the embodiment of the present application enhances the metal boundary effect of the first part and the second part by setting the third part of the work function layer, which helps to reduce the threshold voltage of the transistor where the second part is located, and further improves the electrical property difference between the memory array and the peripheral logic device where the semiconductor device is located.

[0008] The semiconductor device provided by the embodiment of the present application is applied to a memory, which can reduce the threshold voltage of the pull-up transistor in the memory array to improve the electrical property difference (such as threshold voltage, threshold current, etc.) between the memory array and the peripheral logic device, make the timing of the memory array and the peripheral logic device match, enable the memory array to complete the write information operation before the peripheral logic device is turned off, improve the memory performance, and further improve the chip yield.

[0009] In a possible implementation manner, the thickness of the third part is greater than that of the second part, and the thickness of the second part is greater than that of the first part. In this way, by changing the thickness of the third part, the work functions of the first part, the second part, and the third part are different, the diffusion degree of the third part is reduced, and the metal boundary effect is enhanced.

[0010] In a possible implementation manner, the materials of the first part, the second part, and the third part are the same. In this way, the materials of the work function layer are the same, which can better control the work functions of the first part, the second part, and the third part, and is convenient for preparation and easy to implement. [[ID=!1]]

[0011] In a possible implementation manner, along the direction from the first fin to the second fin, the size of the third part is 0.25 times to 0.5 times the distance between the first fin and the second fin. In this way, the metal boundary effect can be further enhanced.

[0012] In a possible implementation manner, the distance between the third part and the first fin is equal to the distance between the third part and the second fin. In this way, the third part is located in the middle of the first fin and the second fin, and the metal boundary effect can be further enhanced.

[0013] In a possible implementation manner, the first part and the second part also extend between the first fin and the second fin. In this way, the first part, the second part, and the third part are connected and disposed on the first fin and the second fin.

[0014] In a possible implementation manner, the material of the work function layer includes titanium nitride or tantalum nitride. In this way, an implementation manner of the work function layer is provided.

[0015] In a possible implementation, the semiconductor device further includes a diffusion layer disposed on the side of the work function layer away from the substrate. In this way, the diffusion of aluminum ions and oxygen ions can be achieved.

[0016] In a possible implementation, the material of the diffusion layer includes titanium aluminum alloy. In this way, the diffusion of aluminum ions and oxygen ions can be achieved.

[0017] In the second aspect of the embodiments of the present application, a semiconductor device is provided, including a substrate, a first fin, a first gate, a second fin, a second gate, and a work function layer. The substrate includes an N-type doped region and a P-type doped region. The first gate straddles the first fin, and both the first fin and the first gate are disposed on the N-type doped region of the substrate. The second gate straddles the second fin, and both the second fin and the second gate are disposed on the P-type doped region of the substrate. The first gate and the second gate are connected. The work function layer includes a first portion, a second portion, and a third portion. The first portion covers the top surface and two opposite side surfaces of the first fin, the second portion covers the top surface and two opposite side surfaces of the second fin, the third portion is located between the first fin and the second fin and connects the first portion and the second portion. The thickness of the third portion is greater than the thickness of the second portion, and the thickness of the second portion is greater than the thickness of the first portion. The materials of the first portion, the second portion, and the third portion are the same.

[0018] In the semiconductor device provided by the embodiments of the present application, the thickness of the third portion is greater than the thickness of the second portion, the thickness of the second portion is greater than the thickness of the first portion, and the materials of the first portion, the second portion, and the third portion are the same, which can make the work function of the third portion greater than the work function of the second portion, and the work function of the second portion greater than the work function of the first portion, that is, the work function of the third portion is the largest, and the third portion connects the first portion and the second portion. The solution of the embodiments of the present application enhances the metal boundary effect of the first portion and the second portion by setting the third portion of the work function layer, helps to reduce the threshold voltage of the transistor where the second portion is located, and further improves the electrical property difference between the memory array and the peripheral logic device where the semiconductor device is located.

[0019] The semiconductor device provided by the embodiments of the present application is applied to a memory, which can reduce the threshold voltage of the pull-up transistor in the memory array to improve the electrical property difference (such as threshold voltage, threshold current, etc.) between the memory array and the peripheral logic device, make the timing of the memory array and the peripheral logic device match, enable the memory array to complete the write information operation before the peripheral logic device is turned off, improve the memory performance, and further improve the chip yield.

[0020] In a possible implementation, along the direction from the first fin to the second fin, the size of the third portion is 0.25 times to 0.5 times the distance between the first fin and the second fin. In this way, the metal boundary effect can be further enhanced.

[0021] In a third aspect of the embodiments of the present application, a method for manufacturing a semiconductor device is provided, including: providing a substrate, the substrate including an N-type doped region and a P-type doped region; forming a first fin and a second fin on the substrate; the first fin and the second fin having a gap therebetween; the first fin being formed on the N-type doped region, and the second fin being formed on the P-type doped region; forming a work function layer; the work function layer including a first portion, a second portion, and a third portion; the first portion being formed on the top surface and two opposite side surfaces of the first fin; the second portion being formed on the top surface and two opposite side surfaces of the second fin; the third portion being formed between the first fin and the second fin and connecting the first portion and the second portion; the work function of the third portion being greater than the work function of the second portion, and the work function of the second portion being greater than the work function of the first portion; forming a first gate and a second gate; the first gate being disposed across the work function layer on a side away from the first fin, the second gate being disposed across the work function layer on a side away from the second fin, and the first gate and the second gate being connected.

[0022] In the method for manufacturing a semiconductor device provided by the embodiments of the present application, the work function of the formed third portion is greater than the work function of the second portion, and the work function of the second portion is greater than the work function of the first portion, that is, the work function of the third portion is the largest, and the third portion connects the first portion and the second portion. The solution of the embodiments of the present application enhances the metal boundary effect of the first portion and the second portion by forming the third portion of the work function layer, which helps to reduce the threshold voltage of the transistor where the second portion is located, and further improves the electrical property difference between the memory array and the peripheral logic device where the semiconductor device is located.

[0023] In addition, the manufacturing method provided by the embodiments of the present application does not require an additional mask, and can be achieved only by changing the mask shape or etching conditions at one time, without increasing additional manufacturing costs.

[0024] The semiconductor device provided by the embodiments of the present application is applied to a memory, and can reduce the threshold voltage of the pull-up transistor in the memory array to improve the electrical property difference (such as threshold voltage, threshold current, etc.) between the memory array and the peripheral logic device, so that the timing of the memory array and the peripheral logic device is matched, and the memory array can complete the write information operation before the peripheral logic device is turned off, improving the memory performance and further improving the chip yield.

[0025] In a possible implementation, forming a work function layer includes: forming a first sub-work function film on a substrate; removing a part of the first sub-work function film to form a first sub-work function layer; the first sub-work function layer is formed between a first fin and a second fin; forming a second sub-work function film on the substrate and covering the first sub-work function layer; removing a part of the second sub-work function film to form a second sub-work function layer; the second sub-work function layer is formed on the top surface and two opposite side surfaces of the second fin and further extends to the side of the first sub-work function layer away from the substrate; forming a third sub-work function layer on the substrate; the third sub-work function layer is formed on the top surface and two opposite side surfaces of the first fin and further extends to the side of the second sub-work function layer away from the substrate; the first sub-work function layer, the second sub-work function layer and the third sub-work function layer constitute the work function layer. In this way, the thicknesses of the first part, the second part and the third part in the work function layer can be better controlled.

[0026] In a possible implementation, after forming the work function layer and before forming the first gate and the second gate, the method further includes: forming a diffusion layer on the side of the work function layer away from the substrate. In this way, the diffusion of aluminum ions and oxygen ions can be realized.

[0027] In a fourth aspect of the embodiments of the present application, a method for manufacturing a semiconductor device is provided, including: providing a substrate including an N-type doped region and a P-type doped region; forming a first fin and a second fin on the substrate; there is a gap between the first fin and the second fin; the first fin is formed on the N-type doped region, and the second fin is formed on the P-type doped region; forming a work function layer; the work function layer includes a first part, a second part and a third part; the first part is formed on the top surface and two opposite side surfaces of the first fin; the second part is formed on the top surface and two opposite side surfaces of the second fin; the third part is formed between the first fin and the second fin and connects the first part and the second part; the thickness of the third part is greater than that of the second part, the thickness of the second part is greater than that of the first part, and the materials of the first part, the second part and the third part are the same; forming a first gate and a second gate; the first gate straddles the side of the work function layer away from the first fin, the second gate straddles the side of the work function layer away from the second fin, and the first gate and the second gate are connected.

[0028] The manufacturing method of the semiconductor device provided by the embodiment of the present application forms a third part with a thickness greater than that of the formed second part, the formed second part has a thickness greater than that of the formed first part, and the materials of the first part, the second part, and the third part are the same. It can make the work function of the formed third part greater than that of the formed second part, and the work function of the formed second part greater than that of the formed first part, that is, the work function of the third part is the largest, and the third part connects the first part and the second part. The solution of the embodiment of the present application enhances the metal boundary effect of the first part and the second part by forming the third part of the work function layer, which helps to reduce the threshold voltage of the transistor where the second part is located, and further improves the electrical property difference between the memory array and the peripheral logic device where the semiconductor device is located.

[0029] In addition, the manufacturing method provided by the embodiment of the present application does not require an additional mask, and only needs to change the mask shape or etching conditions once to achieve, without increasing additional manufacturing costs.

[0030] The semiconductor device provided by the embodiment of the present application is applied to a memory, which can reduce the threshold voltage of the pull-up transistor in the memory array to improve the electrical property difference (such as threshold voltage, threshold current, etc.) between the memory array and the peripheral logic device, make the timing of the memory array and the peripheral logic device match, enable the memory array to complete the write information operation before the peripheral logic device is turned off, improve the memory performance, and further improve the chip yield.

[0031] In the fifth aspect of the embodiment of the present application, a memory is provided, including: a controller and the semiconductor device of the first aspect or the second aspect, and the controller is electrically connected to the semiconductor device.

[0032] The memory provided in the fifth aspect of the embodiment of the present application includes the semiconductor device of any one of the first aspect or the second aspect, and its beneficial effects are the same as those of the semiconductor device, and will not be elaborated here.

[0033] In the sixth aspect of the embodiment of the present application, a chip is provided, including: the semiconductor device as in the first aspect or the second aspect and a packaging layer; the semiconductor device is packaged in the packaging layer.

[0034] The chip provided in the sixth aspect of the embodiment of the present application includes the semiconductor device of any one of the first aspect or the second aspect, and its beneficial effects are the same as those of the semiconductor device, and will not be elaborated here.

[0035] In the seventh aspect of the embodiment of the present application, an electronic device is provided, including: a printed circuit board and the chip of the sixth aspect, and the printed circuit board is electrically connected to the memory.

[0036] The electronic device provided in the seventh aspect of the embodiments of the present application includes the chip of the sixth aspect, and its beneficial effects are the same as those of the chip, which will not be elaborated here. Description of the Drawings

[0037] Figure 1A Schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0038] Figure 1B Schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0039] Figure 2A Schematic diagram of the structure of a storage unit schemed in an embodiment of the present application;

[0040] Figure 2B Circuit diagram of a storage unit schemed in an embodiment of the present application;

[0041] Figure 3A Schematic diagram of the structure of a semiconductor device schemed in an embodiment of the present application;

[0042] Figure 3B Schematic diagram of the threshold voltage change of a storage array and peripheral logic devices schemed in an embodiment of the present application;

[0043] Figure 3C Timing simulation diagram of a storage array schemed in an embodiment of the present application;

[0044] Figure 4 Schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0045] Figure 5 Flow schematic diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0046] Figures 6A - 6N Process schematic diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0047] Figure 7 Schematic diagram of the structure of yet another semiconductor device provided in an embodiment of the present application;

[0048] Figure 8 Schematic diagram of the structure of yet another semiconductor device provided in an embodiment of the present application;

[0049] Figure 9 Schematic diagram of the structure of yet another semiconductor device provided in an embodiment of the present application;

[0050] Figure 10A Schematic diagram of the threshold voltage value distribution of a storage array and peripheral logic devices provided in an embodiment of the present application;

[0051] Figure 10B Schematic diagram of threshold voltage value distribution of another storage array and peripheral logic device provided by an embodiment of the present application

[0052] Figure 10C Schematic diagram of electrical property change of a storage array and peripheral logic device provided by an embodiment of the present application.

[0053] Reference numerals

[0054] 1 - Electronic device; 11 - Storage device; 12 - Processor; 13 - Input device; 14 - Output device; 111 - External memory; 112 - Internal memory; 121 - Arithmetic unit; 122 - Controller; 15 - Display module; 16 - Middle frame; 17 - Housing; 18 - Cover plate; 200 - Storage cell; 210 - Storage array; 220 - Peripheral logic device; 300 - Semiconductor device; 310 - Substrate; 311 - N-type doped region; 312 - P-type doped region; 400 - First transistor; 410 - First gate; 420 - First fin; 401 - First work function layer; 500 - Second transistor; 510 - Second gate; 520 - Second fin; 501 - Second work function layer; 600 - Work function layer; 610 - First part; 620 - Second part; 630 - Third part; 601 - First sub-work function layer; 602 - Second sub-work function layer; 603 - Third sub-work function layer; 710 - Diffusion layer. Detailed implementation manners

[0055] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0056] Hereinafter, terms such as "second" and "first" are only for convenience of description, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "second", "first", etc. may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0057] In addition, in the embodiments of the present application, orientation terms such as "upper", "lower", "left", "right", etc. may include but are not limited to being defined relative to the schematic placement of components in the drawings. It should be understood that these directional terms may be relative concepts, and they are used for relative description and clarification, and they may change correspondingly according to the change of the orientation of the components in the drawings.

[0058] In the embodiments of the present application, unless otherwise clearly specified or limited, the term "connection" shall be understood in a broad sense. For example, "connection" may be a fixed connection, a detachable connection, or an integral one; it may be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" may be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" may be direct contact or indirect contact through an intermediate medium.

[0059] In the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0060] Next, some terms in the embodiments of the present application will be explained first.

[0061] Memory: In a chip, the memory is a memory component used to store program and data information. The information stored in a common memory is stored in the chip in binary units, that is, stored in the memory as "logical 0" or "logical 1". In physical devices, it is usually achieved by means of high or low voltage, large or small resistance, large or small charge amount, etc.

[0062] Bit: It is the smallest unit of the amount of information stored in a memory. n bits can represent 2^n states. For example, one bit can represent two states, 0 or 1. Two bits can represent four states, 00, 01, 10, 11, and so on. That is to say, if the physical information stored in a memory has m states, it is a log2m-bit memory.

[0063] Volatile Memory and Non-volatile Memory (NVM): According to whether the stored signal still exists after the external power supply of the chip is removed, memory can be divided into volatile memory and non-volatile memory. Volatile memory is represented by static random-access memory (SRAM) or dynamic random access memory (DRAM), and the storage of information requires continuous external power supply. When there is no external power supply, the stored information also disappears. Non-volatile memory is represented by traditional read-only memory (ROM), flash memory, ferroelectric random-access memory (FeRAM, ferroelectric field effect transistor, FeFET), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and phase-change random access memory (PCRAM). These non-volatile memories all achieve the characteristic of non-loss of information when power is off through their respective unique physical principles.

[0064] An embodiment of the present application provides an electronic device. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Among them, consumer electronic products such as mobile phones, tablets, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products such as smart door locks, TVs, remote controls, refrigerators, small household appliances for charging (such as soybean milk machines, floor cleaning robots), etc. Vehicle-mounted electronic products such as vehicle navigation devices, in-vehicle DVDs, etc. Financial terminal products such as ATMs, terminals for self-service business handling, etc. Communication electronic products such as servers, memories, radars, base stations and other communication devices.

[0065] An example of an electronic device is asFigure 1A As shown, the electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art can understand that Figure 1A the architecture of the electronic device 1 shown in Figure 1A does not limit the electronic device 1, and the electronic device 1 may include more or fewer components than those shown, or may combine some of the components shown, or may have a different arrangement of the components shown. Figure 1A For example, Figure 1A shown.

[0066] Among them, the storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area. Among them, the program storage area can store and back up the operating system, application programs required for at least one function (such as the sound playback function, the image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc.

[0067] The processor 12 is the control center of the electronic device 1, connects various parts of the entire electronic device 1 through various interfaces and lines, executes various functions of the electronic device 1 and processes data by running or executing software programs and / or modules stored in the storage device 11, and calling data stored in the storage device 11, thereby monitoring the entire electronic device 1. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors. For example, the processor 12 may integrate an application processor and a modem processor. Among them, the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above modem processor may not be integrated into the processor 12. The above application processor may be a central processing unit (CPU) for example. Figure 1A Taking the processor 12 as a CPU as an example in

[0068] The memory hierarchy divides the storage device 11 of the electronic device 1 into a hierarchical structure according to the response time. In some embodiments, the storage device 11 sequentially includes a CPU register, a cache, an internal memory 112, and an external memory 111 in the order from near to far from the CPU. Among them, the closer the memory is to the CPU, the smaller the capacity and the faster the speed.

[0069] Exemplarily, the external memory 111 may include any one or more of a hard disk, a magnetic disk, an optical disc, etc.

[0070] The input device 13 is used to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the electronic device. Exemplarily, the input device 13 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect touch operations of the user on or near the touch screen (such as operations of the user using a finger, a stylus, or any suitable object or accessory on or near the touch screen), and drive the corresponding connection device according to a pre-set program.

[0071] The output device 14 is used to output the input of the input device 13 and signals corresponding to the data stored in the storage device 11. For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the above-mentioned processor 12 can also control the output device 14 to output signals or not output signals.

[0072] It should be noted that Figure 1A The thick arrows in are used to represent the transmission of data, and the direction of the thick arrow represents the direction of data transmission. For example, the single arrow between the input device 13 and the internal memory 112 represents that the data received by the input device 13 is transmitted to the internal memory 112. Another example is that the double arrows between the arithmetic unit 121 and the internal memory 112 represent that the data stored in the internal memory 112 can be transmitted to the arithmetic unit 121, and the data processed by the arithmetic unit 121 can be transmitted to the internal memory 112. Figure 1A The thin arrows in represent the components that the controller 122 can control. Exemplarily, the controller 122 can control the external memory 111, the internal memory 112, the arithmetic unit 121, the input device 13, the output device 14, etc.

[0073] For the convenience of further explaining the structure of the electronic device 1, the electronic device 1 is taken as an example of a mobile phone for exemplary introduction below.

[0074] As Figure 1B shown, the electronic device 1 mainly includes a display module 15, a middle frame 16, a housing (or called a battery cover, a back shell) 17, and a cover plate 18.

[0075] The display module 15 has a light-emitting side where the display screen can be seen and a back surface disposed opposite to the light-emitting side. The back surface of the display module 15 is close to the middle frame 16, and the cover plate 18 is disposed on the light-emitting side of the display module 15.

[0076] The above-mentioned display module 15 includes a display panel (DP).

[0077] In a possible embodiment of the present application, the display module 15 is a liquid crystal display module. In this case, the above-mentioned display screen is a liquid crystal display (LCD). Based on this, the display module 15 further includes a backlight module (BLU) located on the back surface of the liquid crystal display screen (the side away from the side of the LCD for displaying the picture).

[0078] The backlight module can provide light sources for the liquid crystal display screen so that each subpixel in the liquid crystal display screen can emit light to achieve image display.

[0079] Alternatively, in another possible embodiment of the present application, the display module 15 is an organic light-emitting diode display module. In this case, the above-mentioned display screen is an organic light-emitting diode (OLED) display screen. Since an electroluminescent layer is provided in each subpixel of the OLED display screen, the OLED display screen can achieve self-luminescence after receiving the working voltage. In this case, the above-mentioned backlight module does not need to be provided in the display module 15 having the OLED display screen.

[0080] The cover plate 18 is located on the side of the display module 15 away from the middle frame 16. The cover plate 18 can be, for example, a cover glass (CG), and the cover glass can have a certain toughness.

[0081] The middle frame 16 is located between the display module 15 and the housing 17. The surface of the middle frame 16 away from the display module 15 is used to mount internal components such as a battery, a printed circuit board (PCB), a camera, an antenna, and a processor. After the housing 17 is covered with the middle frame 16, the above-mentioned internal components are located between the housing 17 and the middle frame 16.

[0082] Exemplarily, the internal memory 112 in the electronic device 1 can be disposed on the printed circuit board, and the internal memory 112 is electrically connected to the printed circuit board to achieve signal intercommunication.

[0083] As described above, the internal memory 112 may include a random access memory, a read-only memory, etc. According to the working principle, the random access memory may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), a phase change random access memory (PCRAM), a resistive random access memory (ReRAM), or a magnetoresistive random access memory (MRAM). Due to its advantages such as high storage speed, high reliability, and mature technology, the static random access memory is currently widely used in the cache memory or the internal memory 112.

[0084] Exemplarily, a chip including a storage array and peripheral logic devices may be disposed on a printed circuit board. Among them, the chip may be a packaged chip or may also be a bare chip without packaging. The embodiments of the present application do not limit this and can be reasonably set according to the actual situation.

[0085] The following embodiments of this article will be introduced by taking the internal memory 112 as a static random access memory as an example. Figure 2A Schematically shows an architecture diagram of a static random access memory. This static random access memory may also be integrated in the above CPU register or cache memory.

[0086] The memory includes a plurality of storage units. Among them, the plurality of storage units may be arranged in an array.

[0087] As Figure 2A shown, the storage unit 200 includes a storage array 210, peripheral logic devices 220, and an input / output (IO) area 230.

[0088] Exemplarily, the storage array 210 includes means for storing information.

[0089] The peripheral logic devices 220 include a row and column decoding address selection decoder, a precharge array, a write driver array, and a sense amplifier array.

[0090] Among them, the peripheral logic devices 220 include a first peripheral logic device 221, a second peripheral logic device 222, and a third peripheral logic device 223.

[0091] The first peripheral logic device 221, the second peripheral logic device 222, and the third peripheral logic device 223 are respectively disposed around the memory array 210, and are used to read and write information and perform signal transmission with the memory array 210. In the embodiments of the present application, the number of the peripheral logic devices 220 is not limited, and can be reasonably set according to actual situations.

[0092] The IO area 230 is used for input and output of signals.

[0093] In some embodiments, the memory cell 200 includes a plurality of metal oxide semiconductor field effect transistors (metal oxide semiconductor field effect transistor, MOSFET or MOS).

[0094] Among them, according to different carrier types, MOS can be divided into N-channel type (NMOS) and P-channel type (PMOS). [[ID=ll]]

[0095] Exemplarily, the peripheral logic device 220 includes any one of a plurality of NMOSs or PMOSs.

[0096] The IO area 230 includes any one of a plurality of NMOSs or PMOSs.

[0097] The memory array 210 includes a combination of a plurality of NMOSs and PMOSs.

[0098] That is to say, the transistors in the peripheral logic device 220 and the IO area 230 are all of a single type, while the memory array 210 includes two types of transistors.

[0099] As Figure 2B shown, a circuit diagram of a memory array 210 is schematically shown.

[0100] The transistors T1 to T6 can be, for example, the above-mentioned MOS transistors. The transistor T mainly includes a control electrode, such as a gate (gate, G), a first input / output electrode, such as a source (source, S), and a second input / output electrode, such as a drain (drain, D).

[0101] As Figure 2B shown, the transistor T1 and the transistor T2 can be, for example, NMOS transistors, also called pulldown transistors (pulldown, PD). The transistor T3 and the transistor T4 can be, for example, PMOS transistors, also called pull-up transistors (pull up, PU). The transistor T5 and the transistor T6 can be, for example, NMOS transistors, also called pass gate transistors (pass gate, PG).

[0102] The control electrodes of transistor T1 and transistor T3 are coupled. The first input / output electrode of transistor T1 is coupled to the ground voltage (voltage source and sink, VSS). The second input / output electrode of transistor T1 is coupled to the first input / output electrode of transistor T3 and the second input / output electrode of transistor T5.

[0103] The control electrodes of transistor T2 and transistor T4 are coupled. The first input / output electrode of transistor T2 is coupled to VSS. The second input / output electrode of transistor T2 is coupled to the first input / output electrode of transistor T4 and the second input / output electrode of transistor T6.

[0104] The second input / output electrode of transistor T3 is coupled to the working voltage (voltage drain drain, VDD).

[0105] The second input / output electrode of transistor T4 is coupled to VDD.

[0106] The control electrode of transistor T5 is coupled to the word line (write line, WL). The first input / output electrode of transistor T5 is coupled to the bit line (bit line, BL).

[0107] The control electrode of transistor T6 is coupled to the word line WL. The first input / output electrode of transistor T6 is coupled to the bit line BL.

[0108] Due to the working principle and special structure of the SRAM, such as Figure 2B As shown, the control electrodes of transistor T1 and transistor T3 are connected, and transistor T1 and transistor T3 form an inverter. The control electrodes of transistor T2 and transistor T4 are connected, and transistor T2 and transistor T4 form an inverter.

[0109] Hereinafter, taking the semiconductor device provided by the embodiment of the present application as an inverter as an example for illustration. Exemplarily, taking the inverter formed by transistor T1 (the first transistor) and transistor T3 (the second transistor) as an example for illustration. It should be clarified here that the semiconductor device provided by the embodiment of the present application can also be used in the above-mentioned chip. Exemplarily, the chip may include semiconductor devices encapsulated and encapsulated within the encapsulation layer.

[0110] As Figure 3A shown, the semiconductor device 300 includes adjacent first transistor 400 and second transistor 500.

[0111] It is hereby clarified that the above-mentioned transistors may include three-dimensional transistors such as fin field-effect transistors (FinFETs), gate all around field effect transistors (GAAFETs), or fork sheet field effect transistors (forksheet FETs or FSFETs). The embodiments of the present application do not limit this, and it can be reasonably set according to the actual situation.

[0112] Exemplarily, the first transistor 400 is a pull-down transistor, and the second transistor 500 is a pull-up transistor. That is, the first transistor 400 is an NMOS, and the second transistor 500 is a PMOS.

[0113] The control electrode of the first transistor 400 is connected to the control electrode of the second transistor 500. That is to say, the first transistor 400 and the second transistor 500 are connected with a common gate.

[0114] Among them, the work function of the work function layer (the first work function layer 401) of the first transistor 400 is different from the work function of the work function layer (the second work function layer 501) of the second transistor 500.

[0115] As the transistors develop from planar transistors to three-dimensional transistors, during the manufacturing process of the transistors, it is necessary to use two masks to form work function layer materials with different thicknesses as the first work function layer 401 of the first transistor 400 and the second work function layer 501 of the second transistor 500 respectively, so as to realize work function layer materials with different work functions. That is to say, the thickness of the first work function layer 401 is different from the thickness of the second work function layer 501, that is, the thickness of the second work function layer 501 is greater than the thickness of the first work function layer 401.

[0116] Within the memory array 210, due to the difference in the thickness of the work function layer 401 of the first transistor 400 and the work function layer 501 of the second transistor 500, the diffusion degrees of aluminum ions and oxygen ions in the first transistor 400 and the second transistor 500 are different, resulting in different gate work functions for the first transistor 400 and the second transistor 500. In addition, due to the difference in the thickness of the work function layer of the first transistor 400 and the thickness of the work function layer of the second transistor 500, at the junction of the gates of the first transistor 400 and the second transistor 500, a metal boundary effect (MBE) is generated, further affecting the gate work functions of the first transistor 400 and the second transistor 500. In the peripheral logic device 220, only the peripheral logic device 220 is composed of NMOS or PMOS. Therefore, the thickness of the work function layer of the transistors is the same, and the diffusion degrees of aluminum ions and oxygen ions in the transistors are the same, and there is no metal boundary effect.

[0117] That is to say, there is a metal boundary effect in the memory array 210, and there is no metal boundary effect in the peripheral logic device 220. This results in differences in the electrical parameters (such as threshold voltage Vt, saturation current Id, etc.) of the NMOS in the memory array 210 and the NMOS in the peripheral logic device 220 in the same set of process technologies. Exemplarily, there are differences in the electrical parameters of the pull-up transistors (PMOS) in the memory array 210 and the PMOS in the peripheral logic device 220.

[0118] Taking the PMOS as an example, as Figure 3B shown, the variation of the threshold voltage Vt of the memory array 210 and the peripheral logic device 220 is schematically shown. Figure 3B The midpoint A represents the corresponding point of the threshold voltage Vt of the memory array 210 and the peripheral logic device 220 in theory. As Figure 3B can be seen, when the threshold voltage Vt2 of the PMOS in the peripheral logic device 220 reaches point A, the threshold voltage Vt1 of the PMOS in the memory array 210 is higher than the theoretical value, which causes a difference (loading) between the threshold voltage Vt1 of the PMOS in the memory array 210 and the threshold voltage Vt2 of the PMOS in the peripheral logic device 220.

[0119] However, when the difference between the threshold voltage Vt1 and the threshold voltage Vt2 is too large, it will cause a timing mismatch in the memory, resulting in problems with the reading and writing of the memory.

[0120] As Figure 3CAs shown, a timing simulation diagram of PMOS in the storage array 210 is illustrated. After the signal of the peripheral logic device 220 is always turned on, the storage array 210 starts to perform the operation of writing information. Among them, writing information includes pulling down the node 1 of the memory from a high potential (storing 1) to a low potential (storing 0), and at the same time pulling up the memory node 2 from a low potential (storing 0) to a high potential (storing 1). Only when the potential inversion of the two nodes in the memory is completed simultaneously can the operation of writing information to the memory be completed and the information be stored in the storage array 210.

[0121] However, due to the relatively large threshold voltage Vt1, the process of pulling up the node 2 from a low potential to a high potential will be slower (from Figure 3C the process from B1 to B2 in). When the change process of the node 2 is as shown in Figure 3C B2 in, the difference between the threshold voltage Vt1 and the threshold voltage Vt2 is too large, resulting in the clock signal transmitted by the peripheral logic device 220 starting to drop, that is, starting to turn off, while the operation of writing information in the storage array 210 has not ended, resulting in the memory being unable to complete the writing of information, affecting the performance of the memory and reducing the yield of the chip.

[0122] Based on this, in order to reduce the electrical property difference between the storage array and the peripheral logic device, an embodiment of the present application further provides a semiconductor device. As shown in Figure 4 the semiconductor device 300 includes a substrate 310, a first fin 420, a first gate 410, a second fin 520, a second gate 510, and a work function layer 600.

[0123] Among them, the substrate 310 includes an N-type doped region 311 and a P-type doped region 312. The first gate 410 straddles the first fin 420, and both the first fin 420 and the first gate 410 are disposed on the N-type doped region 311 of the substrate 310. The second gate 510 straddles the second fin 520, and both the second fin 520 and the second gate 510 are disposed on the P-type doped region 312 of the substrate 310. The first gate 410 and the second gate 510 are connected. The work function layer 600 includes a first portion 610 covering the top surface and two opposite side surfaces of the first fin 420, a second portion 620 covering the top surface and two opposite side surfaces of the second fin 520, and a third portion 630 connecting the first portion 610 and the second portion 620. The work function of the third portion 630 is greater than the work function of the second portion 620, and the work function of the second portion 620 is greater than the work function of the first portion 610.

[0124] In some embodiments, the semiconductor device 300 may include a first transistor 400 and a second transistor 500. Among them, the first transistor 400 may include a first fin 420, a first gate 410, and a first portion 610 of the work function layer 600. The second transistor 500 may include a second fin 520, a second gate 510, and a second portion 620 of the work function layer 600.

[0125] Exemplarily, the first transistor 400 may be the transistor T1 (i.e., the pull-down transistor PD) described above Figure 2B and the second transistor 500 may be the transistor T3 (i.e., the pull-up transistor PU) described above Figure 2B .

[0126] As Figure 5 shown, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:

[0127] S1. As Figure 6A shown, provide a substrate 310.

[0128] The embodiment of the present application does not limit the material of the substrate 310. Exemplarily, the material of the substrate 310 may be a semiconductor. For example, it may be bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI), etc. The substrate 310 may also be doped (e.g., P-type doping, N-type doping) or undoped.

[0129] Among them, the semiconductor material of the substrate 310 may include any one or a combination of several of silicon, germanium, compound semiconductors, and alloy semiconductors. Among them, compound semiconductors may include, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide. Alloy semiconductors may be, for example: silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide phosphide (GaInAsP).

[0130] SOI includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on the substrate 310, and the substrate 310 is usually a silicon substrate or a glass substrate. Other substrates may also be used, for example, multi-layer or gradient substrates.

[0131] Alternatively, exemplarily, the substrate 310 is a wafer, for example, a silicon wafer.

[0132] Exemplarily, the substrate 310 includes an N-type doped region 311 and a P-type doped region 312.

[0133] Among them, an N-type transistor is to be formed in the N-type doped region 311, and a P-type transistor is to be formed in the P-type doped region 312.

[0134] S2. As Figure 6B shown, a first fin 420 and a second fin 520 are formed on the substrate 310.

[0135] Exemplarily, there is a gap between the first fin 420 and the second fin 520. That is, the first fin 420 and the second fin 520 are spaced apart along the first direction x.

[0136] Among them, the first fin 420 can serve as the source and drain of the first transistor 400 to be formed subsequently. The second fin 520 can serve as the source and drain of the second transistor 500 to be formed subsequently.

[0137] Exemplarily, as Figure 6B shown, a first fin 420, a second fin 520, and a trench �01 are formed on the surface of the substrate 310.

[0138] Among them, the trench 301 is located between the first fin 420 and the second fin 520.

[0139] That is to say, as Figure 6B shown, the first fin 420 is formed on the N-type doped region 311, and the second fin 520 is formed on the P-type doped region 312.

[0140] Or rather, the first fin 420 is formed on the N-type doped region 311, and the second fin 520 is formed on the P-type doped region 312.

[0141] In some embodiments, before forming the first fin 420 and the second fin 520, an active area (AA) is further formed on the substrate 310, and the active area is used to form transistors subsequently.

[0142] In some embodiments, after forming the first fin 420 and the second fin 520, a shallow trench isolation (STI) structure ( Figure 6B not shown in the figure) is further formed.

[0143] The material of the shallow trench isolation structure is an insulating material. Exemplarily, the material of the shallow trench isolation structure may include binary or multi-component compounds composed of elements such as silicon (Si), carbon (C), nitrogen (N), and oxygen (O). Specifically, the material of the shallow trench isolation structure may include, for example, silicon carbonitride (SiC x O y N z ), silicon oxycarbide (SiCx O y )、 silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ), or at least one of them.

[0144] Among them, the method for forming the shallow trench isolation structure may be, for example, first depositing an insulating material through a deposition process; then planarizing the insulating material so that the surface of the insulating material is flush with the top surfaces of the first fin 420 and the second fin 520; then performing etch-back to control the thickness of the shallow trench isolation structure by controlling the etch-back time.

[0145] It should be noted that the shallow trench isolation structure wraps around the peripheries of the first fin 420 and the second fin 520, and is located in the trench 301, and is in partial side contact with the first fin 420 and the second fin 520. Along the thickness direction z of the substrate 310, the surface of the shallow trench isolation structure is lower than the surfaces of the first fin 420 and the second fin 520. That is to say, the shallow trench isolation structure only wraps the portions of the first fin 420 and the second fin 520 close to the substrate 310, and exposes the portions of the first fin 420 and the second fin 520 far from the substrate 310.

[0146] In some embodiments, after forming the first fin 420 and the second fin 520, the manufacturing method of the semiconductor device 300 further includes: forming any one or more of an interface layer, an interlayer dielectric layer, or a capping layer ( Figure 6B not shown in the figure). Among them, the interface layer (interface layer, IL), the interlayer dielectric layer, or the capping layer are stacked in sequence and cover the first fin 420, the second fin 520, and the trench 301.

[0147] Exemplarily, the material of the capping layer may include titanium nitride (TiN) or tantalum nitride (TaN).

[0148] The material of the interlayer dielectric layer may include extreme high-K (HK) materials. For example, the high-K materials may include hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), or aluminum oxide (Al2O3), etc.

[0149] The material of the interface layer is silicon oxide or silicon oxynitride.

[0150] S3. As Figure 6CAs shown, a work function layer 600 is formed. The work function layer 600 includes a first portion 610, a second portion 620, and a third portion 630. The first portion 610 is formed on the top surface and two opposite side surfaces of the first fin 420. The second portion 620 is formed on the top surface and two opposite side surfaces of the second fin 520. The third portion 630 is formed between the first fin 420 and the second fin 520 and connects the first portion 610 and the second portion 630.

[0151] Or rather, the work function layer 600 covers the top surface and two opposite side surfaces of the first fin 420 and also extends to the top surface and two opposite side surfaces of the second fin 520.

[0152] Wherein, the work function of the third portion 630 is greater than that of the second portion 620, and the work function of the second portion 620 is greater than that of the first portion 610.

[0153] Exemplarily, as Figure 6D shown, Figure 6D is Figure 6C a cross-sectional view along the A1A2 direction. The work function layer 600 extends from the N-type doped region 311 to the P-type doped region 312.

[0154] Exemplarily, step S3 may include:

[0155] S31, as Figure 6E shown, form a first sub-work function film 601'.

[0156] Exemplarily, the first sub-work function film 601' is formed on the substrate 310. The first sub-work function film 601' is formed on the N-type doped region 311 and the P-type doped region 312 of the substrate 310.

[0157] That is to say, the first sub-work function film 601' covers the surfaces of the first fin 420 and the second fin 520.

[0158] Exemplarily, the material of the first sub-work function film 601' may include, for example, titanium nitride or tantalum nitride.

[0159] S32, as Figure 6F shown, remove a part of the first sub-work function film 601' to form a first sub-work function layer 601.

[0160] As Figure 6F shown, the first sub-work function layer 601 is located between the first fin 420 and the second fin 520. Exemplarily, the first sub-work function layer 601 is located in the trench 301 between the first fin 420 and the second fin 520 and covers the surface of the substrate 310.

[0161] Exemplarily, as Figure 6FAs shown, the removed part is the first sub-work function film 601' in the N-type doped region 311 and the first sub-work function film 601' in the P-type doped region 312, exposing the substrate 310. That is to say, at least part of the first sub-work function film 601' remains in the N-type doped region 311.

[0162] At this time, when removing part of the first sub-work function film 601', the substrate 310 can be used as an etching stop layer.

[0163] It is clarified here that the remaining first sub-work function film 601' in the N-type doped region 311 is on the side close to the P-type doped region 312.

[0164] Or, it can be understood that when removing the first sub-work function film 601', along the direction from the N-type doped region 311 to the P-type doped region 312, the first sub-work function film 601' in the N-type doped region 311 is not completely removed, that is, a part of the first sub-work function film 601' in the N-type doped region 311 is removed. For example, in the N-type doped region 311, the size of the less removed first sub-work function film 601' is d1 nm. Exemplarily, the direction from the N-type doped region 311 to the P-type doped region 312 is called the first direction x.

[0165] At this time, the first sub-work function film 601' not removed in the N-type doped region 311 is called the first sub-work function layer 601. That is to say, along the first direction x, the size of the first sub-work function layer 601 is d1 nm.

[0166] One side edge of the first sub-work function layer 601 is located in the N-type doped region 311, and the other side edge can be flush with the junction of the N-type doped region 311 and the P-type doped region 312, or can also be located in the N-type doped region 311.

[0167] Or, exemplarily, as Figure 6G As shown, the removed part is the first sub-work function film 601' in the N-type doped region 311 and part of the first sub-work function film 601' in the P-type doped region 312, exposing the substrate 310. That is to say, at least part of the first sub-work function film 601' remains in both the N-type doped region 311 and the P-type doped region 312.

[0168] It is clarified here that the remaining first sub-work function film 601' in the N-type doped region 311 and the remaining first sub-work function film 601' in the P-type doped region 312 are continuous. That is to say, the remaining first sub-work function film 601' is located at the junction of the N-type doped region 311 and the P-type doped region 312.

[0169] Exemplarily, neither the first sub-work function film 601' in the N-type doped region 311 nor the first sub-work function film 601' in the P-type doped region 312 is completely removed. Along the first direction x, in the N-type doped region 311, the size of the less-removed first sub-work function film 601' is d1 nm, and in the P-type doped region 312, the size of the less-removed first sub-work function film 601' is d2 nm.

[0170] At this time, the first sub-work function film 601' that is not removed in the N-type doped region 311 and the P-type doped region 312 is called the first sub-work function layer 601. That is to say, along the first direction x, the size of the first sub-work function layer 601 is d1 + d2 nm.

[0171] One side edge of the first sub-work function layer 601 is located in the N-type doped region 311, and the other side edge is located in the P-type doped region 312.

[0172] Or, exemplarily, as Figure 6H shown, the first sub-work function film 601' located in the N-type doped region 311 and part of the first sub-work function film 601' located in the P-type doped region 312 are removed, exposing the substrate 310. That is to say, at least part of the first sub-work function film 601' remains in the P-type doped region 312.

[0173] It is clarified here that the remaining first sub-work function film 601' in the P-type doped region 312 is close to the side of the N-type doped region 311.

[0174] Exemplarily, the first sub-work function film 601' in the P-type doped region 312 is not completely removed. Along the first direction x, in the P-type doped region 312, the size of the less-removed first sub-work function film 601' is d2 nm.

[0175] At this time, the first sub-work function film 601' that is not removed in the P-type doped region 312 is called the first sub-work function layer 601. That is to say, along the first direction x, the size of the first sub-work function layer 601 is d2 nm.

[0176] One side edge of the first sub-work function layer 601 is located in the P-type doped region 312, and the other side edge can be flush with the junction of the N-type doped region 311 and the P-type doped region 312, or can also be located in the P-type doped region 312.

[0177] Exemplarily, the distance between the first sub-work function layer 601 and the first fin 420 is equal to the distance between the first sub-work function layer 601 and the second fin 520. That is to say, the midpoint of the first sub-work function layer 601 is located between the first fin 420 and the second fin 520. In this way, the third part 630 of the subsequent formed work function layer 600 is located between the first fin 420 and the second fin 520, and the distance between the third part 630 and the first fin 420 is equal to the distance between the third part 630 and the first fin 420. In the embodiment of the present application, the position of the first sub-work function layer 601 is not limited, as long as it is ensured that the first sub-work function layer 601 is near the junction of the N-type doping region 311 and the P-type doping region 312.

[0178] It is clarified here that removing part of the first sub-work function film 601' to form the first sub-work function layer 601 can control the position and size of the first sub-work function layer 601 by changing at least one of the mask or the etching process.

[0179] Exemplarily, by changing the shape of the mask, the mask covers the part of the first sub-work function film 601' to be retained, exposes the part of the first sub-work function film 601' to be removed, and keeps the etching conditions unchanged to form the first sub-work function layer 601.

[0180] Or, exemplarily, the mask only covers the N-type doping region 311. By changing the etching conditions, such as reducing the concentration of the etching gas and the gas pressure of the etching gas, part of the first sub-work function film 601' can still be retained in the P-type doping region 312 to form the first sub-work function layer 601.

[0181] Or, exemplarily, by changing the shape of the mask and the etching conditions, the position and size of the formed first sub-work function layer 601 can be controlled.

[0182] S33, as Figure 6I shown, form the second sub-work function film 602'.

[0183] Exemplarily, the second sub-work function film 602' is formed on the side of the first sub-work function layer 601 away from the substrate 310, and the second sub-work function layer film 602' also extends to the surface of the substrate 310.

[0184] That is to say, the second sub-work function film 602' is formed in the N-type doping region 311 and the P-type doping region 312 of the substrate 310.

[0185] The second sub-work function film 602' covers the surfaces of the first fin 420 and the second fin 520.

[0186] Exemplarily, the material of the second sub-work function film 602' may include, for example, titanium nitride or tantalum nitride. The material of the second sub-work function film 602' may be the same as that of the first sub-work function film 601'.

[0187] S34. As Figure 6J shown, a part of the second sub-work function film 602' is removed to form the second sub-work function layer 602.

[0188] As Figure 6J shown, the second sub-work function layer 602 covers the top surface and two opposite side surfaces of the second fin 520, and further extends to the surface of the first sub-work function layer 601 on the side away from the substrate 310.

[0189] Exemplarily, as Figure 6J shown, a part of the second sub-work function film 602' located in the N-type doped region 311 or a part of the second sub-work function film 602' located in the P-type doped region 312 is removed to expose the substrate 310. Similar to the above step S32, at this time, the substrate 310 serves as an etching stop layer.

[0190] It is clarified here that a part of the second sub-work function film 602' on the surface of the first sub-work function layer 601 on the side away from the substrate 310, and the second sub-work function film 602' of the P-type doped region 312 connected to this part of the second sub-work function film 602' are retained.

[0191] That is to say, at least a part of the second sub-work function film 602' is still retained in the P-type doped region 312.

[0192] In the embodiment of the present application, whether the second sub-work function film 602' located in the N-type doped region 311 will be retained depends on the position of the first sub-work function layer 601 in step S32.

[0193] Exemplarily, if the first sub-work function layer 601 is only located in the N-type doped region 311, the second sub-work function film 602' on the surface of the substrate 310 on the side of the first sub-work function layer 601 away from the P-type doped region 312 is removed, and the remaining second sub-work function film 602' serves as the second sub-work function layer 602.

[0194] Or, exemplarily, one edge of the first sub-work function layer 601 is located in the N-type doped region 311, and the other edge is located in the P-type doped region 312. That is to say, the first sub-work function layer 601 is located in both the N-type doped region 311 and the P-type doped region 312. Only the second sub-work function film 602' on the surface of the substrate 310 in the N-type doped region 311 is removed, and the remaining second sub-work function film 602' serves as the second sub-work function layer 602.

[0195] Alternatively, exemplarily, the first sub-work function layer 601 is only located in the P-type doped region 312, and the second sub-work function film 602' on the surface of the substrate 310 and away from the P-type doped region 312 on one side of the first sub-work function layer 601 is removed, and the remaining second sub-work function film 602' serves as the second sub-work function layer 602.

[0196] That is to say, the second sub-work function layer 602 extends from the surface of the first sub-work function layer 601 away from the substrate 310 to the substrate 310 in the P-type doped region 312. The second sub-work function layer 602 is located in the P-type doped region 312, and may be located in the N-type doped region 311 or may not be located in the N-type doped region 311. The embodiments of the present application do not limit this, and it can be reasonably set according to the actual situation.

[0197] In some other embodiments, as Figure 6K shown, in step S32, only a part of the first sub-work function film 601' located in the P-type doped region 312 may be removed. When removing the second sub-work function film 602' located in the N-type doped region 311 in step S34, the first sub-work function film 601' located in the N-type doped region 311 is removed at the same time.

[0198] It is clarified here that removing a part of the second sub-work function film 602' to form the second sub-work function layer 602 can control the position and size of the second sub-work function layer 602 by changing at least one of the mask and the etching process.

[0199] Exemplarily, by changing the shape of the mask, the mask covers the part of the second sub-work function film 602' to be retained, exposes the part of the second sub-work function film 602' to be removed, and keeps the etching conditions unchanged to form the second sub-work function layer 602.

[0200] Or, exemplarily, the mask only covers the P-type doped region 312, and by changing the etching conditions, such as reducing the concentration of the etching gas and the gas pressure of the etching gas, so that a part of the second sub-work function film 602' is still retained in the N-type doped region 311 to form the second sub-work function layer 602.

[0201] Or, exemplarily, the position and size of the formed second sub-work function layer 602 can be controlled by changing the shape of the mask and changing the etching conditions.

[0202] S35, as Figure 6L shown, form the third sub-work function layer 603.

[0203] Exemplarily, the third sub-work function layer 603 is formed on the side of the second sub-work function layer 602 away from the substrate 310, and the third sub-work function layer 603 also extends to the surface of the substrate 310. As Figure 6LAs shown, the third sub-work function layer 603 covers the top surface and two opposite side surfaces of the first fin 420, and also extends to the side of the second sub-work function layer 602 away from the substrate 310.

[0204] That is to say, the third sub-work function layer 603 is formed in the N-type doped region 311 and the P-type doped region 312.

[0205] Exemplarily, the material of the third sub-work function layer 603 may include, for example, titanium nitride or tantalum nitride.

[0206] It should be clarified here that as Figure 6L shown, there may be an interface between the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603, that is, there is an obvious boundary line. Or, there may be no interface, that is, there is no boundary line. The embodiments of the present application do not limit this, and it can be reasonably set according to the actual situation.

[0207] Exemplarily, the materials of the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603 may be the same. Therefore, the first part 610, the second part 620, and the third part 630 may be an integral structure. That is to say, the first part 610, the second part 620, and the third part 630 can be regarded as a whole. That is, the work function layer 600 is an integral whole.

[0208] In some embodiments, the work function layer 600 may include a first part 610, a second part 620, and a third part 630.

[0209] The first part 610 is formed in the N-type doped region 311, and the second part 620 is formed in the P-type doped region 312. The third part 630 connects the first part 610 and the second part 620.

[0210] Exemplarily, the first part 610 covers at least the top surface and two opposite side surfaces of the first fin 420, the second part 620 covers at least the top surface and two opposite side surfaces of the second fin 520, the third part 630 is formed between the first fin 420 and the second fin 520, and connects the first part 610 and the second part 620.

[0211] Exemplarily, the third part 630 may be formed in the N-type doped region 311. Or, the third part 630 may also be formed in the P-type doped region 312. Or, the third part 630 may also be formed in both the N-type doped region 311 and the P-type doped region 312. The embodiments of the present application do not limit this, as long as it is ensured that the third part 630 is formed on the substrate 310 and connects the first part 610 and the second part 620.

[0212] At this time, a layer of the third sub-work function layer 603 located in the N-type doped region 311 is referred to as the first part 610, a second sub-work function layer 602 and a third sub-work function layer 603 which are sequentially stacked and located in the P-type doped region 312 are referred to as the second part 620, and a first sub-work function layer 601, a second sub-work function layer 602, and a third sub-work function layer 603 which are sequentially stacked are referred to as the third part 630.

[0213] As Figure 6L shown, the first part 610 includes one layer of sub-work function layer (the third sub-work function layer 603), the second part 620 includes two layers of sub-work function layers (the second sub-work function layer 602 and the third sub-work function layer 603), and the third part 630 includes three layers of sub-work function layers (the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603).

[0214] Exemplarily, the thickness of the second part 620 is greater than the thickness of the first part 610.

[0215] That is to say, the work function of the second part 620 is greater than the work function of the first part 610.

[0216] As Figure 6L shown, the thickness of the third part 630 is greater than the thickness of the second part 620, so the thickness of the third part 630 is also greater than the thickness of the first part 610.

[0217] That is to say, the work function of the third part 630 is greater than the work function of the second part 620, and the work function of the third part 630 is also greater than the work function of the first part 610.

[0218] Exemplarily, the materials of the first part 610, the second part 620, and the third part 630 are the same, and the thickness of the third part 630 is greater than the thickness of the second part 620, and the thickness of the second part 620 is greater than the thickness of the first part 610.

[0219] In this way, the diffusion degree of aluminum ions and oxygen ions in the third part 630 is less than the diffusion degree of aluminum ions and oxygen ions in the second part 620, and the diffusion degree of aluminum ions and oxygen ions in the second part 620 is less than the diffusion degree of aluminum ions and oxygen ions in the first part 610, which can enhance the metal boundary effect of the first part 610 and the second part 620.

[0220] Continuing to refer to Figure 6L , the first part 610 is formed on the first fin 420, the second part 620 is formed on the second fin 520, and the third part 630 is formed in the trench 301 between the first fin 420 and the second fin 520.

[0221] In some embodiments, the dimension of the third portion 630 along the first direction x is the same as the dimension of the first sub-work function layer 601 along the first direction x.

[0222] Exemplarily, the dimension of the third portion 630 along the first direction x can be 0.25 to 0.5 times the distance between the first fin 420 and the second fin 520.

[0223] Wherein, the distance between the first fin 420 and the second fin 520 can be understood as the distance between the center lines of the first fin 420 and the second fin 520.

[0224] S4. As Figure 6M shown, form the diffusion layer 710.

[0225] Exemplarily, form the diffusion layer 710 on the side of the work function layer 600 away from the substrate 310.

[0226] That is to say, the diffusion layer 710 is formed on the side of the work function layer 600 away from the substrate 310. For example, the diffusion layer 710 is formed on the surface of the work function layer 600 away from the substrate 310.

[0227] For example, the diffusion layer 710 is formed on the side of the first portion 610 away from the substrate 310, the diffusion layer 710 is also formed on the side of the second portion 620 away from the substrate 310, and the diffusion layer 710 is also formed on the side of the third portion 630 away from the substrate 310.

[0228] Or rather, the diffusion layer 710 is formed on the surface of the third sub-work function layer 603 away from the substrate 310.

[0229] As Figure 6M shown, the diffusion layer 710 is formed on the side of the first portion 610 away from the substrate 310, and the diffusion layer 710 also extends to the side of the second portion 620 away from the substrate 310.

[0230] The material of the diffusion layer 710 can include, for example, titanium aluminum alloy (TiAl).

[0231] The function of the diffusion layer 710 is to enable the diffusion of aluminum ions and oxygen ions.

[0232] S5. As Figure 6N shown, form the first gate 410 and the second gate 510.

[0233] As Figure 6N shown, the first gate 410 straddles the first fin 420 and contacts the top surface and two opposite side surfaces of the first fin 420. The second gate 510 straddles the second fin 520 and contacts the top surface and two opposite side surfaces of the second fin 520.

[0234] That is to say, the first gate 410 is formed on the first part 610, and the second gate 510 is formed on the second part 620.

[0235] Among them, the first gate 410 and the second gate 510 can be formed in the same process step. The first gate 410 and the second gate 510 are connected.

[0236] It is clarified here that the first gate 410 is located in the N-type doped region 311, and the second gate 510 is located in the P-type doped region 312.

[0237] In some embodiments, after step S5, it further includes:

[0238] S6. Form the first source and the first drain.

[0239] Exemplarily, the first source and the first drain can be formed by doping the parts of the first fin 420 on both sides of the first gate 410 to form the first transistor 400.

[0240] S7. Form the second source and the second drain.

[0241] Exemplarily, the second source and the second drain can be formed by doping the parts of the second fin 520 on both sides of the second gate 510 to form the second transistor 500.

[0242] Among them, the type of doping atoms can be selected so that the transistors in the subsequent formed semiconductor device 300 are P-type transistors or N-type transistors.

[0243] It is clarified here that the first source, the first drain, the second source, and the second drain can be formed in the same process step or in different process steps. The embodiments of the present application do not limit this, and it can be reasonably set according to the actual situation.

[0244] In addition, for the above steps S1 - S7, some of the steps can be removed according to needs, and it is not limited that each step must be included. Some steps can also be added according to needs, and it is not limited to only including the above steps.

[0245] For the above preparation method provided by the embodiments of the present application, there is no limitation on the order of any steps, and it can be reasonably adjusted according to needs.

[0246] In some embodiments, the preparation method further includes forming a middle end of line (MEOL) process, a back end of line (BEOL) process, and a packaging process. Exemplarily, metal wires are prepared to connect different devices (such as transistors) or different layers on the substrate 310.

[0247] It should be noted here that the manufacturing process of the transistors in the peripheral logic device 220 of the storage unit 200 in the embodiments of the present application is not limited. It can be carried out in the same process step as the transistors in the above storage array 210, or formed separately. Exemplarily, the work function of the work function layer in the peripheral logic device 220 is the same as that of the above work function layer (the first part 610, the second part 620, or the third part 630), and the work function layer of the peripheral logic device 220 can be formed in the same process step.

[0248] In the manufacturing method of the semiconductor device 300 according to the embodiments of the present application, the work function of the third part 630 formed is greater than the work functions of the first part 610 and the second part 620, that is, the work function of the third part 630 is the largest, and the third part 630 is connected to the first part 610 and the second part 620. The solution of the embodiments of the present application enhances the metal boundary effect of the first part 610 and the second part 620 by setting the third part 630 of the work function layer 600, which helps to reduce the threshold voltage of the transistor (pull-up transistor PU) where the second part 620 is located, and further improves the electrical property difference between the storage array 210 and the peripheral logic device 220 where the semiconductor device 300 is located.

[0249] In addition, the manufacturing method provided by the embodiments of the present application does not require an additional mask plate. It can be achieved only by changing the mask plate shape or etching conditions at one time, without increasing additional manufacturing costs.

[0250] The semiconductor device 300 provided by the embodiments of the present application is applied to a memory, which can reduce the threshold voltage of the pull-up transistor (the second transistor 500) in the storage array 210 to improve the electrical property difference (such as threshold voltage, threshold current, etc.) between the storage array 210 and the peripheral logic device 220, make the timing of the storage array 210 and the peripheral logic device 220 match, enable the storage array 210 to complete the write information operation before the peripheral logic device 220 is turned off, improve the memory performance, and further improve the chip yield.

[0251] The following embodiments illustrate the semiconductor device provided by the embodiments of the present application. The semiconductor device can be manufactured by the manufacturing method of the above semiconductor device structure.

[0252] As Figure 7 shown, the semiconductor device 300 includes a substrate 310, a first fin 420, a first gate 410, a second fin 520, a second gate 510, and a work function layer 600.

[0253] Among them, the substrate 310 includes an N-type doped region 311 and a P-type doped region 312. The first gate 410 straddles the first fin 420, and both the first fin 420 and the first gate 410 are disposed on the N-type doped region 311 of the substrate 310. The second gate 510 straddles the second fin 520, and both the second fin 520 and the second gate 510 are disposed on the P-type doped region 312 of the substrate 310. The first gate 410 and the second gate 510 are connected. The work function layer 600 includes a first portion 610 covering the top surface and two opposite side surfaces of the first fin 420, a second portion 620 covering the top surface and two opposite side surfaces of the second fin 520, and a third portion 630 connecting the first portion 610 and the second portion 620. The work function of the third portion 630 is greater than the work function of the second portion 620, and the work function of the second portion 620 is greater than the work function of the first portion 610.

[0254] In some embodiments, the semiconductor device 300 may include a first transistor 400 and a second transistor 500. Among them, the first transistor 400 may include a first fin 420, a first gate 410, and a first portion 610 of the work function layer 600. The second transistor 500 may include a second fin 520, a second gate 510, and a second portion 620 of the work function layer 600.

[0255] Exemplarily, the first transistor 400 may be the transistor T1 in the above Figure 2B above, and the second transistor 500 may be the transistor T3 in the above Figure 2B above.

[0256] That is to say, the first transistor 400 is a pull-down transistor, and the second transistor 500 is a pull-up transistor.

[0257] Exemplarily, the first transistor 400 and the second transistor 500 are arranged in sequence along the first direction x.

[0258] The embodiments of the present application do not limit the material of the substrate 310. Exemplarily, the material of the substrate 310 may be a semiconductor. For example, it may be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SGOI). The substrate 310 may also be doped (for example, P-type doping, N-type doping) or undoped.

[0259] The semiconductor material of substrate 310 may include any one of silicon, germanium, a compound semiconductor, and an alloy semiconductor, or a combination thereof. Compound semiconductors may include, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide. Alloy semiconductors may include, for example, silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenic phosphide (GaInAsP).

[0260] SOI includes a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate 310, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used.

[0261] Alternatively, illustratively, the substrate 310 is a wafer, such as a silicon wafer.

[0262] like Figure 7 As shown, the work function layer 600 may include a first portion 610 , a second portion 620 , and a third portion 630 .

[0263] The first transistor 400 includes a first fin 420, a first gate 410, a first source ( Figure 7 Not shown) and the first drain ( Figure 7 not shown).

[0264] The first portion 610 is disposed on the top surface and two opposite side surfaces of the first fin 420. The first gate 410 is disposed across the first fin 420. In other words, the first portion 610 is disposed between the first gate 410 and the first fin 420.

[0265] The first source and drain of the first transistor 400 are located on the first fin 420 and on opposite sides of the first gate 410. For example, along the second direction y, the first source and drain are located on opposite sides of the first gate 410. The second direction y intersects the first direction x and the thickness direction z of the substrate 310. For ease of illustration, the thickness direction of the substrate 310 is referred to as the third direction z. For example, the first direction x, the second direction y, and the third direction z all intersect with each other.

[0266] like Figure 7 As shown, the second transistor 500 includes a second fin 520, a second gate 510, a second source ( Figure 7 Not shown) and the second drain ( Figure 7 not shown).

[0267] Among them, the second part 620 is disposed on the top surface and two opposite side surfaces of the second fin 520. The second gate 510 straddles the second fin 520. That is to say, the second part 620 is disposed between the second gate 510 and the second fin 520.

[0268] The second source and the second drain of the second transistor 500 are located on the second fin 520 and on two opposite sides of the second gate 510. For example, along the second direction y, the second source and the second drain are respectively located on two opposite sides of the second gate 510.

[0269] Continue to refer to Figure 7 , the connection between the first gate 410 of the first transistor 400 and the second gate 510 of the second transistor 500 can form an inverter. That is, the first gate 410 and the second gate 510 extend along the first direction x.

[0270] Exemplarily, the first gate 410 and the second gate 510 can be an integral body. The part of the gate located in the first transistor 400 is called the first gate 410, and the part located in the second transistor 500 is called the second gate 510.

[0271] The first part 610 can be regarded as the work function layer of the first transistor 400, and the second part 620 can be regarded as the work function layer of the second transistor 500.

[0272] The third part 630 is located between the first part 610 and the second part 620. The third part 630 can be regarded as the work function layer of the first transistor 400. Or, the third part 630 can also be regarded as the work function layer of the second transistor 500. Or, a part of the third part 630 can be regarded as the work function layer of the first transistor 400, and another part of the third part 630 can be regarded as the work function layer of the second transistor 500. The embodiments of the present application do not make any limitations in this regard, which is related to the position of the third part 630.

[0273] Exemplarily, the third part 630 can completely cover the surface of the substrate 310 between the first fin 420 and the second fin 520.

[0274] At this time, the first part 610 covers the top surface and two opposite side surfaces of the first fin 420 and the surface of the substrate 310 on the side of the first fin 420 away from the second fin 520, and the second part 620 covers the top surface and two opposite side surfaces of the second fin 520 and the surface of the substrate 310 on the side of the second fin 520 away from the first fin 420.

[0275] Or, the third part 630 can also partially cover the surface of the substrate 310 between the first fin 420 and the second fin 520.

[0276] At this time, the first part 610 covers the top surface and two opposite side surfaces of the first fin 420, and the surface of the substrate 310 on the side of the first fin 420 away from the second fin 520, and also extends to the surface of the substrate between the first fin 420 and the second fin 520.

[0277] The second part 620 covers the top surface and two opposite side surfaces of the second fin 520, and the surface of the substrate 310 on the side of the second fin 520 away from the first fin 420, and also extends to the surface of the substrate between the first fin 420 and the second fin 520.

[0278] Exemplarily, the distance between the third part 630 and the first fin 420 is equal to the distance between the third part 630 and the second fin 520. That is to say, the third part 630 is located in the middle of the first fin 420 and the second fin 520.

[0279] Or rather, the central axis of the third part 630 coincides with the midpoint between the first fin 420 and the second fin 520. That is, the central axis of the third part 630 coincides with the junction of the first transistor 400 and the second transistor 500. Among them, the central axis can be considered as the line perpendicular to the geometric center of the surface of the third part 630.

[0280] In this way, the influence on the first transistor 400 and the second transistor 500 is minimized, and the metal boundary effect can be further enhanced.

[0281] Or, exemplarily, the distance between the third part 630 and the first fin 420 is greater than the distance between the third part 630 and the second fin 520. Or, exemplarily, the distance between the third part 630 and the first fin 420 is less than the distance between the third part 630 and the second fin 520. The embodiments of the present application do not limit this, and it can be reasonably set according to the actual situation.

[0282] In some embodiments, the work function of the third part 630 is greater than the work function of the second part 620, and the work function of the second part 620 is greater than the work function of the first part 610.

[0283] Exemplarily, the diffusion degree of aluminum ions and oxygen ions in the third part 630 is less than the diffusion degree of aluminum ions and oxygen ions in the second part 620, and the diffusion degree of aluminum ions and oxygen ions in the second part 620 is less than the diffusion degree of aluminum ions and oxygen ions in the first part 610.

[0284] In this way, the metal boundary effect of the first part 610 and the second part 620 can be enhanced, which helps to reduce the threshold voltage of the transistor 500 where the second part 620 is located.

[0285] Among them, the materials of the first part 610, the second part 620, and the third part 630 can be the same or different. For example, the materials of the first part 610, the second part 620, and the third part 630 are the same. The above materials can include titanium nitride or tantalum nitride. That is, the material of the work function layer 600 includes titanium nitride or tantalum nitride.

[0286] That is to say, the material of the first part 610 includes titanium nitride or tantalum nitride, the material of the second part 620 includes titanium nitride or tantalum nitride, and the material of the third part 630 includes titanium nitride or tantalum nitride.

[0287] Exemplarily, the materials of the first part 610, the second part 620, and the third part 630 are the same. As Figure 7 shown, the thickness of the third part 630 is greater than the thickness of the second part 620, and the thickness of the second part 620 is greater than the thickness of the first part 610.

[0288] That is to say, the thickness of the third part 630 is greater than the thickness of the first part 610, and the thickness of the third part 630 is also greater than the thickness of the second part 620.

[0289] 4In some embodiments, the first part 610 and the second part 620 also extend between the first fin 420 and the second fin 520 to achieve connection with the third part 630.

[0290] Exemplarily, the work function layer 600 can be an integral body. That is, the first part 610, the second part 620, and the third part 630 can be an integral body. The difference lies in that the thicknesses of the first part 610, the second part 620, and the third part 630 are all different.

[0291] For example, the part of the work function layer 600 with the thickest thickness can be called the third part 630, the part of the work function layer 600 with the thinnest thickness can be called the first part 610, and the part of the work function layer 60 that is between the thinnest work function layer 600 and the thickest work function layer 600 can be called the second part 620.

[0292] In the embodiments of the present application, the thickness of the third part 630 is the thickest among the three. Exemplarily, the thickness of the first part 610 is greater than the thickness of the second part 620.

[0293] In some embodiments, as Figure 7 shown, along the direction from the first fin 420 to the second fin 520 (the first direction x), the dimension h2 of the third part 630 does not exceed the distance h1 between the first transistor 400 and the second transistor 500.

[0294] Among them, the distance h1 between the first fin 420 and the second fin 520 can be, for example, the distance h1 from the central axis of the first fin 420 to the central axis of the second fin 520.

[0295] Exemplarily, the dimension h2 of the third part 630 along the first direction x is 0.25 times to 0.5 times the distance h1 between the first fin 420 and the second fin 520.

[0296] In some other embodiments, according to the formation process of the work function layer 600, as Figure 8 shown, the work function layer 600 can be divided into a first sub-work function layer 601, a second sub-work function layer 602, and a third sub-work function layer 603.

[0297] Among them, the first sub-work function layer 601 is disposed between the first fin 420 and the second fin 520.

[0298] The second sub-work function layer 602 extends from the side of the first sub-work function layer 601 away from the substrate 310 to the second transistor 500. That is to say, the second sub-work function layer 602 is disposed on the first sub-work function layer 601, and extends from between the first fin 420 and the second fin 520 to between the second fin 520 and the second gate 510.

[0299] The third sub-work function layer 603 extends from the side of the second sub-work function layer 602 away from the substrate to the first transistor 400. That is to say, the third sub-work function layer 603 is disposed on the side of the second sub-work function layer 602 away from the first sub-work function layer 601, and between the first fin 420 and the first gate 410, and extends to between the second fin 520 and the second gate 510.

[0300] Among them, the materials of the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603 can be the same or different.

[0301] It should be clarified here that there may be an interface at the junction between the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603. That is to say, there is an obvious boundary line between the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603. Or. There may also be no interface at the junction between the first sub-work function layer 601, the second sub-work function layer 602, and the third sub-work function layer 603. The embodiments of the present application do not limit this, and it can be reasonably set according to the actual situation.

[0302] In some embodiments, as Figure 9 shown, the semiconductor device 300 further includes a diffusion layer 710.

[0303] As Figure 9As shown, the diffusion layer 710 is disposed on a side of the third sub-work function layer 603 away from the substrate 310.

[0304] That is to say, the diffusion layer 710 is disposed on a side of the work function layer 600 away from the substrate 310.

[0305] For example, the diffusion layer 710 is disposed between the first portion 610 and the first gate 410, and the diffusion layer 710 also extends between the second portion 620 and the second gate 510. Alternatively, the diffusion layer 710 is disposed between the second portion 620 and the second gate 510, and the diffusion layer 710 also extends between the first portion 610 and the first gate 410.

[0306] Exemplarily, the material of the diffusion layer 710 includes titanium aluminum alloy.

[0307] In some other embodiments, a semiconductor device 300 is further provided. The semiconductor device 300 includes a substrate 310, a first fin 420, a first gate 410, a second fin 520, a second gate 510, and a work function layer 600.

[0308] Among them, the substrate 310 includes an N-type doped region 311 and a P-type doped region 312. The first gate 410 straddles the first fin 420, and both the first fin 420 and the first gate 410 are disposed on the N-type doped region 311 of the substrate 310. The second gate 510 straddles the second fin 520, and both the second fin 520 and the second gate 510 are disposed on the P-type doped region 312 of the substrate 310. The first gate 410 and the second gate 510 are connected. The work function layer 600 includes a first portion 610 covering the top surface and two opposite side surfaces of the first fin 420, a second portion 620 covering the top surface and two opposite side surfaces of the second fin 520, and a third portion 630 connecting the first portion 610 and the second portion 620. The materials of the first portion 610, the second portion 620, and the third portion 630 are the same, and the thickness of the third portion 630 is greater than the thickness of the second portion 620, and the thickness of the second portion 620 is greater than the thickness of the first portion 610.

[0309] In this way, the diffusion degree of aluminum ions and oxygen ions in the third portion 630 is less than the diffusion degree of aluminum ions and oxygen ions in the second portion 620, and the diffusion degree of aluminum ions and oxygen ions in the second portion 620 is less than the diffusion degree of aluminum ions and oxygen ions in the first portion 610, which can enhance the metal boundary effect of the first portion 610 and the second portion 620, and helps to reduce the threshold voltage of the transistor 500 where the second portion 620 is located.

[0310] The diffusion layer 710 is used to realize the diffusion of aluminum ions and oxygen ions in the first transistor 400 and the second transistor 500.

[0311] The embodiments of the present application further provide that the semiconductor device illustrated in the embodiments of the present application is applied as an inverter in the memory array 210 of the above-mentioned memory cell 200, and the threshold voltages of the memory array 210 and the peripheral logic device 220 are simulated and illustrated. Figures 10A - 10C Illustrate the threshold voltage Vt value distribution diagram and the electrical property change diagram of the memory array 210 and the peripheral logic device 220.

[0312] Figure 10A For Figure 3A When the illustrated semiconductor device 300 is applied to the memory array 210, the distribution diagram of the threshold voltage Vt of the memory array 210 and the peripheral logic device 220. Figure 10B For Figure 4 When the illustrated semiconductor device 300 is applied to the memory array 210, the distribution diagram of the threshold voltage Vt of the memory array 210 and the peripheral logic device 220. Figure 10C For the electrical property change diagrams of two memory arrays 210.

[0313] From Figure 10A It can be seen that Figure 3A When the illustrated semiconductor device 300 is applied to the memory array 210, the threshold voltage Vt of the memory array 210 and the peripheral logic device 220 has a large difference. From Figure 10B It can be seen that Figure 4 When the illustrated semiconductor device 300 is applied to the memory array 210, the threshold voltage Vt of the memory array 210 and the peripheral logic device 220 has a small difference. From Figure 10C It can be seen that Figure 3A When the illustrated semiconductor device 300 is applied to the memory array 210, the electrical property difference value is above the target value. Figure 3A When the illustrated semiconductor device 300 is applied to the memory array 210, the electrical property difference value is below the target value. Therefore, the semiconductor device 300 provided by the embodiments of the present application can reduce the threshold voltage of the second transistor 500. Applying the semiconductor device 300 provided by the embodiments of the present application to the memory array 210 can reduce the threshold voltage difference between the memory array 210 and the peripheral logic device 220.

[0314] For the semiconductor device 300 provided by the embodiments of the present application, the work function of the third part 630 is greater than the work functions of the first part 610 and the second part 620, that is, the work function of the third part 630 is the largest, and the third part 630 is connected to the first part 610 and the second part 620. The solution of the embodiments of the present application enhances the metal boundary effect of the first part 610 and the second part 620 by setting the third part 630 of the work function layer 600, which helps to reduce the threshold voltage of the transistor (pull-up transistor PU) where the second part 620 is located, and further improves the electrical property difference between the memory array 210 where the semiconductor device 300 is located and the peripheral logic device 220.

[0315] The semiconductor device 300 provided by the embodiment of the present application is applied to the storage unit 200, which can reduce the threshold voltage of the pull-up transistor (the second transistor 500) in the storage array 210 to improve the electrical differences (such as threshold voltage, threshold current, etc.) between the storage array 210 and the peripheral logic device 220, so that the timing of the storage array 210 and the peripheral logic device 220 is matched, enabling the storage array 210 to complete the write information operation before the peripheral logic device 220 is turned off, improving the memory performance, and further improving the chip yield.

[0316] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate including an N-type doped region and a P-type doped region; A first fin and a first gate disposed on the N-type doped region; The first gate straddling the first fin; A second fin and a second gate disposed on the P-type doped region; the second gate straddling the second fin; the first gate and the second gate being connected; A work function layer including a first portion, a second portion, and a third portion; the first portion covering the top surface and two opposite side surfaces of the first fin; the second portion covering the top surface and two opposite side surfaces of the second fin; the third portion being located between the first fin and the second fin and connecting the first portion and the second portion; Wherein, the work function of the third portion is greater than the work function of the second portion, and the work function of the second portion is greater than the work function of the first portion.

2. The semiconductor device according to claim 1, wherein, The thickness of the third portion is greater than the thickness of the second portion, and the thickness of the second portion is greater than the thickness of the first portion.

3. The semiconductor device according to claim 2, wherein, The materials of the first portion, the second portion, and the third portion are the same.

4. The semiconductor device according to claim 2 or 3, characterized in that, In the direction from the first fin to the second fin, the size of the third portion is 0.25 times to 0.5 times the distance between the first fin and the second fin.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The distance between the third portion and the first fin is equal to the distance between the third portion and the second fin.

6. The semiconductor device according to any one of claims 1-5, characterized in that, The material of the work function layer includes titanium nitride or tantalum nitride.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The semiconductor device further includes a diffusion layer disposed on a side of the work function layer away from the substrate.

8. A semiconductor device, characterized in that, Comprising: A substrate including an N-type doped region and a P-type doped region; A first fin and a first gate disposed on the N-type doped region; The first gate straddling the first fin; A second fin and a second gate disposed on the P-type doped region; the second gate straddling the second fin; the first gate and the second gate being connected; A work function layer including a first portion, a second portion, and a third portion; the first portion covering the top surface and two opposite side surfaces of the first fin; the second portion covering the top surface and two opposite side surfaces of the second fin; the third portion being located between the first fin and the second fin and connecting the first portion and the second portion; Wherein, the thickness of the third portion is greater than the thickness of the second portion, and the thickness of the second portion is greater than the thickness of the first portion; the materials of the first portion, the second portion, and the third portion are the same.

9. The semiconductor device according to claim 8, wherein, In the direction from the first fin to the second fin, the size of the third portion is 0.25 times to 0.5 times the distance between the first fin and the second fin.

10. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate, the substrate including an N-type doped region and a P-type doped region; Forming a first fin and a second fin on the substrate; The first fin and the second fin having a gap; the first fin being formed on the N-type doped region, and the second fin being formed on the P-type doped region; Form a work function layer; the work function layer includes a first part, a second part, and a third part; the first part is formed on the top surface and two opposite side surfaces of the first fin; the second part is formed on the top surface and two opposite side surfaces of the second fin; the third part is formed between the first fin and the second fin and connects the first part and the second part; the work function of the third part is greater than that of the second part, and the work function of the second part is greater than that of the first part; Form a first gate and a second gate; the first gate straddles the side of the work function layer away from the first fin, the second gate straddles the side of the work function layer away from the second fin, and the first gate and the second gate are connected.

11. The manufacturing method of the semiconductor device according to claim 10, characterized in that, Forming the work function layer includes: Form a first sub-work function film, and the first sub-work function film is formed on the substrate; Remove part of the first sub-work function film to form a first sub-work function layer; the first sub-work function layer is formed between the first fin and the second fin; Form a second sub-work function film, and the second sub-work function film is formed on the substrate and covers the first sub-work function layer; Remove part of the second sub-work function film to form a second sub-work function layer; the second sub-work function layer is formed on the top surface and two opposite side surfaces of the second fin and also extends to the side of the first sub-work function layer away from the substrate; Form a third sub-work function layer, and the third sub-work function layer is formed on the substrate; the third sub-work function layer is formed on the top surface and two opposite side surfaces of the first fin and also extends to the side of the second sub-work function layer away from the substrate; the first sub-work function layer, the second sub-work function layer, and the third sub-work function layer constitute the work function layer.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that, After forming the work function layer and before forming the first gate and the second gate, the method further includes: Form a diffusion layer, and the diffusion layer is formed on the side of the work function layer away from the substrate.

13. A method for manufacturing a semiconductor device, characterized in that, including: Provide a substrate, and the substrate includes an N-type doped region and a P-type doped region; Form a first fin and a second fin on the substrate; There is a gap between the first fin and the second fin; the first fin is formed on the N-type doped region, and the second fin is formed on the P-type doped region; Form a work function layer; the work function layer includes a first part, a second part, and a third part; the first part is formed on the top surface and two opposite side surfaces of the first fin; the second part is formed on the top surface and two opposite side surfaces of the second fin; the third part is formed between the first fin and the second fin and connects the first part and the second part; the thickness of the third part is greater than that of the second part, and the thickness of the second part is greater than that of the first part; the materials of the first part, the second part, and the third part are the same; Form a first gate and a second gate; the first gate straddles the side of the work function layer away from the first fin, the second gate straddles the side of the work function layer away from the second fin, and the first gate and the second gate are connected.

14. A memory, characterized in that, Comprising: A controller and the semiconductor device according to any one of claims 1-9, the controller being electrically connected to the semiconductor device.

15. A chip, characterized in that, Comprising: The semiconductor device according to any one of claims 1-9 and a packaging layer; The semiconductor device is packaged within the packaging layer.

16. An electronic device, characterized in that, Comprising: A printed circuit board and the chip according to claim 15, the printed circuit board being electrically connected to the chip.

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