Semiconductor test structure for performing failure analysis

Abstract

The application discloses a semiconductor test structure, which comprises a semiconductor substrate, a first conductive connection structure, a second conductive connection structure and a plurality of test units on the semiconductor substrate, first conductive connection lines of the first conductive connection structure and second conductive connection lines of the second conductive connection structure are arranged alternately and spacedly to form alternating spaces between the first conductive connection lines and the second conductive connection lines; first poles and second poles of the test units are connected to the first conductive connection lines and the second conductive connection lines forming corresponding alternating spaces respectively; first plugs and second plugs arranged outside the test unit array are further included, each first plug is electrically connected to a corresponding first conductive connection line, and each second plug is electrically connected to a corresponding second conductive connection line; the top of the first plug and the top of the second plug are both higher than the top of the first conductive connection line and the top of the second conductive connection line. It is beneficial to quickly lock the failed test units.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and more particularly, to a semiconductor test structure for failure analysis. BACKGROUND

[0002] In the process of semiconductor design and manufacture, various test structures are set on a wafer to perform reliability test on test array unit structure to evaluate and verify the stability and reliability of product process under different conditions.

[0003] Currently, the test key for measuring breakdown voltage (Vbd), time dependent dielectric breakdown (TDDB) or dielectric layer leakage of array unit structure uses the design of multiple test units sharing metal wires. When breakdown actually occurs and it is necessary to quickly find the breakdown unit for failure analysis, it is difficult to quickly and accurately locate the failed test unit, thus requiring more time, manpower and analysis cost. SUMMARY

[0004] To solve the above problems, the present application is proposed. According to an aspect of the present application, a semiconductor test structure for failure analysis is provided, which comprises:

[0005] a semiconductor substrate;

[0006] a first conductive connection structure and a second conductive connection structure on the semiconductor substrate, the first conductive connection structure comprising a plurality of first conductive connection lines arranged horizontally and parallel to each other, the second conductive connection structure comprising a plurality of second conductive connection lines arranged horizontally and parallel to each other, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure being arranged alternately and spaced apart to form an alternating space between the first conductive connection lines and the second conductive connection lines;

[0007] a plurality of test units on the semiconductor substrate, the plurality of test units being arranged horizontally and in array to form a test unit array, the test units being arranged corresponding to the alternating spaces, the test units comprising a first pole and a second pole, the first pole and the second pole being connected to the first conductive connection lines and the second conductive connection lines forming corresponding alternating spaces, respectively;

[0008] at least two first plugs arranged outside the test unit array and spaced apart from each other, each first plug being arranged corresponding to a first conductive connection line, and each first plug being electrically connected to the corresponding first conductive connection line;

[0009] at least two second plugs arranged outside the array of test units and spaced apart from each other, each second plug is arranged corresponding to one second conductive connection line, and each second plug is electrically connected to the corresponding second conductive connection line;

[0010] The top height of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate is higher than the top of the at least two first conductive connection lines and the at least two second conductive connection lines.

[0011] In some embodiments of the present application, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged staggered and spaced apart to form staggered spaces between the staggered first conductive connection lines and second conductive connection lines, including,

[0012] The first conductive connection lines and the second conductive connection lines cross in the extension direction, the first conductive connection lines and the second conductive connection lines are located in different layers, the staggered spaces are located at the intersection of the first conductive connection lines and the second conductive connection lines, and the plurality of staggered spaces are arranged in an array.

[0013] In some embodiments of the present application, the first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged staggered and spaced apart to form staggered spaces between the staggered first conductive connection lines and second conductive connection lines, including,

[0014] The first conductive connection lines and the second conductive connection lines are parallel in the extension direction, the first conductive connection lines and the second conductive connection lines are located in the same or different layers, the first conductive connection lines and the second conductive connection lines are adjacent to each other in a one-to-one correspondence to stagger, and one or more staggered spaces are formed between the adjacent first conductive connection lines and the second conductive connection lines.

[0015] In some embodiments of the present application, the semiconductor test structure further comprises:

[0016] A first common conductive line located at the top of the first plug, the first common conductive line electrically connecting the at least two first plugs.

[0017] In some embodiments of the present application, the semiconductor test structure further comprises:

[0018] A second common conductive line located at the top of the second plug, the second common conductive line electrically connecting the at least two second plugs.

[0019] In some embodiments of the present application, the first common conductive line and the second common conductive line have the same height in a direction perpendicular to the surface of the semiconductor substrate.

[0020] In some embodiments of the present application, the semiconductor test structure further comprises:

[0021] a first test pad electrically connected to the first common conductive line, and a second test pad electrically connected to the second common conductive line, the first test pad and the second test pad being at the same height in a direction perpendicular to the surface of the semiconductor substrate.

[0022] In some embodiments of the application, the first common conductive line and the second common conductive line are both located in a top metal layer of the semiconductor test structure.

[0023] In some embodiments of the application, the semiconductor test structure further comprises:

[0024] a third common conductive line located on a side of the first plug away from the array of test cells and electrically connected to the at least two first conductive connection lines, the third common conductive line and the at least two first conductive connection lines forming a first comb structure.

[0025] In some embodiments of the application, the semiconductor test structure further comprises:

[0026] a fourth common conductive line located on a side of the second plug away from the array of test cells and electrically connected to the at least two second conductive connection lines, the fourth common conductive line and the at least two second conductive connection lines forming a second comb structure.

[0027] In some embodiments of the application, each first plug is electrically connected to a corresponding first conductive connection line through a first adapter structure;

[0028] wherein the first adapter structure comprises at least one first adapter plug and at least one first adapter line, the first adapter plug and the first adapter line being in series in a conductive path between the first plug and the first conductive connection line.

[0029] In some embodiments of the application, a bottom of the first plug is higher or lower in height in a direction perpendicular to the surface of the semiconductor substrate than a top of the first conductive connection line.

[0030] In some embodiments of the application, each second plug is electrically connected to a corresponding second conductive connection line through a second adapter structure, the second adapter structure comprising at least one second adapter plug and at least one second adapter line, the second adapter plug and the second adapter line being in series in a conductive path between the second plug and the second conductive connection line.

[0031] In some embodiments of the application, a bottom of the second plug is higher or lower in height in a direction perpendicular to the surface of the semiconductor substrate than a top of the second conductive connection line.

[0032] In some embodiments of the application, a bottom of the first plug is at the same height in a direction perpendicular to the surface of the semiconductor substrate as a bottom of the second plug.

[0033] In some embodiments of the present application, the top of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate is higher than the top of the test unit.

[0034] In some embodiments of the present application, the test unit comprises a transistor, the transistor comprising a source, a gate, a drain and a channel region, the first pole and the second pole comprising one of the source, the gate and the drain, respectively; or,

[0035] The test unit comprises a capacitor structure, the capacitor structure comprising a first capacitor plate and a second capacitor plate, the first pole comprising the first capacitor plate, and the second pole comprising the second capacitor plate.

[0036] According to the second aspect of the present application, a test method based on the above semiconductor test structure is provided, the test method comprising:

[0037] After confirming the existence of the failed test unit in the test unit array, performing a planarization process on the semiconductor test structure to expose the top of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate;

[0038] The first test probe of the test equipment is sequentially electrically contacted to the top of one of the at least two first plugs, and the second test probe of the test equipment is sequentially electrically contacted to the top of one of the at least two second plugs, and the plurality of test units are sequentially tested to find the failed test unit.

[0039] According to the third aspect of the present application, a test method based on the above semiconductor test structure is provided, the test method comprising:

[0040] After confirming the existence of the failed test unit in the test unit array, cutting the semiconductor test structure along the region between the first plug and the third common conductive line, and the region between the second plug and the fourth common conductive line, to disconnect the electrical connection between the third common conductive line and the first plug, and the electrical connection between the fourth common conductive line and the second plug;

[0041] Exposing the top of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate;

[0042] The first test probe of the test equipment is sequentially electrically contacted to the top of one of the at least two first plugs, and the second test probe of the test equipment is sequentially electrically contacted to the top of one of the at least two second plugs, and the plurality of test units are sequentially tested to find the failed test unit.

[0043] According to the semiconductor test structure provided in the embodiments of the present application, at least two first plugs and at least two second plugs are arranged outside the test unit array and spaced from each other, each first plug is arranged corresponding to a first conductive connection line and electrically connected to the corresponding first conductive connection line, each second plug is arranged corresponding to a second conductive connection line and electrically connected to the corresponding second conductive connection line, and the top height of the at least two first plugs and the at least two second plugs in the direction perpendicular to the surface of the semiconductor substrate is greater than the top of the at least two first conductive connection lines and the at least two second conductive connection lines. During the test of the semiconductor test structure, the semiconductor test structure can be planarized to expose the top of the first plug and the second plug in the direction perpendicular to the surface of the semiconductor substrate, thereby providing an independent test circuit electrically independent of each test unit. When performing failure positioning, the independent test circuit of each test unit can be scanned by using an electron beam, which is beneficial to quickly lock the failed test unit and reduce the time, manpower and analysis cost. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] FIG. 1A A perspective view of a semiconductor test structure according to an embodiment of the present application is shown.

[0046] FIG. 1B A top view of the semiconductor test structure shown. FIG. 1A

[0047] FIG. 2A A perspective view of a semiconductor test structure according to another embodiment of the present application is shown.

[0048] FIG. 2B A top view of the semiconductor test structure shown. FIG. 2A

[0049] FIG. 3 to FIG. 7A A perspective view of a semiconductor test structure according to different embodiments of the present application is shown.

[0050] FIG. 7B A top view of the semiconductor test structure shown. FIG. 7A

[0051] A top view of the semiconductor test structure shown. FIG. 7C FIG. 7A ​​​A perspective view of the semiconductor test structure shown after the common conductive lines and test pads have been cut away;

[0052] FIG. 7D A perspective view of the semiconductor test structure shown after the common conductive lines and test pads have been cut away; FIG. 7C A perspective view of the semiconductor test structure shown after the common conductive lines and test pads have been cut away;

[0053] FIG. 8 A perspective view of the semiconductor test structure shown after the common conductive lines and test pads have been cut away;

[0054] FIG. 9 A perspective view of the semiconductor test structure shown after the common conductive lines and test pads have been cut away;

[0055] FIG. 10 A perspective view of the semiconductor test structure shown after the common conductive lines and test pads have been cut away. DETAILED DESCRIPTION

[0056] In order to make the objects, technical solutions and advantages of the present application more clear, the following will describe the example embodiments according to the present application in detail with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present application.

[0057] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it should be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the present application.

[0058] It should be understood that the present application can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0060] For a thorough understanding of the present application, detailed descriptions will be made in the following description with reference to the accompanying drawings, so as to illustrate the technical solutions proposed by the present application. The optional embodiments of the present application are described in detail as follows, however, the present application can have other implementation manners in addition to these detailed descriptions.

[0061] In the related art, in order to evaluate and verify the reliability of different condition product processes, and monitor the stability of the on-line process, various test cell structures are designed on the wafer, and these structures can be distributed on the scribe lane between each die in the wafer. Reliability testing of these structures is a very important step in the semiconductor process and product manufacturing link.

[0062] Currently, in order to measure the breakdown voltage Vbd of the array structure such as MOS transistor or capacitor, the time-dependent dielectric breakdown TDDB of the dielectric layer, or the dielectric layer leakage, a test structure with upper and lower layers, mutually perpendicular or parallel wiring is designed. Taking a test structure including a MOS transistor test cell array, which performs dielectric layer breakdown test, as an example: for a test cell array, the source, drain and gate of all test cells (i.e. MOS transistors) are respectively connected to the same source test pad, drain test pad and gate test pad through the source wiring, drain wiring and gate wiring. By applying a voltage V, the current flowing through the three terminals of the source test pad, the drain test pad and the gate test pad is tested, so as to determine whether dielectric layer breakdown occurs in the MOS transistor test cell array.

[0063] If electrical breakdown occurs in the MOS transistor test array (i.e. test cell array), it is necessary to deduce the cause of failure by failure analysis method. Generally, the analysis will start with electrical failure analysis (EFA) positioning, and then observe the morphology and other phenomena from the perspective of physical failure analysis (PFA) for further analysis. An important step is to locate the failed test cell in the test cell array. However, due to the limited magnification and clarity of the current OBIRCH (Optical Beam Induced Resistance Change, also known as optical resistance change technology), and the low accuracy of positioning the failure point for the array arranged test structure such as transistor or capacitor, EBIRCH (Electron Beam Induced Resistance Change, also known as electrical resistance change technology) positioning requires a large amount of work.

[0064] In the existing breakdown voltage Vbd test structure, a large number of transistor cells are arranged in an array structure. When an electrical breakdown occurs, it is necessary to first locate the failed test cell, and then proceed to topography observation and failure analysis. However, in the current structure, the test pads are connected to the corresponding electrodes of all test cells by a common conductive line (for example, the gate test pad is connected to all the gates in the test cell array through the gate wiring). Therefore, when performing electrical failure analysis, only the laser beam is introduced through the test pad, and the bright spot area displayed by the OBIRCH covers multiple test cells, and it is not possible to quickly and accurately locate a failed test cell.

[0065] The current failure analysis positioning method is as follows: first, the test structure area to be analyzed is sampled, but some test cell structures will be damaged during the sampling process; then, the structure is scanned using OBIRCH, but it has limited magnification and low accuracy, and can only locate a large area containing the failed test cell; then, EBIRCH and EBAC (Electron Beam Absorbed Current) are used for fine positioning, and the electronic beam is used to scan each point (in resolution size units) in the bright spot area to locate the failed test cell, and then subsequent failure analysis is performed. In this way, a large amount of sampling manpower and analysis cost is required.

[0066] To solve at least some of the above technical problems in the related art, the present application provides the following embodiments.

[0067] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the case of no conflict, the embodiments described below and the features in the embodiments can be combined with each other.

[0068] First, the application scenario of the semiconductor test structure shown in the present application is introduced, which can be applied between dies such as, but not limited to, wafers. Embodiment one

[0069] With reference to FIG. 1A and FIG. 1B , the present application provides a semiconductor test structure, which mainly includes:

[0070] a semiconductor substrate (not shown in the figure);

[0071] The first conductive connection structure and the second conductive connection structure are located on the semiconductor substrate, the first conductive connection structure comprises a plurality of first conductive connection lines 21 arranged horizontally and parallel to each other, and the second conductive connection structure comprises a plurality of second conductive connection lines 31 arranged horizontally and parallel to each other, the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure are arranged alternately and spaced, so as to form an alternating space between the first conductive connection lines 21 and the second conductive connection lines 31;

[0072] A plurality of test units 10 are located on the semiconductor substrate, the plurality of test units 10 are arranged horizontally and arrayed to form a test unit array, the test units 10 are arranged corresponding to the alternating space, and the test units 10 comprise a first pole and a second pole, the first pole and the second pole are connected to the first conductive connection lines 21 and the second conductive connection lines 31 forming the corresponding alternating space respectively;

[0073] At least two first plugs 22 are arranged outside the test unit array and spaced from each other, each first plug 22 is arranged corresponding to a first conductive connection line 21, and each first plug 22 is electrically connected to the corresponding first conductive connection line 21;

[0074] At least two second plugs 32 are arranged outside the test unit array and spaced from each other, each second plug 32 is arranged corresponding to a second conductive connection line 31, and each second plug 32 is electrically connected to the corresponding second conductive connection line 31;

[0075] At least two first plugs 22 and at least two second plugs 32 have a top height in a direction perpendicular to the surface of the semiconductor substrate, which is higher than the top of at least two first conductive connection lines 21 and at least two second conductive connection lines 31.

[0076] The above embodiment has the following beneficial effects: by arranging at least two first plugs 22 and at least two second plugs 32 outside the test unit array and spaced from each other, each first plug 22 is arranged corresponding to a first conductive connection line 21 and electrically connected to the corresponding first conductive connection line 21, and each second plug 32 is arranged corresponding to a second conductive connection line 31 and electrically connected to the corresponding second conductive connection line 31; and at least two first plugs 22 and at least two second plugs 32 have a top height in a direction perpendicular to the surface of the semiconductor substrate, which is higher than the top of at least two first conductive connection lines 21 and at least two second conductive connection lines 31. During the test of the semiconductor test structure, the semiconductor test structure can be planarized to expose the top of the first plug 22 and the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate, thereby providing each test unit 10 with an electrically independent independent test circuit.

[0077] In the failure location, the electron beam can be used for scanning by the independent test circuit of each test unit 10 to quickly lock the failure site (the failed test unit 10), reduce the time, labor and analysis cost. The original test function can be ensured, and the failure location can be quickly and accurately performed to quickly lock the failed test unit 10. The semiconductor test structure can be prepared at the same time as the structure in the bare chip (such as a non-test structure), and only the pattern of the corresponding metal layer in the mask needs to be modified, without affecting the internal structure of the test unit array while realizing the quick and accurate failure location, that is, the semiconductor test structure shown in the embodiment of the application can be prepared without adding a new mask. Specifically, the independent first plug 22 and the second plug 32 are introduced on the basis of the existing test structure, without changing the test function and without adding an additional mask, and the independent test circuit electrically independent of each test unit 10 in the test unit array is provided in the semiconductor test structure, and the test circuit of the entire array is no longer interconnected as a whole. In the failure location, the electrical failure analysis can be directly applied to the nanometer probe needle to scan the independent test circuit electrically connected to the same test unit 10 at both ends (the top of the first plug 22 and the second plug 32) using the electron beam, which is beneficial to quickly lock the failure site. Therefore, for example, for the test of the MOS transistor array, it is not necessary to grind to the top of the gate, damage the test unit 10 structure to prepare a sample, and then perform a large-area fine scanning observation, thereby avoiding the waste of excessive sample preparation labor and analysis cost, thereby saving the sample preparation labor and analysis cost in the failure analysis link.

[0078] The semiconductor test structure will be described in detail below with reference to the accompanying drawings.

[0079] As for the material of the semiconductor substrate, any substrate material can be selected. Exemplarily, the semiconductor substrate can be a substrate of an insulating material, silicon or silicon-on-insulator (SOI). For example, the semiconductor substrate can be a Si-containing semiconductor substrate. The term "Si-containing semiconductor substrate" refers to any semiconductor material containing silicon. Exemplary examples of Si-containing semiconductor materials that can be used as a substrate include Si, SiGe, SiC, SiGeC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI), but are not limited to this. Depending on the device to be manufactured, the substrate can be undoped or doped. Exemplarily, the semiconductor substrate can be prepared from a single-crystal silicon material.

[0080] As for the type of the test unit 10, any electrical device can be used. For example, the test unit 10 can include any one or any combination of a transistor structure, a capacitor structure, etc. Depending on the type of the test unit 10, the electrodes of the test unit 10, such as but not limited to, a source electrode, a drain electrode, a gate electrode, an emitter electrode, a collector electrode, a positive electrode, a negative electrode, etc., are connected to the first conductive connection line 21 and the second conductive connection line 31, so that the test unit 10 can be tested through the first conductive connection line 21 or the second conductive connection line 31.

[0081] For example, the test unit 10 can include a transistor, which can include a source electrode, a gate electrode, a drain electrode, and a channel region. In this case, the first electrode and the second electrode can include one of the source electrode, the gate electrode, and the drain electrode, respectively. Specifically, the first electrode and the second electrode can be the source electrode and the drain electrode, respectively, or the source electrode and the gate electrode, respectively, or the drain electrode and the gate electrode, respectively.

[0082] It should be noted that the transistor included in the test unit 10 can be any type of transistor structure. For example, the transistor can be any type of transistor such as but not limited to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulate-Gate Bipolar Transistor (IGBT), a bipolar transistor, a diode, etc. The first electrode and the second electrode can be any electrode of the transistor, respectively.

[0083] For example, the test unit 10 can include a capacitor structure including a first capacitor plate and a second capacitor plate. The first electrode can include the first capacitor plate, and the second electrode can include the second capacitor plate.

[0084] The capacitor structure can be any type of capacitor structure. For example, the capacitor structure can be any type of capacitor such as but not limited to a cylindrical capacitor, a plate capacitor, etc.

[0085] The capacitor structure and / or the transistor can individually or collectively form a storage unit or a part of a storage unit having a storage function. For example, the storage unit can be any unit structure capable of storing one bit of binary information such as but not limited to a DRAM storage unit, an MRAM storage unit, a FeRAM storage unit, etc.

[0086] Of course, it should be noted that the test unit 10 is not limited to the above-mentioned enumerated structures, and other test units 10 capable of forming an array structure are also applicable and within the scope of the present application.

[0087] The first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure can be arranged in various manners as long as the interleaved spaces for arranging part or all of the structures of the test unit 10 can be formed between the interleaved first conductive connection lines 21 and second conductive connection lines 31. Some examples of interleaved and spaced arrangement are described as follows.

[0088] In some embodiments, with reference to FIG. 1A and FIG. 1B , the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure are interleaved and spaced to form interleaved spaces between the interleaved first conductive connection lines 21 and second conductive connection lines 31, which includes that the extension directions of the first conductive connection lines 21 and the second conductive connection lines 31 are crossed, the first conductive connection lines 21 and the second conductive connection lines 31 are located in different layers, the interleaved spaces are located at the crossing of the first conductive connection lines 21 and the second conductive connection lines 31, and the plurality of interleaved spaces are arranged in an array.

[0089] That is, in the present embodiment, with reference to FIG. 1A and FIG. 1B , the first conductive connection lines 21 and the second conductive connection lines 31 are located in different layers, specifically, the first conductive connection lines 21 can be located above the second conductive connection lines 31 and spaced by the interlayer dielectric layer, or the second conductive connection lines 31 can be located above the first conductive connection lines 21 and spaced by the interlayer dielectric layer. The extension directions of the first conductive connection lines 21 and the second conductive connection lines 31 form a non-zero angle such as but not limited to 90°, 75°, 105°, etc., so that the extension directions of the first conductive connection lines 21 and the second conductive connection lines 31 are crossed. At this time, each first conductive connection line 21 and each second conductive connection line 31 have a crossing, so that a plurality of crossings are formed between all the first conductive connection lines 21 and all the second conductive connection lines 31, and the interleaved spaces for arranging the test unit 10 are located at the crossings of the first conductive connection lines 21 and the second conductive connection lines 31, so that a plurality of interleaved spaces can be formed. Due to the horizontal arrangement of the plurality of first conductive connection lines 21 parallel to each other and the horizontal arrangement of the plurality of second conductive connection lines 31 parallel to each other, the plurality of interleaved spaces can be arranged in an array along the extension directions of the first conductive connection lines 21 and the second conductive connection lines 31, so that the plurality of test units are arranged in an array to form a test unit array.

[0090] For example, with reference to FIG. 1A and FIG. 1BA first conductive connection structure and a second conductive connection structure are disposed on the semiconductor substrate. The first conductive connection structure includes a plurality of first conductive connection lines 21, each of which extends along a first direction, and the plurality of first conductive connection lines 21 are arranged along a second direction with an insulating spacing between adjacent first conductive connection lines 21 by a dielectric material. The first direction and the second direction are arranged in a cross manner, and both the first direction and the second direction are parallel to the surface of the semiconductor substrate. For example, the first direction and the second direction can be arranged in a perpendicular manner, and of course, the first direction and the second direction are not limited to the perpendicular arrangement manner, as long as the first direction and the second direction have an included angle to form a cross arrangement manner, which is within the protection scope of the embodiments of the present application.

[0091] Referring to FIG. 1A and FIG. 1B The second conductive connection structure includes at least two second conductive connection lines 31, each of which extends along the second direction, and the at least two second conductive connection lines 31 are arranged along the first direction with an insulating spacing between adjacent second conductive connection lines 31 by a dielectric material. For example, each of the second conductive connection lines 31 can be parallel to the surface of the semiconductor substrate.

[0092] Referring to FIG. 1A and FIG. 1B The first conductive connection lines 21 and the second conductive connection lines 31 are located on two different planes in a direction perpendicular to the surface of the semiconductor substrate, i.e., the first conductive connection lines 21 and the second conductive connection lines 31 are located in different layers. For example, the first conductive connection lines 21 and the second conductive connection lines 31 are located in different metal layers of the semiconductor test structure.

[0093] Referring to FIG. 1A and FIG. 1B A plurality of test units 10 are further disposed on the semiconductor substrate, and the plurality of test units 10 are located at the intersection of the at least two first conductive connection lines 21 and the at least two second conductive connection lines 31, so that the plurality of test units 10 form a test unit array.

[0094] Referring to FIG. 1A and FIG. 1BAt least two first plugs 22 are further arranged on the semiconductor substrate, and the at least two first plugs 22 are located outside the array of test units. Each first plug 22 is arranged corresponding to a first conductive connection line 21, and each first plug 22 is electrically connected to the corresponding first conductive connection line 21 to form an independent test circuit. Specifically, the different first plugs 22 are insulated and separated from each other by a dielectric material such as but not limited to an oxide, and the different first conductive connection lines 21 are also insulated and separated from each other by a dielectric material such as but not limited to an oxide, so that each first plug 22 is only electrically connected to the corresponding first conductive connection line 21, and is insulated and separated from other first conductive connection lines 21 by the dielectric material, and is electrically independent from each other.

[0095] The top height of each first plug 22 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the at least two first conductive connection lines 21 and the at least two second conductive connection lines 31. That is, the top height of the first plug 22 in the direction perpendicular to the surface of the semiconductor substrate is not only higher than the top height of all the first conductive connection lines 21, but also higher than the top height of all the second conductive connection lines 31. During the grinding process from the top surface of the semiconductor substrate downward, the top of the first plug 22 is exposed before the first conductive connection lines 21 and the second conductive connection lines 31.

[0096] It should be noted that the electrical connection between the first plug 22 and the first conductive connection line 21 can be achieved in various ways, and some exemplary ways are described as follows.

[0097] Exemplarily, referring to FIG. 3 , 2A and FIG. 4 , the bottom of the first plug 22 can be directly in contact with the corresponding first conductive connection line 21 for electrical connection, so as to achieve the electrical connection between the first plug 22 and the first conductive connection line 21.

[0098] However, sometimes considering the spatial arrangement and process sequence in the process, the bottom of the first plug 22 is not directly electrically connected to the corresponding first conductive connection line 21.

[0099] In some embodiments, each first plug 22 is electrically connected to a corresponding first conductive connection line 21 through a first adapter structure. The first adapter structure includes at least one first adapter plug 26 and at least one first adapter line 25, and the first adapter plug 26 and the first adapter line 25 are connected in series on the conductive path between the first plug 22 and the first conductive connection line 21. Specifically, the bottom of the first plug 22 can also be indirectly electrically connected to a corresponding first conductive connection line 21 through the first adapter structure composed of the first adapter line 25 and the first adapter plug 26 arranged on the semiconductor substrate. It is only necessary to ensure that the first adapter structures corresponding to different first plugs 22 are electrically independent of each other and are insulated from each other, so as to ensure that the electrical independent function of the independent test circuit is not lost.

[0100] When the first plug 22 is electrically connected to the corresponding first conductive connection line 21 through the first adapter structure, the height of the bottom of the first plug 22 in the direction perpendicular to the surface of the semiconductor substrate can be higher or lower than the top of the first conductive connection line 21. Specifically, whether the height of the bottom of the first plug 22 is higher or lower than the top of the first conductive connection line 21 can be determined according to the specific positions of the first plug 22 and the first conductive connection line 21 and the preparation process.

[0101] In some embodiments, the height of the bottom of the first plug 22 is higher than the top of the first conductive connection line 21. At this time, in the vertical direction perpendicular to the semiconductor substrate, the first adapter plug 26 and the first adapter line 25 can be located between the bottom of the first plug 22 and the first conductive connection line 21, that is, the first adapter plug 26 can be connected to the upper surface of the first conductive connection line 21 and then extend upward to be connected to the first adapter line 25, and the upper surface of the first adapter line 25 is connected to the bottom of the first plug 22.

[0102] For example, sometimes the first adapter plug 26 connected to the first conductive connection line 21 does not directly communicate upward, but is first connected to the first adapter line 25 located in the lower layer of the first conductive connection line 21, and then is connected to the upper layer through the first plug 22, that is, the bottom of the first plug 22 is lower than the first conductive connection line 21.

[0103] The present application is not limited thereto. In some embodiments, the first adapter structure includes a plurality of first adapter lines 25 and a plurality of first adapter plugs 26, and the first adapter lines 25 and the first adapter plugs 26 are connected in series between the first plug 22 and the first conductive connection line 21 alternately.

[0104] For example, referring to FIG. 5 and FIG. 4The semiconductor test structure further comprises at least two first transfer lines 25 extending along the first direction and arranged at intervals along the second direction, each first transfer line 25 corresponding to a first conductive connection line 21 and being located below the corresponding first conductive connection line 21, and adjacent two first transfer lines 25 are insulated and separated from each other by a dielectric material, thereby maintaining electrical independence from each other. Each first transfer line 25 is electrically connected to the corresponding first conductive connection line 21 by a first transfer plug 26, and is not connected to other first conductive connection lines 21 and is electrically independent of each other. And each first transfer line 25 corresponds to a first plug 22 and is in direct contact and electrical connection with the bottom of the corresponding first plug 22, and is not connected to other first plugs 22 and is electrically independent of each other. Thus, the bottom of the first plug 22 is sequentially electrically connected to the corresponding first transfer line 25, the first transfer plug 26, and the corresponding first conductive connection line 21, forming an electrically independent independent test circuit.

[0105] For example, referring to FIG. 5 and FIG. 1A The first transfer line 25 can be located in the adjacent metal layer below the first conductive connection line 21, and the adjacent metal layers are of course insulated and separated by a dielectric layer. For example, the first transfer line 25 and the first conductive connection line 21 can also include at least one metal layer, that is, the metal layers where the first transfer line 25 and the first conductive connection line 21 are located are not adjacent.

[0106] For example, referring to FIG. 1B and FIG. 1A At least two second plugs 32 are further provided on the semiconductor substrate and are spaced apart from each other, and the at least two second plugs 32 are located outside the test cell array, each second plug 32 corresponding to a second conductive connection line 31, and each second plug 32 is electrically connected to the corresponding second conductive connection line 31 to form an electrically independent independent test circuit. Specifically, different second plugs 32 are insulated and separated by a dielectric material such as but not limited to oxide, and different second conductive connection lines 31 are also insulated and separated by a dielectric material such as but not limited to oxide, so that each second plug 32 is only electrically connected to its corresponding second conductive connection line 31, and is insulated and separated from other second conductive connection lines 31 by a dielectric material, and is electrically independent of each other.

[0107] and the top height of each second plug 32 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the at least two first conductive connection lines 21 and the at least two second conductive connection lines 31. That is, the top height of the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of all the first conductive connection lines 21 and greater than the top height of all the second conductive connection lines 31, and in the process of grinding the semiconductor substrate from the top surface downward, the top of the second plug 32 is exposed before the first conductive connection lines 21 and the second conductive connection lines 31.

[0108] It should be noted that the electrical connection between the second plug 32 and the second conductive connection line 31 can be achieved in various ways, and some exemplary ways are described below.

[0109] Exemplarily, referring to FIG. 1B and FIG. 4 the bottom of the second plug 32 can be in direct contact with the corresponding second conductive connection line 31 for electrical connection, thereby achieving the electrical connection between the second plug 32 and the second conductive connection line 31.

[0110] However, sometimes considering the spatial arrangement and process sequence in the process, the bottom of the second plug 32 is not directly electrically connected to the corresponding second conductive connection line 31.

[0111] In some other embodiments, each second plug 32 is electrically connected to the corresponding second conductive connection line 31 through a second adapter structure, and the second adapter structure includes at least one second adapter plug 36 and at least one second adapter line 35, and the second adapter plug 36 and the second adapter line 35 are in series in the conductive path between the second plug 32 and the second conductive connection line 31. Specifically, the bottom of the second plug 32 can also be indirectly electrically connected to the corresponding second conductive connection line 31 through the second adapter structure composed of the second adapter line 35 and the second adapter plug 36 arranged on the semiconductor substrate. However, it is necessary to ensure that the second adapter structures corresponding to different second plugs 32 are electrically independent of each other and are insulated from each other, thereby ensuring the electrical independence of the independent test circuit.

[0112] When the second plug 32 is electrically connected to the corresponding second conductive connection line 31 through the second adapter structure, the height of the bottom of the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate can be higher or lower than the top of the second conductive connection line 31, and the height of the bottom of the second plug 32 can be higher or lower than the top of the second conductive connection line 31 according to the specific positions of the second plug 32 and the second conductive connection line 31 and the preparation process.

[0113] In some embodiments, the bottom of the second plug 32 is higher than the top of the second conductive connection line 31, and the second transfer plug 36 and the second transfer line 35 are located between the bottom of the second plug 32 and the second conductive connection line 31 in the vertical direction perpendicular to the semiconductor substrate, that is, the second transfer plug 36 is connected to the upper surface of the second conductive connection line 31 and extends upward to connect to the second transfer line 35, and the upper surface of the second transfer line 35 is connected to the bottom of the second plug 32.

[0114] For example, the second transfer plug 36 connected to the second conductive connection line 31 does not directly communicate upward, but is connected to the second transfer line 35 located in the lower layer of the second conductive connection line 31, and then accesses the upper layer through the second plug 32, that is, the bottom of the second plug 32 is lower than the second conductive connection line 31.

[0115] The present application is not limited to this, and in some embodiments, the second transfer structure includes a plurality of second transfer lines 35 and a plurality of second transfer plugs 36, and the second transfer lines 35 and the second transfer plugs 36 are alternately connected in series between the second plug 32 and the second conductive connection line 31.

[0116] For example, referring to FIG. 5 and FIG. 4 , the semiconductor test structure further includes at least two second transfer lines 35 extending along the second direction and arranged at intervals along the first direction, each second transfer line 35 corresponds to a second conductive connection line 31 and is located below the corresponding second conductive connection line 31, and the two adjacent second transfer lines 35 are insulated and separated by a dielectric material, thereby maintaining electrical independence from each other. Each second transfer line 35 is electrically connected to the corresponding second conductive connection line 31 through the second transfer plug 36, and is not connected to other second conductive connection lines 31, and is electrically independent from each other. And each second transfer line 35 corresponds to a second plug 32 and is directly in contact and electrically connected with the bottom of the corresponding second plug 32, and is not connected to other second plugs 32, and is electrically independent from each other. Thus, the bottom of the second plug 32 is sequentially electrically connected to the corresponding second conductive connection line 31 through the corresponding second transfer line 35 and the second transfer plug 36, forming an electrically independent independent test circuit.

[0117] For example, referring to FIG. 5 and FIG. 1A , the second transfer line 35 can be located in the adjacent metal layer below the second conductive connection line 31, and of course the adjacent metal layers are insulated and separated by a dielectric layer. For example, the second transfer line 35 and the second conductive connection line 31 can also include at least one metal layer, that is, the metal layers where the second transfer line 35 and the second conductive connection line 31 are not adjacent.

[0118] For example, in the direction perpendicular to the surface of the semiconductor substrate, the bottom height of the first plug 22 is the same as the bottom height of the second plug 32. It should be noted that this can be applied to the case where the first plug 22 is directly in contact with the first conductive connection line 21 and the second plug 32 is directly in contact with the second conductive connection line 31, in which case the first conductive connection line 21 and the second conductive connection line 31 are located in the same layer.

[0119] The above embodiments can also be applied to the case where the first plug 22 is connected to the first conductive connection line 21 through a first transfer structure and / or the second plug 32 is connected to the second conductive connection line 31 through a second transfer structure. For example, in the case where the first transfer structure and the second transfer structure are both present, the first transfer line 25 and the second transfer line 35 can be located in the same layer, so that the bottom height of the first plug 22 is the same as the bottom height of the second plug 32 and the bottom of the first plug 22 is in contact with the upper surface of the first transfer line 25 and the bottom of the second plug 32 is in contact with the upper surface of the second conductive connection line 31. For example, in the case where only the first transfer structure is present and the second transfer structure is not present, the first transfer line 25 and the second conductive connection line 31 can be located in the same layer, so that the bottom height of the first plug 22 is the same as the bottom height of the second plug 32, the bottom of the first plug 22 is in contact with the upper surface of the first transfer line 25, and the bottom of the second plug 32 is in contact with the upper surface of the second conductive connection line 31. In the case where only the second transfer structure is present and the first transfer structure is not present, the second transfer line 35 and the first conductive connection line 21 can be located in the same layer, so that the bottom height of the first plug 22 is the same as the bottom height of the second plug 32, the bottom of the first plug 22 is in contact with the upper surface of the first conductive connection line 21, and the bottom of the second plug 32 is in contact with the upper surface of the second transfer line 35.

[0120] In this way, the first plug 22 and the second plug 32 can be prepared at the same time, the conductive line connected to the first plug 22 (the first conductive connection line 21 or the first transfer line 25) and the conductive line connected to the second plug 32 (the second conductive connection line 31 or the second transfer line 35) are prepared in the same layer, avoiding the preparation of deep holes of different depths, reducing the process difficulty, and further reducing the production cost.

[0121] In some embodiments, the top height of the at least two first plugs 22 and the at least two second plugs 32 in the direction perpendicular to the surface of the semiconductor substrate is higher than the top of the test unit 10. Thus, when the semiconductor test structure is ground from top to bottom, the top of the first plug 22 and the second plug 32 can be exposed without grinding the test unit 10, without damaging the test unit 10, so as to accurately locate the failed test unit 10 in the test unit array.

[0122] For example, referring to FIG. 1B and FIG. 1AIn the case that the top height of the test unit 10 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the first conductive connecting line 21 and the second conductive connecting line 31 in the direction perpendicular to the surface of the semiconductor substrate, the top height of each first plug 22 in the direction perpendicular to the surface of the semiconductor substrate can be greater than the top height of the test unit 10. Thus, when the semiconductor test structure is ground from top to bottom, the top of the first plug 22 can be exposed without grinding to the test unit 10, without damaging the test unit 10, so as to accurately locate the failed test unit 10 in the test unit array.

[0123] For example, referring to FIG. 1B and FIG. 2A In the case that the top height of the test unit 10 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the first conductive connecting line 21 and the second conductive connecting line 31 in the direction perpendicular to the surface of the semiconductor substrate, the top height of each second plug 32 in the direction perpendicular to the surface of the semiconductor substrate can be greater than the top height of the test unit 10. Thus, when the semiconductor test structure is ground from top to bottom, the top of the second plug 32 can be exposed without grinding to the test unit 10, without damaging the test unit 10, so as to accurately locate the failed test unit 10 in the test unit array.

[0124] For example, referring to FIG. 2B and FIG. 2A The semiconductor test structure can further comprise a first common conductive line 23 on the top of the first plug 22, the first common conductive line 23 electrically connecting at least two first plugs 22. For example, the first common conductive line 23 can extend in the same direction as the arrangement direction of the plurality of first plugs 22, and perpendicular to the extension direction of the first conductive connecting line 21, thereby connecting all the first plugs 22. For example, referring to FIG. 2B and FIG. 2A The first common conductive line 23 extends in the second direction to electrically connect at least two first plugs 22 arranged in the second direction.

[0125] The above embodiment has the following beneficial effects: by forming the first common conductive line 23 on the top of the first plug 22 to electrically connect at least two first plugs 22, it is convenient to apply a voltage V for example but not limited to, to test the current flowing through the test unit array, so as to determine whether the dielectric layer breakdown occurs.

[0126] It should be noted that the manner in which the first common conductive line 23 electrically connects the at least two first plugs 22 can adopt various manners, and some manners are exemplarily introduced as follows.

[0127] For example, referring to FIG. 2B andFIG. 2A The first common conductive line 23 can be directly connected to the top of the first plug 22, so as to realize direct electrical connection between the first common conductive line 23 and the first plug 22.

[0128] In other embodiments, the first common conductive line 23 can be electrically connected to the first plug 22 through an interconnection structure composed of conductive connection lines and metal plugs arranged on the semiconductor substrate, so as to realize indirect electrical connection between the first common conductive line 23 and the first plug 22.

[0129] For example, referring to FIG. 2B and FIG. 2A The semiconductor test structure further comprises a second common conductive line 33 located at the top of the second plug 32, and the second common conductive line 33 is electrically connected to at least two second plugs 32. For example, the second common conductive line 33 can extend in the same direction as the arrangement direction of the plurality of second plugs 32, and perpendicular to the extension direction of the second conductive connection line 31, so as to connect all the second plugs 32. For example, referring to FIG. 2B and FIG. 2A The second common conductive line 33 extends in the first direction to electrically connect at least two second plugs 32 arranged at intervals in the first direction.

[0130] The above embodiments have the following beneficial effects: by forming the second common conductive line 33 electrically connected to at least two second plugs 32 at the top of the second plug 32, it is convenient to apply a voltage V for example but not limited to, through the second common conductive line 33, to test the current flowing through the test cell array, so as to determine whether the dielectric layer breakdown occurs.

[0131] It should be noted that the second common conductive line 33 can be electrically connected to at least two second plugs 32 in various ways, some of which are exemplarily introduced as follows.

[0132] For example, referring to FIG. 2B and FIG. 3 The second common conductive line 33 can be directly connected to the top of the second plug 32, so as to realize direct electrical connection between the second common conductive line 33 and the second plug 32.

[0133] In other embodiments, the second common conductive line 33 can be electrically connected to the second plug 32 through an interconnection structure composed of conductive connection lines and metal plugs arranged on the semiconductor substrate, so as to realize indirect electrical connection between the second common conductive line 33 and the second plug 32.

[0134] For example, the first common conductive line 23 and the second common conductive line 33 are at the same height in the direction perpendicular to the surface of the semiconductor substrate. Specifically, the top of the first plug 22 and the top of the second plug 32 can be at the same height, and the first common conductive line 23 and the second common conductive line 33 are at the same layer, so that the first common conductive line 23 and the second common conductive line 33 are directly electrically connected to the top of the first plug 22 and the second plug 32 respectively. By arranging the first common conductive line 23 and the second common conductive line 33 at the same height, the top of the first plug 22 and the top of the second plug 32 can be exposed at the same time when the semiconductor substrate is grinded from top to bottom to a certain extent.

[0135] Of course, in other embodiments, the first common conductive line 23 and the second common conductive line 33 can be at different heights in the direction perpendicular to the surface of the semiconductor substrate, i.e., the first common conductive line 23 and the second common conductive line 33 are at different layers.

[0136] For example, referring to FIG. 3 and FIG. 1A , the semiconductor test structure can further include a first test pad 24 electrically connected to the first common conductive line 23, and a second test pad 34 electrically connected to the second common conductive line 33, the first test pad 24 and the second test pad 34 are at the same height in the direction perpendicular to the surface of the semiconductor substrate.

[0137] The above embodiments have the following beneficial effects: by arranging the first test pad 24 electrically connected to the first common conductive line 23, and the second test pad 34 electrically connected to the second common conductive line 33, when a voltage V is applied to the first common conductive line 23, the voltage V can be applied to the first common conductive line 23 through the first test pad 24, thereby reducing the difficulty of applying the voltage V to the first common conductive line 23. When a voltage V is applied to the second common conductive line 33, the voltage V can be applied to the second common conductive line 33 through the second test pad 34, thereby reducing the difficulty of applying the voltage V to the second common conductive line 33. Furthermore, by arranging the first test pad 24 and the second test pad 34 at the same layer of the semiconductor test structure, the voltage V can be applied to the first test pad 24 and the second test pad 34 at the same time, for example, the current flowing through the test cell array can be tested to determine whether the dielectric layer breakdown occurs.

[0138] It should be noted that the electrical connection between the first common conductive line 23 and the first test pad 24 can be achieved in various ways.

[0139] In some embodiments, referring to FIG. 1BThe first common conductive line 23 and the first test pad 24 can be connected by direct contact. For example, the first common conductive line 23 and the first test pad 24 can be disposed on the same metal layer of the semiconductor substrate.

[0140] In other embodiments, the first common conductive line 23 may also be electrically connected to the first test pad 24 through an interconnect structure formed by conductive connecting lines and metal plugs disposed on a semiconductor substrate.

[0141] Similarly, the electrical connection between the second common conductive line 33 and the second test pad 34 can be achieved in various ways.

[0142] In some embodiments, reference FIG. 2A The second common conductive line 33 and the second test pad 34 can be connected by direct contact. For example, the second common conductive line 33 and the second test pad 34 can be disposed on the same metal layer of the semiconductor substrate.

[0143] In other embodiments, the second common conductive line 33 may also be electrically connected to the second test pad 34 through an interconnect structure formed by conductive connecting lines and metal plugs disposed on a semiconductor substrate.

[0144] For example, the first test pad 24 and the second test pad 34 can both be located on the top metal layer of the semiconductor test structure, thus exposing the first test pad 24 and the second test pad 34 to the semiconductor test structure for testing without grinding and damaging the interconnect structure. Optionally, the first test pad 24, the second test pad 34, the first common conductive line 23, and the second common conductive line 33 are all located on the top metal layer of the semiconductor test structure, and the first common conductive line 23 and the second common conductive line 33 are directly connected to the first plug 22 and the second plug 32, respectively. Optionally, the first common conductive line 23 and the second common conductive line 33 are both located on the top metal layer of the semiconductor test structure. Thus, the tops of the first plug 22 and the second plug 32 can be exposed without grinding and damaging the interconnect structure, allowing for the formation of independent test circuits for testing.

[0145] For example, the first conductive connection line 21 can be stacked with one or N metal layers above it, but the first conductive connection line 21 and the corresponding first plug 22 are designed to be electrically connected independently, and are insulated from other first conductive connection lines 21 and first plugs 22, electrically independent and not interfering with each other. The first common conductive line 23 electrically connected to each first conductive connection line 21 in the top metal layer of the stacked structure is electrically connected, and then the first test pad 24 is connected. The second conductive connection line 31 can be stacked with one or N metal layers above it, but the second conductive connection line 31 and the corresponding second plug 32 are designed to be electrically connected independently, and are insulated from other second conductive connection lines 31 and second plugs 32, electrically independent and not interfering with each other. The second common conductive line 33 electrically connected to each second conductive connection line 31 in the top metal layer of the stacked structure is electrically connected, and then the second test pad 34 is connected. The positions of the first test pad 24 and the second test pad 34 are in the same layer.

[0146] For example, the test unit array can be a storage unit array composed of transistor and capacitor structures. At this time, referring to FIG. 2B and FIG. 2A One of the first conductive connection line 21 and the second conductive connection line 31 can be a word line (Word line, abbreviated as WL), and the other can be a bit line (Bit line, abbreviated as BL).

[0147] For example, referring to FIG. 2B and FIG. 2A A semiconductor test structure is shown, the first conductive connection line 21 is a bit line (Bit line, BL), and the second conductive connection line 31 is a word line (Word line, WL). The second conductive connection line 31 and the first conductive connection line 21 are located in different layers, the upper layer of the second conductive connection line 31 is designed perpendicularly to the lower layer of the first conductive connection line 21, and a test unit array composed of structures such as but not limited to transistors and / or capacitors is arranged at the cross-over position.

[0148] A plurality of first conductive connection lines 21 are designed to be electrically independent, each first conductive connection line 21 is electrically connected by a corresponding first plug 22 and connected to the metal layer above it, and the metal layer above it is provided with a first common conductive line 23. The top of the first common conductive line 23 electrically connects all the first plugs 22, so that all the first conductive connection lines 21 are electrically connected through the first common conductive line 23 and then connected through the same layer first test pad 24.

[0149] The second conductive connection lines 31 are electrically independent. Each second conductive connection line 31 is electrically connected to the metal layer above it by a corresponding second plug 32. The metal layer above it has a second common conductive line 33, which is electrically connected to the top of all second plugs 32, so that all second conductive connection lines 31 are electrically connected through the second common conductive line 33 and then led out through the second test pads 34 in the same layer.

[0150] FIG. 2B and FIG. 1A The semiconductor test structure shown is different from existing test structures in that: between each first conductive connection line 21 and the first common conductive line 23, an independent first plug 22 is designed for electrical connection; and between each second conductive connection line 31 and the second common conductive line 33, an independent second plug 32 is designed for electrical connection. The structure is characterized by providing an independent circuit for each test unit 10 in the test unit array.

[0151] For FIG. 1B and FIG. 7A The semiconductor test structure shown has the advantage that it can quickly and accurately locate the failed test unit 10. As an example, a failure analysis method for the semiconductor test structure is introduced as follows.

[0152] After confirming the existence of failed units in the test unit array, electrical failure analysis is performed to locate the failed test unit 10: first, the first test pads 24, the second test pads 34, the first common conductive line 23, and the second common conductive line 33 are removed by planarization, which can be chemical mechanical polishing, to obtain FIG. 7B and FIG. 7A The result shown exposes the top of the first plug 22 and the second plug 32. At this time, each test unit 10 in the test unit array is connected by an independent test circuit formed by the first plug 22, the first conductive connection line 21, the second conductive connection line 31, and the second plug 32. Then, the first test probe of the test equipment is electrically contacted to the top of one of the at least two first plugs 22, and the second test probe of the test equipment is electrically contacted to the top of one of the at least two second plugs 32. The test units 10 are tested in sequence to find the failed test unit 10. As an example, OBIRCH can be used to locate a large area by bright spots, and then EBIRCH probes are sequentially inserted into each first plug 22 corresponding to the first conductive connection line 21 and each second plug 32 corresponding to the second conductive connection line 31 for scanning and measurement, which can quickly and accurately locate the failed test unit 10.

[0153] As an example, refer to FIG. 7B andFIG. 7A The semiconductor test structure further comprises: a third common conductive line 27 located on the side of the first plug 22 away from the test cell array and electrically connected to the at least two first conductive connection lines 21, and the third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb structure. Specifically, the third common conductive line 27 is located in the same layer as the first conductive connection lines 21 and is electrically connected to the same end of the at least two first conductive connection lines 21 to form the first comb structure with the at least two first conductive connection lines 21. At this time, the bottom of the first plug 22 and the connection point of the first conductive connection lines 21 are located between the third common conductive line 27 and the test cell array.

[0154] For example, referring to FIG. 7B and FIG. 7A , the third common conductive line 27 extends in the second direction, the third common conductive line 27 is located on the side of the first plug 22 away from the test cell array and electrically connected to the first end of the at least two first conductive connection lines 21, and the third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb structure.

[0155] Specifically, referring to FIG. 7B and FIG. 7A , the third common conductive line 27 is further provided on the semiconductor substrate, the third common conductive line 27 extends in the second direction and is located on the side of the first plug 22 away from the test cell array, that is, the first plug 22 is located between the test cell array and the third common conductive line 27, and the electrical connection point of the first plug 22 and the corresponding first conductive connection line 21 is located between the third common conductive line 27 and the test cell array. The third common conductive line 27 is also electrically connected to the first end of the at least two first conductive connection lines 21, so that the third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb structure, that is, the third common conductive line 27 and the at least two first conductive connection lines 21 are located in the same metal layer, and the third common conductive line 27 and the first conductive connection line 21 are directly in contact and electrically connected.

[0156] The above embodiment has the following beneficial effects: by providing the third common conductive line 27 on the basis of the first plug 22, the third common conductive line 27 is located on the side of the first plug 22 away from the test cell array and electrically connected to the first end of the at least two first conductive connection lines 21, and the third common conductive line 27 and the at least two first conductive connection lines 21 form a first comb structure, so that the first plug 22 can be used as a redundant plug to locate the failed test cell 10 when subsequent electrical failure analysis is performed on the semiconductor test structure.

[0157] The above embodiment is the same as the prior test structure in that each first conductive connection line 21 in the regular arrangement is electrically connected with the third common conductive line 27 in the same layer. The above embodiment is different from the prior test structure in that a redundant, electrically independent first plug 22 is arranged on each first conductive connection line 21 in the regular arrangement between the test unit array and the third common conductive line 27. The structure is characterized in that, after the third common conductive line 27 is removed by cutting or the like, the first plug 22 can be used to provide each test unit 10 in the test unit array with an electrically independent independent test circuit, facilitating quick positioning of the failed test unit 10.

[0158] The lead-out mode of the first plug 22 can extend upward by at least one metal layer, and preferably, the top of the first plug 22 is higher than the top of the test unit 10. Preferably, the first plug 22 can be directly extended to the top metal layer of the semiconductor test structure to provide each first conductive connection line 21 with an electrically independent independent test circuit, thereby cooperating with the second conductive connection line 31 to provide each test unit 10 with an electrically independent independent test circuit.

[0159] For example, referring to FIG. 7B and FIG. 7A , the semiconductor test structure can further include a third test pad 28 electrically connected with the third common conductive line 27.

[0160] The above embodiment has the following beneficial effects: by arranging the third test pad 28 electrically connected with the third common conductive line 27, when a voltage V is applied to the third common conductive line 27, the third test pad 28 can be used to reduce the difficulty of applying the voltage V to the third common conductive line 27.

[0161] It should be noted that the electrical connection between the third common conductive line 27 and the third test pad 28 can be achieved in various ways.

[0162] In some embodiments, referring to FIG. 7B and FIG. 7A , the third common conductive line 27 and the third test pad 28 can be in direct contact with each other. For example, the third common conductive line 27 and the third test pad 28 can be arranged in the same metal layer of the semiconductor substrate.

[0163] In some other embodiments, the third common conductive line 27 can also be electrically connected to the third test pad 28 through an interconnection structure formed by the conductive connection lines and the metal plug disposed on the semiconductor substrate, so that the third test pad 28 can be arranged in any metal layer, for example, so that the third test pad 28 is arranged in the top metal layer, and the difficulty of applying a voltage V to the third test pad 28 can be reduced.

[0164] For example, referring to FIG. 7B and FIG. 7A , the semiconductor test structure further comprises: a fourth common conductive line 37 located on the side of the second plug 32 away from the test cell array and electrically connected to the first ends of the at least two second conductive connection lines 31, the fourth common conductive line 37 and the at least two second conductive connection lines 31 forming a second comb structure.

[0165] For example, referring to FIG. 7B and FIG. 7A , the fourth common conductive line 37 extends in the first direction, the fourth common conductive line 37 is located on the side of the second plug 32 away from the test cell array and electrically connected to the first ends of the at least two second conductive connection lines 31, and the fourth common conductive line 37 and the at least two second conductive connection lines 31 form a second comb structure.

[0166] Specifically, referring to FIG. 7B and FIG. 7A , the semiconductor substrate further comprises a fourth common conductive line 37, the fourth common conductive line 37 extends in the first direction and is located on the side of the second plug 32 away from the test cell array, i.e. the second plug 32 is located between the test cell array and the fourth common conductive line 37, and the electrical connection point of the second plug 32 and the corresponding second conductive connection line 31 is located between the fourth common conductive line 37 and the test cell array. The fourth common conductive line 37 is also electrically connected to the first ends of the at least two second conductive connection lines 31, so that the fourth common conductive line 37 and the at least two second conductive connection lines 31 form a second comb structure, i.e. the fourth common conductive line 37 and the at least two second conductive connection lines 31 are located in the same metal layer, and the fourth common conductive line 37 and the second conductive connection line 31 are directly in contact and electrically connected.

[0167] The above embodiment has the following beneficial effects: by arranging the fourth common conductive wire 37 on the basis of the second plug 32, the fourth common conductive wire 37 is located on the side of the second plug 32 away from the test unit array and electrically connected to the first ends of the at least two second conductive connection wires 31, and the fourth common conductive wire 37 and the at least two second conductive connection wires 31 form a second comb structure, so that the second plug 32 can be used as a redundant plug for subsequent electrical failure analysis of the semiconductor test structure to locate the failed test unit 10.

[0168] The above embodiment is different from the prior art test structure in that: between the test unit array and the fourth common conductive wire 37, each second conductive connection wire 31 arranged in a regular pattern is designed with a redundant, electrically independent second plug 32. The feature of this structure is that after the fourth common conductive wire 37 is removed by cutting or the like, each test unit 10 in the test unit array can be provided with an electrically independent independent test circuit through the second plug 32, facilitating quick location of the failed test unit 10.

[0169] The lead-out mode of the second plug 32 can extend upward by at least one metal layer, preferably, the top height of the second plug 32 is higher than the top height of the test unit 10, preferably, the second plug 32 can be directly extended to the top metal layer of the semiconductor test structure to provide each second conductive connection wire 31 with an electrically independent independent test circuit, thereby cooperating with the first conductive connection wire 21 to provide each test unit 10 with an electrically independent independent test circuit.

[0170] For example, referring to FIG. 7B and FIG. 7C , the semiconductor test structure can further include: a fourth test pad 38 electrically connected to the fourth common conductive wire 37.

[0171] The above embodiment has the following beneficial effects: by arranging the fourth test pad 38 electrically connected to the fourth common conductive wire 37, when a voltage V is applied to the fourth common conductive wire 37, for example, but not limited to, the fourth test pad 38 can be used to reduce the difficulty of applying a voltage V to the fourth common conductive wire 37.

[0172] It should be noted that the electrical connection between the fourth common conductive wire 37 and the fourth test pad 38 can be achieved in various ways.

[0173] In some embodiments, referring to FIG. 7D and FIG. 7C , the fourth common conductive wire 37 and the fourth test pad 38 can be directly contacted and electrically connected. For example, the fourth common conductive wire 37 and the fourth test pad 38 can be arranged on the same metal layer of the semiconductor substrate.

[0174] In some other embodiments, the fourth common conductive line 37 can also be electrically connected with the fourth test pad 38 through an interconnection structure formed by the conductive connection lines and the metal plugs disposed on the semiconductor substrate, so that the fourth test pad 38 can be arranged in any metal layer, for example, so that the fourth test pad 38 is arranged in the top metal layer, and the difficulty of applying a voltage V to the fourth test pad 38 can be reduced.

[0175] For the above-mentioned scheme including the third comb structure, the first plug 22, the fourth comb structure, and the second plug 32, an example of a failure analysis method is described as follows.

[0176] Reference is made to FIG. 7D and FIG. 3 After the electrical breakdown occurs, when the test unit 10 in which the failure occurs is positioned by the electrical failure analysis, since the third test pad 28, the third common conductive line 27, the fourth test pad 38, and the fourth common conductive line 37 are all located outside the first plug 22 and the second plug 32, the third test pad 28, the third common conductive line 27, the fourth test pad 38, and the fourth common conductive line 37 can be removed by cutting, for example, sawing or laser cutting, and reference is made to FIG. 6 and FIG. 3 The first plug 22 and the second plug 32 involved in the remaining structure. Subsequently, the upper layer of the semiconductor test structure is ground until the top end of the first plug 22 and the second plug 32 is exposed, at which time it is indicated that each test unit 10 in the closely arranged test unit array structure below is in an electrically independent state. By sequentially sticking a probe on each first plug 22 and second plug 32, the failed test unit 10 can be quickly and accurately located.

[0177] In some other embodiments, the semiconductor test structure can further include:

[0178] The first common conductive line 23 located on the top of the first plug 22, the first common conductive line 23 electrically connecting at least two first plugs 22; and

[0179] The fourth common conductive line 37, the fourth common conductive line 37 being located on the side of the second plug 32 away from the test unit array and electrically connecting at least two second conductive connection lines 31, the fourth common conductive line 37 and the at least two second conductive connection lines 31 forming a second comb structure.

[0180] Specifically, in the present embodiment, the combination of the first common conductive line 23 and the second comb structure in the above-mentioned embodiment is adopted, so that when failure analysis is performed on the semiconductor test structure, the top of the first plug 22 and the second plug 32 can be exposed by grinding the semiconductor test structure from top to bottom, and the fourth common conductive line 37 can be cut off, so that the first plug 22 and the second plug 32 are arranged in an electrically independent manner, and then the above-mentioned failure analysis method is used for testing.

[0181] For example, after confirming that there is a failed test unit 10 in the test unit array, the semiconductor test structure is cut along the region between the second plug 32 and the fourth common conductive line 37 to disconnect the electrical connection between the fourth common conductive line 37 and the second conductive connection line 31, and the second conductive connection line 31 can provide independent test circuit for the test unit 10 in the test unit array;

[0182] Referring to FIG. 6 and FIG. 3 , the semiconductor test structure is thinned to expose the top of the first plug 22 and the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate, and the thinning process, such as a planarization process, removes the first common conductive line 23, so that the first conductive connection line 21 can provide independent test circuit for the test unit 10 in the test unit array;

[0183] The first test probe of the test equipment is electrically contacted with the top of one of the at least two first plugs 22 in sequence, and the second test probe of the test equipment is electrically contacted with the top of one of the at least two second plugs 32 in sequence, and a plurality of test units 10 are tested in sequence to find the failed test unit 10.

[0184] It should be understood that the staggered and spaced arrangement of the first conductive connection line 21 of the first conductive connection structure and the second conductive connection line 31 of the second conductive connection structure is not limited to the above-mentioned manner in which the two are arranged in different layers and cross each other, but other manners can also be adopted.

[0185] For example, in some other embodiments, the first conductive connection lines 21 of the first conductive connection structure and the second conductive connection lines 31 of the second conductive connection structure are arranged staggered and spaced to form staggered spaces between the staggered first conductive connection lines 21 and second conductive connection lines 31 can include that the first conductive connection lines 21 and the second conductive connection lines 31 are parallel in the extending direction, the first conductive connection lines 21 and the second conductive connection lines 31 are located in the same or different layers, the first conductive connection lines 21 and the second conductive connection lines 31 are adjacent to each other in one-to-one correspondence to stagger, and one or more staggered spaces are formed between the adjacent first conductive connection lines 21 and second conductive connection lines 31. That is, in the present embodiment, the first conductive connection lines 21 and the second conductive connection lines 31 are arranged parallel between the extending direction of the first conductive connection lines 21 and the extending direction of the second conductive connection lines 31, and the first conductive connection lines 21 and the second conductive connection lines 31 are adjacent to each other in one-to-one correspondence to stagger, so as to form staggered spaces between the adjacent first conductive connection lines 21 and second conductive connection lines 31. At this time, different arrangement modes can be adopted according to whether the first conductive connection lines 21 and the second conductive connection lines 31 are located in the same layer or different layers. The following will be described respectively.

[0186] First, in some embodiments, the first conductive connection lines 21 and the second conductive connection lines 31 are located in different layers, specifically, the first conductive connection lines 21 can be located above the second conductive connection lines 31 and are insulatively spaced by the interlayer dielectric layer, or the second conductive connection lines 31 can be located above the first conductive connection lines 21 and are insulatively spaced by the interlayer dielectric layer. At this time, the plurality of first conductive connection lines 21 and the plurality of second conductive connection lines 31 are respectively arranged horizontally and spaced in the same direction in different layers, specifically, the plurality of first conductive connection lines 21 are horizontally and spaced in the layer in which the first conductive connection lines 21 are located, along the direction perpendicular to the extending direction of the first conductive connection lines 21, and the plurality of second conductive connection lines 31 are horizontally and spaced in the layer in which the second conductive connection lines 31 are located, along the direction perpendicular to the extending direction of the second conductive connection lines 31. Since the extending direction of the first conductive connection lines 21 and the extending direction of the second conductive connection lines 31 are parallel, the arrangement direction of the plurality of first conductive connection lines 21 and the plurality of second conductive connection lines 31 are also parallel.

[0187] At this time, each first conductive connection line 21 corresponds to one second conductive connection line 31 and is staggered with the corresponding second conductive connection line 31 at least in the vertical direction (a direction perpendicular to the surface of the semiconductor substrate) to use the space between the adjacent first conductive connection line 21 and the second conductive connection line 31 as a staggered space. Further, each first conductive connection line 21 and the corresponding second conductive connection line 31 can be arranged in overlapping or staggered in the vertical direction. Specifically, when the first conductive connection line 21 and the corresponding second conductive connection line 31 are arranged directly opposite in the vertical direction, they are arranged in overlapping in the vertical direction. When the first conductive connection line 21 and the corresponding second conductive connection line 31 are not arranged directly opposite in the vertical direction, that is, there is a staggered part between the first conductive connection line 21 and the corresponding second conductive connection line 31 in the vertical direction, they are arranged in staggered in the vertical direction.

[0188] The number of staggered spaces formed by the space between the adjacent first conductive connection line 21 and the second conductive connection line 31 is determined according to the number of test units 10 arranged. Specifically, if one test unit 10 is arranged in the space between the adjacent first conductive connection line 21 and the second conductive connection line 31, the space between the adjacent first conductive connection line 21 and the second conductive connection line 31 is used as one staggered space to arrange one test unit 10. If multiple test units 10 are arranged in the space between the adjacent first conductive connection line 21 and the second conductive connection line 31, for example, multiple test units 10 are arranged along the extension direction of the first conductive connection line 21, the space between the adjacent first conductive connection line 21 and the second conductive connection line 31 is further divided into multiple subspaces, and each subspace is used as one staggered space to arrange one test unit 10.

[0189] For convenience of distinction, the following examples replace the second conductive connection line 31 described above with a third conductive connection line, and replace the second plug described above with a third plug for a simple description, and the parts not described below can be referred to the connection and lead-out mode of the second conductive connection line 31 and the second plug described above.

[0190] Reference FIG. 6 and FIG. 3The semiconductor test structure can comprise at least two third conductive connection lines 41 on the semiconductor substrate and extending along a first direction, the at least two third conductive connection lines 41 are spaced apart along a second direction crossing the first direction, i.e. adjacent two third conductive connection lines 41 are insulated and spaced apart by a dielectric material, and thus are electrically independent. The third conductive connection lines 41 and the first conductive connection lines 21 are located in different planes in a direction perpendicular to the surface of the semiconductor substrate, i.e. the first conductive connection lines 21 and the third conductive connection lines 41 are located in different metal layers of the semiconductor test structure. Specifically, the third conductive connection lines 41 are parallel to the extending direction of the first conductive connection lines 21 and are located directly above the first conductive connection lines 21, and the plurality of third conductive connection lines 41 are spaced apart along the second direction. Each first conductive connection line 21 and the third conductive connection line 41 are spaced apart in a vertical direction perpendicular to the surface of the semiconductor substrate, so that there is a spacing space between them, which serves as one or more staggered spaces between them, so that part or all of the structure of the test unit 10 can be arranged in the spacing space between the first conductive connection line 21 and the third conductive connection line 41 in the vertical direction.

[0191] For example, referring to FIG. 3 and FIG. 3 The semiconductor test structure can further comprise at least two third plugs 42 spaced apart from each other outside the array of test units, each third plug 42 is arranged corresponding to a third conductive connection line 41, and each third plug 42 is electrically connected to the corresponding third conductive connection line 41 to form an independent test circuit electrically independent. Specifically, different third plugs 42 are insulated and spaced apart by a dielectric material such as but not limited to oxide, and different third conductive connection lines 41 are also insulated and spaced apart by a dielectric material such as but not limited to oxide, so that each third plug 42 is only electrically connected to its corresponding third conductive connection line 41, and is insulated and spaced apart from other third conductive connection lines 41 by a dielectric material, and is electrically independent.

[0192] The top height of the at least two first plugs 22 and the at least two third plugs 42 in a direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the at least two first conductive connection lines 21 and the at least two third conductive connection lines 41. Specifically, the top height of all the first plugs 22 is higher than the top height of all the first conductive connection lines 21 and the third conductive connection lines 41. Also, the top height of all the third plugs 42 is higher than the top height of all the first conductive connection lines 21 and the third conductive connection lines 41, i.e. the top height of each third plug 42 in a direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the at least two first conductive connection lines 21 and the at least two third conductive connection lines 41. Thus, an independent lead-out circuit is provided for each third conductive connection line 41. Thus, when the semiconductor test structure is ground from top to bottom, the top of the first plugs 22 and the third plugs 42 is exposed before the first conductive connection lines 21 and the third conductive connection lines 41.

[0193] The lead-out mode of the third plugs 42 can also be applied to the arrangement mode of the aforementioned second common conductive lines 33, the second test pads 34, the fourth common conductive lines 37, the fourth test pads 38, the second transfer lines 35 and the second transfer plugs 36, only need to replace the second plugs 32 with the third plugs 42 and make adaptive adjustment to the arrangement position and extension direction of the second common conductive lines 33, the second test pads 34, the fourth common conductive lines 37, the fourth test pads 38, the second transfer lines 35 and the second transfer plugs 36.

[0194] It should be noted that in other embodiments, in addition to the first conductive connection lines 21 and the second conductive connection lines 31 arranged at different layers and intersected with each other, the semiconductor test structure can further include a third conductive connection line arranged at a different layer from at least one of the first conductive connection lines 21 and the second conductive connection lines 31. Details are described as follows.

[0195] For example, referring to FIG. 3 and FIG. 6 the semiconductor test structure can further include a third conductive connection structure arranged on the semiconductor substrate. The third conductive connection structure includes at least two third conductive connection lines 41 extending along a third direction, and the at least two third conductive connection lines 41 are arranged in a fourth direction intersecting the third direction and spaced apart from each other, i.e. adjacent two third conductive connection lines 41 are insulated and separated from each other by a dielectric material, so as to be electrically independent from each other. The third conductive connection lines 41 are arranged on three different planes in a direction perpendicular to the surface of the semiconductor substrate from the first conductive connection lines 21 and the second conductive connection lines 31, i.e. the first conductive connection lines 21, the second conductive connection lines 31 and the third conductive connection lines 41 are arranged on different metal layers of the semiconductor test structure.

[0196] Furthermore, the third direction is arranged to intersect at least one of the first and second directions, thereby enabling the test unit 10 to be located at the intersection of the third conductive connection line 41 with at least one of the first conductive connection line 21 and the second conductive connection line 31, thus allowing the test unit 10 to be electrically connected to the third conductive connection line 41. Similarly, the above-mentioned intersecting arrangement is such that the two directions have an angle between them, such as but not limited to 90°, so that the two directions can intersect. For example, the third direction can intersect the first direction and be parallel to the second direction; the third direction can also intersect the second direction and be parallel to the first direction; or, the third direction can intersect both the first and second directions. The fourth direction only needs to intersect the third direction, without being limited to whether the fourth direction intersects the first and second directions. In some embodiments, the fourth direction can be parallel to one of the first and second directions.

[0197] For example, refer to FIG. 6 The third conductive connection line 41 extends parallel to the first conductive connection line 21 and is located directly above the first conductive connection line 21. Multiple third conductive connection lines 41 are arranged at intervals along the second direction. That is, in this embodiment, the third direction is parallel to the first direction, and the fourth direction is parallel to the second direction. The third conductive connection line 41 can also be electrically connected to the test unit 10. For example, when the test unit 10 is a vertical MOS transistor structure, the third conductive connection line 41 can be electrically connected to the drain of the vertical transistor structure, the first conductive connection line 21 is connected to the source of the vertical transistor structure, and the second conductive connection line 31 is connected to the gate of the vertical transistor structure. The first conductive connection line 21, the second conductive connection line 31, and the third conductive connection line 41 are arranged in a cross shape, and the test unit 10 is electrically connected at the intersection to form a test unit array.

[0198] For example, refer to FIG. 6 The semiconductor test structure may further include at least two third plugs 42 disposed outside the test unit array and spaced apart from each other. Each third plug 42 corresponds to a third conductive connection line 41, and each third plug 42 is electrically connected to its corresponding third conductive connection line 41 to form an electrically independent test circuit. Specifically, different third plugs 42 are insulated from each other by a dielectric material such as, but not limited to, oxides, and different third conductive connection lines 41 are also insulated from each other by a dielectric material such as, but not limited to, oxides, so that each third plug 42 is only electrically connected to its corresponding third conductive connection line 41, and is insulated from other third conductive connection lines 41 by a dielectric material, and is electrically independent of each other.

[0199] The top height of the at least two first plugs 22, the at least two second plugs 32 and the at least two third plugs 42 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the at least two first conductive connection lines 21, the at least two second conductive connection lines 31 and the at least two third conductive connection lines 41. Specifically, the top height of all the first plugs 22 is higher than the top height of all the first conductive connection lines 21, the second conductive connection lines 31 and the third conductive connection lines 41, and the top height of all the second plugs 32 is higher than the top height of all the first conductive connection lines 21, the second conductive connection lines 31 and the third conductive connection lines 41. The above-mentioned corresponding descriptions of the first plugs 22 and the second plugs 32 can be referred to for details.

[0200] In addition, the top height of all the third plugs 42 is higher than the top height of all the first conductive connection lines 21, the second conductive connection lines 31 and the third conductive connection lines 41, i.e. the top height of each third plug 42 in the direction perpendicular to the surface of the semiconductor substrate is greater than the top height of the at least two first conductive connection lines 21, the at least two second conductive connection lines 31 and the at least two third conductive connection lines 41. Thus, an independent lead-out circuit is provided for each third conductive connection line 41. Thus, when the semiconductor test structure is ground from top to bottom, the top of the first plug 22, the second plug 32 and the third plug 42 is exposed before the first conductive connection line 21, the second conductive connection line 31 and the third conductive connection line 41.

[0201] For example, referring to FIG. 6 The third plug 42 and the first plug 22 are respectively located on opposite sides of the test unit array.

[0202] It should be noted that the third plug 42 and the third conductive connection line 41 can be electrically connected in various ways, some of which are described below.

[0203] For example, referring to FIG. 6 The bottom of the third plug 42 can be in direct contact with the corresponding third conductive connection line 41 to achieve electrical connection between the third plug 42 and the third conductive connection line 41.

[0204] However, sometimes, considering the spatial arrangement and process sequence in the manufacturing process, the bottom of the third plug 42 is not directly electrically connected to the corresponding third conductive connection line 41. In other embodiments, the bottom of the third plug 42 can also be indirectly electrically connected to the corresponding third conductive connection line 41 through a third adapter structure composed of a third adapter line 45 and a third adapter plug 46 disposed on the semiconductor substrate. It is only necessary to ensure that the third adapter structures corresponding to different third plugs 42 are electrically independent of each other and separated by insulating material, thereby ensuring that the electrical independence function of the independent test circuit is not lost.

[0205] For example, sometimes the third adapter plug 46 connecting the third conductive connection line 41 is not directly connected to the upper layer, but is first connected to the third adapter line 45 located below the third conductive connection line 41, and then connected to the upper layer through the third plug 42, that is, the bottom of the third plug 42 is lower than the third conductive connection line 41.

[0206] This application is not limited thereto. In some embodiments, the third adapter structure includes a plurality of third adapter wires 45 and a plurality of third adapter plugs 46, wherein the third adapter wires 45 and the third adapter plugs 46 are alternately connected in series between the third plug 42 and the third conductive connection wire 41.

[0207] For example, refer to FIG. 8 The semiconductor test structure also includes at least two third adapter lines 45, each extending along a third direction and spaced apart along a fourth direction. For example, the first direction is parallel to the third direction, and the second direction is parallel to the fourth direction. Each third adapter line 45 corresponds to a third conductive connection line 41 and is located below the corresponding third conductive connection line 41. Adjacent third adapter lines 45 are insulated from each other by a dielectric material, thus maintaining electrical independence. Each third adapter line 45 is electrically connected to its corresponding third conductive connection line 41 via a third adapter plug 46, but is not connected to other third conductive connection lines 41, maintaining electrical independence. Furthermore, each third adapter line 45 corresponds to a third plug 42 and is directly contacted and electrically connected to the bottom of its corresponding third plug 42, but is not connected to other third plugs 42, maintaining electrical independence. This allows the bottom of the third plug 42 to be sequentially connected to its corresponding third conductive connection line 41 via the corresponding third adapter line 45 and the third adapter plug 46, forming an electrically independent test circuit.

[0208] For example, the third adapter line 45 may be located in an adjacent metal layer below the third conductive connection line 41, and the adjacent metal layers are insulated from each other by a dielectric layer. For example, at least one metal layer may also be included between the third adapter line 45 and the third conductive connection line 41, that is, the metal layers where the third adapter line 45 and the third conductive connection line 41 are located are not adjacent.

[0209] For example, referring to FIG. 8 The semiconductor test structure can further include a fifth common conductive line 43 on top of the third plug 42 and extending in the second direction, the fifth common conductive line 43 electrically connecting the at least two third plugs 42.

[0210] The above embodiment has the following beneficial effect: by forming the fifth common conductive line 43 on top of the third plug 42, the fifth common conductive line 43 electrically connecting the at least two third plugs 42, it is convenient to apply, for example but not limited to, a voltage V through the fifth common conductive line 43 to perform a test, for example, to test the current flowing through the test cell array, so as to determine whether the dielectric layer breakdown occurs.

[0211] It should be noted that the fifth common conductive line 43 and the at least two third plugs 42 can be electrically connected in various ways, for example, some ways are exemplarily introduced as follows.

[0212] For example, referring to FIG. 8 The fifth common conductive line 43 can be directly in contact with the top of the third plug 42 to be electrically connected, so as to realize the direct electrical connection between the fifth common conductive line 43 and the third plug 42.

[0213] In other embodiments, the fifth common conductive line 43 can be electrically connected to the third plug 42 through an interconnection structure composed of conductive connection lines and metal plugs arranged on the semiconductor substrate, so as to realize the indirect electrical connection between the fifth common conductive line 43 and the third plug 42.

[0214] For example, referring to FIG. 8 The semiconductor test structure can further include a fifth test pad 44 electrically connected to the fifth common conductive line 43.

[0215] The above embodiment has the following beneficial effect: by arranging the fifth test pad 44 electrically connected to the fifth common conductive line 43, when the voltage V is applied to the fifth common conductive line 43, the fifth test pad 44 can be used to reduce the difficulty of applying the voltage V to the fifth common conductive line 43.

[0216] It should be noted that the fifth common conductive line 43 and the fifth test pad 44 can be electrically connected in various ways.

[0217] In some embodiments, referring to FIG. 9 The fifth common conductive line 43 and the fifth test pad 44 can be directly in contact with each other to be electrically connected. For example, the fifth common conductive line 43 and the fifth test pad 44 can be arranged on the same metal layer of the semiconductor substrate.

[0218] In some other embodiments, the fifth common conductive line 43 can also be electrically connected with the fifth test pad 44 through an interconnection structure formed by the conductive connection lines and the metal plug on the semiconductor substrate.

[0219] Preferably, the fifth common conductive line 43 and the fifth test pad 44 are both disposed on the top metal layer, so that when the fifth common conductive line 43 and the fifth test pad 44 are removed to make the third plug 42 form an independent circuit, the interconnection structure of other metal layers of the test structure can not be affected.

[0220] Correspondingly, in the aforementioned embodiments provided with the third conductive connection line 41 and the third plug 42, the following arrangement can also be adopted.

[0221] For example, referring to FIG. 10 The semiconductor test structure can further include a sixth common conductive line 47 extending in a fourth direction, the sixth common conductive line 47 being located on a side of the third plug 42 away from the test cell array and electrically connected with first ends of at least two third conductive connection lines 41, and the sixth common conductive line 47 and the at least two third conductive connection lines 41 forming a third comb structure. For example, the second direction and the fourth direction are arranged in parallel.

[0222] Specifically, referring to FIG. 9 The semiconductor substrate is further provided with the sixth common conductive line 47 extending in the fourth direction and located on a side of the third plug 42 away from the test cell array, i.e., the third plug 42 is located between the test cell array and the sixth common conductive line 47, and the electrical connection point of the third plug 42 and the corresponding third conductive connection line 41 is located between the sixth common conductive line 47 and the test cell array. The sixth common conductive line 47 is also electrically connected with the first ends of the at least two third conductive connection lines 41, so that the sixth common conductive line 47 and the at least two third conductive connection lines 41 form a third comb structure, i.e., the sixth common conductive line 47 and the at least two third conductive connection lines 41 are located in the same metal layer, and the sixth common conductive line 47 and the third conductive connection line 41 are directly in contact and electrically connected.

[0223] The above embodiments have the following beneficial effects: by arranging the sixth common conductive line 47 on the basis of the third plug 42, the sixth common conductive line 47 is located on a side of the third plug 42 away from the test cell array and electrically connected with the first ends of the at least two third conductive connection lines 41, and the sixth common conductive line 47 and the at least two third conductive connection lines 41 form a third comb structure, so that the third plug 42 can be used as a redundant plug to locate the failed test cell 10 when the semiconductor test structure is subsequently subjected to electrical failure analysis.

[0224] The above embodiment is the same as the prior test structure in that each third conductive connection line 41 in the regular arrangement is electrically connected with the sixth common conductive line 47 in the same layer. The above embodiment is different from the prior test structure in that a third plug 42 electrically independent is designed on each third conductive connection line 41 in the regular arrangement between the test unit array and the sixth common conductive line 47 for electrical connection. The feature of this structure is that after the sixth common conductive line 47 is removed by cutting or the like, an electrically independent independent test circuit can be provided for each test unit 10 in the test unit array, facilitating quick positioning of the failed test unit 10.

[0225] The third plug 42 can extend upward by at least one metal layer until the top of the third plug 42 is higher than the top of the test unit 10. The third plug 42 can be directly extended to the top metal layer of the semiconductor test structure to provide an electrically independent independent test circuit for each third conductive connection line 41, thereby cooperating with the second conductive connection line 31 to provide an electrically independent independent test circuit for each test unit 10.

[0226] For example, referring to FIG. 10 , the semiconductor test structure can further include a sixth test pad 48 electrically connected with the sixth common conductive line 47.

[0227] The above embodiment has the following beneficial effects: by providing the sixth test pad 48 electrically connected with the sixth common conductive line 47, when a voltage V is applied to the sixth common conductive line 47, the difficulty of applying a voltage V to the sixth common conductive line 47 can be reduced by means of the sixth test pad 48.

[0228] It should be noted that the electrical connection between the sixth common conductive line 47 and the sixth test pad 48 can be achieved in various ways.

[0229] In some embodiments, referring to FIG. 9 , the sixth common conductive line 47 and the sixth test pad 48 can be directly contacted and electrically connected. For example, the sixth common conductive line 47 and the sixth test pad 48 can be arranged in the same metal layer of the semiconductor substrate.

[0230] In other embodiments, the sixth common conductive line 47 can also be electrically connected with the sixth test pad 48 through an interconnection structure formed by conductive connection lines and metal plugs arranged on the semiconductor substrate. Preferably, the sixth test pad 48 can be arranged in the top metal layer, further reducing the difficulty of applying a voltage V.

[0231] Next, in other embodiments, referring to FIG. 10 and FIG. 1A, the first conductive connection lines 21 and the second conductive connection lines 31 are located at the same layer, and the first conductive connection lines 21 and the second conductive connection lines 31 are arranged in parallel and staggered at intervals. In this case, the first conductive connection lines 21 and the second conductive connection lines 31 can be arranged in parallel and staggered at intervals in a horizontal direction perpendicular to the extension direction of the first conductive connection lines 21 or the second conductive connection lines 31 and parallel to the surface of the semiconductor substrate, so that the interval space between adjacent first conductive connection lines 21 and second conductive connection lines 31 in the horizontal direction is divided into one or more staggered spaces. Specifically, if one test unit 10 is arranged in the interval space between adjacent first conductive connection lines 21 and second conductive connection lines 31, the interval space between adjacent first conductive connection lines 21 and second conductive connection lines 31 is taken as a whole as one staggered space to arrange one test unit 10. If multiple test units 10 are arranged in the interval space between adjacent first conductive connection lines 21 and second conductive connection lines 31, the interval space between adjacent first conductive connection lines 21 and second conductive connection lines 31 is further divided into multiple subspaces, and each subspace is taken as a staggered space to arrange one test unit 10.

[0232] For example, referring to FIG. 1B and FIG. 7A to FIG. 7D , the first conductive connection lines 21 and the second conductive connection lines 31 are located at the same layer, the extension direction of the first conductive connection lines 21 and the second conductive connection lines 31 are both in the first direction, and the plurality of first conductive connection lines 21 and the plurality of second conductive connection lines 31 are arranged in parallel and staggered at intervals in the second direction, so that the staggered space for arranging one or more test units 10 is formed in the interval space between adjacent first conductive connection lines 21 and second conductive connection lines 31 in the horizontal direction. The manner in which the first conductive connection lines 21 and the second conductive connection lines 31 are electrically connected to the test units 10 can refer to the manner described in the foregoing embodiments, which will not be described here.

[0233] For example, referring to FIG. 7C , the first common conductive line 23 and the second common conductive line 33 both extend in the second direction and are respectively arranged on both sides of the test unit array in the first direction. In this case, the arrangement manner of the first common conductive line 23, the second common conductive line 33, the first test pad 24, the second test pad 34, the first plug 22 and the second plug 32 can refer to the description of the foregoing embodiments, which will not be described here.

[0234] For example, referring to FIG. 7D , the third common conductive line 27 and the fourth common conductive line 37 both extend in the second direction and are respectively arranged on both sides of the test unit array in the first direction. In this case, the arrangement manner of the third common conductive line 27, the fourth common conductive line 37, the third test pad 28, the fourth test pad 38, the first plug 22 and the second plug 32 can refer to the description of the foregoing embodiments, which will not be described here.

[0235] The leading-out manner of the first plug 22 and the second plug 32 in this embodiment can also be applied to the arrangement manner of the first common conductive line 23, the first test pad 24, the third common conductive line 27, the third test pad 28, the first adapter line 25, the first adapter plug 26, the second common conductive line 33, the second test pad 34, the fourth common conductive line 37, the fourth test pad 38, the second adapter line 35 and the second adapter plug 36, and only the arrangement position and the extending direction of the first common conductive line 23, the first test pad 24, the third common conductive line 27, the third test pad 28, the first adapter line 25, the first adapter plug 26, the second common conductive line 33, the second test pad 34, the fourth common conductive line 37, the fourth test pad 38, the second adapter line 35 and the second adapter plug 36 need to be adjusted adaptively.

[0236] Exemplarily, the material of the conductive connection line, the conductive line, the adapter line, the metal plug and the plug can include any one or any combination of aluminum (Al), copper (Cu), tungsten (W), gold, silver and tin. Of course, it should be noted that the material of the conductive connection line, the conductive line, the adapter line, the metal plug and the plug is not limited to the above-mentioned materials, and can also be other conductive structures containing metal materials, for example, polysilicon, a conductive layer formed by doping ions in single crystal silicon, etc. can also be used as the material for preparing the conductive connection line, the conductive line, the adapter line, the metal plug and the plug.

[0237] Exemplarily, the material of the conductive connection line, the conductive line, the metal plug and the plug can be the same, so as to facilitate the implementation in the semiconductor process. Of course, in some special cases, different materials can also be used to fill the conductive connection line, the conductive line, the metal plug and the plug in some other embodiments. Embodiment Two

[0238] The embodiment provides a test method based on the above-mentioned semiconductor test structure, and the test method mainly comprises the following steps.

[0239] Reference FIG. 7A to FIG. 7D and FIG. 7C After confirming that there is a failed test unit 10 in the test unit array, the semiconductor test structure is subjected to a planarization treatment to expose the top of the first plug 22 and the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate;

[0240] The first test probe of the test equipment is electrically contacted with the top of one of the at least two first plugs 22 in sequence, the second test probe of the test equipment is electrically contacted with the top of one of the at least two second plugs 32 in sequence, and a plurality of test units 10 are tested in sequence to find the failed test unit 10.

[0241] The semiconductor test structure can be used for any one or more of the following tests: reliability test, leakage current test, capacitance value test, transistor current test, threshold voltage test, short circuit test, breakdown voltage test, dielectric layer breakdown over time test, dielectric layer leakage test.

[0242] That is, the semiconductor test structure can be used not only for reliability test, but also for other related electrical tests on the test cell array in addition to the reliability test, such as but not limited to leakage test, capacitance value test when the test cell 10 is a capacitance structure, transistor current and threshold voltage test, etc. Embodiment Three

[0243] The embodiment provides a test method based on the semiconductor test structure, and the test method mainly includes the following steps:

[0244] Referring to FIG. 7D After confirming that there is a failed test cell 10 in the test cell array, the semiconductor test structure is cut along the region between the first plug 22 and the third common conductive line 27 to disconnect the electrical connection between the third common conductive line 27 and the first plug 22.

[0245] Referring to ​ and ​ The top of the first plug 22 and the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate is exposed.

[0246] The first test probe of the test equipment is electrically contacted with the top of one of the at least two first plugs 22 in sequence, and the second test probe of the test equipment is electrically contacted with the top of one of the at least two second plugs 32 in sequence, and a plurality of test cells 10 are tested in sequence to find the failed test cell 10.

[0247] The specific test method can refer to the description in the foregoing embodiment one and embodiment two, and will not be described here again. Embodiment Four

[0248] The embodiment provides a test method based on the semiconductor test structure, and the test method mainly includes the following steps:

[0249] Referring to ​After confirming the existence of the failed test unit 10 in the test unit array, the semiconductor test structure is cut along the area between the first plug 22 and the third common conductive line 27, and the area between the second plug 32 and the fourth common conductive line 37, to break the electrical connection between the third common conductive line 27 and the first plug 22, and the electrical connection between the fourth common conductive line 37 and the second plug 32;

[0250] Reference ​ and ​ exposing the top of the first plug 22 and the second plug 32 in the direction perpendicular to the surface of the semiconductor substrate;

[0251] sequentially electrically contacting the first test probe of the test equipment to the top of one of the at least two first plugs 22, and sequentially electrically contacting the second test probe of the test equipment to the top of one of the at least two second plugs 32, to test the test units 10 to find the failed test unit 10 in the test units 10.

[0252] The specific testing method can refer to the description in the foregoing embodiment one, embodiment two and embodiment three, which will not be repeated here.

[0253] The present application has been described by the foregoing embodiments, but it should be understood that the foregoing embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the present application is not limited to the foregoing embodiments, and more variations and modifications can be made according to the teachings of the present application, which all fall within the scope of the present application. The scope of protection of the present application is defined by the attached claims and their equivalent scope.

Claims

1. A semiconductor testing structure, characterized in that, include: Semiconductor substrate; A first conductive connection structure and a second conductive connection structure are located on the semiconductor substrate. The first conductive connection structure includes multiple parallel and horizontally arranged first conductive connection lines, and the second conductive connection structure includes multiple parallel and horizontally arranged second conductive connection lines. The first conductive connection lines of the first conductive connection structure and the second conductive connection lines of the second conductive connection structure are arranged alternately and at intervals to form an interlacing space between the interlacing first conductive connection lines and second conductive connection lines. A plurality of test units are located on the semiconductor substrate, the plurality of test units are arranged in a horizontal array to form a test unit array, the test units are arranged corresponding to the staggered space, and the test unit includes a first electrode and a second electrode, the first electrode and the second electrode being respectively connected to the first conductive connection line and the second conductive connection line forming the corresponding staggered space; At least two first plugs are disposed outside the test unit array and spaced apart from each other. Each first plug corresponds to a first conductive connection line, and each first plug is electrically connected to the corresponding first conductive connection line. At least two second plugs are disposed outside the test unit array and spaced apart from each other. Each second plug corresponds to a second conductive connection line, and each second plug is electrically connected to the corresponding second conductive connection line. Wherein, the top height of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate is higher than the top of the at least two first conductive connection lines and the at least two second conductive connection lines.

2. The semiconductor test structure as described in claim 1, characterized in that, The first conductive connection line of the first conductive connection structure and the second conductive connection line of the second conductive connection structure are arranged in an alternating and spaced manner to form an alternating space between the alternating first conductive connection line and the second conductive connection line. The first conductive connecting line and the second conductive connecting line extend in opposite directions. The first conductive connecting line and the second conductive connecting line are located on different layers. The intersecting space is located at the intersection of the first conductive connecting line and the second conductive connecting line. Multiple intersecting spaces are arranged in an array.

3. The semiconductor test structure as described in claim 1, characterized in that, The first conductive connection line of the first conductive connection structure and the second conductive connection line of the second conductive connection structure are arranged in an alternating and spaced manner to form an alternating space between the alternating first conductive connection line and the second conductive connection line. The first conductive connection line and the second conductive connection line extend in parallel directions. The first conductive connection line and the second conductive connection line are located in the same or different layers. The first conductive connection line and the second conductive connection line are adjacent to each other in a staggered manner, and one or more staggered spaces are formed between adjacent first conductive connection lines and second conductive connection lines.

4. The semiconductor test structure as described in claim 1, characterized in that, Also includes: A first common conductive line is located at the top of the first plug, and the first common conductive line is electrically connected to the at least two first plugs.

5. The semiconductor test structure as described in claim 4, characterized in that, Also includes: A second common conductive line is located at the top of the second plug, and the second common conductive line is electrically connected to the at least two second plugs.

6. The semiconductor test structure as described in claim 5, characterized in that, The first common conductive line and the second common conductive line have the same height in a direction perpendicular to the surface of the semiconductor substrate.

7. The semiconductor test structure as described in claim 5, characterized in that, Also includes: A first test pad electrically connected to the first common conductive line, and a second test pad electrically connected to the second common conductive line, wherein the first test pad and the second test pad are at the same height in a direction perpendicular to the surface of the semiconductor substrate.

8. The semiconductor test structure as described in claim 5, characterized in that, Both the first common conductive line and the second common conductive line are located on the top metal layer of the semiconductor test structure.

9. The semiconductor test structure as described in claim 1, characterized in that, Also includes: The third common conductive line is located on the side of the first plug away from the test unit array and is electrically connected to at least two of the first conductive connection lines. The third common conductive line and the at least two of the first conductive connection lines form a first comb structure.

10. The semiconductor test structure as described in claim 9, characterized in that, Also includes: The fourth common conductive line is located on the side of the second plug away from the test unit array and is electrically connected to at least two of the second conductive connection lines. The fourth common conductive line and the at least two of the second conductive connection lines form a second comb structure.

11. The semiconductor test structure as described in claim 1, characterized in that... Each of the first plugs is electrically connected to the corresponding first conductive connection line through a first adapter structure; The first adapter structure includes at least one first adapter plug and at least one first adapter wire, wherein the first adapter plug and the first adapter wire are connected in series on the conductive path between the first plug and the first conductive connection wire.

12. The semiconductor test structure as described in claim 11, characterized in that, The bottom of the first plug is at a height higher than or lower than the top of the first conductive connection line in a direction perpendicular to the surface of the semiconductor substrate.

13. The semiconductor test structure as described in claim 11, characterized in that, Each of the second plugs is electrically connected to the corresponding second conductive connection line via a second adapter structure. The second adapter structure includes at least one second adapter plug and at least one second adapter line, with the second adapter plug and the second adapter line connected in series on the conductive path between the second plug and the second conductive connection line.

14. The semiconductor test structure as described in claim 13, characterized in that, The bottom of the second plug is at a height higher than or lower than the top of the second conductive connection line in a direction perpendicular to the surface of the semiconductor substrate.

15. The semiconductor test structure according to any one of claims 11 to 14, characterized in that, In a direction perpendicular to the surface of the semiconductor substrate, the bottom height of the first plug is the same as the bottom height of the second plug.

16. The semiconductor test structure as described in claim 1, characterized in that, The top height of the at least two first plugs and the at least two second plugs in a direction perpendicular to the surface of the semiconductor substrate is higher than the top of the test unit.

17. The semiconductor test structure as described in claim 16, characterized in that, The test unit includes a transistor, which includes a source, a gate, a drain, and a channel region. The first electrode and the second electrode each include one of the source, the gate, and the drain; or, The test unit includes a capacitor structure, which includes a first capacitor plate and a second capacitor plate. The first capacitor plate is included in the first capacitor plate, and the second capacitor plate is included in the second capacitor plate.

18. A test method based on a semiconductor test structure as described in any one of claims 4 to 7, characterized in that, include: After confirming the presence of a failed test cell in the test cell array, the semiconductor test structure is planarized to expose the tops of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate. The first test probe of the test device is sequentially electrically contacted to the top of one of the at least two first plugs, and the second test probe of the test device is sequentially electrically contacted to the top of one of the at least two second plugs, and the plurality of test units are tested in sequence to identify the failed test unit.

19. A test method based on the semiconductor test structure as described in claim 10, characterized in that, include: After confirming that there is a failed test unit in the test unit array, the semiconductor test structure is cut along the region between the first plug and the third common conductive line, and the region between the second plug and the fourth common conductive line, to disconnect the electrical connection between the third common conductive line and the first plug, and the electrical connection between the fourth common conductive line and the second plug. Exposing the tops of the first plug and the second plug in a direction perpendicular to the surface of the semiconductor substrate; The first test probe of the test device is sequentially electrically contacted to the top of one of the at least two first plugs, and the second test probe of the test device is sequentially electrically contacted to the top of one of the at least two second plugs, and the plurality of test units are tested in sequence to identify the failed test units among the plurality of test units.

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