Time-wavelength multiplexing large-bit-width optical digital multiplier
Through a large-bit wide optical digital multiplier with time-wavelength multiplexing, the multiplier is loaded into the time and wavelength dimensions, solving the problems of large hardware overhead and poor scalability in optical logic calculation, realizing low-energy consumption and efficient optical computing, and supporting the commercial application of large-scale on-chip logic photon computing circuits.
Patent Information
- Application Number
- CN202510513007.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-08-05
AI Technical Summary
The existing optical logic computing technology has problems such as large hardware overhead, poor scalability and high energy consumption when dealing with large-bit wide optical digital multipliers. Traditional electronic hardware is close to the physical limit in computing speed and energy consumption optimization, and it is difficult to meet the needs.
The large-bit-width optical digital multiplier using time-wavelength multiplexing uses the high modulation bandwidth and wide spectrum characteristics of the optical device to achieve bit-wise delay and incoherent superposition of partial products, reducing hardware requirements and logarithmic relationships with bit width, and supporting existing silicon optical processes.
It greatly reduces hardware overhead, improves the scalability of optical multipliers, realizes high-efficiency optical computing with low energy consumption, and supports the commercial application of large-scale on-chip logic photon computing circuits.
Smart Images
Figure CN120428948A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of optical logic calculation, and more specifically, relates to a time-wavelength multiplexed large-bit-width optical digital multiplier. Background Art
[0002] With the rapid development of artificial intelligence, the Internet of Things, and cloud computing, the demand for computing resources and power consumption has skyrocketed. However, traditional electronic hardware has reached its physical limits in terms of processing speed and energy efficiency, leaving a significant gap between its technical solutions and actual needs. Optical computing, on the other hand, offers advantages such as ultra-large bandwidth, low power consumption, and independence from advanced manufacturing processes. Furthermore, photons exist in multiple dimensions and can process data in parallel. This makes optical computing a promising path forward for high-performance, low-power chips.
[0003] Current paradigms for optical logic computing include all-optical logic and electro-optical logic. All-optical logic schemes suffer from the inevitable large pump energy losses caused by optical nonlinearities, resulting in high power consumption of all-optical logic gates. Furthermore, logic operations rely on signal wavelength and inherent material properties, lacking broadband logic computing and making them difficult to cascade and scale. While electro-optical logic schemes can leverage the convenience of electricity to construct more versatile advanced logic devices, their arithmetic and logic operation bit width is limited, making breakthrough applications difficult. If the concept of spatiotemporal multiplexing is introduced into optical logic computing, and optical neural network operators are used to construct a base-to-base converter, its low power consumption and versatility will pave the way for subsequent system cascading and expansion. Therefore, developing a large-bitwidth optical digital multiplier based on wavelength division multiplexing and incoherent power delay superposition has important practical value. Summary of the Invention
[0004] In view of the defects of the prior art, the present invention aims to provide a time-wavelength multiplexed large-bit-width optical digital multiplier, aiming to realize large-bit-width optical digital multiplication operations.
[0005] To achieve the above object, the present invention provides a time-wavelength multiplexed large-bit-width optical digital multiplier, comprising a data loading unit, a partial product summation unit, a cascaded binarization unit, and a cyclic binarization unit, wherein the data loading unit is used to convert A1, A2, A3, ..., A n The sequence of equal-length channel intervals is loaded onto the continuous light corresponding to n wavelengths, and the optical signal encoded by the binary multiplier A is obtained. Then B1, B2, B3, ..., B in the binary multiplier B are converted into n Loading the optical signal with equal time series to obtain the partial product of A and B;
[0006] The partial product summing unit is used to align the partial products mapped on each wavelength in time sequence and then superimpose them, and output an incoherent superposition signal of the partial products that are delayed and aligned according to bit time, wherein the incoherent superposition signal is in decimal form;
[0007] The input of the cascade binarization unit is the incoherent superposition signal output by the partial product summation unit, and is used to convert the decimal signal into a binary signal, and delay the high bit of the binary signal bit by bit, and output a carry superposition signal;
[0008] The input of the cyclic binarization unit is the carry-add signal output by the cascade binarization unit, which is used to combine the carry-add signal with the high-order delay of the 2-bit converter, and the output is the result of the multiplication operation.
[0009] Preferably, the data loading unit is used to load the two multipliers in the multiplier and generate the corresponding partial products. The partial product summing unit is used to superimpose the partial products and delay the partial products mapped on each wavelength bit by bit to achieve timing alignment and complete the incoherent superposition of the partial products after delay. The cascade binarization unit converts the input decimal signal into a binary signal and performs bitwise delay on the high bit. Output bit delay to realize the transmission and superposition of carry signal. The cyclic binary unit combines the previous binary signal with the high bit of its own binary converter. Delayed combination, its low That is, output the result of the multiplier operation
[0010] Furthermore, the data loading unit includes a multi-wavelength laser source, an optical waveform shaper, and an intensity modulator. The multi-wavelength laser source is used to generate continuous light of n wavelengths and input it to the optical waveform shaper. The optical waveform shaper is used to convert A1, A2, A3, ..., A in the multiplier A signal into n The intensity modulator loads B1, B2, B3, ..., B in the multiplier B signal in the form of a wavelength sequence with equal channel spacing. n , the data loading unit output is the partial product of the multiplier A and multiplier B signals.
[0011] Furthermore, the partial product summation unit includes a first wavelength division multiplexer, a second wavelength division multiplexer, and n-1 delay lines. The first wavelength division multiplexer realizes demultiplexing of the partial product sequence. The delay line delays the partial products mapped on each wavelength bit by bit to achieve timing alignment, and finally inputs them into the second wavelength division multiplexer to achieve incoherent superposition of the partial products, and the output signal is S0.
[0012] Furthermore, the cascade binarization unit includes a binarization units cascaded in sequence, wherein the i-th binarization unit includes mi Bit converter, m i -1 delay line, the third wavelength division multiplexer, the binary converter is used to convert the input signal S i-1 Convert from decimal to binary The delay line is used to convert the high bit of the base converter Output bit delay, thereby realizing the transmission of carry signal, the wavelength division multiplexer is used to i -1 delay line output carry signals are incoherently superimposed and input to the next level binary converter. That is, the first binarization unit includes m1 binary converter, m1-1 delay lines, and the third wavelength division multiplexer. The m1 binary converter is used to convert the input signal S0 from a decimal optical signal to a binary electrical signal, and then to a binary optical signal. The delay line is used to convert the binary optical signal C 1 High position The third wavelength division multiplexer is used to perform incoherent superposition of the carry signals output by the m1-1 delay lines, and input the incoherent superposition signal S1 to the second binarization unit. The second binarization unit includes an m2 bit converter, m2-1 delay lines, and a third wavelength division multiplexer. The output signal of the second binarization unit is S2, and the output signal S2 is input to the third binarization unit, and the cascade is performed in sequence until the output signal S a ,in
[0013] Furthermore, the cyclic binarization unit includes a 2×1 combiner, a 2-bit converter, and a delay line. The 2-bit converter is used to convert the signal output by the 2×1 combiner from a decimal optical signal to a binary optical signal. The high-order optical signal of the 2-bit converter is After passing through the delay line for one bit delay, the optical signal S is combined with the binary optical signal output by the cascade binarization unit. a In the 2×1 combiner, the low bit of the base converter is That is, output the operation result of the multiplier.
[0014] Furthermore, the multiplier A signal and the multiplier B signal are loaded into the optical domain in the form of wavelength and time, respectively, and the corresponding partial product results are generated. Relying on the high modulation bandwidth and wide spectrum characteristics of optical devices, by loading the information of the two multipliers into the time and wavelength dimensions respectively, the number of hardware a required for the multiplier is logarithmically related to the multiplier bit width n. in It represents rounding down, which greatly reduces the hardware overhead and greatly improves the scalability of the optical multiplier.
[0015] Furthermore, the base-to-base converter can be implemented by an all-optical solution or an optoelectronic-optical solution. The all-optical solution can be obtained by combining an optical linear matrix with optical nonlinear materials to form an optical neural network and training it. The optoelectronic-optical solution can use a light detector to convert the optical signal into an electrical signal, drive the electrically tunable microring resonance peak to move to a specified wavelength position, and pass an optical signal of the corresponding wavelength to achieve it. It can also directly input the electrical signal into an electrical ADC, and use the quantized electrical signal result to drive the intensity modulator to realize the base-to-base conversion function in the optical domain.
[0016] Furthermore, the delays of the (n-1) delay lines in the partial product summation unit are τ, 2τ, ..., (n-1)τ, respectively, and the delays of the (n-1) delay lines in the cascade binarization unit are The delay lines of the first binary unit are τ, 2τ, ..., (m1-1)τ, and the delay lines of the ith binary unit are τ, 2τ, ..., (m i -1)τ, the delays of the (n-1) delay lines in the cyclic binarization unit are all τ, and τ corresponds to the code length of one symbol of the multiplier signal.
[0017] Furthermore, the multi-wavelength laser source is an optical frequency comb, or is realized by combining laser beams of different wavelengths output by multiple lasers.
[0018] Furthermore, the intensity modulator is a Mach-Zehnder modulator or an electrically tunable microring, and the delay line is a spiral waveguide.
[0019] Furthermore, all devices involved in the multiplier support existing mature silicon photonic processes, can realize large-scale on-chip logical photonic operation circuits, and have the potential for commercial application.
[0020] Compared with the prior art, the above technical solutions proposed by the present invention can achieve the following:
[0021] Beneficial effects:
[0022] 1. The present invention provides a large-bit-width optical digital multiplier for time-wavelength multiplexing, which loads two multipliers into the time and wavelength dimensions respectively, implements delayed carry in the time dimension, and realizes a large-bit-width optical digital multiplier.
[0023] 2. The large-bit-width optical digital multiplier with time-wavelength multiplexing provided by the present invention has the advantages of low energy consumption and low loss compared with traditional electrical digital multipliers because it completes the main computing tasks in the optical domain.
[0024] 3. The present invention provides a large-bit-width optical digital multiplier for time-wavelength multiplexing. Since the number of required devices and the bit width of the multiplier are logarithmically related, it greatly reduces hardware overhead while greatly improving the scalability of the optical multiplier.
[0025] 4. All devices involved in the time-wavelength multiplexed large-bitwidth optical digital multiplier provided by the present invention support existing mature silicon photonics processes, can realize large-scale on-chip logical optical multiplication circuits, and have the potential for commercial application. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 The present invention provides a system structure diagram of a time-wavelength multiplexed large-bit-width optical digital multiplier.
[0027] Figure 2 This is a diagram showing the main working principles of a data loading unit and a partial product summing unit in a time-wavelength multiplexed large-bit-width optical digital multiplier provided by the present invention.
[0028] Figure 3 This is a system and actual calculation process demonstration diagram of a time-wavelength multiplexed large-bit-width optical digital multiplier provided by the present invention.
[0029] Figure 4 The invention provides a solution for realizing a binarization unit in a large-bit-width optical digital multiplier for time-wavelength multiplexing. DETAILED DESCRIPTION
[0030] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
[0031] The present invention provides a time-wavelength multiplexed large-bit-width optical digital multiplier, comprising a data loading unit 1, a partial product summing unit 2, a cascade binarization unit 3 and a cyclic binarization unit 4. The data loading unit 1 is used to convert A1, A2, A3, ..., A in a binary multiplier A into a binary value. n The sequence of equal-length channel intervals is loaded onto the continuous light corresponding to n wavelengths, and the optical signal encoded by the binary multiplier A is obtained. Then B1, B2, B3, ..., B in the binary multiplier B are converted into n Loading the optical signal with equal time series to obtain the partial product of A and B;
[0032] The partial product summing unit 2 is used to delay the partial products mapped on each wavelength by bit, superimpose them after achieving timing alignment, and output an incoherent superposition signal of the partial products that are delayed by bit and aligned, wherein the incoherent superposition signal is in decimal form;
[0033] The input of the cascade binarization unit 3 is the incoherent superposition signal output by the partial product summation unit 2, which is used to convert the decimal signal into a binary signal, and delay the high bit of the binary signal bit by bit to output a carry superposition signal;
[0034] The input of the cyclic binarization unit 4 is the carry-add signal output by the cascade binarization unit 3, which is used to combine the carry-add signal with the high-order delay of the 2-bit converter, and the output is the result of the multiplication operation.
[0035] like Figure 1 As shown, an embodiment of the present invention provides a time-wavelength multiplexed large-bitwidth optical digital multiplier, comprising a data loading unit 1, a partial product summation unit 2, a cascaded binarization unit 3, and a cyclic binarization unit 4. In the data loading unit 1, the multi-wavelength laser source 11 is used to generate n wavelengths, which are respectively input to an optical waveform shaper 12 for loading an A signal. The optical waveform shaper 12 for loading an A signal is used to load the multiplier A signal onto the n wavelengths in the form of a wavelength sequence with equal channel spacing, and output it to a subsequent intensity modulator 13. The intensity modulator 13 for loading a B signal is used to load B1, B2, B3, ..., B in the multiplier B signal. n Since the intensity modulator can perform a logical AND function, the intensity modulator 13 loads B1, B2, B3, ..., B in the multiplier B signal in an equal time sequence. n , the output is the partial product result of the A and B signals, and the signal is then input to the partial product summing unit 2. The signal is first input to the first wavelength division multiplexer 21 to realize the demultiplexing of the partial product sequence. The delay lines 221, 222, ..., 22(n-1) delay the partial products mapped on each wavelength by bit to achieve timing alignment, and finally input to the second wavelength division multiplexer 23 to achieve incoherent superposition of the partial products. The superposition signal S0 is then input to the cascaded binarization unit 3. Among them, the base converter 32 is used to convert the input signal from a decimal signal to a binary signal, and the delay lines 331, 332, ..., 33(m1-1) are used to convert the high-order bits of the base converter 32 The delay is performed by bit, thereby realizing the transmission of the carry signal. The wavelength division multiplexer 34 is used to perform incoherent superposition on the carry signals output by the m1-1 delay lines 331, 332, ..., 33 (m1-1), and then input the incoherent superposition signal S1 to the second cascade unit. Its structure is similar to that of the first binarization unit, including m2 bit converters, m2-1 delay lines, and a wavelength division multiplexer. The output signal of the second cascade unit is S2, and then the output signal S2 is further input to the next cascade unit, and the cascade is performed in sequence. The subsequent cascade units include m3, ..., m a Bit converter, m3-1,…,m a -1 delay line, the corresponding output signals are S3,…,S a , and superimpose the signal S a Input to the cyclic binarization unit 4, the superimposed signal S a The high bit of the 2-bit converter 42 After a one-bit delay of the delay line 43, the beam is combined, and the low-order bit of the base converter 42 is That is, output the operation result of the multiplier.
[0036] Figure 2 The main working principle diagram of the data loading unit and the partial product summation unit in the present invention is shown as follows: Figure 2 As shown in (a), the optical waveform shaper and intensity modulator in series can form a logic AND gate. i , B j When (i, j = 1, 2, ..., n) are all 1, there is light output at the jth timing corresponding to the i-th wavelength, and the output level can be considered to be 1. In other cases, there is no light output, and the output level can be considered to be 0. Figure 2 (b) in the figure shows the principle of accumulation of partial products in the two dimensions of time and wavelength by delaying them bit by bit. Figure 1 The role of the delay line, and B2, B3, ..., B n The relevant partial products are delayed by τ, 2τ, ..., (n-1)τ, where τ corresponds to the time interval of one symbol of the multiplier signal. The partial product summation unit 2 realizes the partial product signal by delaying the bit.
[0037] Figure 3 The multiplication calculation process in the present invention is shown, as Figure 3 (a) shows the logical AND operation of the multipliers, A = 11001101, B = 10110011, which are loaded and completed by the optical waveform shaper and intensity modulator to generate partial products. Figure 3 (b) in the figure shows the partial product results mapped on time and wavelength. Figure 3 (c) in the figure shows the process of superposition of partial products after bitwise delay. Figure 3 (d) shows the process of partial product superposition signals passing through the base-to-base converter and then being delayed and superimposed bit by bit. Figure 3 (e) shows that after the previous stage superposition signal enters the cyclic binarization unit, it undergoes three cycles of base conversion and outputs the final result 1000111101010111. It can be clearly seen that the calculated results are consistent with the theory.
[0038] Figure 4 The implementation scheme of cascaded binarization unit and cyclic binarization unit is shown. Figure 4 (a) in the figure represents the first unit of the cascaded binarization unit. The signal after the partial product S0 is delayed and superimposed bit by bit is converted into an electrical signal by the first photodetector and then input into the m1bit converter to output a binary electrical signal. The second multi-wavelength laser emits a wavelength of After the laser beams of λ3, λ2, and λ1 pass through the polarization controller, the binary electrical signal is loaded into the laser beam through the intensity modulator to form a binary optical signal. The high bit of the binary optical signal The multiplexed incoherent superposition signal S1 is delayed and multiplexed bit by bit, and is converted into an electrical signal by the second photodetector, and then input to the next level base converter and the above steps are repeated. Figure 4 (b) in the figure represents the i-th unit of the cascaded binarization unit, until i=a, the output S of the cascaded binarization unit a Input to the combiner, such as Figure 4 (c) in the figure represents a cyclic binarization unit, whose 2-bit base converter converts the signal output by the 2×1 combiner into a binary signal. The low bit of the binary signal is High is The high-order signal is converted into a high-order optical signal The signal S a With the high-order optical signal The delayed τ signal is combined and input into the 2-bit converter again after passing through the photoelectric detector. This is the multiplier output result.
[0039] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A large-bitwidth optical digital multiplier for time-wavelength multiplexing, characterized in that: The invention comprises a data loading unit (1), a partial product summing unit (2), a cascade binarization unit (3) and a cyclic binarization unit (4), wherein the data loading unit (1) is used to convert A1, A2, A3, ..., A n The sequence of equal-length channel intervals is loaded onto the continuous light corresponding to n wavelengths, and the optical signal encoded by the binary multiplier A is obtained. Then B1, B2, B3, ..., B in the binary multiplier B are converted into n Loading the optical signal with equal time series respectively, thereby obtaining the partial product of A and B; The partial product summing unit (2) is used to delay the partial products mapped on each wavelength in bit order, superimpose them after achieving timing alignment, and output an incoherent superposition signal of the partial products that are delayed in bit order and aligned, wherein the incoherent superposition signal is in decimal form; The input of the cascade binarization unit (3) is the incoherent superposition signal output by the partial product summation unit (2), and is used to convert the decimal signal into a binary signal, and to delay the high bit of the binary signal bit by bit, and output the incoherent superposition signal with the carry bit delayed; The input of the cyclic binarization unit (4) is the incoherent superposition signal output by the cascade binarization unit (3), and is used to combine the carry superposition signal with the high-order delay of the 2-bit converter, and the output is the result of the multiplication operation.
2. The large bit-width optical digital multiplier for time-wavelength multiplexing according to claim 1, characterized in that: The data loading unit (1) comprises a first multi-wavelength laser source (11), an optical waveform shaper (12) and an intensity modulator (13). The first multi-wavelength laser source (11) is used to generate continuous light of n wavelengths and input the light to the optical waveform shaper (12). The optical waveform shaper (12) is used to convert A1, A2, A3, ..., A in the multiplier A signal into an intensity modulator (13). n The intensity modulator (13) is used to load B1, B2, B3, ..., B in the binary multiplier B signal in the form of a wavelength sequence with equal channel spacing. n , multiplied by the multiplier A to obtain the partial product.
3. The large bit-width optical digital multiplier for time-wavelength multiplexing according to claim 1, characterized in that: The partial product summing unit (2) comprises a first wavelength division multiplexer (21), a second wavelength division multiplexer (23) and n-1 delay lines (221, 222, ..., 22(n-1)). The first wavelength division multiplexer (21) is used to realize demultiplexing of the partial product sequence. The delay lines (221, 222, ..., 22(n-1)) are used to delay the partial products mapped on each wavelength in bit order to realize timing alignment. Finally, the partial products are input to the second wavelength division multiplexer (23) to realize incoherent superposition of the partial products. The output signal is an incoherent superposition signal S0.
4. The large bit-width optical digital multiplier for time-wavelength multiplexing according to claim 3, characterized in that: The cascaded binarization unit (3) comprises a number of binarization units cascaded in sequence, wherein the first binarization unit comprises an m1 bit converter (32), m1-1 delay lines (331, 332, ..., 33 (m1-1)) and a third wavelength division multiplexer (34), wherein the m1 bit converter (32) is used to convert an input signal S0 from a decimal optical signal into a binary electrical signal, and then convert the decimal optical signal into a binary optical signal. The delay line (331, 332, ..., 33 (m1-1)) is used to convert the binary optical signal C 1 High position The method comprises the following steps: performing bit-wise delay to realize the transmission of the carry signal; the third wavelength division multiplexer (34) is used to perform incoherent superposition on the carry signals output by the m1-1 delay lines (331, 332, ..., 33 (m1-1)) to obtain an incoherent superposition signal S1; the incoherent superposition signal S1 is input to the second binarization unit; the second binarization unit comprises an m2 bit converter (32), m2-1 delay lines (331, 332, ..., 33 (m2-1)), a third wavelength division multiplexer (34); the second binarization unit outputs an incoherent superposition signal S2; the incoherent superposition signal S2 is input to the third binarization unit, and the binarization units are sequentially cascaded until the incoherent superposition signal S1 is output. a ,in 5. The large bit-width optical digital multiplier for time-wavelength multiplexing according to claim 4, characterized in that: The cyclic binarization unit (4) comprises a 2×1 beam combiner (41), a 2-bit converter (42) and a delay line (43). The 2-bit converter (42) is used to convert the signal output by the 2×1 beam combiner (41) from a decimal optical signal to a binary optical signal. The high-order bit of the binary optical signal output by the 2-bit converter (42) is After passing through the delay line (43) for one-bit delay, the binary optical signal S is output by the cascade binarization unit (3). a The 2×1 beam combiner (41) performs beam combining, and the lower bit of the 2-bit converter (42) That is, output the operation result of the multiplier.
6. The large bit-width optical digital multiplier for time-wavelength multiplexing according to claim 4, characterized in that: The number a of cascaded binarization units satisfies: Indicates rounding down.
7. The large bit width optical digital multiplier for time-wavelength multiplexing according to claim 5, characterized in that: The delays of the n-1 delay lines (221, 222, ..., 22(n-1)) in the partial product summation unit (2) are τ, 2τ, ..., (n-1)τ respectively, and the delays of the n-1 delay lines (221, 222, ..., 22(n-1)) in the cascade binarization unit (3) are The delay lines of the first binary unit (331, 332, ..., 33 (m1-1)) are τ, 2τ, ..., (m1-1)τ, respectively, and the delay lines of the ith binary unit are τ, 2τ, ..., (m1-1)τ, respectively. i -1)τ, the delay of the delay line (43) in the cyclic binarization unit (4) is τ, and τ corresponds to the code length of one code element of the multiplier signal.
8. The large bit-width optical digital multiplier for time-wavelength multiplexing according to claim 2, characterized in that: The first multi-wavelength laser source (11) is an optical frequency comb, or is realized by combining laser beams of different wavelengths output by multiple lasers.