High-speed peripheral component interconnect bus resource allocation system and method

Abstract

The present application discloses a high-speed peripheral component interconnect (PCIe) bus resource allocation system and method, relating to the technical field of servers. The system comprises: a basic input / output (BIOS) chip and a baseboard management controller (BMC); the BIOS chip is configured to send an alarm message when the number of bus numbers allocated to high-speed peripheral component interconnect (PCIe) devices of a first target type exceeds an upper limit on the number of reserved bus numbers; the BMC is configured to process the alarm message to trigger a restart of the BIOS; the BIOS chip is further configured to reallocate bus numbers of the high-speed peripheral component interconnect (PCIe) bus after the BIOS is restarted, and to set different upper limits on high-speed peripheral component interconnect (PCIe) bus resources according to different types of PCIe devices and perform secondary allocation, thereby solving the technical problem of low utilization efficiency of high-speed peripheral component interconnect (PCIe) bus resources and achieving the technical effect of improving utilization efficiency of high-speed peripheral component interconnect (PCIe) bus resources.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a high-speed peripheral component interconnection bus resource allocation system and method. Background Art

[0002] During server startup, the Basic Input / Output System (BIOS) allocates bus resources for high-speed Peripheral Component Interconnect Express (PCIe) devices. PCIe bus resources are a key resource in the server hardware architecture. Proper allocation of these resources directly impacts the performance and stability of individual PCIe devices and the server as a whole. Traditional methods for allocating bus resources for PCIe devices typically employ a unified allocation strategy, which can lead to wasted or insufficient bus resources and inefficient bus resource utilization. Summary of the Invention

[0003] The present application provides a high-speed peripheral component interconnect bus resource allocation system and method to at least solve the problem of low utilization efficiency of peripheral component interconnect bus resources in related technologies.

[0004] The present application provides a high-speed peripheral component interconnect bus resource allocation system, the system comprising: a basic input and output system chip and a baseboard management controller;

[0005] The basic input / output system chip is configured to, during a process in which the basic input / output system enumerates a target high-speed peripheral component interconnect device of a server, allocate a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device; obtain a type of the target high-speed peripheral component interconnect device; and, if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds an upper limit of the number of bus numbers reserved for the first target type, send a target alarm message to the baseboard management controller; the target alarm message is used to indicate insufficient high-speed peripheral component interconnect bus resources;

[0006] The baseboard management controller is configured to receive the target alarm information and process the target alarm information based on the type of the target high-speed peripheral component interconnect device that triggers the target alarm information to trigger a restart of the basic input and output system;

[0007] The basic input / output system chip is further configured to, after the basic input / output system is restarted, re-allocate a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device based on target high-speed peripheral component interconnect bus resources if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers already allocated to the target high-speed peripheral component interconnect device exceeds an upper limit of the number of bus numbers reserved for the first target type.

[0008] The present application also provides a high-speed peripheral component interconnect bus resource allocation method, which is applied to any of the above-mentioned high-speed peripheral component interconnect bus resource allocation systems, and the method includes:

[0009] The basic input / output system chip performs an operation of allocating a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device of the server during the process of the basic input / output system enumerating the target high-speed peripheral component interconnect device of the server; obtains the type of the target high-speed peripheral component interconnect device; and sends a target alarm message to a baseboard management controller if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type; the target alarm message is used to indicate insufficient resources of the high-speed peripheral component interconnect bus;

[0010] The baseboard management controller receives the target alarm information, and processes the target alarm information based on the type of the target peripheral component interconnect high-speed device that triggers the target alarm information to trigger the basic input and output system to restart;

[0011] After the basic input / output system is restarted, the basic input / output system chip re-assigns a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device based on target high-speed peripheral component interconnect bus resources if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers already allocated to the target high-speed peripheral component interconnect device exceeds an upper limit of the number of bus numbers reserved for the first target type.

[0012] The present application also provides a server comprising any of the above-mentioned high-speed peripheral component interconnection bus resource allocation systems.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned high-speed peripheral component interconnect bus resource allocation methods when executing the computer program.

[0014] The present application also provides a non-transitory computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned high-speed peripheral component interconnect bus resource allocation methods are implemented.

[0015] The present application also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned high-speed peripheral component interconnect bus resource allocation methods when executed by a processor.

[0016] Through the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is the first target type, it is determined whether the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type. When the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type, a target alarm information is sent to the baseboard management controller of the server to trigger a resource shortage alarm, and the high-speed peripheral component interconnect bus resources are secondary allocated. A differentiated high-speed peripheral component interconnect bus resource allocation strategy is adopted, and different high-speed peripheral component interconnect bus resource upper limits are set according to different types of enumerated PCIe devices, so as to realize the reservation of high-speed peripheral component interconnect bus resources for high-performance dedicated PCIe devices and the general allocation of high-speed peripheral component interconnect bus resources. Through the reasonable allocation and secondary allocation of high-speed peripheral component interconnect bus resources of PCIe devices, the alarm of insufficient high-speed peripheral component interconnect bus resources can be resolved more promptly and efficiently. By reserving exclusive high-speed peripheral component interconnect bus resources for PCIe devices of the first target type, the normal operation and performance of the PCIe devices of the first target type are ensured, and the device function is avoided from being restricted due to unreasonable resource allocation. The high-speed peripheral component interconnect bus resources of the second target type are restricted based on the root bridge, and the high-speed peripheral component interconnect bus resources of each root bridge are reasonably utilized, thereby reducing the waste and shortage of high-speed peripheral component interconnect bus resources. The allocation of high-speed peripheral component interconnect bus resources is more reasonable, thereby solving the technical problem of low utilization efficiency of high-speed peripheral component interconnect bus resources and achieving the technical effect of improving the utilization efficiency of high-speed peripheral component interconnect bus resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1A schematic diagram of an application environment architecture of a high-speed peripheral component interconnect bus resource allocation system provided in an embodiment of the present application;

[0019] Figure 2 A schematic diagram of the structure of a high-speed peripheral component interconnect bus resource allocation system provided in an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of one of the operation flow charts of a high-speed peripheral component interconnect bus resource allocation system provided in an embodiment of the present application;

[0021] Figure 4 The second schematic diagram of the operation flow of a high-speed peripheral component interconnect bus resource allocation system provided in an embodiment of the present application;

[0022] Figure 5 A flowchart of a high-speed peripheral component interconnect bus resource allocation method provided in an embodiment of the present application;

[0023] Figure 6 A schematic diagram of the structure of a server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0025] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0026] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] In the related art, the Basic Input Output System (BIOS) chip allocates high-speed peripheral component interconnect bus resources to PCIe devices during the process of enumerating PCIe devices, usually using a simple sequential allocation method and allocating them with a fixed bus resource upper limit. The device type of the PCIe device is not distinguished in the allocation, that is, regardless of the type of PCIe device, the same allocation method and the same bus resource upper limit are used. In the case of insufficient high-speed peripheral component interconnect bus resources being detected, the BIOS chip triggers the same level of alarm information regardless of the type of PCIe device to which the high-speed peripheral component interconnect bus resources are allocated. Moreover, the above-mentioned alarm information only includes a simple prompt of insufficient high-speed peripheral component interconnect bus resources, and the prompt of the baseboard management controller (BMC) to the server administrator also only includes the phenomenon of insufficient high-speed peripheral component interconnect bus resources.

[0028] For example, during the process of enumerating PCIe devices, the BIOS chip can allocate PCIe Bus numbers (Bus numbers) in sequence according to the order in which the PCIe devices are enumerated. When the number of allocated Bus numbers reaches the preset global upper limit, an OOR alarm is triggered, and the allocation of high-speed peripheral component interconnection bus resources within the root bridge (RB) is stopped.

[0029] However, with the development of information technology, the types and number of PCIe devices in servers are increasing. Among them, various types of high-performance, specialized PCIe devices, such as data processing units (DPUs), are becoming increasingly widely used, improving server performance. To ensure the normal operation and performance of these various types of high-performance, specialized PCIe devices, a certain amount of high-speed peripheral component interconnect (PCI) bus resources must generally be reserved. The widespread use of these high-performance, specialized PCIe devices also places higher demands on the management of PCI bus resources (which may include allocating PCI bus resources and handling alarms for insufficient PCI bus resources). Given the different characteristics of these various types of high-performance, specialized PCIe devices and non-type PCIe devices (referred to as "ordinary PCIe devices" in the following embodiments of this application), these various types of high-performance, specialized PCIe devices and ordinary PCIe devices may have different requirements and priorities for the allocation of high-speed PCI bus resources.

[0030] Related technologies fail to consider the high-speed peripheral component interconnect (PCIe) bus resource reservation requirements for high-performance, dedicated PCIe devices like DPUs. This can easily lead to these devices malfunctioning or underperforming due to insufficient high-speed PCIe bus resources. Furthermore, OOR alarm information is relatively sparse, hindering rapid problem location and troubleshooting.

[0031] First, the relevant technology lacks a differentiated resource allocation strategy, does not distinguish between high-performance dedicated PCIe devices and ordinary PCIe devices, and cannot reserve the necessary high-speed peripheral component interconnection bus resources for high-performance dedicated PCIe devices. This can easily lead to the performance of high-performance dedicated PCIe devices being limited or unable to start normally, thereby affecting the overall function of the server.

[0032] Secondly, the alarm information in the relevant technology has the defect of unclear meaning. The unified alarm level and simple alarm content make it difficult for server managers to quickly distinguish whether the OOR alarm is triggered by a high-performance dedicated PCIe device or an ordinary PCIe device. It is even more difficult to accurately obtain the specific location and related information of the PCIe device that triggered the OOR alarm, which increases the difficulty and time cost of server maintenance.

[0033] Third, the related technologies lack flexibility in managing high-speed peripheral component interconnect bus resources. High-speed peripheral component interconnect bus resources are global resources with a fixed upper limit. They cannot be dynamically adjusted according to the high-speed peripheral component interconnect bus resource requirements of different types of PCIe devices, resulting in unreasonable allocation of high-speed peripheral component interconnect bus resources, which easily leads to waste or shortage of high-speed peripheral component interconnect bus resources, and low utilization efficiency of high-speed peripheral component interconnect bus resources.

[0034] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the high-speed peripheral component interconnect bus resource allocation system and method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0035] refer to Figure 1 The high-speed peripheral component interconnect bus resource allocation system provided by this application can be applied to Figure 1 The architecture shown in the figure. The high-speed peripheral component interconnect bus resource allocation system can include two parts: a basic input and output system (BIOS) chip and a baseboard management controller (BMC). The BIOS chip can communicate with the BMC through wired communication or other means.

[0036] PCIe devices can be connected to the BIOS chip via the PCIe bus. The BIOS chip allocates peripheral component interconnect bus (PCIe Bus) resources (specifically, assigns PCIe Bus numbers) during PCIe device enumeration and sends corresponding alarm information to the BMC when high-speed peripheral component interconnect bus resources are insufficient (Out of Resource, OOR).

[0037] In some embodiments, the BIOS chip can be connected to a PCIe bridge (PCIe Switch) via a PCIe bus, communicating using the PCIe bus. The PCIe bridge can connect to various types of PCIe devices, such as the aforementioned common PCIe devices and DPU devices. All of these types of PCIe devices communicate using the PCIe bus.

[0038] The BIOS chip can interact directly with the BMC. When it detects insufficient PCIe bus resources, it sends the BMC an OOR warning. User terminals and other devices can receive the BMC's warning based on this information, triggering a BIOS reboot and re-allocation of PCIe bus resources to resolve the warning.

[0039] In some embodiments, the BMC can monitor the server's hardware status data, such as power, CPU, memory, hard disk, and environmental parameters, in real time through a built-in sensor network. It also supports out-of-band communication with the motherboard via the baseband management interface. To manage the server, the BMC can communicate with other devices based on the Intelligent Platform Management Interface (IPMI) standard.

[0040] The BMC can be used to process the alarm information sent by the BIOS chip so that the server administrator can promptly handle the situation of insufficient resources on the high-speed peripheral component interconnection bus.

[0041] In the following embodiments of this application, the BIOS chip adopts different high-speed peripheral component interconnect bus resource restriction and allocation strategies based on the different types of PCIe devices (e.g., high-performance dedicated PCIe devices or ordinary PCIe devices). Accordingly, after receiving alarm information from the BIOS chip, the BMC can trigger alarm events and generate a system event log (SEL) through different pre-configured sensors, implementing hierarchical processing and display of OOR alarm information.

[0042] An embodiment of the present application provides a high-speed peripheral component interconnect bus resource allocation system. The system is described in detail in conjunction with the structure of the high-speed peripheral component interconnect bus resource allocation system.

[0043] Specifically, Figure 2 This is a schematic diagram of a high-speed peripheral component interconnect bus resource allocation system according to an embodiment of the present application. The high-speed peripheral component interconnect bus resource allocation system 200 can be applied to a server. The high-speed peripheral component interconnect bus resource allocation system 200 may include a basic input / output system chip 210 and a baseboard management controller 220.

[0044] In actual implementation, the basic input / output system chip 210 and the baseboard management controller 220 may be a BIOS chip and a BMC in the same server.

[0045] The basic input / output system chip 210 is configured to, during a process in which the basic input / output system enumerates a target high-speed peripheral component interconnect device of the server, assign a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device; obtain the type of the target high-speed peripheral component interconnect device; and, if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers assigned to the target high-speed peripheral component interconnect device exceeds an upper limit on the number of bus numbers reserved for the first target type, send a target alarm message to the baseboard management controller 220; the target alarm message is used to indicate insufficient high-speed peripheral component interconnect bus resources.

[0046] In actual execution, when the BIOS detects that a new PCIe device is connected to the server, the BIOS chip may use the PCIe device as a target high-speed peripheral component interconnect device and start enumerating the PCIe device.

[0047] After enumerating the target PCI Express device, the BIOS chip may allocate PCI Express bus resources to the target PCI Express device, attempting to allocate a PCI Express Bus number to the target PCI Express device. In some embodiments, the BIOS chip may record information about the root bridge to which the target PCI Express device belongs.

[0048] In actual execution, the BIOS chip may determine the device type of the target high-speed peripheral component interconnect device and identify the type of the target high-speed peripheral component interconnect device.

[0049] In some embodiments, the BIOS chip may obtain the type of the target high-speed peripheral component interconnect device based on the identification information of the target high-speed peripheral component interconnect device.

[0050] In some embodiments, the identification information of the target HSPCI device may include at least one of an identification number (ID) of the target HSPCI device and an identification number of a manufacturer of the target HSPCI device.

[0051] In actual implementation, if the type of the target high-speed peripheral component interconnect device is the first target type, it can be checked whether the number of PCIe Bus bus numbers allocated to the target high-speed peripheral component interconnect device is greater than a reserved value. It should be noted that the reserved value is the upper limit of the number of PCIe Bus bus numbers reserved for the first target type.

[0052] In some embodiments, the first target type may include at least one type of the aforementioned high-performance dedicated PCIe device, such as a DPU. The number of first target types may be at least one, and each first target type may have a reserved value.

[0053] In some embodiments, the BIOS chip can maintain an upper limit on the number of PCIe Bus numbers reserved for each first target type, i.e., a reserved value. Each reserved value can be determined by a default setting of the BIOS or input by a server administrator.

[0054] If the number of PCIe Bus bus numbers allocated to the target high-speed peripheral component interconnect device is greater than or equal to the upper limit of the number of PCIe Bus bus numbers reserved for the first target type, it indicates that regardless of whether the high-speed peripheral component interconnect bus resources of the root bridge to which the target high-speed peripheral component interconnect device belongs are sufficient, the current high-speed peripheral component interconnect bus resources cannot meet the needs of the target high-speed peripheral component interconnect device, and the high-speed peripheral component interconnect bus resources are insufficient, which can trigger an OOR alarm. In some embodiments, the BIOS chip can send a target alarm message to the BMC of the same server, so that the BMC triggers the OOR alarm. The target alarm message can indicate that the high-speed peripheral component interconnect bus resources are insufficient.

[0055] In some embodiments, when the number of PCIe Bus bus numbers allocated to the target high-speed peripheral component interconnect device is greater than or equal to the upper limit of the number of PCIe Bus bus numbers reserved for the first target type, the BIOS chip may stop executing the operation of allocating PCIe Bus bus numbers to the target high-speed peripheral component interconnect device, no longer allocate PCIe Bus bus numbers exceeding the aforementioned reserved value to the target high-speed peripheral component interconnect device, and end the allocation of high-speed peripheral component interconnect bus resources to the root bridge (i.e., the current root bridge) to which the target high-speed peripheral component interconnect device belongs.

[0056] In some embodiments, when the number of bus numbers of the PCIe Bus allocated to the target high-speed peripheral component interconnect device is greater than or equal to the upper limit of the number of bus numbers of the PCIe Bus reserved for the first target type, the BIOS chip may also record the bus number of the PCIe Bus of the first-level upstream bridge (Bridge) of the target high-speed peripheral component interconnect device and information about the root bridge to which the target high-speed peripheral component interconnect device belongs.

[0057] The baseboard management controller 220 is configured to receive target alarm information and process the target alarm information based on the type of the target high-speed peripheral component interconnect device that triggers the target alarm information to trigger a restart of the basic input and output system.

[0058] In actual implementation, when the high-speed peripheral component interconnect bus resources are insufficient, the BIOS chip can send a target alarm message indicating insufficient high-speed peripheral component interconnect bus resources to the baseboard management controller 220 of the same server. The baseboard management controller 220 can receive the target alarm message.

[0059] In some embodiments, the embodiments of the present application do not limit the specific format of the target alarm information. In some embodiments, the target alarm information can conform to the format of the original equipment manufacturer command of the intelligent platform management interface standard.

[0060] In some embodiments, the type of the target Peripheral Component Interconnect Express device that triggers the target alarm information may be acquired according to the content of the target alarm information.

[0061] In actual implementation, the BMC can process the above target alarm information accordingly based on the type of the target high-speed peripheral component interconnect device that triggers the BIOS chip to send the target alarm information, so that the server administrator can quickly locate and solve the problem of insufficient high-speed peripheral component interconnect bus resources.

[0062] It's important to note that when a server's high-speed peripheral component interconnect bus runs low on resources, prompt alerts must be sent to server administrators so they can take appropriate action. However, prior art lacks an effective mechanism for distinguishing and categorizing OOR alerts triggered by different types of PCIe devices. This makes it difficult for administrators to quickly and accurately locate problematic devices, impacting server maintenance and management efficiency.

[0063] In some embodiments, the baseboard management controller 220 processes the target alarm information to trigger a restart of the basic input and output system based on the type of the target peripheral component interconnect (PCI) high-speed device that triggers the target alarm information.

[0064] In some embodiments, the baseboard management controller 220 may process the target alarm information and send a control instruction to the basic input and output system chip 210; the basic input and output system chip 210 may restart the BIOS in response to the control instruction.

[0065] In some embodiments, the baseboard management controller 220 can send an alarm to a user terminal or other device by processing the target alarm information, and the above-mentioned device sends a control instruction to the basic input and output system chip 210; the basic input and output system chip 210 can restart the BIOS in response to the control instruction.

[0066] The BIOS chip 210 is further configured to, after the BIOS is restarted, re-allocate a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device based on target high-speed peripheral component interconnect bus resources if the type of the target high-speed peripheral component interconnect device is the first target type and the number of bus numbers already allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type.

[0067] In actual execution, after the BIOS is restarted, the basic input and output system chip 210 can re-execute the aforementioned steps: in the process of the basic input and output system enumerating the target high-speed peripheral component interconnect device of the server, the operation of allocating the bus number of the high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device is performed, and the type of the target high-speed peripheral component interconnect device is obtained.

[0068] When it is determined again that the type of the target high-speed peripheral component interconnect device is the first target type, and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type, the basic input and output system chip 210 can re-allocate the high-speed peripheral component interconnect bus resources, that is, re-allocate the bus number of the high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device, so as to resolve the OOR alarm.

[0069] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is the first target type, it is determined whether the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type. When the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type, a target alarm message is sent to the baseboard management controller of the server to trigger a resource shortage alarm, and the high-speed peripheral component interconnect bus resources are secondary allocated. A differentiated high-speed peripheral component interconnect bus resource allocation strategy is adopted, and different high-speed peripheral component interconnect bus resource upper limits are set according to different types of enumerated PCIe devices, so as to achieve The reservation of high-speed peripheral component interconnect bus resources for high-performance dedicated PCIe devices and the reasonable allocation and secondary allocation of high-speed peripheral component interconnect bus resources for ordinary PCIe devices can more promptly and efficiently resolve the alarm of insufficient high-speed peripheral component interconnect bus resources. By reserving exclusive high-speed peripheral component interconnect bus resources for PCIe devices of the first target type, the normal operation and performance of PCIe devices of the first target type are ensured, and the device function is avoided from being restricted due to unreasonable resource allocation. The high-speed peripheral component interconnect bus resources of PCIe devices of the second target type are restricted based on the root bridge, and the high-speed peripheral component interconnect bus resources of each root bridge are reasonably utilized, thereby reducing the waste and shortage of high-speed peripheral component interconnect bus resources. The allocation of high-speed peripheral component interconnect bus resources is more reasonable, and the utilization efficiency of high-speed peripheral component interconnect bus resources can be improved.

[0070] Furthermore, by triggering different levels of alarm information according to the type of the target high-speed peripheral component interconnect device that triggers the target alarm information, the baseboard management controller processes the target alarm information based on the type of the target high-speed peripheral component interconnect device that triggers the target alarm information, and can quickly determine which type of high-speed peripheral component interconnect device has the problem of insufficient high-speed peripheral component interconnect bus resources, which can make it easier for server managers to quickly locate and solve the problem of insufficient high-speed peripheral component interconnect bus resources.

[0071] In some embodiments of the present application, the basic input / output system chip 210 is specifically configured to release the bus number of the high-speed peripheral component interconnect bus that has been allocated and is not used by other high-speed peripheral component interconnect devices of the first target type under the target root bridge, and allocate it to the target high-speed peripheral component interconnect device; the target root bridge is the root bridge to which the target high-speed peripheral component interconnect device belongs.

[0072] In actual execution, after the BIOS is restarted, the basic input and output system chip 210 can adopt a secondary allocation strategy for releasing unused reserved resources when it is determined again that the type of the target high-speed peripheral component interconnect device is the first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type.

[0073] The secondary allocation strategy for releasing unused reserved resources includes checking for allocated and unused PCIe bus resources (specifically, PCIe bus numbers) for other high-speed peripheral component interconnect devices of the first target type under the root bridge to which the target high-speed peripheral component interconnect device belongs. If such allocated and unused PCIe bus resources exist, the basic input / output system chip 210 can reclaim the allocated and unused PCIe bus resources and, based on the allocated and unused PCIe bus resources, reallocate PCIe bus resources to the target high-speed peripheral component interconnect device, allocating a high-speed peripheral component interconnect bus number to the target high-speed peripheral component interconnect device.

[0074] In some embodiments, the SecondaryStatus register in the configuration space of the PCIe bridge can be used to check the PCIe bus resources allocated and unused by other high-speed peripheral component interconnect devices of the first target type under the root bridge to which the target high-speed peripheral component interconnect device belongs. The secondary status is status information in the configuration space of the PCIe bridge, which is used to indicate the secondary status of the PCIe bridge.

[0075] Exemplarily, the implementation of the above-mentioned secondary allocation strategy for releasing unused reserved resources may include: the other high-speed peripheral component interconnect device is DPU1, and the Bus numbers allocated to the device are 10 to 12, but only Bus numbers 10 and 11 are actually used, so Bus number 12 can be recycled and allocated to the target high-speed peripheral component interconnect device.

[0076] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by releasing the bus numbers of the high-speed peripheral component interconnect buses that have been allocated and unused by other high-speed peripheral component interconnect devices of the first target type under the target root bridge and allocating them to the target high-speed peripheral component interconnect device, secondary allocation of high-speed peripheral component interconnect bus resources is performed to resolve the resource shortage alarm. This can more quickly and reasonably handle the high-speed peripheral component interconnect bus resource shortage alarm, and can improve the efficiency of handling the high-speed peripheral component interconnect bus resource shortage alarm.

[0077] In some embodiments of the present application, the basic input / output system chip 210 is specifically configured to allocate, to a target high-speed peripheral component interconnect device, a bus number of a high-speed peripheral component interconnect bus that is released by reducing the upper limit of the number of bus numbers of high-speed peripheral component interconnect devices other than the first target type under the target root bridge, when there are no or insufficient bus numbers of the high-speed peripheral component interconnect buses that have been allocated and are not in use by other high-speed peripheral component interconnect devices of the first target type under the target root bridge.

[0078] In actual implementation, if the secondary allocation strategy of releasing unused reserved resources is not successfully implemented, a secondary allocation strategy of compressing common device resources may be adopted.

[0079] In some embodiments, situations in which the above-mentioned secondary allocation strategy for releasing unused reserved resources is not successfully implemented may include: there is no bus number of a high-speed peripheral component interconnect bus that has been allocated and not used by other high-speed peripheral component interconnect devices of the first target type under the target root bridge, or the bus numbers of the high-speed peripheral component interconnect buses that have been allocated and not used by other high-speed peripheral component interconnect devices of the first target type under the target root bridge are insufficient, that is, they do not meet the requirements of the target high-speed peripheral component interconnect device, etc.

[0080] The secondary allocation strategy for compressing common device resources may include: reducing the upper limit of bus number allocation of the PCIe bus of non-first target type PCIe devices under the target root bridge, and allocating the PCIe bus resources released by the above measures to the target high-speed peripheral component interconnect device.

[0081] In some embodiments, the reduction of the upper limit of Bus number allocation for the PCIe buses of non-first target type PCIe devices under the target root bridge can be based on the priority of the non-first target type PCIe devices. That is, the upper limit of Bus number allocation for the PCIe buses of low-priority non-first target type PCIe devices can be reduced first. If the requirements of the target high-speed peripheral component interconnection device are still not met, the upper limit of Bus number allocation for the PCIe buses of high-priority non-first target type PCIe devices can be reduced again, until the upper limit of Bus number allocation for the PCIe buses of all non-first target type PCIe devices under the target root bridge is reduced, or the requirements of the target high-speed peripheral component interconnection device are met.

[0082] In some embodiments, the priority of PCIe devices of the first target type can be pre-set. For example, non-first target type PCIe devices may include a network card and a sound card. The network card has a higher priority than the sound card. Based on the secondary allocation strategy for compressing common device resources, the upper limit of the bus number allocation of the PCIe bus of the sound card can be reduced first, and then the upper limit of the bus number allocation of the PCIe bus of the network card can be reduced.

[0083] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiments of the present application, by allocating the bus number of the high-speed peripheral component interconnect bus released by reducing the upper limit of the number of bus numbers of high-speed peripheral component interconnect devices of non-first target type under the target root bridge to the target high-speed peripheral component interconnect device, secondary allocation of high-speed peripheral component interconnect bus resources is performed to resolve the resource shortage alarm. This system can more quickly and reasonably handle the high-speed peripheral component interconnect bus resource shortage alarm, thereby improving the efficiency of handling the high-speed peripheral component interconnect bus resource shortage alarm.

[0084] In some embodiments of the present application, the basic input / output system chip 210 is specifically configured to allocate the bus numbers of the remaining high-speed peripheral component interconnect buses under other root bridges to the target high-speed peripheral component interconnect device when the bus numbers of the high-speed peripheral component interconnect buses released by reducing the upper limit of the number of bus numbers of non-first target type high-speed peripheral component interconnect devices under the target root bridge are insufficient.

[0085] In actual implementation, if the secondary allocation strategy of compressing common device resources is not successfully implemented, the secondary allocation strategy of borrowing resources across root bridges can be adopted.

[0086] In some embodiments, situations in which the secondary allocation strategy for compressing common device resources is not successfully implemented may include: reducing the upper limit of the number of bus numbers of non-first target type high-speed peripheral component interconnect devices under the target root bridge, and the bus numbers of the high-speed peripheral component interconnect buses released are insufficient, that is, they cannot meet the requirements of the target high-speed peripheral component interconnect buses, etc.

[0087] The secondary allocation strategy for borrowing resources across root bridges may include: when there are remaining PCIe bus resources in other root bridges, the resource pool of the root bridge to which the target high-speed peripheral component interconnect device belongs can be dynamically expanded through the PCIe bridge, and the PCIe bus resources of other root bridges can be mapped to the current domain, so that the bus number of the remaining high-speed peripheral component interconnect buses under other root bridges can be allocated to the target high-speed peripheral component interconnect device.

[0088] In some embodiments, dynamically expanding the resource pool of the root bridge to which the target high-speed peripheral component interconnect device belongs by a PCIe bridge and mapping the PCIe bus resources of other root bridges to the current domain can be implemented through the primary status register and / or secondary status register of the configuration space of the PCIe bridge.

[0089] It can be understood that the above-mentioned secondary allocation strategy of releasing unused reserved resources, the secondary allocation strategy of compressing ordinary equipment resources and the secondary allocation strategy of borrowing resources across root bridges can be implemented in sequence according to priority, that is, the secondary allocation strategy of releasing unused reserved resources is implemented first; if the secondary allocation strategy of releasing unused reserved resources is unsuccessful, the secondary allocation strategy of compressing ordinary equipment resources is implemented; if the secondary allocation strategy of compressing ordinary equipment resources is unsuccessful, the secondary allocation strategy of borrowing resources across root bridges is implemented.

[0090] Figure 3 This is one of the operational flow diagrams of a high-speed peripheral component interconnect bus resource allocation system provided in an embodiment of the present application. Figure 3 FIG. 4 shows the process of secondary allocation of the high-speed peripheral component interconnect bus resources. Figure 3 As shown, the process of secondary allocation of high-speed peripheral component interconnect bus resources may include the following steps.

[0091] Step 310: BIOS restarts.

[0092] Insufficient PCIe bus resources of the target high-speed peripheral component interconnect device trigger a resource shortage alarm and trigger a BIOS restart.

[0093] Step 320: Determine whether the target high-speed peripheral component interconnect device has triggered a resource shortage alarm.

[0094] Determine whether a resource shortage alarm has been triggered. Through the above steps, it can be determined that a resource shortage alarm has been triggered on the target peripheral component interconnect (PCI) Express device.

[0095] Step 330: Determine whether the resources meet the requirements.

[0096] Determine whether the current PCIe bus resources meet the requirements of the target high-speed peripheral component interconnect device of the first target type. If yes, execute step 340; if not, execute step 350.

[0097] Step 340: Allocate resources and continue enumeration.

[0098] Based on allocating PCIe bus resources to the target Peripheral Component Interconnect Express device of the first target type, enumeration of the target Peripheral Component Interconnect Express device of the first target type is continued.

[0099] Step 350: Implement a secondary allocation strategy for releasing unused reserved resources.

[0100] Step 360: Implement a secondary allocation strategy for compressing common device resources.

[0101] Step 370: Implement a secondary allocation strategy for borrowed resources across root bridges.

[0102] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, by allocating the bus numbers of the remaining high-speed peripheral component interconnect buses under other root bridges to the target high-speed peripheral component interconnect device, secondary allocation of high-speed peripheral component interconnect bus resources is performed to resolve the resource shortage alarm. This can more quickly and reasonably handle the high-speed peripheral component interconnect bus resource shortage alarm, and can improve the efficiency of handling the high-speed peripheral component interconnect bus resource shortage alarm.

[0103] In some embodiments of the present application, the basic input / output system chip 210 is further configured to send target alarm information to the baseboard management controller when the type of the target high-speed peripheral component interconnect device is the second target type and the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs.

[0104] In actual execution, when the type of the target high-speed peripheral component interconnect device is the second target type, it can be checked whether the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers of the PCIe Bus corresponding to the root bridge.

[0105] In some embodiments, the BIOS chip can pre-set an upper limit on the number of PCIe Bus bus numbers corresponding to each root bridge. In some embodiments, the upper limit on the number of PCIe Bus bus numbers corresponding to each root bridge can be determined based on the hardware specifications of the root bridge and the configuration of the server.

[0106] In some embodiments, the second target type may include at least one type of the aforementioned common PCIe devices.

[0107] If the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of PCIe Bus numbers corresponding to the root bridge, it indicates that the high-speed peripheral component interconnect bus resources of the root bridge are insufficient, and an OOR alarm may be triggered. In some embodiments, the BIOS chip may send a target alarm message to the BMC of the same server, causing the BMC to trigger an OOR alarm. The target alarm message may indicate insufficient high-speed peripheral component interconnect bus resources.

[0108] In some embodiments, when the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers of the PCIe Bus corresponding to the root bridge, the BIOS chip may stop executing the operation of allocating PCIe Bus numbers to the target high-speed peripheral component interconnect device, and terminate the allocation of high-speed peripheral component interconnect bus resources to the root bridge to which the target high-speed peripheral component interconnect device belongs (i.e., the current root bridge or the target root bridge).

[0109] In some embodiments, when the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers of the PCIe Bus corresponding to the root bridge, the BIOS chip may further record the bus number of the PCIe Bus of the target high-speed peripheral component interconnect device and information about the root bridge to which the target high-speed peripheral component interconnect device belongs.

[0110] It should be noted that after the BIOS is restarted, the PCIe bus resources allocated to the non-first target type PCI devices in each root bridge may be released and reallocated.

[0111] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is the second target type, it is determined whether the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs. When the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs, a target alarm message is sent to the baseboard management controller of the server to trigger a resource shortage alarm, and a differentiated high-speed peripheral component interconnect bus resource allocation strategy is adopted. According to the different types of enumerated PCIe devices, Different high-speed peripheral component interconnect bus resource upper limits are used to reserve high-speed peripheral component interconnect bus resources for high-performance dedicated PCIe devices and reasonably allocate high-speed peripheral component interconnect bus resources for ordinary PCIe devices. By reserving exclusive high-speed peripheral component interconnect bus resources for PCIe devices of the first target type, the normal operation and performance of PCIe devices of the first target type are ensured, and the device function is avoided from being restricted due to unreasonable resource allocation. The high-speed peripheral component interconnect bus resources of PCIe devices of the second target type are restricted based on the root bridge, and the high-speed peripheral component interconnect bus resources of each root bridge are reasonably utilized, thereby reducing the waste and shortage of high-speed peripheral component interconnect bus resources. The allocation of high-speed peripheral component interconnect bus resources is more reasonable, and the utilization efficiency of high-speed peripheral component interconnect bus resources can be improved.

[0112] In some embodiments of the present application, the basic input and output system chip 210 includes: a generating module and a sending module.

[0113] The generating module is used to generate target alarm information; the target alarm information carries first information; the first information is used to indicate the type of the target high-speed peripheral component interconnect device.

[0114] In actual implementation, no matter whether the target high-speed peripheral component interconnect device of the first target type or the second target type triggers the OOR alarm, the generation module in the BIOS chip can generate target alarm information carrying the first information for indicating the type of the target high-speed peripheral component interconnect device based on the BIOS.

[0115] In some embodiments, the first information may include at least one of the following information, such as the name and number of the first target type, which can uniquely identify the type of the PCIe device. The embodiment of the present application does not limit the specific type of information used by the first information.

[0116] In some embodiments, the embodiments of the present application do not limit the specific format of the target alarm information.

[0117] The sending module is configured to send target alarm information to the baseboard management controller 220 .

[0118] In actual execution, after generating the target alarm information, the sending module in the BIOS chip may send the target alarm information to the BMC of the same server through the BIOS, so that the BMC triggers an OOR alarm.

[0119] In some embodiments, since the target alarm information carries first information for indicating the type of the target high-speed peripheral component interconnect device, the BMC can trigger an alarm event carrying the first information to prompt the server administrator which type of PCIe device has insufficient high-speed peripheral component interconnect bus resources, triggering the OOR alarm.

[0120] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, by sending a target alarm message carrying first information for indicating the type of the target high-speed peripheral component interconnect device to the baseboard management controller, the BMC can trigger an OOR alarm event carrying information for indicating the type of the target high-speed peripheral component interconnect device, so that the server administrator can quickly determine which type of PCIe device triggered the high-speed peripheral component interconnect bus resource shortage problem and the specific location of the problem device, which can make it easier for the server administrator to quickly locate and solve the high-speed peripheral component interconnect bus resource shortage problem and shorten the troubleshooting time. In addition, timely and accurate alarm information helps the server administrator take measures more promptly, including adjusting the allocation of high-speed peripheral component interconnect bus resources and / or increasing high-speed peripheral component interconnect bus resources, etc., which can avoid PCIe device or even server failure or server system crash caused by insufficient resources, and can improve the stability and reliability of the server system.

[0121] In some embodiments of the present application, the target alarm information carries second information and third information; the second information is used to indicate the root bridge to which the target high-speed peripheral component interconnection device belongs; the third information is used to indicate the address of the target high-speed peripheral component interconnection device; the address includes a bus number, a device number, and a function number.

[0122] In actual implementation, no matter whether the target high-speed peripheral component interconnect device of the first target type or the second target type triggers the OOR alarm, the BIOS may generate the second information and the third information carrying the first information, the second information and the third information.

[0123] The second information may be used to indicate the root bridge to which the target high-speed peripheral component interconnect device belongs. In some embodiments, the second information may include at least one of a root bridge name and an ID that can uniquely identify the root bridge. The embodiments of the present application do not limit the specific type of information used in the second information.

[0124] The third information may be used to indicate the address of the target high-speed peripheral component interconnect device. In some embodiments, the third information may be the address information of a PCIe device. The address information of the PCIe device may include at least one of the bus number, device number, and function number of the PCIe device. It is understood that the bus number, device number, and function number described above may be collectively referred to as a BDF.

[0125] It should be noted that the target alarm information carries the second information and the third information. The BMC can trigger an alarm event carrying the second information and the third information to remind the server administrator which PCIe device has insufficient high-speed peripheral component interconnect bus resources, triggering the OOR alarm.

[0126] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by sending a target alarm message carrying second information for indicating the root bridge to which the target high-speed peripheral component interconnect device belongs and third information for indicating the address of the target high-speed peripheral component interconnect device to the baseboard management controller, the BMC can trigger an OOR alarm event carrying information for indicating the root bridge to which the target high-speed peripheral component interconnect device belongs and the address information for the target high-speed peripheral component interconnect device, so that the administrator can quickly determine which type of PCIe device triggered the high-speed peripheral component interconnect bus resource shortage problem and the specific location of the problem device, which can make it easier for the server administrator to quickly locate and solve the high-speed peripheral component interconnect bus resource shortage problem, shortening the troubleshooting time. In addition, timely and accurate alarm information helps the server administrator take measures more promptly, including adjusting the allocation of high-speed peripheral component interconnect bus resources and / or increasing high-speed peripheral component interconnect bus resources, etc., which can avoid PCIe device or even server failure or server system crash caused by insufficient resources, and improve the stability and reliability of the server system.

[0127] In some embodiments of the present application, the basic input and output system chip 210 is further configured to, when the type of the target high-speed peripheral component interconnect device is the first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device does not exceed the upper limit of the number of bus numbers reserved for the first target type, continue to execute the operation of allocating a bus number of the high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device until the high-speed peripheral component interconnect bus resource demand of the target high-speed peripheral component interconnect device is met.

[0128] In actual execution, when the type of the target PCI Express device is the first target type, the BIOS chip 210 may check whether the number of PCIe Bus numbers allocated to the target PCI Express device is greater than the reserved value.

[0129] If the number of PCIe Bus bus numbers allocated to the target high-speed peripheral component interconnect device is less than the upper limit of the number of PCIe Bus bus numbers reserved for the first target type, it indicates that current high-speed peripheral component interconnect bus resources can meet the needs of the target high-speed peripheral component interconnect device and there is no temporary shortage of high-speed peripheral component interconnect bus resources. The BIOS chip may continue to execute the operation of allocating PCIe Bus bus numbers to the target high-speed peripheral component interconnect device until the high-speed peripheral component interconnect bus resource needs of the target high-speed peripheral component interconnect device are met or the number of PCIe Bus bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of PCIe Bus bus numbers reserved for the first target type.

[0130] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is the first target type, it is determined whether the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type; when the number of bus numbers not allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type, the high-speed peripheral component interconnect bus resources are continued to be allocated to the target high-speed peripheral component interconnect device, and a differentiated high-speed peripheral component interconnect bus resource allocation strategy is adopted to set different high-speed peripheral component interconnect bus resources according to different types of enumerated PCIe devices. The invention sets a source upper limit, realizes the reservation of high-speed peripheral component interconnect bus resources for high-performance dedicated PCIe devices and the reasonable allocation of high-speed peripheral component interconnect bus resources for ordinary PCIe devices, and ensures the normal operation and performance of the PCIe devices of the first target type by reserving exclusive high-speed peripheral component interconnect bus resources for the PCIe devices of the first target type, avoids the limitation of device functions due to unreasonable resource allocation, and restricts the high-speed peripheral component interconnect bus resources for the PCIe devices of the second target type based on the root bridge, reasonably utilizes the high-speed peripheral component interconnect bus resources of each root bridge, reduces the waste and shortage of high-speed peripheral component interconnect bus resources, makes the allocation of high-speed peripheral component interconnect bus resources more reasonable, and can improve the utilization efficiency of high-speed peripheral component interconnect bus resources.

[0131] In some embodiments of the present application, the basic input and output system chip 210 is further configured to, when the type of the target high-speed peripheral component interconnect device is the second target type and the number of bus numbers allocated by the target root bridge does not exceed the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs, continue to execute the operation of allocating a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device until the enumeration of the target high-speed peripheral component interconnect device is completed.

[0132] In actual execution, when the type of the target high-speed peripheral component interconnect device is the second target type, the basic input and output system chip 210 can check whether the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers of the PCIe Bus corresponding to the root bridge.

[0133] If the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs does not exceed the upper limit of the number of PCIe Bus bus numbers corresponding to the root bridge, it means that the current high-speed peripheral component interconnect bus resources can meet the needs of the target high-speed peripheral component interconnect device and there is no temporary shortage of high-speed peripheral component interconnect bus resources. The BIOS chip can continue to execute the operation of allocating PCIe Bus bus numbers to the target high-speed peripheral component interconnect device until the enumeration of the target high-speed peripheral component interconnect device is completed.

[0134] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is the second target type, it is determined whether the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs; when the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs does not exceed the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs, the high-speed peripheral component interconnect bus resources are continued to be allocated to the target high-speed peripheral component interconnect device, and differentiated high-speed peripheral component interconnect bus resource allocation strategies are adopted to set respectively according to different types of enumerated PCIe devices. Different high-speed peripheral component interconnect bus resource upper limits are used to reserve high-speed peripheral component interconnect bus resources for high-performance dedicated PCIe devices and reasonably allocate high-speed peripheral component interconnect bus resources for ordinary PCIe devices. By reserving exclusive high-speed peripheral component interconnect bus resources for PCIe devices of the first target type, the normal operation and performance of PCIe devices of the first target type are ensured, and the device function is avoided from being restricted due to unreasonable resource allocation. The high-speed peripheral component interconnect bus resources of PCIe devices of the second target type are restricted based on the root bridge, and the high-speed peripheral component interconnect bus resources of each root bridge are reasonably utilized, thereby reducing the waste and shortage of high-speed peripheral component interconnect bus resources. The allocation of high-speed peripheral component interconnect bus resources is more reasonable, and the utilization efficiency of high-speed peripheral component interconnect bus resources can be improved.

[0135] In some embodiments of the present application, the generating module is specifically configured to generate target alarm information in a format of an original equipment manufacturer command that complies with the intelligent platform management interface standard.

[0136] In actual implementation, the generation module in the BIOS chip sends the target alarm information to the BMC of the same server, and the format of the original equipment manufacturer (OEM) command (IPMI OEM command) that complies with the Intelligent Platform Management Interface (IPMI) standard can be used.

[0137] In some embodiments, the interaction between the BIOS chip and the BMC in the same server can be performed using the above-mentioned IPMI OEM command, and thus the target alarm information sent by the BIOS chip to the BMC is also an IPMI OEM command.

[0138] In some embodiments, the format of the IPMI OEM command may be as shown in Table 1.

[0139] Table 1 IPMI OEM command format

[0140]

[0141] Among them, the field NETFN represents the network function number, and its exemplary value is 0x3D (which may not be limited to this value); the field CMD represents the command number, and its exemplary value is 0x00 (which may not be limited to this value); the field Data1 represents data 1, which is used to distinguish between setting data (SetData, the corresponding exemplary value is 0x00, but may not be limited to this value) or getting data (GetData, the corresponding exemplary value is 0x01, but may not be limited to this value); the field Data2 represents data 2, which is used to distinguish the event type, for example, the exemplary value corresponding to OOR is 0x00, but may not be limited to this value; the field Data3 represents data 3, which is used to distinguish the type of PCIe device that triggers the alarm, for example, the exemplary value corresponding to DPU is 0x00, and the exemplary value corresponding to ordinary PCIe device is 0x01, but may not be limited to the above two types or values); fields Data4 to Data7 can respectively carry information such as the Root Bridge number, Bus number, Device number, Function number, etc.

[0142] In some embodiments, based on the format of the IPMI OEM command shown in Table 1, the content of the target alarm information triggered by a target high-speed peripheral component interconnect device of the first target type may include the bus number of the first-level upstream bridge of the target high-speed peripheral component interconnect device, the number of the root bridge to which the target high-speed peripheral component interconnect device belongs, and the BDF information (Bus, Device, Function) of the target high-speed peripheral component interconnect device, corresponding to the above-mentioned fields Data4 to Data7; the content of the target alarm information triggered by a target high-speed peripheral component interconnect device of the second target type may include the bus number of the target high-speed peripheral component interconnect device, the number of the root bridge to which the target high-speed peripheral component interconnect device belongs, and the BDF information (Bus, Device, Function) of the target high-speed peripheral component interconnect device, corresponding to the above-mentioned fields Data4 to Data7.

[0143] In some embodiments, the type of the target Peripheral Component Interconnect Express device that triggers the target alarm information may be acquired according to the content of the target alarm information.

[0144] For example, when the target alarm information adopts the format shown in Table 1, it can be determined whether the target alarm information is triggered by a device of the first target type (such as a DPU device, etc.) or a device of the second target type (such as an ordinary PCIe device, etc.) based on the value of the field Data3 being 0x00 or 0x01.

[0145] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiments of the present application, target alarm information is transmitted to the BMC via an original equipment manufacturer command format that complies with the Intelligent Platform Management Interface standard. The BMC can trigger an OOR alarm event that carries information indicating the type of the target high-speed peripheral component interconnect device, information indicating the root bridge to which the target high-speed peripheral component interconnect device belongs, and address information for the target high-speed peripheral component interconnect device. This makes it easier for server administrators to quickly locate and resolve the problem of insufficient high-speed peripheral component interconnect bus resources. In addition, the use of standardized interfaces and management, and the use of IPMI OEM commands for information exchange between the BIOS chip and the BMC, complies with the Intelligent Platform Management Interface standard, facilitates integration with other system management tools, and can help achieve unified management and monitoring of server hardware resources.

[0146] In some embodiments of the present application, the first target type includes a data processing unit.

[0147] In actual implementation, the first target type may include a DPU. Compared to common PCIe devices, a DPU offers advantages such as higher performance and specialized functionality. Furthermore, a certain amount of high-speed peripheral component interconnect bus resources typically need to be reserved to ensure the normal operation and performance of the DPU. If the first target type includes a DPU, the necessary high-speed peripheral component interconnect bus resources can be reserved for the DPU, thereby ensuring the normal operation and performance of the DPU and preventing performance limitations or failure to start the DPU properly, which could impact the overall functionality of the server.

[0148] The computing power of a DPU surpasses that of a central processing unit (CPU) and a graphics processing unit (GPU). Data center servers utilize DPUs extensively, efficiently handling large-scale data workloads within the data center, including data transmission, protocol, protection, compression, analysis, and encryption. Therefore, compared to other types of PCIe devices, the allocation of high-speed peripheral component interconnect bus resources is even more crucial for DPUs.

[0149] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is a DPU, it is determined whether the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the DPU. When the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the DPU, a target alarm information is sent to the baseboard management controller of the server to trigger a resource shortage alarm. A differentiated high-speed peripheral component interconnect bus resource allocation strategy is adopted, and different high-speed peripheral component interconnect bus resource upper limits are set according to different types of enumerated PCIe devices. This achieves reasonable allocation of high-speed peripheral component interconnect bus resources reserved for the DPU and high-speed peripheral component interconnect bus resources for ordinary PCIe devices. The allocation of high-speed peripheral component interconnect bus resources is more reasonable, and the utilization efficiency of high-speed peripheral component interconnect bus resources can be improved.

[0150] In order to facilitate the understanding of the above embodiments, Figure 4 , describes an implementation process of a method for allocating high-speed peripheral component interconnect bus resources. The BIOS chip can perform PCIe device enumeration during the BIOS startup process, and execute the following for each new PCIe device: Figure 4 The process shown. Figure 4 This is a second schematic diagram of the operation flow of a high-speed peripheral component interconnect bus resource allocation system provided in an embodiment of the present application. Figure 4 As shown, the allocation of high-speed peripheral component interconnect bus resources may include the following steps: wherein the first target type and the second target type are respectively exemplified by DPU and ordinary PCIe device.

[0151] Step 410: Enumerate new devices.

[0152] When the BIOS chip detects that a new PCIe device is connected to the server, it starts to enumerate the PCIe device.

[0153] Step 420: Allocate a bus number.

[0154] The BIOS chip attempts to assign a PCIe Bus number to the PCIe device and records the root bridge information to which the PCIe device belongs.

[0155] Step 430: Determine whether it is the first target type.

[0156] To determine the type of the PCIe device, the PCIe device identification information (e.g., the PCIe device ID and / or manufacturer ID) may be used to determine whether the PCIe device is a DPU device. If so, step 340 may be executed; if not, step 360 may be executed.

[0157] Step 440: Determine whether the number of allocated bus numbers is greater than the reserved value.

[0158] If the PCIe device is a DPU, check whether the number of PCIe Bus numbers allocated to the DPU exceeds the reserved value. The BIOS can maintain an upper limit on the number of PCIe Bus numbers reserved for DPUs (this value can be determined by BIOS configuration or default settings and is a reserved limit or value). Obtain the number of PCIe Bus numbers currently allocated to the DPU and compare it with the reserved value.

[0159] If the number of allocated PCIe Bus numbers has not exceeded the reserved value, the number of allocated PCIe Bus numbers for the DPU device continues to increase until the DPU device's high-speed peripheral component interconnect bus resource requirements are met or the number of allocated PCIe Bus numbers for the DPU device reaches the reserved value. If the number of allocated PCIe Bus numbers for the DPU device exceeds the reserved value, step 350 is executed.

[0160] Step 450: End the current root bridge bus resource allocation, and the first target type device triggers a resource shortage alarm.

[0161] Trigger the OOR alarm of the DPU device, end the high-speed peripheral component interconnect bus resource allocation process of the DPU device, no longer allocate the PCIe Bus number that exceeds the reserved value, end the high-speed peripheral component interconnect bus resource allocation of the current Root Bridge, and record the Bus number of the first-level upstream Bridge of the DPU device and the information of the Root Bridge to which it belongs.

[0162] Step 460: Determine whether resources are insufficient.

[0163] If the PCIe device is not a DPU device, that is, it is a standard PCIe device, check whether the number of PCIe Bus numbers assigned to the current Root Bridge exceeds the upper limit of the number of PCIe Bus numbers corresponding to the current Root Bridge. The BIOS can preset an upper limit for the number of PCIe Bus numbers for each Root Bridge (this value can be determined based on the hardware specifications of the current Root Bridge and the server configuration, and serves as the preset upper limit). Obtain the number of PCIe Bus numbers assigned to the current Root Bridge and compare it with the preset upper limit.

[0164] If the number of PCIe Buses does not exceed the preset upper limit, the number of PCIe Buses is continuously allocated to the common PCIe device until the enumeration of the common PCIe device is completed. If the number of PCIe Buses exceeds the preset upper limit, step 370 is executed.

[0165] Step 470: End the current root bridge bus resource allocation, and the second target type device triggers a resource shortage alarm.

[0166] If the preset upper limit is exceeded, the OOR alarm of the ordinary PCIe device in the Root Bridge is triggered, the Bus number allocation process of the PCIe Bus of the Root Bridge is terminated, and the Bus number of the PCIe Bus of the ordinary PCIe device and the information of the Root Bridge to which the ordinary PCIe device belongs are recorded.

[0167] Step 480: Determine whether all root bridges have been enumerated.

[0168] Determine whether all Root Bridges of the server have been enumerated. If there are any Root Bridges that have not been enumerated, return to step 310 and continue processing the PCIe device in the next Root Bridge.

[0169] Step 490, end.

[0170] If the enumeration of all Root Bridges is completed, the entire process of allocating high-speed peripheral component interconnect bus resources is ended.

[0171] In some embodiments of the present application, the baseboard management controller 220 includes: an acquisition module and an alarm module.

[0172] The acquisition module is used to obtain the first information carried by the target warning information.

[0173] In actual implementation, after the BMC receives the target alarm information, the acquisition module can obtain the first information carried in the target alarm information by parsing the target alarm information, etc. After obtaining the first information, the type of the target high-speed peripheral component interconnect device can be obtained based on the indication of the first information. The target high-speed peripheral component interconnect device is the PCIe device that triggered the target alarm information.

[0174] The alarm module is used to trigger an alarm event of a level corresponding to the type of the target high-speed peripheral component interconnect device of the target alarm information.

[0175] In actual implementation, after the BMC obtains the type of the target high-speed peripheral component interconnect device, the alarm module may generate an alarm event of a level corresponding to the type, so as to implement hierarchical processing of the target alarm information.

[0176] It is understandable that the types of PCIe devices that trigger target alarm information are different, and the levels of the alarm events triggered by the BMC are different.

[0177] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, an alarm event of a level corresponding to the type of the target high-speed peripheral component interconnect device of the target alarm information is triggered based on the first information carried by the target alarm information. The type information of the PCIe device is included in the alarm content, so it can quickly determine which type of high-speed peripheral component interconnect device has the problem of insufficient high-speed peripheral component interconnect bus resources, which can make it easier for server administrators to quickly locate and solve the problem of insufficient high-speed peripheral component interconnect bus resources.

[0178] In some embodiments of the present application, the alarm module is specifically used to: trigger a first level alarm event when the first information indicates that the type of the target high-speed peripheral component interconnect device is a first target type; trigger a second level alarm event when the first information indicates that the type of the target high-speed peripheral component interconnect device is a second target type; the first level is higher than the second level.

[0179] In actual implementation, after obtaining the first information carried in the target alarm information, if the first information indicates that the type of the target high-speed peripheral component interconnect device is the first target type, the BMC's alarm module may trigger a first-level alarm event; if the first information indicates that the type of the target high-speed peripheral component interconnect device is the second target type, the BMC's alarm module may trigger a second-level alarm event. The first level is higher than the second level, and the first-level alarm event is a more serious alarm event than the second-level alarm event. The priority of handling the first-level alarm event is higher than the priority of handling the second-level alarm event.

[0180] In some embodiments, a first-level alarm event, which can be a critical or key level, is assigned to a target high-speed peripheral component interconnect device of a first target type, such as a DPU. A second-level alarm event, which can be an information level (Info or Information), is assigned to a target high-speed peripheral component interconnect device of a second target type, such as a common PCIe device. It is understood that a critical level (or key level) is higher than an information level, indicating a higher degree of severity.

[0181] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, by triggering a first-level alarm event when the type of the target high-speed peripheral component interconnect device is a first target type, and triggering a second-level alarm event lower than the first level when the type of the target high-speed peripheral component interconnect device is a second target type, it can effectively distinguish and hierarchically handle high-speed peripheral component interconnect bus resource shortage alarms triggered by different types of high-speed peripheral component interconnect devices. Server administrators can more quickly and accurately locate the problem of high-speed peripheral component interconnect bus resource shortage, thereby improving the efficiency of server maintenance and management.

[0182] In some embodiments of the present application, the first level alarm event is not resolved if the server is not reconfigured and hardware adjustments are not performed.

[0183] In actual implementation, if the server has not been reconfigured and hardware adjustments have not been made, a triggered Level 1 alarm event cannot be dismissed. It should be noted that the triggering of a Level 1 alarm event indicates that the server's first target type of high-speed peripheral component interconnect device may be experiencing performance limitations or failure to start properly, and even restarting the host bridge cannot resolve these issues. Therefore, if the server has not been reconfigured and hardware adjustments have not been made, the Level 1 alarm event will not be dismissed to ensure that the issue of insufficient high-speed peripheral component interconnect bus resources for the first target type of high-speed peripheral component interconnect device is resolved by the server administrator.

[0184] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiments of the present application, by not releasing first-level alarm events even when the server has not been reconfigured or hardware adjustments have been made, server administrators can still be notified of first-level alarm events even in situations such as restarting the host bridge, thereby improving the timeliness and completeness of first-level alarm event resolution by server administrators. Furthermore, by setting different event triggering and release mechanisms based on the type of high-speed peripheral component interconnect device, the timeliness and completion rate of alarm events caused by insufficient high-speed peripheral component interconnect bus resources can be improved.

[0185] In some embodiments of the present application, the second level alarm event is resolved when the host bridge is restarted.

[0186] In actual implementation, the situation of insufficient high-speed peripheral component interconnect bus resources of the second target type of high-speed peripheral component interconnect device can be solved by restarting the host bridge, etc., so that the triggered second level alarm event can be automatically released when the host bridge is restarted.

[0187] The high-speed peripheral component interconnect bus alarm distribution system provided by the embodiments of the present application improves the efficiency and timeliness of resolving and handling high-speed peripheral component interconnect bus resource shortage alarms by automatically resolving triggered second-level alarm events when the server restarts the host bridge. Furthermore, by setting different event triggering and resolving mechanisms based on the type of high-speed peripheral component interconnect device, the timeliness and completion rate of alarm events caused by high-speed peripheral component interconnect bus resource shortages can be improved.

[0188] In some embodiments of the present application, the alarm module is specifically configured to update the state of the first sensor to a first target state so that the first sensor triggers a first level alarm event; the first sensor corresponds to the first target type.

[0189] In actual implementation, the BMC alarm module can trigger alarm events of different levels through different sensors.

[0190] In some embodiments, the BMC may use two sensors to distinguish between Peripheral Component Interconnect High-Speed ​​bus resource insufficient alarms triggered by Peripheral Component Interconnect High-Speed ​​devices of a first target type and a second target type.

[0191] In some embodiments, the parameters of the two sensors may be as shown in Table 2.

[0192] Table 2 Sensor setting table

[0193]

[0194] Among them, Sensor name is the name of the sensor, the first target type and the second target type take DPU and ordinary PCIe device as examples respectively, and the names of the two sensors can be DPU_OOR_Error and PCIE_OOR_Error respectively; EventType is the event type, and the exemplary value is 0x00 (which may not be limited to this value); Sensor type is the type of sensor, such as Event only shown in Table 2, but it may not be limited to this type; offset is the offset value used to indicate the state of the sensor, and the exemplary value 00 indicates the resource does not exceed the limit (Limit Not Exceeded) state, and 01 indicates the resource exceeds the limit (Limit Exceeded) state, but it may not be limited to the above two states, nor is it limited to the above two values; Trigger Release indicates the triggering and releasing settings of the alarm event triggered by the sensor.

[0195] In some embodiments, the first sensor may correspond to a first target type. When the BMC needs to trigger a first level alarm event, the alarm module may update the state of the first sensor to a first target state; when the state of the first sensor is the first target state, the first sensor may trigger a first level alarm event.

[0196] In some embodiments, updating the state of a first sensor to a first target state may include modifying the offset value of the first sensor to a value corresponding to the first target state. For example, if the target alarm information is triggered by a DPU device (assuming the first target type is DPU), the sensor named DPU_OOR_Error in Table 2 is the first sensor. The offset value of this sensor can be modified to 01, and the state of the first sensor can be updated to the first target state. The first target state of the first sensor is the Limit Exceeded state, indicating that a resource shortage event has been triggered. Once triggered, this event will not be resolved until the server is reconfigured or the hardware is adjusted. It is understood that the above-mentioned resource shortage event is a first-level alarm event.

[0197] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, by updating the state of the first sensor to the first target state, the first sensor triggers a first-level alarm event when its own state is the first target state, and can distinguish between high-speed peripheral component interconnect bus resource shortage alarms triggered by high-speed peripheral component interconnect devices of the first target type and the second target type, thereby effectively distinguishing and hierarchically processing high-speed peripheral component interconnect bus resource shortage alarms triggered by different types of high-speed peripheral component interconnect devices. Server administrators can more quickly and accurately locate the problem of high-speed peripheral component interconnect bus resource shortage, which can improve the efficiency of server maintenance and management.

[0198] In some embodiments of the present application, the alarm module is specifically configured to update the state of the second sensor to a second target state so that the second sensor triggers a second level alarm event; the second sensor corresponds to the second target type.

[0199] In actual implementation, the second sensor may correspond to the second target type. When the BMC needs to trigger a second-level alarm event, the alarm module may update the state of the second sensor to the second target state; when the state of the second sensor is the second target state, the second sensor may trigger a second-level alarm event.

[0200] In some embodiments, updating the state of the second sensor to the second target state may include modifying the offset value of the second sensor to a value corresponding to the second target state. For example, if the target alarm information is triggered by a standard PCIe device (assuming the second target type is a standard PCIe device), the sensor named PCIE_OOR_Error in Table 2 is the second sensor. The offset value of this sensor can be modified to 01, and the state of the second sensor can be updated to the second target state. The second target state of the second sensor is the Limit Exceeded state, indicating that a resource shortage event has been triggered. This event is automatically resolved upon a Host Bridge restart because the allocation of resources, such as the high-speed peripheral component interconnect bus resources of a standard PCIe device, can be readjusted after a Host Bridge restart. It is understood that this resource shortage event is a second-level alarm event.

[0201] According to the high-speed peripheral component interconnect bus resource allocation system provided in the embodiment of the present application, by updating the state of the second sensor to the second target state, the second sensor triggers a second-level alarm event when its own state is the second target state, and can distinguish between high-speed peripheral component interconnect bus resource shortage alarms triggered by high-speed peripheral component interconnect devices of the first target type and the second target type, thereby effectively distinguishing and hierarchically processing high-speed peripheral component interconnect bus resource shortage alarms triggered by different types of high-speed peripheral component interconnect devices. Server administrators can more quickly and accurately locate the problem of high-speed peripheral component interconnect bus resource shortage, and improve the efficiency of server maintenance and management.

[0202] In some embodiments of the present application, the acquisition module is further used to acquire the second information and the third information carried by the target warning information.

[0203] In actual execution, after receiving the target alarm information, the BMC may also obtain the second information and the third information carried in the target alarm information by parsing the target alarm information and other methods.

[0204] The baseboard management controller 220 further includes a log module configured to generate a system event log based on the first information, the second information, the third information, and the status of the alarm event.

[0205] In actual execution, after the BMC triggers an alarm event of a level corresponding to the type of the target high-speed peripheral component interconnect device of the target alarm information, the log module may further generate a system event log.

[0206] In some embodiments, the logging module can generate a corresponding system event log based on the sensor name and the target PCI Express device information. The system event log can include the target PCI Express device type, root bridge number, BDF information, and the status of the triggered alarm event (e.g., triggered or cleared).

[0207] For example, taking the sensors shown in Table 2 as an example, the content of the system event log of the first sensor DPU_OOR_Error may include: “DPU_OOR_Error Limit Exceeded DPU bus resource exceeded the limit, Root Bridge: xx, Device: xx-xx-xx -Assert”.

[0208] For another example, taking the sensor shown in Table 2 as an example, the system event log of the second sensor PCIE_OOR_Error can be divided into a trigger log and a release log; the content of the trigger log may include: "PCIE_OOR_Error LimitExceeded PCIe bus out of resource, Root Bridge: xx, Device:xx-xx-xx -Assert"; the content of the release log may include: "PCIE_OOR_Error LimitNotExceeded PCIe bus out ofresource, Root Bridge: xx, Device:xx-xx-xx -Deassert".

[0209] According to the high-speed peripheral component interconnect bus resource allocation system provided by the embodiment of the present application, by generating a system event log based on the first information indicating the type of the target high-speed peripheral component interconnect device, the second information indicating the root bridge to which the target high-speed peripheral component interconnect device belongs, the third information indicating the address of the target high-speed peripheral component interconnect device, and the status of the alarm event, the system event log can be more accurately and detailedly recorded. The relevant information of the triggered alarm event of insufficient high-speed peripheral component interconnect bus resources is more helpful for subsequent tracing and summarizing, thereby improving the efficiency of subsequent server maintenance and management. In addition, by including detailed identification information of the target high-speed peripheral component interconnect device, such as the first information, the second information, and the third information, in the content of the alarm information, it is easier for server administrators to quickly locate and resolve the problem of insufficient high-speed peripheral component interconnect bus resources.

[0210] An embodiment of the present application further provides a high-speed peripheral component interconnect bus resource allocation method, which is applied to any of the above-mentioned high-speed peripheral component interconnect bus resource allocation systems. Figure 5 The flowchart of a high-speed peripheral component interconnect bus resource allocation method provided in the embodiment of the present application is as follows. Figure 5 As shown, the method includes: step 510, step 520 and step 530.

[0211] Step 510: The BIOS chip allocates a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device during the process of the BIOS enumerating the target high-speed peripheral component interconnect device of the server; obtains the type of the target high-speed peripheral component interconnect device; and sends a target alarm message to the baseboard management controller if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type. The target alarm message is used to indicate insufficient high-speed peripheral component interconnect bus resources.

[0212] Step 520: The baseboard management controller receives the target alarm information and processes the target alarm information based on the type of the target high-speed peripheral component interconnect device that triggers the target alarm information to trigger a restart of the basic input and output system.

[0213] Step 530: After the BIOS is restarted, if the type of the target high-speed peripheral component interconnect device is the first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type, the BIOS chip re-allocates a bus number of the high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device based on the target high-speed peripheral component interconnect bus resources.

[0214] For the description of the features in the embodiment corresponding to the high-speed peripheral component interconnect bus resource allocation method, reference can be made to the relevant description of the embodiment corresponding to the high-speed peripheral component interconnect bus resource allocation system, which will not be repeated here.

[0215] According to the high-speed peripheral component interconnect bus resource allocation method provided by the embodiment of the present application, by identifying the type of the target high-speed peripheral component interconnect device, when it is determined that the type of the target high-speed peripheral component interconnect device is the first target type, it is determined whether the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type. When the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type, a target alarm message is sent to the baseboard management controller of the server to trigger a resource shortage alarm, and the high-speed peripheral component interconnect bus resources are secondary allocated. A differentiated high-speed peripheral component interconnect bus resource allocation strategy is adopted, and different high-speed peripheral component interconnect bus resource upper limits are set according to different types of enumerated PCIe devices, so as to achieve The reservation of high-speed peripheral component interconnect bus resources for high-performance dedicated PCIe devices and the reasonable allocation and secondary allocation of high-speed peripheral component interconnect bus resources for ordinary PCIe devices can more promptly and efficiently resolve the alarm of insufficient high-speed peripheral component interconnect bus resources. By reserving exclusive high-speed peripheral component interconnect bus resources for PCIe devices of the first target type, the normal operation and performance of PCIe devices of the first target type are ensured, and the device function is avoided from being restricted due to unreasonable resource allocation. The high-speed peripheral component interconnect bus resources of PCIe devices of the second target type are restricted based on the root bridge, and the high-speed peripheral component interconnect bus resources of each root bridge are reasonably utilized, thereby reducing the waste and shortage of high-speed peripheral component interconnect bus resources. The allocation of high-speed peripheral component interconnect bus resources is more reasonable, and the utilization efficiency of high-speed peripheral component interconnect bus resources can be improved.

[0216] Furthermore, by triggering different levels of alarm information according to the type of the target high-speed peripheral component interconnect device that triggers the target alarm information, the baseboard management controller processes the target alarm information based on the type of the target high-speed peripheral component interconnect device that triggers the target alarm information, and can quickly determine which type of high-speed peripheral component interconnect device has the problem of insufficient high-speed peripheral component interconnect bus resources, which can make it easier for server managers to quickly locate and solve the problem of insufficient high-speed peripheral component interconnect bus resources.

[0217] In some embodiments, the method may further include: in memory resource management scenarios, for critical applications requiring large amounts of memory resources (such as artificial intelligence computing modules), a certain memory resource usage limit may be reserved for third-target type applications as a limit. When the memory requirements of third-target type applications exceed this limit, a high-priority alarm is triggered. For ordinary applications not targeting the third-target type, a memory resource usage limit is set based on the processor node or process group to which they belong. If this limit is exceeded, a low-priority alarm is triggered. Through similar hierarchical alarm and resource allocation strategies, refined management of memory resources is achieved.

[0218] In some embodiments, CPU core resource management involves reserving a specific number of CPU cores for tasks of the fourth target type with high real-time requirements (such as industrial control tasks). If the number of cores required by a task of the fourth target type exceeds the reserved number, a high-priority alarm (e.g., a Critical-level alarm) is triggered. For ordinary tasks not of the fourth target type (e.g., background tasks), a core usage cap is set based on processor sockets or core groupings. If the core usage cap is exceeded, a low-priority alarm (e.g., an Info-level alarm) is triggered. This mechanism can improve CPU resource utilization efficiency and ensure the stable operation of critical tasks.

[0219] The core ideas of the above-mentioned embodiments of this application (including differentiated resource allocation, hierarchical alarms and detailed information transmission, etc.) can be applied to other hardware resource management fields to form a universal hardware resource management and alarm system that is suitable for various complex computing environments and has broad application prospects and promotion value.

[0220] In some embodiments of the present application, triggering an alarm event of a level corresponding to the type of the target high-speed peripheral component interconnect device of the target alarm information includes: triggering an alarm event on a corresponding page and / or target device of a baseboard management controller.

[0221] In actual implementation, corresponding alarm events may be triggered on a corresponding page of the baseboard management controller and / or a target device through sensors and the like.

[0222] It should be noted that the BMC, as a management unit of the server, has a page to implement various management functions. This page is the BMC page. The BMC can also communicate with electronic devices.

[0223] In some embodiments, an alarm event of a level corresponding to the type of the target Peripheral Component Interconnect Express device of the target alarm information may be triggered on a BMC page.

[0224] In some embodiments, an alarm event of a level corresponding to the type of the target high-speed peripheral component interconnect device of target alarm information can be triggered on a target device in communication with the BMC. The target device is an electronic device, which may include at least one of a computer and a terminal used by a server administrator.

[0225] In some embodiments, the parameters of the alarm event may include the aforementioned first information. Based on the parameters of the alarm event displayed on the BMC page and / or on the target device, the server administrator can obtain information about the type of the target high-speed peripheral component interconnect device, thereby more quickly locating the specific type of high-speed peripheral component interconnect device, thereby improving the efficiency of locating the target high-speed peripheral component interconnect device.

[0226] In some embodiments, in addition to the aforementioned first information, the parameters of the alarm event may also include second information and third information. Based on the parameters of the alarm event displayed on the BMC page and / or on the target device, the server administrator can obtain information about the type of the target high-speed peripheral component interconnect device, as well as information about the root bridge to which the target high-speed peripheral component interconnect device belongs, as well as address information such as the bus number, device number, and function number of the target high-speed peripheral component interconnect device. This allows the server administrator to locate the target high-speed peripheral component interconnect device more quickly than by first locating a specific type of high-speed peripheral component interconnect device, thereby improving the efficiency of locating the target high-speed peripheral component interconnect device.

[0227] It should be noted that in the related art, the alarm information for high-speed peripheral component interconnect bus resources is only used to indicate that the high-speed peripheral component interconnect bus resources are insufficient, and does not include more information, such as various identification information of the high-speed peripheral component interconnect device that triggered the high-speed peripheral component interconnect bus resource shortage alarm. The BMC cannot distinguish the high-speed peripheral component interconnect device that triggered the high-speed peripheral component interconnect bus resource shortage alarm, and therefore there is no need to trigger different alarm events. In the embodiments of the present application, however, by including various identification information of the high-speed peripheral component interconnect device that triggered the high-speed peripheral component interconnect bus resource shortage alarm in the alarm information, the BMC can distinguish the high-speed peripheral component interconnect device that triggered the high-speed peripheral component interconnect bus resource shortage alarm, thereby enabling hierarchical processing, improving efficiency and targeted processing of alarms.

[0228] According to the high-speed peripheral component interconnect bus resource alarm method provided in the embodiment of the present application, by triggering an alarm event on the page and / or target device corresponding to the baseboard management controller, the server administrator can obtain alarm information more promptly, thereby being able to handle the problem of insufficient high-speed peripheral component interconnect bus resources more promptly.

[0229] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0230] An embodiment of the present application also provides a server. Figure 6 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. Figure 6 As shown, the server 600 may include any of the above-mentioned high-speed peripheral component interconnect bus resource allocation systems 200 .

[0231] For the description of the features in the embodiment corresponding to the server 600, reference can be made to the relevant description of the embodiment corresponding to the high-speed peripheral component interconnect bus resource allocation system, which will not be repeated here.

[0232] An embodiment of the present application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned embodiments of the high-speed peripheral component interconnect bus resource allocation method or the steps in any of the above-mentioned embodiments of the high-speed peripheral component interconnect bus resource allocation method.

[0233] An embodiment of the present application also provides a non-transitory computer-readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps of any one of the above-mentioned high-speed peripheral component interconnect bus resource allocation method embodiments or the steps of any one of the above-mentioned high-speed peripheral component interconnect bus resource allocation method embodiments when running.

[0234] In an exemplary embodiment, the above-mentioned non-transitory computer-readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0235] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned high-speed peripheral component interconnect bus resource allocation method embodiments or the steps in any of the above-mentioned high-speed peripheral component interconnect bus resource allocation method embodiments.

[0236] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps in any of the above-mentioned high-speed peripheral component interconnect bus resource allocation method embodiments or the steps in any of the above-mentioned high-speed peripheral component interconnect bus resource allocation method embodiments.

[0237] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0238] The above describes in detail a high-speed peripheral component interconnect bus resource allocation system and method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core concept of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, various improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A high-speed peripheral component interconnect bus resource allocation system, characterized in that: include: Basic input and output system chips and baseboard management controllers; The basic input and output system chip is used to perform an operation of allocating a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device during the process of the basic input and output system enumerating the target high-speed peripheral component interconnect device of the server; Obtaining a type of the target high-speed peripheral component interconnect device; and sending target alarm information to the baseboard management controller if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds an upper limit of the number of bus numbers reserved for the first target type; The target alarm information is used to indicate insufficient resources of a high-speed peripheral component interconnect bus; The baseboard management controller is configured to receive the target alarm information and process the target alarm information based on the type of the target high-speed peripheral component interconnect device that triggers the target alarm information to trigger a restart of the basic input and output system; The basic input / output system chip is further configured to, after the basic input / output system is restarted, re-allocate a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device based on target high-speed peripheral component interconnect bus resources if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers already allocated to the target high-speed peripheral component interconnect device exceeds an upper limit of the number of bus numbers reserved for the first target type.

2. The high-speed peripheral component interconnect bus resource allocation system according to claim 1, characterized in that: The basic input / output system chip is specifically configured to release the bus number of an allocated and unused high-speed peripheral component interconnect bus of other high-speed peripheral component interconnect devices of the first target type under a target root bridge, and allocate the bus number to the target high-speed peripheral component interconnect device; the target root bridge is the root bridge to which the target high-speed peripheral component interconnect device belongs.

3. The high-speed peripheral component interconnect bus resource allocation system according to claim 2, characterized in that: The basic input / output system chip is specifically configured to allocate, to the target high-speed peripheral component interconnect device, a bus number of a high-speed peripheral component interconnect bus that is released by reducing the upper limit of the number of bus numbers of high-speed peripheral component interconnect devices other than the first target type under the target root bridge, when there are no or insufficient bus numbers of the high-speed peripheral component interconnect buses that have been allocated and are not in use by other high-speed peripheral component interconnect devices of the first target type under the target root bridge.

4. The high-speed peripheral component interconnect bus resource allocation system according to claim 3, characterized in that: The basic input / output system chip is specifically configured to allocate, to the target high-speed peripheral component interconnect device, the bus numbers of the remaining high-speed peripheral component interconnect buses under other root bridges when the bus numbers of the high-speed peripheral component interconnect buses released by reducing the upper limit of the number of bus numbers of the high-speed peripheral component interconnect devices of the non-first target type under the target root bridge are insufficient.

5. The high-speed peripheral component interconnect bus resource allocation system according to any one of claims 1 to 4, characterized in that: The basic input / output system chip is further configured to send the target alarm information to the baseboard management controller when the type of the target high-speed peripheral component interconnect device is the second target type and the number of bus numbers allocated to the root bridge to which the target high-speed peripheral component interconnect device belongs exceeds an upper limit on the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs.

6. The high-speed peripheral component interconnect bus resource allocation system according to any one of claims 1 to 4, characterized in that: The basic input and output system chip includes: A generating module, configured to generate the target alarm information; the target alarm information carries first information; the first information is used to indicate the type of the target high-speed peripheral component interconnect device; A sending module is used to send the target alarm information to the baseboard management controller.

7. The high-speed peripheral component interconnect bus resource allocation system according to claim 6, characterized in that: The target alarm information carries second information and third information; the second information is used to indicate the root bridge to which the target high-speed peripheral component interconnection device belongs; the third information is used to indicate the address of the target high-speed peripheral component interconnection device; the address includes a bus number, a device number and a function number.

8. The high-speed peripheral component interconnect bus resource allocation system according to any one of claims 1 to 4, characterized in that: The basic input / output system chip is further configured to, if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device does not exceed the upper limit of the number of bus numbers reserved for the first target type, continue to execute the operation of allocating a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device until a high-speed peripheral component interconnect bus resource demand of the target high-speed peripheral component interconnect device is met.

9. The high-speed peripheral component interconnect bus resource allocation system according to claim 5, characterized in that: The basic input / output system chip is further configured to, if the type of the target high-speed peripheral component interconnect device is the second target type and the number of bus numbers allocated by the target root bridge does not exceed the upper limit of the number of bus numbers corresponding to the root bridge to which the target high-speed peripheral component interconnect device belongs, continue to execute the operation of allocating a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device until the enumeration of the target high-speed peripheral component interconnect device is completed.

10. The high-speed peripheral component interconnect bus resource allocation system according to claim 6, characterized in that: The generating module is specifically configured to generate the target alarm information in the format of an original equipment manufacturer command that complies with the intelligent platform management interface standard.

11. The high-speed peripheral component interconnect bus resource allocation system according to claim 1, characterized in that: The first target type includes data processing units.

12. The high-speed peripheral component interconnect bus resource allocation system according to claim 7, characterized in that: The baseboard management controller includes: an acquisition module, configured to acquire the first information carried by the target warning information; An alarm module is used to trigger an alarm event of a level corresponding to the type of the target high-speed peripheral component interconnect device of the target alarm information.

13. The high-speed peripheral component interconnect bus resource allocation system according to claim 12, characterized in that: The alarm module is specifically used to: triggering a first level alarm event when the first information indicates that the type of the target Peripheral Component Interconnect Express device is a first target type; triggering a second level alarm event when the first information indicates that the type of the target Peripheral Component Interconnect Express device is a second target type; The first level is higher than the second level.

14. The high-speed peripheral component interconnect bus resource allocation system according to claim 13, characterized in that: The first level alarm event is not resolved if the server is not reconfigured and hardware adjustment is not performed.

15. The high-speed peripheral component interconnect bus resource allocation system according to claim 13, characterized in that: The second-level alarm event is resolved when the host bridge is restarted.

16. The high-speed peripheral component interconnect bus resource allocation system according to claim 14, characterized in that: The alarm module is specifically configured to update the state of the first sensor to a first target state, so that the first sensor triggers an alarm event of the first level; the first sensor corresponds to the first target type.

17. The high-speed peripheral component interconnect bus resource allocation system according to claim 15, characterized in that: The alarm module is specifically configured to update the state of the second sensor to a second target state, so that the second sensor triggers an alarm event of the second level; the second sensor corresponds to the second target type.

18. The high-speed peripheral component interconnect bus resource allocation system according to any one of claims 12 to 17, characterized in that: The acquisition module is further configured to acquire the second information and the third information carried by the target warning information; The baseboard management controller further includes: The log module is used to generate a system event log based on the first information, the second information, the third information and the status of the alarm event.

19. A high-speed peripheral component interconnect bus resource allocation method, characterized in that: Applied to the high-speed peripheral component interconnect bus resource allocation system according to any one of claims 1 to 18, the method comprises: The basic input / output system chip performs an operation of allocating a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device of the server during the process of the basic input / output system enumerating the target high-speed peripheral component interconnect device of the server; obtains the type of the target high-speed peripheral component interconnect device; and sends a target alarm message to a baseboard management controller if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers allocated to the target high-speed peripheral component interconnect device exceeds the upper limit of the number of bus numbers reserved for the first target type; the target alarm message is used to indicate insufficient resources of the high-speed peripheral component interconnect bus; The baseboard management controller receives the target alarm information, and processes the target alarm information based on the type of the target peripheral component interconnect high-speed device that triggers the target alarm information to trigger the basic input and output system to restart; After the basic input / output system is restarted, the basic input / output system chip re-assigns a bus number of a high-speed peripheral component interconnect bus to the target high-speed peripheral component interconnect device based on target high-speed peripheral component interconnect bus resources if the type of the target high-speed peripheral component interconnect device is a first target type and the number of bus numbers already allocated to the target high-speed peripheral component interconnect device exceeds an upper limit of the number of bus numbers reserved for the first target type.

20. A server, characterized in that: include: A high-speed peripheral component interconnect bus resource allocation system as claimed in any one of claims 1 to 18.

21. An electronic device, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the high-speed peripheral component interconnect bus resource allocation method as claimed in claim 19 when executing the computer program.

22. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the high-speed peripheral component interconnect bus resource allocation method according to claim 19 are implemented.

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