Data transmission method, device and equipment for AXI bus clock domain conversion, medium and product

Abstract

The invention provides a data transmission method and device for AXI bus clock domain conversion, equipment, a medium and a product. The method comprises the steps that an effective transmission signal set with a set channel mode from an AXI bus is received; the effective transmission signal set comprises a plurality of effective transmission signals; sequentially writing the effective transmission signals into a set array structure according to the set channel mode and a first clock domain module; the set array structure is an array used for storing and transmitting an effective transmission signal set in a channel between the first clock domain module and the second clock domain module; and sequentially reading the effective transmission signals from the set array structure according to the second clock domain module. According to the invention, the array structure is set for data transmission in the design of AXI bus clock domain conversion, so that the process of clock domain conversion is simplified, the occupation of design resources is reduced, and the design cost is saved.

Description

Technical Field

[0001] The present application belongs to the field of chip design technology, and in particular relates to a data transmission method, apparatus, device, medium and product for AXI bus clock domain conversion. Background Art

[0002] The Advanced eXtensible Interface (AXI) protocol is an on-chip bus designed for high performance, high bandwidth, and low latency. With its fast transmission rate and high bandwidth, the AXI bus protocol is a high-performance, low-latency on-chip bus ideal for data transmission requiring high bandwidth.

[0003] In the OpenBMC (Open Baseboard Management Controller) design project, the AXI bus is used as the on-chip data bus, responsible for transmitting data signals between the DDR and other submodules. The AXI bus is a multi-channel transmission bus that sends write addresses, write data, write responses, and read addresses, read data, and responses on separate channels. Master and slave devices can be flexibly connected over the AXI bus. However, if the data clock domains of the master and slave devices are inconsistent, data transmission will not work properly, significantly impacting the overall design. Summary of the Invention

[0004] The present application provides a data transmission method, apparatus, device, medium and product for AXI bus clock domain conversion, which is used to solve the problem that in the existing AXI bus protocol, when the data clock domains of the master device and the slave device are inconsistent, data cannot be transmitted normally, thereby greatly affecting the overall design.

[0005] In a first aspect, the present application provides a data transmission method for AXI bus clock domain conversion, the method comprising: receiving a valid transmission signal set from a set channel mode in the AXI bus; the valid transmission signal set comprises a plurality of valid transmission signals; according to the set channel mode, each of the valid transmission signals is sequentially written into a set array structure according to a first clock domain module; the set array structure is an array for storing and transmitting the valid transmission signal set in the channel between the first clock domain module and the second clock domain module; and each of the valid transmission signals is sequentially read from the set array structure according to the second clock domain module.

[0006] The present application simplifies the clock domain conversion process in the design of AXI bus clock domain conversion by writing a valid transmission signal set into a setting array structure according to a first clock domain module, passing the setting array structure of the written data to a second clock domain module, and reading each of the valid transmission signals from the setting array structure in sequence according to the second clock domain module, thereby reducing the occupancy of design resources and saving design costs.

[0007] In an implementation of the first aspect, while writing each of the valid transmission signals into the set array structure in sequence according to the set channel mode according to the first clock domain module, it also includes: using a preset write counter to count each of the valid transmission signals written in the set array structure, and passing the preset write counter to the second clock domain module.

[0008] In an implementation of the first aspect, while reading each of the valid transmission signals from the set array structure in sequence according to the second clock domain module, it also includes: using a preset read counter to count each of the read valid transmission signals, and passing the preset read counter to the first clock domain module.

[0009] In an implementation of the first aspect, the method further includes: generating a valid preparation signal for the first clock domain module channel based on the preset write counter of the first clock domain module itself and the preset read counter transmitted by the second clock domain module; generating a valid signal for the second clock domain module channel based on the preset read counter of the second clock domain module itself and the preset write counter transmitted by the first clock domain module.

[0010] In an implementation of the first aspect, the set channel mode includes at least one of a write address channel mode, a write data channel mode, and a read address channel mode, the first clock domain module is a clock domain slave end, and the second clock domain module is a clock domain master end; while writing each of the valid transmission signals into the set array structure in sequence according to the first clock domain module according to the set channel mode, it also includes: using a preset write counter to count each of the valid transmission signals written in the set array structure, and passing the preset write counter to the clock domain master end.

[0011] In an implementation of the first aspect, while reading each of the valid transmission signals from the set array structure in sequence according to the second clock domain module, it also includes: using a preset read counter to count each of the read valid transmission signals, and transmitting the preset read counter to the clock domain slave end.

[0012] In an implementation of the first aspect, the method further includes: generating a valid preparation signal for a clock domain slave channel based on a preset write counter of the clock domain slave itself and a preset read counter transmitted by the clock domain master; and generating a valid signal for a clock domain master channel based on a preset read counter of the clock domain master itself and a preset write counter transmitted by the clock domain slave.

[0013] In an implementation of the first aspect, the set channel mode includes at least one of a write response channel mode and a read data response channel mode, the first clock domain module is the clock domain master end, and the second clock domain module is the clock domain slave end; according to the set channel mode, each of the valid transmission signals is written into the set array structure in sequence according to the first clock domain module, and it also includes: using a preset write counter to count each of the valid transmission signals written in the set array structure, and passing the preset write counter to the clock domain slave end.

[0014] In an implementation of the first aspect, while reading each of the valid transmission signals from the set array structure in sequence according to the second clock domain module, it also includes: using a preset read counter to count each of the read valid transmission signals, and transmitting the preset read counter to the clock domain master end.

[0015] In an implementation of the first aspect, the method further includes: generating a valid preparation signal for the clock domain master channel based on the preset write counter of the clock domain master itself and the preset read counter transmitted by the clock domain slave; generating a valid signal for the clock domain slave channel based on the preset read counter of the clock domain slave itself and the preset write counter transmitted by the clock domain master.

[0016] In the second aspect, the present application provides a data transmission device for AXI bus clock domain conversion, the device comprising: a setting array structure, configured to store and transmit an array of valid transmission signal sets in the channel between the first clock domain module and the second clock domain module; the first clock domain module, configured to receive a valid transmission signal set from a set channel mode in the AXI bus; the valid transmission signal set includes several valid transmission signals; the first clock domain module is also configured to write each of the valid transmission signals into the setting array structure in sequence according to the set channel mode; the second clock domain module is configured to read each of the valid transmission signals from the setting array structure in sequence.

[0017] In an implementation of the second aspect, the first clock domain module includes: a write control logic generation unit, configured to use a preset write counter to count each of the valid transmission signals written in the array structure, and pass the preset write counter to the second clock domain module; the write control logic generation unit is also configured to generate a valid ready signal for the first clock domain module channel based on the preset write counter of the first clock domain module itself and the preset read counter passed by the second clock domain module.

[0018] In an implementation of the second aspect, the second clock domain module includes: a read control logic generation unit, configured to use a preset read counter to count each of the valid transmission signals read, and pass the preset read counter to the first clock domain module; the read control logic generation unit is also configured to generate a valid signal for the second clock domain module channel based on the preset read counter of the second clock domain module itself and the preset write counter passed by the first clock domain module.

[0019] In a third aspect, the present application provides an electronic device comprising a processor and a memory; the memory is configured to store a computer program; the processor is configured to execute the computer program stored in the memory so that the electronic device performs the data transmission method of AXI bus clock domain conversion as described above.

[0020] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by an electronic device, implements the data transmission method for AXI bus clock domain conversion described above.

[0021] In a fifth aspect, the present application provides a computer program product, which includes computer program code. When the computer program code runs on a computer, the computer implements the data transmission method of AXI bus clock domain conversion described above.

[0022] As described above, the data transmission method, apparatus, device, medium, and product for AXI bus clock domain conversion described in this application have the following beneficial effects:

[0023] The present application receives a valid transmission signal set from a set channel mode in an AXI bus; the valid transmission signal set includes several valid transmission signals; each of the valid transmission signals is sequentially written into a setting array structure according to a first clock domain module according to the set channel mode; the setting array structure is an array used for storing and transmitting the valid transmission signal set in the channel between the first clock domain module and the second clock domain module; and each of the valid transmission signals is sequentially read from the setting array structure according to the second clock domain module. By writing the valid transmission signal set into the setting array structure according to the first clock domain module, and transmitting the setting array structure with written data to the second clock domain module, and simultaneously reading each of the valid transmission signals sequentially from the setting array structure according to the second clock domain module, the AXI bus protocol is kept consistent in the data clock domains of the master device and the slave device, data can be transmitted normally, and the clock domain conversion process is simplified in the design of the AXI bus clock domain conversion, thereby reducing the occupation of overall design resources, saving design costs, and reducing the adverse effects on the overall design of the AXI bus clock domain conversion device.

[0024] The present application uses a preset write counter to count each valid transmission signal written into the set array structure, and transmits the preset write counter to the second clock domain module. Furthermore, the present application uses a preset read counter to count each valid transmission signal read, and transmits the preset read counter to the first clock domain module. Based on the preset write counter of the first clock domain module and the preset read counter transmitted by the second clock domain module, a valid preparation signal for the first clock domain module channel is generated; and based on the preset read counter of the second clock domain module and the preset write counter transmitted by the first clock domain module, a valid signal for the second clock domain module channel is generated. The preset write counter and the preset read counter in the present application are both transmitted using Johnson counters. Compared to the existing binary adder counter followed by conversion to Gray code, this can reduce the overall design resource usage, save design costs, and thus reduce the adverse impact on the overall design of the AXI bus clock domain conversion device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shown is a schematic diagram of a hardware application scenario of the data transmission method for AXI bus clock domain conversion described in an embodiment of the present application.

[0026] Figure 2 Shown is a flow chart of a data transmission method for AXI bus clock domain conversion according to an embodiment of the present application.

[0027] Figure 3 Shown is a schematic diagram of the array structure described in an embodiment of the present application.

[0028] Figure 4 Shown is a hardware structure diagram of the data transmission method for AXI bus clock domain conversion described in an embodiment of the present application.

[0029] Figure 5 Shown is a schematic diagram of the overall flow of the data transmission method for AXI bus clock domain conversion according to an embodiment of the present application.

[0030] Figure 6 Shown is a structural schematic diagram of the AXI bus clock domain conversion device described in an embodiment of the present application.

[0031] Figure 7 Shown is a hardware structure diagram of the write address channel clock domain conversion module described in an embodiment of the present application.

[0032] Figure 8 Shown is a schematic diagram of the overall process of the write address channel mode described in an embodiment of the present application.

[0033] Figure 9 Shown is a hardware structure diagram of the write data channel clock domain conversion module described in an embodiment of the present application.

[0034] Figure 10 Shown is a schematic diagram of the overall process of the write data channel mode described in an embodiment of the present application.

[0035] Figure 11 Shown is a hardware structure diagram of the read address channel clock domain conversion module described in an embodiment of the present application.

[0036] Figure 12 Shown is a schematic diagram of the overall process of the read address channel mode described in an embodiment of the present application.

[0037] Figure 13 Shown is a hardware structure diagram of the write response channel clock domain conversion module described in an embodiment of the present application.

[0038] Figure 14 Shown is a schematic diagram of the overall process of the write response channel mode described in an embodiment of the present application.

[0039] Figure 15 Shown is a hardware structure diagram of the read data response channel clock domain conversion module described in an embodiment of the present application.

[0040] Figure 16 Shown is a schematic diagram of the overall process of the read data response channel mode described in an embodiment of the present application.

[0041] Figure 17 Shown is a structural schematic diagram of a data transmission device for AXI bus clock domain conversion according to an embodiment of the present application.

[0042] Figure 18 Shown is a structural schematic diagram of a data transmission device for AXI bus clock domain conversion according to another embodiment of the present application.

[0043] Figure 19 Shown is a structural schematic diagram of an electronic device described in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0045] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0046] The following embodiments of the present application provide a data transmission method, apparatus, device, medium, and product for AXI bus clock domain conversion, which solves the problem that in the existing AXI bus protocol, when the data clock domains of the master device and the slave device are inconsistent, data cannot be transmitted normally, thereby greatly affecting the overall design.

[0047] like Figure 1 As shown, this embodiment provides a hardware application scenario of a data transmission method for AXI bus clock domain conversion, specifically including: an AXI bus clock domain conversion module 3, which is used for data transmission and conversion between AXI module 1 and AXI module 2. The AXI bus clock domain conversion module 3 includes a clock domain master terminal 31 and a clock domain slave terminal 32. The AXI bus clock domain conversion module 3 receives data or address information from AXI module 1, completes the data clock domain conversion through the clock domain master terminal 31 and the clock domain slave terminal 32, and transmits the converted data or address information to AXI module 2.

[0048] The AXI bus clock domain conversion module 3 includes but is not limited to a clock domain master terminal 31 and a clock domain slave terminal 32 .

[0049] It should be noted that the embodiments of this application are described using an AXI bus as an example system bus. The AXI bus can be AXI3 or AXI4. The bus versions of AXI3 and AXI4 differ only in the bit widths and names of individual signals in individual channels. For example, the awlock signal in the write address channel is 2-bit in AXI3 and 1-bit in AXI4; the awlen signal is 4-bit in AXI3 and 8-bit in AXI4; the wid signal in the write data channel exists only in the AXI3 protocol and not in the AXI4 protocol; the arlock signal in the read address channel is 2-bit in AXI3 and 1-bit in AXI4; the arlen signal is 4-bit in AXI3 and 8-bit in AXI4, and so on.

[0050] The system bus used in the embodiments of the present application is not limited to AXI3, AXI4 and custom buses that require clock domain conversion, but can also be ISA bus, EISA bus, VESA bus, PCI bus, USB bus, SPI bus or I2C bus. Any bus that requires clock domain conversion can use the AXI bus clock domain conversion data transmission method described in the embodiments of the present application for data transmission, and no specific restrictions are made here.

[0051] When the AXI module 1 and the AXI module 2 are respectively AXI3, AXI4 and custom buses that require clock domain conversion, as well as one of the ISA bus, EISA bus, VESA bus, PCI bus, USB bus, SPI bus or I2C bus, when the AXI module 1 and the AXI module 2 perform data transmission, there will be inconsistencies in the data clock domains of some channels, resulting in data transmission failure. At this time, the AXI bus clock domain conversion module 3 needs to perform data clock domain matching to ensure successful data transmission between the buses of the AXI module 1 and the AXI module 2.

[0052] AXI is an on-chip bus designed for high performance, high bandwidth, and low latency, primarily used for data transmission and communication between components within a chip. It meets the demands of ultra-high performance and complex system-on-chip (SoC) designs and is widely used in high-speed data transmission scenarios requiring specific addresses, such as processor access to memory.

[0053] ISA bus: An industry-standard architecture bus, it was an extension of the XT bus to accommodate 8 / 16-bit data buses and was widely used during the 80286 and 80486 eras. It has 98 pins, a slower transmission rate, 16-bit or 32-bit data lines, and 20-bit or more address lines. This allows for a larger addressable space but a relatively low data transfer bandwidth, and has been gradually replaced by more advanced buses.

[0054] The EISA bus is an extended industry standard architecture bus, developed from the ISA bus while maintaining compatibility with the ISA bus. It increases the data and address line widths, supporting higher data transfer rates and a larger memory addressing space, meeting the demands of multimedia data processing such as graphics and images at the time. However, with the continuous advancement of computer technology, the EISA bus gradually withdrew from the mainstream market.

[0055] The VESA bus, also known as the Video Electronics Standards Association local bus, is a high-speed local bus standard. It is primarily used to connect the CPU, memory, and high-speed peripherals such as graphics cards and hard disk controllers. It provides high data transmission bandwidth to meet the demands of multimedia and graphics processing applications that require high data transmission speeds. The emergence of the VESA bus has driven improvements in personal computer performance, particularly in graphics display.

[0056] The PCI bus is one of the most widely used buses in personal computers. It offers high performance and efficiency, utilizes an independent address-multiplexed bus, supports plug-and-play functionality, and enables automatic device configuration and dynamic resource allocation. The PCI bus supports 32-bit or 64-bit data transmission, and its operating frequency continues to increase, meeting the data transmission bandwidth requirements of various devices. Network cards, sound cards, graphics cards, hard drives, and other devices all use the PCI bus interface.

[0057] USB bus: Universal Serial Bus, a serial bus standard. It's easy to use, hot-swappable, and can connect multiple devices. It's widely used to connect computers to various external devices, such as mice, keyboards, printers, removable storage devices, and cameras. The USB bus has several versions, including USB 1.0, USB 2.0, USB 3.0, and USB4. The higher the version, the faster the data transfer rate.

[0058] SPI bus: Serial Peripheral Interface bus, primarily used for EEPROM, Flash memory, real-time clocks, A / D converters, and between digital signal processors and digital signal decoders. It is a synchronous serial communication bus with one master and one or more slave devices, operating in a master-slave mode. It offers high communication speeds and stable and reliable data transmission.

[0059] I2C bus: Inter-Integrated Circuit bus, a new bus standard introduced by Philips. It boasts advantages such as fewer interface lines, simplified control, compact device packaging, and high communication speeds, making it widely adopted in the field of microelectronic communication control. The I2C bus utilizes synchronous communication, allowing multiple devices to connect to the bus. Addresses are used to identify communication partners, making it a common method for connecting microcontrollers and their peripherals, such as sensors, memory devices, and displays.

[0060] The technical solutions in the embodiments of the present application will be described in detail below with reference to the accompanying drawings in the embodiments of the present application.

[0061] like Figure 2 As shown, this embodiment provides a data transmission method for AXI bus clock domain conversion, and the method includes the following steps S11 to S13.

[0062] Step S11: Receive a valid transmission signal set from an AXI bus for setting a channel mode; the valid transmission signal set includes a plurality of valid transmission signals, wherein the set channel mode includes a write address channel mode, a write data channel mode, a write response channel mode, a read address channel mode, and / or a read data response channel mode.

[0063] Specifically, the valid transmission signal set refers to the collective term for all signals other than valid and ready within a channel at a given moment (cycle) when both the valid and ready signals are high (indicating successful channel handshake within the AXI bus clock domain converter). For example, the read data response channel signals [rid, rdata, rresp, rlast] are used. Rrid represents the read ID tag, rdata represents the read data, rresp represents the read response, and rlast represents the last indication signal.

[0064] Step S12, according to the set channel mode, each of the valid transmission signals is sequentially written into the set array structure according to the first clock domain module; the set array structure is an array used for storing and transmitting the valid transmission signal set in the channel between the first clock domain module and the second clock domain module.

[0065] Specifically, the array structure (Array) is an ordered sequence of elements (see Figure 3 As shown in the figure, an array is a collection of data of the same type. A finite set of variables of the same type is named an array. The individual variables that make up an array are called array components, also known as array elements, and sometimes subscript variables. The numbers used to distinguish between array elements are called subscripts. In programming, an array is a format for organizing multiple elements of the same type into an ordered structure for ease of processing. This collection of ordered, homogeneous data elements is called an array.

[0066] The first clock domain module and the second clock domain module refer to the areas composed of registers driven by the same clock signal in the synchronous circuit. The first clock domain module and the second clock domain module determine whether they are the clock domain master or the clock domain slave based on the set channel mode to which the valid transmission signal set transmitted belongs. When the set channel mode is a write address channel mode, a write data channel mode and / or a read address channel mode, the first clock domain module is a clock domain slave and the second clock domain module is a clock domain master. When the set channel mode includes a write response channel mode and / or a read data response channel mode, the first clock domain module is a clock domain master and the second clock domain module is a clock domain slave.

[0067] The clock domain master is the clock domain in which the device or module responsible for initiating data transfer requests resides during AXI bus transmission. It typically initiates data transfers, deciding when to begin and what data to transfer. The primary function of the clock domain master is to generate and send transaction requests, including addresses, control information, and data (if applicable). It also controls the flow of data transfers, such as by indicating the validity of address, data, or control information through VALID signals.

[0068] A clock domain slave is the clock domain in which the device or module that responds to data transfer requests resides during AXI bus transmission. It is typically the receiver of data transmissions and performs operations based on the master's requests. The primary function of a clock domain slave is to receive and process requests from the master. It uses the READY signal to indicate its readiness to receive data or control information and, upon receiving a valid request, executes the corresponding operation, such as reading or writing data.

[0069] Clock masters and slaves play a crucial role in AXI bus transmission. They ensure accurate and stable data transmission through precise clock synchronization and handshaking mechanisms. The clock master initiates data transmission requests, while the clock slave responds to these requests and performs corresponding data processing and feedback. This collaborative operation enables the AXI bus to operate reliably in complex system environments.

[0070] Step S13: Read each of the valid transmission signals in sequence from the set array structure according to the second clock domain module.

[0071] The present application simplifies the clock domain conversion process in the design of AXI bus clock domain conversion by writing a valid transmission signal set into a setting array structure using a first clock domain module, and passing the setting array structure of the written data to a second clock domain module, and at the same time reading each of the valid transmission signals from the setting array structure in sequence according to the second clock domain module, thereby reducing the occupation of design resources and saving design costs.

[0072] In one embodiment of the present application, while each of the valid transmission signals is written into the setting array structure in sequence according to the first clock domain module according to the set channel mode, it also includes step S121A: using a preset write counter to count each of the valid transmission signals written into the setting array structure, and passing the preset write counter to the second clock domain module.

[0073] In one embodiment of the present application, while the second clock domain module reads each of the valid transmission signals from the set array structure in sequence, it also includes step S131A: using a preset read counter to count each of the read valid transmission signals, and passing the preset read counter to the first clock domain module.

[0074] Specifically, the preset write counter and the preset read counter in the present application are both transferred using a Johnson counter, rather than the existing binary adder counter and then converted to Gray code, thereby reducing the occupation of design resources and saving costs.

[0075] The Johnson counter is a shift register-based counter that improves upon the ring counter. For example, a Johnson counter is constructed from n shift registers. In this case, the counter has 2n valid states, with only one bit transition between two consecutive count values. Here, n is a positive integer greater than or equal to 1.

[0076] In an embodiment of the present application, the data transmission method using AXI bus clock domain conversion further includes the following steps S14A to S15A.

[0077] Step S14A: Generate a valid ready signal for the first clock domain module channel according to the preset write counter of the first clock domain module itself and the preset read counter transmitted by the second clock domain module.

[0078] Step S15A: Generate a valid signal of the second clock domain module channel according to the preset read counter of the second clock domain module and the preset write counter transmitted by the first clock domain module.

[0079] Specifically, the present application uses a preset write counter to count each of the valid transmission signals written in the set array structure, and passes the preset write counter to the second clock domain module. At this time, the preset write counter will obtain the valid number of data in the set array structure after counting operation; then uses a preset read counter to count each of the valid transmission signals read, and passes the preset read counter to the first clock domain module. At this time, the preset read counter will also obtain the valid number of data in the set array structure after counting operation; finally, based on the valid number of data in the set array structure obtained by the preset write counter of the first clock domain module itself and the valid number of data in the set array structure obtained by the preset read counter operation passed by the second clock domain module, a valid ready signal for the first clock domain module channel is generated, and based on the valid number of data in the set array structure obtained by the preset read counter of the second clock domain module itself and the valid number of data in the set array structure obtained by the preset write counter operation passed by the first clock domain module, a valid signal for the second clock domain module channel is generated.

[0080] Figure 4 Shown is a hardware structure diagram of the data transmission method for AXI bus clock domain conversion described in an embodiment of the present application. Figure 5 Shown is a schematic diagram of the overall flow of the data transmission method for AXI bus clock domain conversion described in an embodiment of the present application. Figure 4-5 As shown, the AXI module 1 and the AXI module 2 perform data transmission through the clock domain conversion module, which specifically includes the following steps S21 to S27.

[0081] Step S21 : firstly presetting an array structure for transmitting a plurality of valid transmission signal sets in a channel between a slave end and a master end in two different clock domains.

[0082] Step S22 : The clock domain slave then writes each generated valid transmission signal set into the corresponding position of the set array structure in sequence.

[0083] Step S23: Use a Johnson counter (write counter) to count the valid signal written in, and then transmit the Johnson counter to the clock domain master.

[0084] Step S24 : The clock domain master reads each valid transmission signal set from the corresponding position of the set array structure in sequence.

[0085] Step S25: Count the valid signal read using a Johnson counter (read counter), and transmit the Johnson counter to the clock domain slave end.

[0086] Step S26 : The clock domain slave uses the write counter generated by itself and the read counter transmitted from the clock domain master to generate a valid ready signal for the clock domain slave channel.

[0087] Step S27 : The clock domain master uses the read counter generated by itself and the write counter transmitted from the clock domain slave to generate a valid signal of the clock domain master channel.

[0088] Figure 6 Shown is a schematic diagram of the structure of the AXI bus clock domain conversion device described in an embodiment of the present application. Figure 6 As shown in the figure, the AXI bus includes five channels: write address channel, write data channel, write response channel, read address channel, and read data response channel. The number of channels for write and read is asymmetric, with three channels for write (i.e., write address channel, write data channel, and write response channel) and two channels for read (i.e., read address channel and read data response channel). The read data response channel includes two parts: read data and read response, which share the read valid signal and read valid ready signal. The write data and write response channels are separate.

[0089] In one embodiment of the present application, the set channel mode includes a write address channel mode, a write data channel mode and / or a read address channel mode, the first clock domain module is the clock domain slave end, and the second clock domain module is the clock domain master end; according to the set channel mode, each of the valid transmission signals is written into the set array structure in sequence according to the first clock domain module, and step S121B is also included: each of the valid transmission signals written into the set array structure is counted using a preset write counter, and the preset write counter is passed to the clock domain master end.

[0090] In one embodiment of the present application, the second clock domain module reads each of the valid transmission signals from the set array structure in sequence, and includes step S131B: using a preset read counter to count each of the read valid transmission signals, and transmitting the preset read counter to the clock domain slave end.

[0091] In one embodiment of the present application, the method further includes the following steps S14B to S15B.

[0092] Step S14B, generating a valid ready signal for a clock domain slave channel according to a preset write counter of the clock domain slave and a preset read counter transmitted by the clock domain master;

[0093] Step S15B: Generate a valid signal of the clock domain master channel according to the preset read counter of the clock domain master itself and the preset write counter transmitted by the clock domain slave.

[0094] Figure 7Shown is a hardware structure diagram of the write address channel clock domain conversion module described in an embodiment of the present application. Figure 8 Shown is a schematic diagram of the overall process of the write address channel mode described in the embodiment of this application. Figure 7-8 As shown, AXI module 1 and AXI module 2 perform data transmission through the write address channel clock domain conversion module. Specifically, for the AXI write address channel, the following steps S31 to S37 are included.

[0095] Step S31, first preset a setting array structure struct_aw, that is, the write address channel array structure struct_aw (for example, the struct_aw array structure size can accommodate 4 channel signal sets, represented by positions struct_aw[0], struct_aw[1], struct_aw[2], and struct_aw[3] respectively) for transmitting multiple valid transmission signal sets in the write address channel between the slave end and the master end in two different clock domains (referring to the set of other signals in the channel except awvalid and awready when awvalid and awready are high at the same time, for example, the write address channel signals are shown in Table 1, and the valid transmission signal set in the write address channel is {awid, awaddr, awlen, awsize}).

[0096] Step S32, the clock domain slave end then writes each write address valid transmission signal set generated into the corresponding positions struct_aw[0], struct_aw[1], struct_aw[2], and struct_aw[3] of the write address array structure struct_aw in sequence.

[0097] Step S33: Use a Johnson counter (write counter) to count the valid signal written in, and then transmit the Johnson counter to the clock domain master.

[0098] Step S34: The clock domain master reads each valid transmission signal set from the corresponding positions struct_aw[0], struct_aw[1], struct_aw[2], and struct_aw[3] of the write address array structure struct_aw in sequence.

[0099] Step S35: Count the valid signal read using a Johnson counter (read counter), and transmit the Johnson counter to the clock domain slave end.

[0100] Step S36 : The clock domain slave uses the write counter generated by itself and the read counter transmitted from the clock domain master to generate the valid ready signal awready of the clock domain slave write address channel (ie, the slave write address channel valid ready signal awready).

[0101] Step S37 : The clock domain master uses the read counter generated by itself and the write counter transmitted from the clock domain slave to generate a valid signal awvalid of the clock domain master write address channel (ie, a master write address channel valid signal awvalid).

[0102]

[0103] Table 1

[0104] It should be noted that the write address channel signals include but are not limited to {awid, awaddr, awlen, awsize, awvalid, and awready}. For example, the write address channel signals also include {awuser, awlock, awregion, awburst, awcache, awprot, and awqos}. Among them, awuser represents the write address channel user signal, awlock represents the lock type, awregion represents the region identifier, awburst represents the burst type, awcache represents the cache type, awprot represents the protection type, and awqos represents the quality of service. At this time, the set of multiple valid transmission signals in the write address channel is {awuser, awid, awaddr, awlen, awlock, awregion, awsize, awburst, awcache, awprot, and awqos}.

[0105] Figure 9 Shown is a hardware structure diagram of the write data channel clock domain conversion module described in an embodiment of the present application. Figure 10 Shown is a schematic diagram of the overall process of the write data channel mode described in the embodiment of this application. Figure 9-10 As shown, AXI module 1 and AXI module 2 perform data transmission through a write data channel clock domain conversion module. Specifically, for the AXI write data channel, the following steps S41 to S47 are included.

[0106] Step S41, first preset a setting array structure struct_w, that is, the write data channel array structure struct_w (for example, the size of the array structure struct_w can accommodate 4 channel signal sets, represented by positions struct_w[0], struct_w[1], struct_w[2], and struct_w[3] respectively) for transmitting multiple valid transmission signal sets in the write data channel between the slave end and the master end in two different clock domains (referring to the set of other signals in the channel except wvalid and wready when wvalid and wready are high at the same time, for example, the write data channel signals are shown in Table 2, and the valid transmission signal set in the write data channel is {wid, wuser, wlast, wstrb, wdata}).

[0107] Step S42, then the clock domain slave end writes each set of valid transmission signals of write data generated into the corresponding positions struct_w[0], struct_w[1], struct_w[2], struct_w[3] of the write data array struct_w in sequence.

[0108] Step S43: Use a Johnson counter (write counter) to count the valid signal written in, and then transmit the Johnson counter to the clock domain master.

[0109] Step S44: The clock domain master reads each valid transmission signal set from the corresponding positions struct_w[0], struct_w[1], struct_w[2], and struct_w[3] of the write data array struct_w in sequence.

[0110] Step S45: Count the valid signal read using a Johnson counter (read counter), and transmit the Johnson counter to the clock domain slave end.

[0111] Step S46 : The clock domain slave uses the write counter generated by itself and the read counter transmitted from the clock domain master to generate a valid ready signal wready for the clock domain slave write data channel (ie, a valid ready signal wready for the slave write data channel).

[0112] Step S47 : The clock domain master uses the read counter generated by itself and the write counter transmitted from the clock domain slave to generate a valid signal wvalid of the clock domain master write data channel (ie, a master write data channel valid signal wvalid).

[0113]

[0114] Table 2

[0115] It should be noted that the write data channel signals include but are not limited to {wid, wuser, wlast, wstrb, wdata, wvalid, wready}.

[0116] Figure 11 Shown is a hardware structure diagram of the read address channel clock domain conversion module described in an embodiment of the present application. Figure 12 The diagram shows the overall flow of the read address channel mode described in the embodiment of the present application. Figure 11-12 As shown, AXI module 1 and AXI module 2 perform data transmission through the read address channel clock domain conversion module. Specifically, for the AXI read address channel, the following steps S51 to S57 are included.

[0117] Step S51, first preset a setting array structure struct_ar, that is, the read address channel array structure struct_ar (for example, the size of the array structure struct_ar can accommodate 4 channel signal sets, represented by positions struct_ar[0], struct_ar[1], struct_ar[2], and struct_ar[3] respectively) for the transmission of multiple valid transmission signal sets in the read address channel between the slave end and the master end in two different clock domains (referring to the set of other signals in the channel except arvalid and arready when arvalid and arready are high at the same time, for example, the read address channel signals are shown in Table 3, and the valid transmission signal set in the read address channel is {arid, araddr, arlen, arsize}).

[0118] Step S52, the clock domain slave end then writes each generated read address valid transmission signal set into the corresponding positions struct_ar[0], struct_ar[1], struct_ar[2], and struct_ar[3] of the read address array struct_ar in sequence.

[0119] Step S53: Use a Johnson counter (write counter) to count the valid signal written in, and then transmit the Johnson counter to the clock domain master.

[0120] Step S54 , the clock domain master reads each valid transmission signal set in sequence from the corresponding positions struct_ar[0], struct_ar[1], struct_ar[2], and struct_ar[3] of the read address array struct_ar.

[0121] Step S55: Count the valid signal read using a Johnson counter (read counter), and transmit the Johnson counter to the clock domain slave end.

[0122] Step S56 , the clock domain slave uses the write counter generated by itself and the read counter transmitted from the clock domain master to generate a valid ready signal arready for the clock domain slave read address channel (ie, a valid ready signal arready for the slave read address channel).

[0123] Step S57 : The clock domain master uses the read counter generated by itself and the write counter transmitted from the clock domain slave to generate a valid signal arvalid of the clock domain master read address channel (ie, the master read address channel valid signal arvalid).

[0124]

[0125] Table 3

[0126] It should be noted that the read address channel signals include but are not limited to {arid, araddr, arlen, arsize, arvalid, and arready}. For example, the read address channel signals also include {aruser, arlock, arregion, arburst, arcache, arprot, and arqos}. Among them, aruser represents a user-defined signal in the read address channel; arlock represents the blocking type, which provides more specific additional information about the transmission in the burst; arregion represents the region identifier, which allows the same physical interface on the device to be used as multiple logical interfaces; arburst represents the burst type, which together with arsize determines the calculation method of the read address for each transmission in the burst; arcache represents the memory type, which indicates the specification of the transmission in the system; arprot represents the protection type, which indicates the priority and security level of the transmission, and whether the transmission accesses data or instructions; arqos represents the quality of service, which sends a QoS identifier for each read transmission and can be used to guide the execution order of read operations. At this time, the set of multiple valid transmission signals in the read address channel is {aruser, arid, araddr, arlen, arlock, arregion, arsize, arburst, arcache, arprot, arqos}.

[0127] In one embodiment of the present application, the set channel mode includes a write response channel mode and / or a read data response channel mode, the first clock domain module is the clock domain master end, and the second clock domain module is the clock domain slave end; according to the set channel mode, each of the valid transmission signals is written into the set array structure in sequence according to the first clock domain module, and step S121C is also included: each of the valid transmission signals written into the set array structure is counted using a preset write counter, and the preset write counter is passed to the clock domain slave end.

[0128] In one embodiment of the present application, while reading each of the valid transmission signals from the set array structure in sequence according to the second clock domain module, it also includes step S131C: using a preset read counter to count each of the read valid transmission signals, and transmitting the preset read counter to the clock domain master end.

[0129] In one embodiment of the present application, the method further includes the following steps S14C to S15C.

[0130] Step S14C: Generate a valid ready signal of the clock domain master channel according to the preset write counter of the clock domain master itself and the preset read counter transmitted by the clock domain slave.

[0131] Step S15C: Generate a valid signal of the clock domain slave channel according to the preset read counter of the clock domain slave itself and the preset write counter transmitted by the clock domain master.

[0132] Figure 13 Shown is a hardware structure diagram of the write response channel clock domain conversion module described in an embodiment of the present application. Figure 14 Shown is a schematic diagram of the overall process of the write response channel mode described in the embodiment of this application. Figure 13-14 As shown, AXI module 1 and AXI module 2 perform data transmission through the write response channel clock domain conversion module. Specifically, for the AXI write response channel, the following steps S61 to S67 are included.

[0133] Step S61, first preset a preset array structure struct_b, that is, the write response channel array structure struct_b (for example, the size of the array structure struct_b can accommodate 4 channel signal sets, represented by positions struct_b[0], struct_b[1], struct_b[2], and struct_b[3] respectively) for the transmission of multiple valid transmission signal sets in the write response channel between the slave end and the master end in two different clock domains (referring to the set of other signals in the channel except bvalid and bready when bvalid and bready are high at the same time, for example, the write response channel signals are shown in Table 4, and the valid transmission signal set in the write response channel is {bid, buser, bresp}).

[0134] Step S62, the clock domain master then writes each generated write response valid transmission signal set into the corresponding positions struct_b[0], struct_b[1], struct_b[2], and struct_b[3] of the write response array struct_b in sequence.

[0135] Step S63: Use a Johnson counter (write counter) to count the valid signal written in, and then transmit the Johnson counter to the clock domain slave end.

[0136] Step S64: The clock domain slave end sequentially reads each valid transmission signal set from the corresponding positions struct_b[0], struct_b[1], struct_b[2], and struct_b[3] of the write response array struct_b.

[0137] Step S65: Count the read valid signal using a Johnson counter (read counter), and transmit the Johnson counter to the clock domain master.

[0138] Step S66: The clock domain master uses the write counter generated by itself and the read counter transmitted from the clock domain slave to generate a valid preparation signal bready for the clock domain master write response channel (ie, master write response channel valid preparation signal bready).

[0139] Step S67 : The clock domain slave uses the read counter generated by itself and the write counter transmitted from the clock domain master to generate a valid signal bvalid of the clock domain slave write response channel (ie, a slave write response channel valid signal bvalid).

[0140] Signal Source Description bid Slave Write response ID. This signal is the ID tag of write data transmission bresp Slave Write response. This signal indicates the status of the write operation buser Slave User-defined signals bvalid Slave Write response valid. This signal indicates that the channel is sending a valid write response signal bready Master Write response ready. This signal indicates that the host can accept the write response

[0141] Table 4

[0142] It should be noted that the write response channel signals include but are not limited to {bid, bresp, buser, bvalid, bready}.

[0143] Figure 15 Shown is a hardware structure diagram of the read data response channel clock domain conversion module described in an embodiment of the present application. Figure 16 Shown is a schematic diagram of the overall process of the read data response channel mode described in the embodiment of the present application. Figure 15-16 As shown, AXI module 1 and AXI module 2 perform data transmission through the read data response channel clock domain conversion module. Specifically, for the AXI read data response channel, the following steps S71 to S77 are included.

[0144] Step S71, first preset a setting array structure struct_r, that is, the read data response channel array structure struct_r (for example, the size of the array structure struct_r can accommodate 4 channel signal sets, represented by positions struct_r[0], struct_r[1], struct_r[2], and struct_r[3] respectively) for the transmission of multiple valid transmission signal sets in the read data response channel between the slave end and the master end in two different clock domains (referring to the set of other signals in the channel except rvalid and rready when rvalid and rready are high at the same time, for example, the read data response channel signals are shown in Table 5, and the valid transmission signal set in the read data response channel is {rid, ruser, rlast, rresp, rdata}).

[0145] Step S72, the clock domain master then writes each generated read data response valid transmission signal set into the corresponding positions struct_r[0], struct_r[1], struct_r[2], and struct_r[3] of the read data response array struct_r in sequence.

[0146] Step S73: Use a Johnson counter (write counter) to count the valid signal written in, and then transmit the Johnson counter to the clock domain slave end.

[0147] Step S74 , the clock domain slave end sequentially reads each valid transmission signal set from the corresponding positions struct_r[0], struct_r[1], struct_r[2], and struct_r[3] of the read data response array struct_r.

[0148] Step S75: Count the valid signal read using a Johnson counter (read counter), and transmit the Johnson counter to the clock domain master.

[0149] Step S76: The clock domain master uses the write counter generated by itself and the read counter transmitted from the clock domain slave to generate a valid ready signal rready of the clock domain master read data response channel (ie, a master read data response channel valid ready signal rready).

[0150] Step S77 , the clock domain slave uses the read counter generated by itself and the write counter transmitted from the clock domain master to generate a valid signal rvalid of the clock domain slave read data response channel (ie, a slave read data response channel valid signal rvalid).

[0151] Signal Source Description rid Slave Read ID tag. This signal is generated by the slave device that reads the data signal of the identification tag. rdata Slave Reading in data rresp Slave Read response. This signal indicates the status of the read transfer rlast Slave LAST indicator signal. This signal indicates the last transfer in the read operation ruser Slave User-defined signals rvalid Slave Read valid. This signal indicates that the channel is sending the required read data rready Master Read ready. This signal indicates that the host can accept read data and response information

[0152] Form 5

[0153] It should be noted that the read data response channel signals include but are not limited to {rid, ruser, rlast, rresp, rdata, rvalid, rready}.

[0154] The protection scope of the data transmission method for AXI bus clock domain conversion described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing, or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.

[0155] An embodiment of the present application also provides a data transmission device for AXI bus clock domain conversion, which can implement the data transmission method for AXI bus clock domain conversion described in the present application. However, the implementation device of the data transmission method for AXI bus clock domain conversion described in the present application includes but is not limited to the structure of the data transmission device for AXI bus clock domain conversion listed in the present embodiment. All structural variations and replacements of the prior art made according to the principles of the present application are included in the protection scope of the present application.

[0156] like Figure 17 As shown, this embodiment provides a data transmission device for AXI bus clock domain conversion, and the device 4 includes: a setting array structure 41, a first clock domain module 42 and a second clock domain module 43.

[0157] The setting array structure 41 is configured to store and transmit an array of valid transmission signal sets in a channel between the first clock domain module 42 and the second clock domain module 43 .

[0158] The first clock domain module 42 is configured to receive a valid transmission signal set from a set channel mode in the AXI bus; the valid transmission signal set includes a plurality of valid transmission signals; the first clock domain module 42 is also configured to write each of the valid transmission signals into the set array structure 41 in sequence according to the set channel mode.

[0159] The second clock domain module 43 is configured to read each of the valid transmission signals from the setting array structure 41 in sequence.

[0160] like Figure 18 As shown, in one embodiment of the present application, the first clock domain module 42 includes a write control logic generation unit 421 .

[0161] The write control logic generating unit 421 is configured to count each of the valid transmission signals written into the setting array structure using a preset write counter, and transmit the preset write counter to the second clock domain module 43;

[0162] The write control logic generation unit 421 is further configured to generate a valid ready signal for the channel of the first clock domain module 42 according to the preset write counter of the first clock domain module 42 itself and the preset read counter transmitted by the second clock domain module 43 .

[0163] In an embodiment of the present application, the second clock domain module 43 includes a read control logic generation unit 431 .

[0164] The read control logic generating unit 431 is configured to count each of the valid transmission signals read using a preset read counter, and transmit the preset read counter to the first clock domain module 42;

[0165] The read control logic generation unit 431 is further configured to generate a valid signal for a channel of the second clock domain module 43 according to a preset read counter of the second clock domain module 43 and a preset write counter transmitted by the first clock domain module 42 .

[0166] It should be noted that the functions or operations of the setting array structure 41, the first clock domain module 42, the write control logic generation unit 421, the second clock domain module 43 and the read control logic generation unit 431 described in the embodiment of the present disclosure correspond one-to-one to the steps in the data transmission method of the AXI bus clock domain conversion described above, so they will not be repeated here.

[0167] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices or methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.

[0168] The modules / units described as separate components may or may not be physically separate, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in the various embodiments of the present application may be integrated into a processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into a single module / unit.

[0169] Those skilled in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0170] like Figure 19 As shown, this embodiment provides an electronic device, the electronic device 5 includes a processor 51 and a memory 52; the memory 52 is used to store a computer program for running the data transmission device 4 for AXI bus clock domain conversion; the processor 51 is used to execute the computer program stored in the memory 52, so that the electronic device 5 performs the data transmission method for AXI bus clock domain conversion as described above.

[0171] The embodiment of the present application also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid-state drive (SSD)), etc.

[0172] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, which, when running on a computer, enables the computer to execute the data transmission method of AXI bus clock domain conversion in any of the embodiments shown above.

[0173] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer instructions (programs) are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer or data center to another website, computer or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0174] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product can be a software installation package. When the above method is needed, the computer program product can be downloaded and executed on the computer.

[0175] In summary, the data transmission method, apparatus, device, medium, and product for AXI bus clock domain conversion described in the embodiments of the present application have the following beneficial effects:

[0176] The present application receives a valid transmission signal set from a set channel mode in an AXI bus; the valid transmission signal set includes several valid transmission signals; each of the valid transmission signals is sequentially written into a setting array structure according to a first clock domain module according to the set channel mode; the setting array structure is an array used for storing and transmitting the valid transmission signal set in the channel between the first clock domain module and the second clock domain module; and each of the valid transmission signals is sequentially read from the setting array structure according to the second clock domain module. By writing the valid transmission signal set into the setting array structure according to the first clock domain module, and transmitting the setting array structure with written data to the second clock domain module, and simultaneously reading each of the valid transmission signals sequentially from the setting array structure according to the second clock domain module, the AXI bus protocol is kept consistent in the data clock domains of the master device and the slave device, data can be transmitted normally, and the clock domain conversion process is simplified in the design of the AXI bus clock domain conversion, thereby reducing the occupation of overall design resources, saving design costs, and reducing the adverse effects on the overall design of the AXI bus clock domain conversion device.

[0177] The present application uses a preset write counter to count each valid transmission signal written into the set array structure, and transmits the preset write counter to the second clock domain module. Furthermore, the present application uses a preset read counter to count each valid transmission signal read, and transmits the preset read counter to the first clock domain module. Based on the preset write counter of the first clock domain module and the preset read counter transmitted by the second clock domain module, a valid preparation signal for the first clock domain module channel is generated; and based on the preset read counter of the second clock domain module and the preset write counter transmitted by the first clock domain module, a valid signal for the second clock domain module channel is generated. The preset write counter and the preset read counter in the present application are both transmitted using Johnson counters. Compared to the existing binary adder counter followed by conversion to Gray code, this can reduce the overall design resource usage, save design costs, and thus reduce the adverse impact on the overall design of the AXI bus clock domain conversion device.

[0178] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0179] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A data transmission method for AXI bus clock domain conversion, characterized in that: The method comprises: Receiving a valid transmission signal set for setting a channel mode from an AXI bus; the valid transmission signal set includes a plurality of valid transmission signals; According to the set channel mode, each of the valid transmission signals is sequentially written into a set array structure according to the first clock domain module; the set array structure is an array for storing and transmitting a set of valid transmission signals in a channel between the first clock domain module and the second clock domain module; The valid transmission signals are sequentially read from the setting array structure according to the second clock domain module.

2. The data transmission method of AXI bus clock domain conversion according to claim 1, characterized in that: While writing each of the valid transmission signals into the set array structure in sequence according to the first clock domain module according to the set channel mode, the method further includes: A preset write counter is used to count each of the valid transmission signals written into the setting array structure, and the preset write counter is transmitted to the second clock domain module.

3. The data transmission method of AXI bus clock domain conversion according to claim 2, characterized in that: While sequentially reading each of the valid transmission signals from the setting array structure according to the second clock domain module, the method further includes: A preset read counter is used to count each of the valid transmission signals read, and the preset read counter is transferred to the first clock domain module.

4. The data transmission method for AXI bus clock domain conversion according to claim 3, characterized in that: The method further comprises: Generate a valid ready signal for the first clock domain module channel according to the preset write counter of the first clock domain module itself and the preset read counter transmitted by the second clock domain module; A valid signal of a second clock domain module channel is generated according to a preset read counter of the second clock domain module itself and a preset write counter transmitted by the first clock domain module.

5. The data transmission method of AXI bus clock domain conversion according to claim 1, characterized in that: The setting channel mode includes at least one of a write address channel mode, a write data channel mode and a read address channel mode, the first clock domain module is a clock domain slave end, and the second clock domain module is a clock domain master end; While writing each of the valid transmission signals into the set array structure in sequence according to the first clock domain module according to the set channel mode, it also includes: using a preset write counter to count each of the valid transmission signals written in the set array structure, and transmitting the preset write counter to the clock domain master end.

6. The data transmission method for AXI bus clock domain conversion according to claim 5, characterized in that: While sequentially reading each of the valid transmission signals from the setting array structure according to the second clock domain module, the method includes: A preset read counter is used to count each of the valid transmission signals read, and the preset read counter is transmitted to the clock domain slave end.

7. The data transmission method for AXI bus clock domain conversion according to claim 6, characterized in that: The method further comprises: Generate a valid ready signal for a clock domain slave channel according to a preset write counter of the clock domain slave itself and a preset read counter transmitted by the clock domain master; A valid signal of a clock domain master channel is generated according to a preset read counter of the clock domain master itself and a preset write counter transmitted by the clock domain slave.

8. The data transmission method for AXI bus clock domain conversion according to claim 1, characterized in that: The setting channel mode includes at least one of a write response channel mode and a read data response channel mode, the first clock domain module is a clock domain master end, and the second clock domain module is a clock domain slave end; While writing each of the valid transmission signals into the set array structure in sequence according to the first clock domain module according to the set channel mode, it also includes: using a preset write counter to count each of the valid transmission signals written in the set array structure, and transmitting the preset write counter to the clock domain slave end.

9. The data transmission method for AXI bus clock domain conversion according to claim 8, characterized in that: While sequentially reading each of the valid transmission signals from the setting array structure according to the second clock domain module, the method further includes: A preset read counter is used to count each of the valid transmission signals read, and the preset read counter is transmitted to the clock domain master.

10. The data transmission method for AXI bus clock domain conversion according to claim 9, characterized in that: The method further comprises: Generate a valid preparation signal for a clock domain master channel according to a preset write counter of the clock domain master and a preset read counter transmitted by the clock domain slave; A valid signal of a clock domain slave channel is generated according to a preset read counter of the clock domain slave itself and a preset write counter transmitted by the clock domain master.

11. A data transmission device for AXI bus clock domain conversion, characterized in that: include: Setting an array structure configured to store and transmit an array of valid transmission signal sets in a channel between a first clock domain module and a second clock domain module; The first clock domain module is configured to receive a valid transmission signal set of a set channel mode from the AXI bus; the valid transmission signal set includes a plurality of valid transmission signals; the first clock domain module is further configured to write each of the valid transmission signals into an array structure in sequence according to the set channel mode; The second clock domain module is configured to read each of the valid transmission signals from the setting array structure in sequence.

12. The data transmission device for AXI bus clock domain conversion according to claim 11, characterized in that: The first clock domain module includes: a write control logic generating unit configured to count each of the valid transmission signals written into the setting array structure using a preset write counter, and transmit the preset write counter to the second clock domain module; The write control logic generation unit is further configured to generate a valid ready signal for the first clock domain module channel according to a preset write counter of the first clock domain module itself and a preset read counter transmitted by the second clock domain module.

13. The data transmission device for AXI bus clock domain conversion according to claim 12, characterized in that: The second clock domain module includes: a read control logic generating unit, configured to count each of the valid transmission signals read using a preset read counter, and transmit the preset read counter to the first clock domain module; The read control logic generation unit is further configured to generate a valid signal of the second clock domain module channel according to a preset read counter of the second clock domain module itself and a preset write counter transmitted by the first clock domain module.

14. An electronic device, characterized in that: including processor and memory; The memory is configured to store a computer program; The processor is configured to execute the computer program stored in the memory, so as to enable the electronic device to perform the data transmission method for AXI bus clock domain conversion according to any one of claims 1 to 10.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by an electronic device, the data transmission method for AXI bus clock domain conversion according to any one of claims 1 to 10 is implemented.

16. A computer program product, characterized in that The computer program product includes computer program code, and when the computer program code is run on a computer, the computer is enabled to implement the data transmission method for AXI bus clock domain conversion according to any one of claims 1 to 10.

Images