A photolithography simulation method and device based on a large language model, equipment and medium

Abstract

The application discloses a photolithography simulation method and device based on a large language model, equipment and a medium, relates to the technical field of photolithography simulation, and comprises the following steps: inputting a chip layout to be simulated into a pre-trained large language model, performing polygon traversal and coding on the chip layout to be simulated, generating sequence information of a single polygon, splicing all the sequence information in sequence to obtain a complete layout sequence corresponding to the chip layout to be simulated; performing sequence feature extraction on the complete layout sequence to obtain target sequence features, capturing target coding features representing the global context relationship of the polygons in the target sequence features, generating predicted target sequence data based on the target coding features, extracting vertex coordinates, edge directions and length information of each polygon, reconstructing the target geometric contour of each polygon based on the vertex coordinates, edge directions and length information of each polygon, and outputting a complete photolithography simulation layout combined by all the target geometric contours. The fast simulation of the layout is realized.

Description

Technical Field

[0001] The present invention relates to the field of photolithography simulation technology, and in particular to a photolithography simulation method, device, equipment and medium based on a large language model. Background Art

[0002] With the continuous advancement of technology, chip sizes are becoming smaller and smaller, while chip multifunctionality is also increasing. Currently, domestic process technology has reached the 7-nanometer level, while overseas process technology has reached the 2-nanometer level, and even smaller process technologies may emerge in the future. This trend is making chips more efficient and increasingly integrated. Effective, accurate, and fast lithography simulation is becoming increasingly important for manufacturing. It also enables rapid performance evaluation during the design phase, reducing risks and improving design and development efficiency.

[0003] Traditional photolithography simulation methods rely on classical Fourier optics theory to implement incomplete coherence imaging to calculate the light intensity distribution within the photoresist on the wafer. This is then combined with a classical photoresist model to produce a simulated photoresist pattern. To achieve higher accuracy at advanced process nodes, photolithography simulations incorporate thick mask scattering models into the optical imaging model. Both strict physical models and compact photoresist models must account for complex considerations such as the negative development photoresist effect. Consequently, traditional methods require repeated invocation of complex physical models (such as the optical imaging model and the photoresist model), resulting in significant computational overhead. At 7nm and below, the computational complexity of simulations increases exponentially, leading to extended design cycles. The underlying reason is the high complexity of the physical models, which prevents them from fully utilizing the parallel computing capabilities of the hardware. Raster-based data processing methods (such as discretizing the image into a pixel grid) require extensive repetitive computation. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a lithography simulation method, device, equipment, and medium based on a large language model, which can quickly and accurately simulate complex lithography patterns in different process scenarios and reduce the simulation process. The specific solution is as follows:

[0005] In a first aspect, the present application discloses a lithography simulation method based on a large language model, comprising:

[0006] Obtaining a chip layout to be simulated, inputting the chip layout to be simulated into a pre-trained large language model, so as to perform polygon traversal and encoding on the chip layout to be simulated by the pre-trained large language model, generate sequence information of a single polygon, and sequentially splice all the sequence information to obtain a complete layout sequence corresponding to the chip layout to be simulated;

[0007] Performing sequence feature extraction on the complete map sequence using the pre-trained large language model to obtain target sequence features, and then capturing target coding features representing the global contextual relationship of polygons in the target sequence features to generate predicted target sequence data based on the target coding features;

[0008] The pre-trained large language model is used to extract the vertex coordinates, edge direction and length information of each polygon from the target sequence data, so as to reconstruct the target geometric outline of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and output a complete lithography simulation layout combining all the target geometric outlines.

[0009] Optionally, obtaining the layout of the chip to be simulated includes:

[0010] An initial chip layout to be simulated in a preset format is exported, and a multi-deformation closure check and a coordinate accuracy check are performed on the initial chip layout to be simulated to obtain a chip layout to be simulated that meets photolithography simulation conditions.

[0011] Optionally, the polygon traversal and encoding of the chip layout to be simulated by the pre-trained large language model is performed to generate sequence information of a single polygon, and all sequence information is sequentially spliced ​​to obtain a complete layout sequence corresponding to the chip layout to be simulated, including:

[0012] Using the semantic encoding layer of the pre-trained large language model, starting from the upper left corner vertex of the polygon, traverse all edges of each polygon in the chip layout to be simulated in a clockwise direction;

[0013] The direction information and length information of each edge in each polygon obtained by traversal are encoded to obtain the sequence information of a single polygon;

[0014] The sequence information of each polygon is sequentially spliced ​​according to the arrangement order of the polygons in the chip layout to be simulated, so as to obtain a complete layout sequence corresponding to the chip layout to be simulated.

[0015] Optionally, encoding the direction information and length information of each edge in each polygon obtained by traversal to obtain sequence information of a single polygon includes:

[0016] Encoding the direction information of each edge of each polygon obtained through traversal according to a preset direction coding rule to obtain corresponding direction coding sequence information; wherein the preset direction coding rule is that the left direction is coded as 0, the right direction is coded as 1, the downward direction is coded as 2, and the upward direction is coded as 3;

[0017] The length information of each edge of each polygon obtained by traversal is encoded according to a preset length encoding rule to obtain corresponding length encoding sequence information; wherein the preset length encoding rule is to set the chip layout coordinate unit as the edge length unit;

[0018] The sequence information of the corresponding single polygon is determined based on the direction coding sequence information and the length coding sequence information.

[0019] Optionally, before inputting the chip layout to be simulated into the pre-trained large language model, the method further includes:

[0020] Obtain several historical chip layouts covering different process nodes and different layout scenarios; where the layout scenarios include dense graphics and isolated graphics;

[0021] Performing photolithography simulation on each of the historical chip layouts to generate a corresponding photoresist profile as label data to obtain a historical chip layout carrying the label data;

[0022] Inputting each historical chip layout carrying the label data into the large language model so that the semantic encoding layer of the large language model performs polygon traversal and encoding on each historical chip layout to obtain a historical complete layout sequence corresponding to each historical chip layout;

[0023] Based on the historical complete map sequence and the tag data sequence corresponding to the tag data, generating a historical complete map sequence carrying the tag data;

[0024] The large language model is trained using each historical complete layout sequence carrying label data to obtain a pre-trained large language model that has learned the mapping relationship between the historical complete layout sequence and the target geometric contour after lithography.

[0025] Optionally, the large language model includes an encoder, a decoder, and an output layer connected in sequence, wherein the large language model is trained using each historical complete layout sequence carrying label data to obtain a pre-trained large language model that learns the mapping relationship between the historical complete layout sequence and the target geometric contour after lithography, including:

[0026] Capturing the proximity effect relationship and global layout association relationship between polygons of each sequence element in the historical complete map sequence through the multi-head self-attention layer in the encoder of the large language model to obtain an attention-weighted feature vector;

[0027] The attention-weighted feature vector is added to the input information of the multi-head self-attention layer through the residual connection layer in the encoder to obtain the corresponding global feature;

[0028] Inputting a target label data sequence before a current time step in the label data sequence into the decoder of the large language model, so as to predict a next label data sequence element based on the target label data sequence through a masked multi-head self-attention layer of the decoder;

[0029] Generate a complete prediction label sequence time step by time based on the local features and the global features output by the decoder through the output layer of the large language model;

[0030] The loss function is used to calculate the loss value of the complete predicted label sequence and the corresponding label data sequence, so as to reversely optimize the model parameters of the large language model based on the loss value result until the iteration stop condition is met, and the current large language model is output as the pre-trained large language model.

[0031] Optionally, generating a complete predicted label sequence time-step by time-step based on the local features and the global features output by the decoder through the output layer of the large language model includes:

[0032] Using the cross-attention layer of the decoder of the large language model as a query vector, the local features output by the decoder are used to query the corresponding target global features from the global features according to the query vector at the current time step as the corresponding key and value, and performing weighted processing to obtain a fused feature;

[0033] A complete predicted label sequence is generated through the output layer of the large language model and based on the fused features at each time step.

[0034] In a second aspect, the present application discloses a lithography simulation device based on a large language model, comprising:

[0035] a sequence processing module, configured to obtain a chip layout to be simulated, input the chip layout to be simulated into a pre-trained large language model, perform polygon traversal and encoding on the chip layout to be simulated by the pre-trained large language model, generate sequence information of a single polygon, and sequentially concatenate all the sequence information to obtain a complete layout sequence corresponding to the chip layout to be simulated;

[0036] a feature extraction module, configured to perform sequence feature extraction on the complete layout sequence using the pre-trained large language model to obtain target sequence features, and then capture target coding features representing the global contextual relationship of polygons in the target sequence features to generate predicted target sequence data based on the target coding features;

[0037] A simulation prediction module is used to extract the vertex coordinates, edge direction and length information of each polygon from the target sequence data through the pre-trained large language model, so as to reconstruct the target geometric outline of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and output a complete lithography simulation layout combining all the target geometric outlines.

[0038] In a third aspect, the present application discloses an electronic device, comprising:

[0039] Memory, used to store computer programs;

[0040] A processor is used to execute the computer program to implement the steps of the aforementioned large language model-based lithography simulation method.

[0041] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned large language model-based lithography simulation method are implemented.

[0042] It can be seen that the present application discloses a lithography simulation method based on a large language model, including: obtaining a chip layout to be simulated, inputting the chip layout to be simulated into a pre-trained large language model, so that the chip layout to be simulated is traversed and encoded by the pre-trained large language model, generating sequence information of a single polygon, and splicing all the sequence information in sequence to obtain a complete layout sequence corresponding to the chip layout to be simulated; extracting sequence features of the complete layout sequence by the pre-trained large language model to obtain a target sequence feature, and then capturing the target coding feature representing the global context relationship of the polygon in the target sequence feature to generate predicted target sequence data based on the target coding feature; extracting the vertex coordinates, edge direction and length information of each polygon from the target sequence data by the pre-trained large language model, so as to reconstruct the target geometric outline of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and outputting a complete lithography simulation layout composed of all the target geometric outlines. This demonstrates that by directly serializing polygons, the original vector data is preserved, avoiding the dimensional expansion associated with rasterization. Furthermore, through precise encoding, the vector features of the original chip design are preserved, preventing loss of geometric information. A pre-trained large language model is used to extract the global spatial relationships of polygons in the layout, directly deserializing the predicted sequence to generate vector polygons, preserving geometric integrity. This not only enables dynamic capture of cross-regional process effects, but also enables end-to-end learning through the trained large language model, enabling mapping from serialized layouts to lithographic profiles without the need for manual rules, reducing human intervention and improving model generalization. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0044] Figure 1 A flow chart of a lithography simulation method based on a large language model disclosed in this application;

[0045] Figure 2 A diagram of the serialization process of a chip layout to be simulated disclosed in this application;

[0046] Figure 3 This is a model architecture diagram of a pre-trained large language model disclosed in this application;

[0047] Figure 4 Schematic diagram of an encoder and decoder for a pre-trained large language model disclosed in this application;

[0048] Figure 5 A diagram of the deserialization process of sequence data disclosed in this application;

[0049] Figure 6 This is a schematic structural diagram of a lithography simulation device based on a large language model disclosed in this application;

[0050] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0052] With the continuous advancement of technology, chip sizes are becoming smaller and smaller, while chip versatility is also increasing. Currently, domestic process technology has reached the 7-nanometer level, while international process technology has reached the 2-nanometer level, with even smaller process technologies likely to emerge in the future. This trend is leading to more efficient chips and increasing integration. Effective, accurate, and fast lithography simulation is becoming increasingly crucial for manufacturing. It also enables rapid performance evaluation and risk reduction during the design phase, thereby improving design and development efficiency. Traditional lithography simulation methods rely on classical Fourier optics theory to implement incomplete coherence imaging to calculate the light intensity distribution in the photoresist on the wafer. This is then combined with a classical photoresist model to simulate the photoresist pattern. To achieve higher accuracy at advanced process nodes, lithography simulation incorporates a scattering model for thick masks into the optical imaging model. Furthermore, both strict physical models and compact photoresist models must account for complex considerations such as the negative development photoresist effect.

[0053] The current state of chip manufacturing, which is constantly evolving, requires more complex scenarios. Furthermore, as chip sizes shrink, they must accommodate more and more elements, increasing the computational complexity. If traditional methods are used, performance will become a key constraint on the development of lithography simulation tools, requiring significant debugging effort to meet user precision requirements. Traditional lithography simulation methods require constant invocation of lithography simulation models, resulting in low efficiency. Image-based lithography machine learning models require rasterization of graphics, resulting in a loss of pattern accuracy. Furthermore, for efficiency reasons, the computational process cannot account for the influence of distant environmental graphics, impacting the accuracy of the final model results.

[0054] To this end, the present invention provides a lithography simulation solution based on a large language model, which can quickly and accurately simulate complex lithography graphics under different process scenarios and reduce the simulation process.

[0055] Reference Figure 1 As shown, the embodiment of the present application discloses a lithography simulation method based on a large language model, including:

[0056] Step S11: Obtain the chip layout to be simulated, and input the chip layout to be simulated into a pre-trained large language model so that the chip layout to be simulated is polygonally traversed and encoded by the pre-trained large language model to generate sequence information of a single polygon, and all the sequence information is spliced ​​in order to obtain a complete layout sequence corresponding to the chip layout to be simulated.

[0057] In this embodiment, an initial chip layout to be simulated is exported in a preset format, and polygon closure verification and coordinate accuracy verification are performed on the initial chip layout to be simulated to obtain a chip layout to be simulated that meets the conditions for lithography simulation. It is understood that the initial chip layout to be simulated is exported from a design tool in a format of GDS (Graphic Data System) or OASIS (Open Artwork System Interchange Standard), and then the layout data of the exported initial chip layout to be simulated is further verified to ensure that the exported initial chip layout to be simulated meets the requirements for lithography simulation (polygon closure, coordinate accuracy, etc.) to obtain the chip layout to be simulated.

[0058] In this embodiment, the semantic encoding layer of the pre-trained large language model takes the upper left corner vertex of the polygon as the starting point and traverses all edges of each polygon in the chip layout to be simulated in a clockwise direction; the direction information and length information of each edge in each polygon obtained by traversal are encoded to obtain the sequence information of a single polygon; the sequence information of each polygon is sequentially spliced ​​according to the arrangement order of each polygon in the chip layout to be simulated to obtain a complete layout sequence corresponding to the chip layout to be simulated. It can be understood that before the pre-trained large language model is simulated, the layout data of the chip layout to be simulated is serialized by the semantic encoding layer in front of the encoder. The serialization needs to retain the position and overall outline of each polygon in the original layout, and the serialized information is as little as possible to obtain a complete layout sequence corresponding to the chip layout to be simulated after serialization. Specifically, each polygon in the chip layout to be simulated is traversed and encoded by the semantic encoding layer, starting from the upper left corner vertex of the polygon, and traversing all edges in a clockwise direction. Further, the direction and length of each edge are recorded, wherein the edge direction recording rules are as follows:

[0059] Encoding the direction information of each edge of each polygon obtained through traversal according to a preset direction coding rule to obtain corresponding direction coding sequence information; wherein the preset direction coding rule is that the left direction is coded as 0, the right direction is coded as 1, the downward direction is coded as 2, and the upward direction is coded as 3;

[0060] The edge length recording rule is as follows: the length information of each edge in each polygon obtained by traversal is encoded according to a preset length encoding rule to obtain corresponding length encoding sequence information; wherein, the preset length encoding rule is to set the chip layout coordinate unit as the edge length unit;

[0061] Determine the sequence information of the corresponding single polygon based on the direction encoding sequence information and the length encoding sequence information.

[0062] As shown in Figure 2 As shown in the figure, the coordinates of all points of the polygon P1 are known, the length of each edge can be calculated, and the point at the top left corner of the polygon P1 is taken as the starting point V1, and each edge E1, E2, E3, E4 is recorded in the clockwise direction of the point, and the corresponding direction of each edge is recorded until the starting point V1 is reached. After all the edges of P1 are traversed, a vector is formed by the starting point and all the edges, that is, [V1, E1, E2, E3, E4], where V1 represents the coordinates of (x0, y0), and E* (which is the id number of the edge) represents (direction, d*), direction is the direction of edge traversal, mainly including four kinds: left, right, down and up, which can be replaced by four directions. Enumerate as numbers, left as 0, right as 1, down as 2, and up as 3, d* (which is the id number of the edge) is the length of the edge. Then add a start symbol and an end symbol, so the conversion format of the vector sequence is: [S, x0, y0, direction1, length1, direction2, length2,..., E], and the vector expression (sequence information) of [V1, E1, E2, E3, E4] converted according to the above conversion format is [S, x0, y0, 1, d1, 2, d2, 0, d3, 3, d4, E]. Further, all polygons P2, P3, P4, P5 in the layout are processed according to the sequence processing method of P1 to obtain the corresponding sequence information, that is, the vector data starting with S and ending with E is obtained, and these vectors are spliced together to form the serialized data [LS, P1, P2, P3, P4, P5, LE], where LS is the start symbol, LE is the end symbol, and P* corresponds to the vector of each polygon. In this way, the complete layout sequence corresponding to the chip layout to be simulated after serialization is obtained.

[0063] Step S12: performing sequence feature extraction on the complete layout sequence through the pre-trained large language model to obtain target sequence features, then capturing target encoding features representing the global context relationship of the polygons in the target sequence features, and generating predicted target sequence data based on the target encoding features.

[0064] In this embodiment, before the chip layout to be simulated is input into the pre-trained large language model, the following steps are further included: obtaining a plurality of historical chip layouts covering different process nodes and different layout scenes; wherein, the layout scene includes dense graphics and isolated graphics; performing photolithography simulation on each of the historical chip layouts to generate a corresponding photoresist contour as label data, so as to obtain a historical chip layout carrying label data; it can be understood that the GDS data (photoresist contour) generated by traditional photolithography simulation is divided into training set and test set according to 8:2. The training target of the large language model is to minimize the geometric distance between the predicted polygon and the real polygon, for example: the position deviation of the edge and the vertex. Specifically, collect historical chip layout data (layout) in GDSII or OASIS format from photolithography simulation tools or chip design databases, which contains a large amount of geometric information of polygons, to ensure that the data covers different process nodes (such as 7nm, 5nm) and complex scenes (such as dense graphics, isolated graphics), so as to enhance the generalization ability of the model. Use traditional photolithography simulation tools to simulate each historical chip layout to generate a corresponding photoresist contour as label data. The label data needs to include the accurate geometric shape (vertex coordinates and edge direction) of the polygon after lithography. According to the above serialization processing requirements, perform polygon encoding processing, single polygon sequence generation, and all polygon sequence splicing on the historical chip layout, so as to obtain a historical complete layout sequence carrying label data.

[0065] In this embodiment, each historical chip layout carrying label data is input into the large language model, so that the semantic encoding layer of the large language model performs polygon traversal and encoding on each of the historical chip layouts, to obtain a historical complete layout sequence corresponding to each of the historical chip layouts; based on the historical complete layout sequence and the label data sequence corresponding to the label data, a historical complete layout sequence carrying label data is generated; the large language model is trained using each historical complete layout sequence carrying label data, to obtain a pre-trained large language model which has learned the mapping relationship between the historical complete layout sequence and the target geometric contour after lithography. For example, Figure 3As shown, the model architecture of the large language model or pre-trained large language model of the present invention includes a semantic encoding layer 1, an embedding layer 1, and LLM (Large Language Model) encoders 1 to N on the encoder side; a semantic encoding layer 2, an embedding layer 2, LLM decoders 1 to N, and an output layer on the decoder side. Therefore, when training this large language model, the chip layout is the historical chip layout, and the label data is the photoresist profile corresponding to the historical chip layout. Therefore, semantic encoding layers 1 and 2 are primarily responsible for preprocessing the layout data / label data, converting it into corresponding sequence information. Each sequence information is then converted into a high-dimensional vector through embedding layers 1 and 2, and positionally encoded. The LLM core structure consists of two parts: a multi-layer encoder and a decoder, which is derived from the encoder and decoder of the Transformer architecture. The encoder encodes the sequence data, extracts the sequence's feature information, and then transmits it to the decoder at each layer. The decoder uses the encoder output data as part of its input and, through a multi-head self-attention mechanism, establishes and outputs polygonal relationships between points and edges (note that the output polygons are derived from the output label data). The final output layer consists of a fully connected layer and an activation function. The softmax operator then calculates the final predicted probability distribution. The predictions here primarily focus on the corresponding points and edges within the polygon. The final model loss calculates the distance between the predicted polygon composed of these points and edges and the output label data. Finally, there may be some discrepancies between the polygon predicted by the LLM model and the output polygon, which requires further fine-tuning using methods such as Optical Proximity Correction (OPC).

[0066] Specifically, the multi-head self-attention layer in the encoder of the large language model captures the proximity effect relationship and global layout association relationship between the polygons of each sequence element in the historical complete map sequence to obtain the attention-weighted feature vector; the residual connection layer in the encoder adds the attention-weighted feature vector and the input information of the multi-head self-attention layer to obtain the corresponding global feature; the target label data sequence before the current time step in the label data sequence is input into the decoder of the large language model, so as to predict the next label data sequence element based on the target label data sequence through the masked multi-head self-attention layer of the decoder; the output layer of the large language model generates a complete predicted label sequence time step by time based on the local features of the decoder output and the global features; the loss value of the complete predicted label sequence and the corresponding label data sequence is calculated by the loss function to reversely optimize the model parameters of the large language model based on the loss value result, until the iteration stop condition is met, and the current large language model is output as the pre-trained large language model. The method of generating a complete prediction label sequence based on the local features of the decoder output and the global features at each time step through the output layer of the large language model includes: using the local features output by the decoder as query vectors through the cross-attention layer of the decoder of the large language model to query the corresponding target global features from the global features as the corresponding keys and values ​​according to the query vector at the current time step, and performing weighted processing to obtain fused features; generating a complete prediction label sequence based on the fused features at each time step through the output layer of the large language model. Figure 4As shown in Figure 2, the encoder training process is as follows: Input information passes through the multi-head self-attention layer in the encoder of the large language model to capture the proximity effect relationships and global layout associations between polygons in each sequence element in the historical complete map sequence, thereby obtaining an attention-weighted feature vector. The multi-head self-attention mechanism is used to capture the global contextual relationships of polygons in the map, such as their spatial relationships and long-range dependencies. It is important to note that the multi-head self-attention layer's parallel computation of multiple attention heads during the extraction of global contextual relationships enhances the model's ability to understand complex contexts. Furthermore, the attention-weighted feature vector output by the multi-head attention is residually connected and standardized with the original input information through residual connection and layer normalization 1 to obtain the corresponding intermediate features (the original input information is integrated with the context dependency extracted by the self-attention mechanism). This can alleviate the problem of gradient disappearance in the model training process. The intermediate features are then input into the feedforward neural network 1 (two fully connected layers) for feature connection processing, and the feature connection results are residually connected and standardized again with the intermediate features output by the residual connection and layer normalization 1 to obtain high-level features. It should be noted that in this embodiment, only one LLM encoder is used as an example. In fact, N LLM encoders are set up. The processing process of each LLM encoder is the same as the processing process of a single LLM encoder in this embodiment, and the output result of the last LLM encoder is that as multiple encoder layers are processed (such as 6 layers), the features are gradually refined and highly abstract global features are output, such as the overall layout of the layout and process constraints. Next, the LLM decoder training process is as follows: After the input information is fed into the LLM decoder's masked multi-head self-attention layer, future time-step information is masked, forcing the model to rely solely on historical data to generate current predictions. Specifically, an upper triangular matrix is ​​used to mask the input sequence, masking some elements in the sequence (future time-step information). The model then predicts the masked area based on the current time-step elements, thereby achieving the purpose of training the model. The output of the masked multi-head self-attention layer is then connected and normalized with the original input information through residual connections and layer normalization 3 to obtain local features. Further, the local features are passed to the cross-attention layer. Based on the local features of the current time step, the cross-attention layer matches the corresponding key and value from the global features output by the LLM encoder. The cross-attention layer performs residual connections and normalization 4 to obtain the corresponding concatenation results. This concatenation result is then input into the feedforward neural network 2, residual connections, and layer normalization 5 for further feature processing to obtain the final fused features, thereby generating a complete predicted label sequence for each time step.Furthermore, the difference between the complete predicted label sequence and the label data is calculated through the cross loss function. With the goal of minimizing the difference value, the large language model is continuously iteratively trained until the difference value meets the preset threshold condition. The training is stopped to obtain a pre-trained large language model. The pre-trained large language model can complete simulation prediction based on the input sequence data of the chip layout to be simulated.

[0067] In this embodiment, the complete map sequence is input into the pre-trained large language model, and the sequence features and predictions are extracted by the encoder and decoder of the pre-trained large language model to generate the predicted target sequence data, such as Figure 5 As shown, the previous sequence is passed to the LLM model for calculation to obtain the expected sequence data. Taking P1 as an example, the target sequence data predicted by the LLM model is [V1', E1', E2', E3', E4', E5', E6', E7', E8'].

[0068] Step S13: Extract the vertex coordinates, edge direction and length information of each polygon from the target sequence data through the pre-trained large language model, reconstruct the target geometric outline of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and output the complete lithography simulation layout combining all the target geometric outlines.

[0069] In this embodiment, the serialization process of the layout data in the aforementioned steps is reversed to implement the deserialization of the target sequence data, and reconstruct the target geometric contours of each polygon of the chip layout to be simulated. It should be noted that the current target geometric contour is the predicted photoresist contour (target geometric contour). Finally, all the target geometric contours are combined in the aforementioned order to obtain a complete photolithography simulation layout.

[0070] It can be seen that the application discloses a photolithography simulation method based on a large language model, which comprises the following steps: obtaining a chip layout to be simulated, inputting the chip layout to be simulated into a pre-trained large language model, performing polygon traversal and coding on the chip layout to be simulated by using the pre-trained large language model, generating sequence information of a single polygon, and splicing all the sequence information in sequence to obtain a complete layout sequence corresponding to the chip layout to be simulated; performing sequence feature extraction on the complete layout sequence by using the pre-trained large language model to obtain target sequence features, then capturing target coding features representing the global context relationship of the polygons in the target sequence features, and generating predicted target sequence data based on the target coding features; extracting the vertex coordinates, edge direction and length information of each polygon from the target sequence data by using the pre-trained large language model, reconstructing the target geometric contour of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and outputting a complete photolithography simulation layout obtained by combining all the target geometric contours. It can be seen that, by directly performing serialization processing on the polygons, the original vector data is retained, the dimension expansion caused by rasterization is avoided, the original chip design vector features are retained by accurate coding, and the geometric information loss is avoided; the global spatial relationship of the polygons in the layout is extracted by using the pre-trained large language model, the vector polygons are generated by directly performing reverse serialization on the predicted sequence, and the geometric integrity is retained. Not only the dynamic capture of the process effects across regions is realized, but also the pre-trained large language model after training realizes end-to-end learning, realizes the mapping from the serialized layout to the photolithography contour, does not need manual rules, reduces manual intervention, and improves the model generalization capability.

[0071] Referring to Figure 6 The application also discloses a photolithography simulation device based on a large language model, which comprises the following components:

[0072] A sequence processing module 11 is configured to obtain a chip layout to be simulated, input the chip layout to be simulated into a pre-trained large language model, perform polygon traversal and coding on the chip layout to be simulated by using the pre-trained large language model, generate sequence information of a single polygon, and splice all the sequence information in sequence to obtain a complete layout sequence corresponding to the chip layout to be simulated.

[0073] A feature extraction module 12 is configured to perform sequence feature extraction on the complete layout sequence by using the pre-trained large language model to obtain target sequence features, then capture target coding features representing the global context relationship of the polygons in the target sequence features, and generate predicted target sequence data based on the target coding features.

[0074] The simulation prediction module 13 is used to extract the vertex coordinates, edge direction and length information of each polygon from the target sequence data through the pre-trained large language model, so as to reconstruct the target geometric outline of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and output a complete lithography simulation layout combining all the target geometric outlines.

[0075] It can be seen that the present application discloses obtaining a chip layout to be simulated, inputting the chip layout to be simulated into a pre-trained large language model, so that the pre-trained large language model is used to perform polygon traversal and encoding on the chip layout to be simulated, and sequence information of a single polygon is generated, and all sequence information is spliced ​​in sequence to obtain a complete layout sequence corresponding to the chip layout to be simulated; sequence feature extraction is performed on the complete layout sequence by the pre-trained large language model to obtain a target sequence feature, and then the target coding feature representing the global contextual relationship of the polygon in the target sequence feature is captured to generate predicted target sequence data based on the target coding feature; the vertex coordinates, edge direction and length information of each polygon are extracted from the target sequence data by the pre-trained large language model to reconstruct the target geometric outline of each polygon based on the vertex coordinates, edge direction and length information of each polygon, and a complete lithography simulation layout composed of all the target geometric outlines is output. This demonstrates that by directly serializing polygons, the original vector data is preserved, avoiding the dimensional expansion associated with rasterization. Furthermore, through precise encoding, the vector features of the original chip design are preserved, preventing loss of geometric information. A pre-trained large language model is used to extract the global spatial relationships of polygons in the layout, directly deserializing the predicted sequence to generate vector polygons, preserving geometric integrity. This not only enables dynamic capture of cross-regional process effects, but also enables end-to-end learning through the trained large language model, enabling mapping from serialized layouts to lithographic profiles without the need for manual rules, reducing human intervention and improving model generalization.

[0076] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram should not be considered as any limitation to the scope of application of the present application.

[0077] Figure 7A structural schematic diagram of an electronic device 20 is provided in the embodiments of the present application. The electronic device 20 can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is configured to store a computer program, and the processor 21 is configured to load and execute the computer program to implement the related steps in the photolithography simulation method based on a large language model disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the embodiments can be an electronic computer.

[0078] In the embodiments, the power supply 23 is configured to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 is capable of creating a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solutions of the present application, which is not specifically limited herein; the input / output interface 25 is configured to obtain external input data or output data to the outside world, and the specific interface type can be selected according to the specific application needs, which is not specifically limited herein.

[0079] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array) and a PLA (Programmable Logic Array). The processor 21 can also include a main processor and a coprocessor. The main processor is a processor for processing data in a wake-up state, also known as a CPU (Central Processing Unit). The coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 can also include an AI (Artificial Intelligence) processor for processing machine learning-related computing operations.

[0080] In addition, the memory 22 as a carrier for resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0081] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, so as to enable the processor 21 to calculate and process the massive amount of data 223 in the memory 22. The operating system 221 can be Windows Server, NetWare, Unix, Linux, etc. In addition to including computer programs capable of implementing the large language model-based lithography simulation method disclosed in any of the aforementioned embodiments and executed by the electronic device 20, the computer program 222 can further include computer programs capable of performing other specific tasks. The data 223 can include data received by the electronic device from external devices, as well as data collected by its own input and output interface 25.

[0082] Furthermore, this application discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned large language model-based lithography simulation method. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0083] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0084] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, various components have been described above generally in terms of their functionality, without limitation. The handwiring and software implementations of the examples described herein could be accomplished using any number of microprocessors, microcontrollers, programmable consumption logic devices, application-specific integrated circuits, or general-purpose computers with interconnecting circuits that either run software programs or use opencircuit or other hardware components that are designed to perform the functions described herein. The embodiments described herein can be implemented along with software modules, and the software modules can be stored on any of a variety of non-transitory machine-readable media. A non-transitory machine-readable medium includes any medium that participates in providing instructions to a processor for execution. Such a medium can take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical or magnetic disks and other persistent memory. Volatile media includes dynamic memories, and physical registers. Transmission media includes coaxial cables, copper wires and fiber optic cables, including wires that comprise bus conductors. Transmission media also can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media include, for example, a floppy disk, a flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc - Read Only Memory (CD-ROM), any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a programmable ROM (PROM), an erasable PROM (EPROM), a FLASH-EPROM, any other memory chip or cartridge, a carrier wave, a data signal, or any other medium from which a computer can read.

[0085] Finally, it should also be noted that, in the present text, relational terms such as first and second and the like can only be used to distinguish one entity or operation from another entity or operation, without necessarily implying any such actual relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an occurrence of the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus including the element.

[0086] The above has carried on the detailed introduction to the scheme provided by the present application, the principle and implementation mode of the present application are described by applying the specific examples in the present text, the above example explanation is only for helping the understanding of the method and core idea of the present application; simultaneously, for the general technical personnel of the field, according to the idea of the present application, there will be the change in the specific implementation mode and application range, the above-mentioned content should not be understood as the limitation of the present application.

Claims

1. A lithography simulation method based on a large language model, characterized in that: include: Obtaining a chip layout to be simulated, inputting the chip layout to be simulated into a pre-trained large language model, so as to perform polygon traversal and encoding on the chip layout to be simulated by the pre-trained large language model, generate sequence information of a single polygon, and sequentially splice all the sequence information to obtain a complete layout sequence corresponding to the chip layout to be simulated; Performing sequence feature extraction on the complete map sequence using the pre-trained large language model to obtain target sequence features, and then capturing target coding features representing the global contextual relationship of polygons in the target sequence features to generate predicted target sequence data based on the target coding features; Extracting vertex coordinates, edge direction, and length information of each polygon from the target sequence data using the pre-trained large language model, reconstructing a target geometric profile of each polygon based on the vertex coordinates, edge direction, and length information of each polygon, and outputting a complete lithography simulation layout combining all the target geometric profiles; Before inputting the chip layout to be simulated into the pre-trained large language model, the method further includes: Obtain several historical chip layouts covering different process nodes and different layout scenarios; where the layout scenarios include dense graphics and isolated graphics; Performing photolithography simulation on each of the historical chip layouts to generate a corresponding photoresist profile as label data to obtain a historical chip layout carrying the label data; Inputting each historical chip layout carrying the label data into the large language model so that the semantic encoding layer of the large language model performs polygon traversal and encoding on each historical chip layout to obtain a historical complete layout sequence corresponding to each historical chip layout; Based on the historical complete map sequence and the tag data sequence corresponding to the tag data, generating a historical complete map sequence carrying the tag data; The large language model is trained using each historical complete layout sequence carrying label data to obtain a pre-trained large language model that learns the mapping relationship between the historical complete layout sequence and the target geometric contour after lithography; The large language model includes an encoder, a decoder, and an output layer connected in sequence, wherein the large language model is trained using each historical complete layout sequence carrying label data to obtain a pre-trained large language model that learns the mapping relationship between the historical complete layout sequence and the target geometric contour after lithography, including: Capturing the proximity effect relationship and global layout association relationship between polygons of each sequence element in the historical complete map sequence through the multi-head self-attention layer in the encoder of the large language model to obtain an attention-weighted feature vector; The attention-weighted feature vector is added to the input information of the multi-head self-attention layer through the residual connection layer in the encoder to obtain the corresponding global feature; Inputting a target label data sequence before a current time step in the label data sequence into the decoder of the large language model, so as to predict a next label data sequence element based on the target label data sequence through a masked multi-head self-attention layer of the decoder; Generate a complete prediction label sequence time step by time based on the local features and the global features output by the decoder through the output layer of the large language model; The loss function is used to calculate the loss value of the complete predicted label sequence and the corresponding label data sequence, so as to reversely optimize the model parameters of the large language model based on the loss value result until the iteration stop condition is met, and the current large language model is output as the pre-trained large language model.

2. The lithography simulation method based on a large language model according to claim 1, characterized in that: The obtaining of the chip layout to be simulated includes: An initial chip layout to be simulated in a preset format is exported, and a multi-deformation closure check and a coordinate accuracy check are performed on the initial chip layout to be simulated to obtain a chip layout to be simulated that meets photolithography simulation conditions.

3. The lithography simulation method based on a large language model according to claim 1, characterized in that: The method of performing polygon traversal and encoding on the chip layout to be simulated by using the pre-trained large language model to generate sequence information of a single polygon, and sequentially splicing all sequence information to obtain a complete layout sequence corresponding to the chip layout to be simulated includes: Using the semantic encoding layer of the pre-trained large language model, starting from the upper left corner vertex of the polygon, traverse all edges of each polygon in the chip layout to be simulated in a clockwise direction; The direction information and length information of each edge in each polygon obtained by traversal are encoded to obtain the sequence information of a single polygon; The sequence information of each polygon is sequentially spliced ​​according to the arrangement order of the polygons in the chip layout to be simulated, so as to obtain a complete layout sequence corresponding to the chip layout to be simulated.

4. The lithography simulation method based on a large language model according to claim 3, characterized in that: The encoding process is performed on the direction information and length information of each edge in each polygon obtained through traversal to obtain sequence information of a single polygon, including: Encoding the direction information of each edge of each polygon obtained through traversal according to a preset direction coding rule to obtain corresponding direction coding sequence information; wherein the preset direction coding rule is that the left direction is coded as 0, the right direction is coded as 1, the downward direction is coded as 2, and the upward direction is coded as 3; The length information of each edge of each polygon obtained by traversal is encoded according to a preset length encoding rule to obtain corresponding length encoding sequence information; wherein the preset length encoding rule is to set the chip layout coordinate unit as the edge length unit; The sequence information of the corresponding single polygon is determined based on the direction coding sequence information and the length coding sequence information.

5. The lithography simulation method based on a large language model according to claim 1, characterized in that: Generating a complete prediction label sequence time-step by time-step based on the local features and the global features output by the decoder through the output layer of the large language model includes: Using the cross-attention layer of the decoder of the large language model as a query vector, the local features output by the decoder are used to query the corresponding target global features from the global features according to the query vector at the current time step as the corresponding key and value, and performing weighted processing to obtain a fused feature; A complete predicted label sequence is generated through the output layer of the large language model and based on the fused features at each time step.

6. A lithography simulation device based on a large language model, characterized in that: include: a sequence processing module, configured to obtain a chip layout to be simulated, input the chip layout to be simulated into a pre-trained large language model, perform polygon traversal and encoding on the chip layout to be simulated by the pre-trained large language model, generate sequence information of a single polygon, and sequentially concatenate all the sequence information to obtain a complete layout sequence corresponding to the chip layout to be simulated; a feature extraction module, configured to perform sequence feature extraction on the complete layout sequence using the pre-trained large language model to obtain target sequence features, and then capture target coding features representing the global contextual relationship of polygons in the target sequence features to generate predicted target sequence data based on the target coding features; a simulation prediction module, configured to extract the vertex coordinates, edge direction, and length information of each polygon from the target sequence data using the pre-trained large language model, reconstruct the target geometric profile of each polygon based on the vertex coordinates, edge direction, and length information of each polygon, and output a complete lithography simulation layout composed of all the target geometric profiles; The lithography simulation device is further used to obtain several historical chip layouts covering different process nodes and different layout scenarios; wherein the layout scenarios include dense graphics and isolated graphics; perform lithography simulation on each of the historical chip layouts to generate a corresponding photoresist contour as label data to obtain a historical chip layout carrying label data; input each of the historical chip layouts carrying label data into a large language model so that the semantic encoding layer of the large language model performs polygon traversal and encoding on each of the historical chip layouts to obtain a historical complete layout sequence corresponding to each of the historical chip layouts; based on the historical complete layout sequence and the label data sequence corresponding to the label data, generate a historical complete layout sequence carrying label data; use each of the historical complete layout sequences carrying label data to train the large language model to obtain a pre-trained large language model that has learned the mapping relationship between the historical complete layout sequence and the target geometric contour after lithography; the large language model includes an encoder, a decoder, and an output layer connected in sequence; The lithography simulation device is also used to capture the proximity effect relationship and global layout association relationship between polygons between sequence elements in the historical complete layout sequence through the multi-head self-attention layer in the encoder of the large language model to obtain an attention-weighted feature vector; add the attention-weighted feature vector and the input information of the multi-head self-attention layer through the residual connection layer in the encoder to obtain the corresponding global feature; input the target label data sequence before the current time step in the label data sequence into the decoder of the large language model, so as to predict the next label data sequence element based on the target label data sequence through the masked multi-head self-attention layer of the decoder; generate a complete predicted label sequence time step by time based on the local features and the global features output by the decoder through the output layer of the large language model; calculate the loss value of the complete predicted label sequence and the corresponding label data sequence through the loss function, so as to reversely optimize the model parameters of the large language model based on the loss value result, until the iteration stop condition is met, and output the current large language model as the pre-trained large language model.

7. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the lithography simulation method based on a large language model as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that Used to store a computer program; wherein, when the computer program is executed by a processor, the steps of the lithography simulation method based on a large language model as described in any one of claims 1 to 5 are implemented.

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