Gear adjusting circuit, chip and electronic equipment

Abstract

The invention discloses a gear adjusting circuit, a chip and electronic equipment, and belongs to the technical field of display electronics. The gear adjusting circuit comprises a control signal adjusting circuit, a selector and a low dropout regulator. The control signal adjusting circuit is used for receiving the M first control signals and outputting L second control signals to the selector; the selector is used for sequentially selecting reference voltage from the voltage of at least three gears under the control of L second control signals and providing the reference voltage for the low dropout linear regulator, and the reference voltage is increased by at least two gears gear by gear along with time; and the low dropout linear regulator is used for outputting power supply voltage according to the sequentially selected reference voltage. According to the low-dropout linear regulator, the reference voltage is increased for multiple times, and only one gear is increased each time, so that the single-time increasing amplitude of the reference voltage is reduced, the peak value of overshoot current generated in the low-dropout linear regulator is reduced, the performance of a circuit is improved, and the service life of the circuit is prolonged.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display electronic technology, and in particular to a gear adjustment circuit, a chip, and an electronic device. Background Art

[0002] With the development of display electronics technology, the resolution and refresh rate of displays are getting higher and higher, which requires the circuits inside the chip to provide a lower supply voltage. In the actual chip design process, considering factors such as circuit performance and power consumption, the gear adjustment circuit is often used to provide the supply voltage.

[0003] In related technologies, the gear adjustment circuit includes a selector and a low-dropout linear regulator (LDO). The selector is used to provide a reference voltage to the LDO, which then outputs a supply voltage based on the reference voltage. If the reference voltage jumps from a lower gear to a higher gear, the LDO's internal feedback will cause an overshoot current, affecting the circuit's performance and lifespan. Summary of the Invention

[0004] The present application provides a gear adjustment circuit, chip, and electronic device that can reduce the peak overshoot current generated inside the LDO and improve the performance and life of the circuit. The technical solution includes the following contents.

[0005] In one aspect, a gear adjustment circuit is provided, the gear adjustment circuit comprising a control signal adjustment circuit, a selector and a low-voltage dropout linear regulator, wherein the selector is connected to the control signal adjustment circuit and the low-voltage dropout linear regulator;

[0006] The control signal conditioning circuit is configured to receive M first control signals and output L second control signals to the selector, where L and M are both positive integers, wherein when the M first control signals collectively instruct to increase the reference voltage by at least two levels at once, the L second control signals collectively instruct to increase the reference voltage by at least two levels over time;

[0007] The selector is configured to receive voltages of at least three gears, and under the control of the L second control signals, sequentially select a reference voltage from the voltages of the at least three gears, and provide the sequentially selected reference voltages to the low-dropout linear regulator, wherein the reference voltage increases by at least two gears over time.

[0008] The low voltage dropout linear regulator is used to output a supply voltage according to the reference voltages selected in sequence.

[0009] On the other hand, a chip is provided, which includes the gear adjustment circuit described above.

[0010] On the other hand, an electronic device is provided, comprising the chip described above.

[0011] The technical solution provided by this application brings at least the following beneficial effects:

[0012] In the technical solution provided in this application, a control signal conditioning circuit can receive M first control signals and output L second control signals to a selector. The selector can receive at least three voltage levels and, based on the L second control signals, select a voltage level from the at least three voltage levels to obtain a reference voltage, and then provide the reference voltage to a low-dropout linear regulator. Since the M first control signals instruct to increase the reference voltage level by at least two levels, the L second control signals instruct to increase the reference voltage level by at least two levels step by step. Therefore, the selector can increase the reference voltage multiple times, and each time the reference voltage is increased, the increased reference voltage is only increased by one level relative to the reference voltage before the increase.

[0013] Compared to increasing the reference voltage by at least two levels at once, increasing the reference voltage multiple times, each time by only one level, reduces the magnitude of the reference voltage increase. By reducing the magnitude of the single reference voltage increase during the process of the low-dropout linear regulator outputting a supply voltage based on the reference voltage, the peak value of the overshoot current generated within the low-dropout linear regulator is reduced, thereby reducing the impact of the overshoot current on the circuit and improving the circuit's performance and lifespan. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 This is a structural diagram of an LDO provided by related technology;

[0016] Figure 2 This is a structural diagram of a gear adjustment circuit provided by the relevant technology;

[0017] Figure 3 This is a schematic structural diagram of a gear adjustment circuit provided in an embodiment of the present application;

[0018] Figure 4 This is a structural diagram of another gear adjustment circuit provided in an embodiment of the present application;

[0019] Figure 5This is a schematic structural diagram of a delay unit provided in an embodiment of the present application;

[0020] Figure 6 This is a schematic diagram of the structure of an encoder provided in an embodiment of the present application;

[0021] Figure 7 This is a flow chart of adjusting voltage levels provided by an embodiment of the present application;

[0022] Figure 8 This is a timing diagram of a signal provided in an embodiment of the present application;

[0023] Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0024] Figure 10 This is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0026] It should be noted that the terms "first," "second," and the like in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0027] With the development of display electronics technology, the resolution and refresh rate of displays are getting higher and higher, which requires the display driver integrated circuit (DDIC) to be able to transmit display information at a higher rate. To meet the DDIC's ability to transmit high-speed data, more advanced processes are often used, which also requires a lower supply voltage within the circuit. Generally, a low dropout linear regulator (LDO) can be added inside the DDIC to provide a lower supply voltage.

[0028] In the field of semiconductor integrated circuits, LDO is a common voltage stabilization circuit that can provide a stable power supply voltage to other circuits. In practical applications, LDO includes P-type LDO and N-type LDO. Among them, P-type LDO is a circuit implemented based on PMOS (P-Channel Metal Oxide Semiconductor), while N-type LDO is a circuit implemented based on NMOS (N-Channel Metal Oxide Semiconductor). The implementation principles of the two are similar. Below, taking P-type LDO as an example, the circuit structure and implementation process of P-type LDO are explained. The circuit structure and implementation process of N-type LDO are similar and will not be repeated in the embodiments of this application.

[0029] like Figure 1 As shown, Figure 1 The circuit structure of a P-type LDO is shown. The P-type LDO includes an error amplifier (EA), a transistor (also called a power transistor) PM0, a resistor R1, a resistor R2, a resistor ESR, and a capacitor Clext.

[0030] Among them, transistor PM0 is a PMOS. In this example, the output of the error amplifier EA is connected to the gate of transistor PM0, the source of transistor PM0 is connected to the power supply, and the drain of transistor PM0 is connected to the output of a P-type LDO, which is used to provide the power supply voltage VDDR. One end of resistor R1 is connected to the drain of transistor PM0, the other end of resistor R1 is connected to one end of resistor R2, and the other end of resistor R2 is grounded. Resistors R1 and R2 form a sampling module for sampling the power supply voltage VDDR and obtaining the feedback voltage VFB. The positive input of the error amplifier EA (i.e., the non-inverting input, referred to as the positive terminal) is connected to the connection node between resistors R1 and R2 and is used to receive the feedback voltage VFB. The negative input of the error amplifier EA (i.e., the inverting input, referred to as the negative terminal) receives the reference voltage VBGR. In addition, the power supply terminal of the error amplifier EA is connected to the power supply. One end of the resistor ESR is connected to the output end of the P-type LDO, the drain of the transistor PM0, and one end of the resistor R1. The other end of the resistor ESR is connected to one end of the capacitor Clext. The other end of the capacitor Clext is grounded.

[0031] When the P-type LDO is in steady state, capacitor Clext no longer charges or discharges, and the supply voltage VDDR remains stable. Resistors R1 and R2 sample the supply voltage VDDR to generate feedback voltage VFB, which is then input to the error amplifier EA. Based on the error between feedback voltage VFB and reference voltage VBGR, the error amplifier EA generates a control voltage VG, which controls the on-current of transistor PM0. Since the circuit is in steady state, the value of control voltage VG remains unchanged, resulting in a constant on-current of transistor PM0 and, consequently, constant supply voltage VDDR. At this point, the P-type LDO can provide a stable supply voltage VDDR.

[0032] LDOs can provide a stable supply voltage to power the load. During chip design, considering factors such as circuit performance and power consumption, LDOs can provide multiple supply voltage levels. In practical applications, the LDO can output the appropriate supply voltage level to power the corresponding load.

[0033] Since the supply voltage provided by the LDO is related to the input reference voltage, the supply voltage output by the LDO can be adjusted by inputting different reference voltages to the LDO. Figure 2 As shown, Figure 2 The figure shows a gear adjustment circuit. The gear adjustment circuit includes a bandgap reference circuit (BGR) 01, a multiplexer (MUX) 02, and an LDO 03. BGR01 is used to provide multiple gear voltages to MUX02. For ease of description, assuming that BGR01 provides N+1 gear voltages to MUX02, the voltages of N+1 gears can be expressed in sequence as: VREF <1> 、……、VREF<N+1> , N is a positive integer. MUX02 can receive multiple control signals provided by the external circuit. For the convenience of description, it is assumed that the external circuit provides M control signals, then the M control signals can be expressed as LV <m:1>, M is a positive integer. MUX02 receives the control signal LV <m:1>After that, according to the control signal LV <m:1>, select a voltage from the N+1 voltage levels to get the reference voltage VBGR. For example, MUX02 selects the voltage VREF <1> , then the reference voltage VBGR is the voltage VREF <1> MUX02 provides reference voltage VBGR to LDO03, so that LDO03 can output power supply voltage VDDR. <m:1>, control MUX02 to select reference voltage VBRG of different gears, thereby controlling LDO03 to output power supply voltage VDDR of different gears.

[0034] If the reference voltage VBRG switches from a high-range voltage to a low-range voltage, the control voltage VG increases, increasing the resistance of transistor PM0 and reducing its on-current. At this point, capacitor Clext discharges, causing the supply voltage VDDR to decrease. After the supply voltage VDDR is sampled by resistors R1 and R2, the feedback voltage VFB decreases. Through feedback, the LDO reduces the feedback voltage VFB when the reference voltage VBRG decreases. This reduces the difference between the positive and negative voltages of the error amplifier EA, thereby suppressing any increase in the control voltage VG. Ultimately, the LDO returns to a steady state, maintaining the supply voltage VDDR constant.

[0035] Conversely, if the reference voltage VBRG switches from a low-range voltage to a high-range voltage, the control voltage VG decreases, reducing the resistance of transistor PM0, thereby increasing the on-current of transistor PM0. At this time, capacitor Clext charges, causing the supply voltage VDDR to increase. After the supply voltage VDDR is sampled by resistors R1 and R2, the feedback voltage VFB increases. Through feedback, the LDO increases the feedback voltage VFB when the reference voltage VBRG increases, reducing the difference between the positive and negative terminal voltages of the error amplifier EA, thereby suppressing the decrease in the control voltage VG. Ultimately, the LDO can return to a steady state, maintaining the supply voltage VDDR unchanged.

[0036] During circuit startup or switching, the current can momentarily exceed its stable value before returning to its stable value. This current is often referred to as overshoot. As previously mentioned, when the reference voltage VBRG switches from a low-range voltage to a high-range voltage, the on-state current of transistor PM0 increases, resulting in an overshoot current that charges capacitor Clext. It's understandable that the greater the increase in the reference voltage VBRG, the greater the peak overshoot current. This can easily lead to the following problems:

[0037] 1. The peak value of the overshoot current is large, which will cause the circuit wiring to generate a lot of heat due to the current overload, and there is a problem of burning the wiring;

[0038] 2. If the reference voltage VBRG is switched from a low-level voltage to a high-level voltage multiple times, the heat accumulated due to overshoot current will be difficult to dissipate, causing the circuit to overheat and affecting the performance and life of the circuit.

[0039] 3. In practical applications, an external power management integrated circuit (PMIC) can provide power to multiple DDICs. Furthermore, each DDIC can include multiple LDOs. If the reference voltage VBRG of several LDOs switches from a low-range voltage to a high-range voltage simultaneously, the combined effect will generate a larger overshoot current, triggering the PMIC's current overload protection mechanism. This can cause the PMIC to power down abnormally, degrading circuit performance.

[0040] Based on the above problems, an embodiment of the present application provides a gear adjustment circuit, which can reduce the peak value of the overshoot current generated inside the LDO. By reducing the peak value of the overshoot current, on the one hand, the phenomenon of current overload is reduced, thereby reducing the heat generated by the circuit, and further reducing the phenomenon of wiring burnout. On the other hand, because the heat generated by the circuit is low, the performance and life of the circuit can be improved. On the other hand, because a single LDO generates an overshoot current with a low peak value, the peak value of the superimposed overshoot current will also be low, which can reduce the situation of abnormal power failure of the PMIC, thereby improving the performance of the circuit.

[0041] The gear adjustment circuit provided by the embodiment of the present application is described in detail below. Figure 3 As shown, the gear adjustment circuit 00 includes a control signal adjustment circuit 10, a selector 20, and a low-dropout linear regulator 30 (hereinafter referred to as LDO 30). The selector 20 is connected to the control signal adjustment circuit 10 and the LDO 30. Specifically, the output end of the control signal adjustment circuit 10 is connected to the input end of the selector 20, and the output end of the selector 20 is connected to the input end of the LDO 30.

[0042] like Figure 4 As shown, Figure 4 The figure shows a gear adjustment circuit 00. The gear adjustment circuit 00 includes a control signal adjustment circuit 10, a MUX (selector) 20, and an LDO 30. The output of the control signal adjustment circuit 10 is connected to the input of the MUX 20, and the output of the MUX 20 is connected to the input of the LDO 30. Optionally, the gear adjustment circuit 00 also includes a BGR 40, the output of which is connected to the input of the MUX 20.

[0043] The control signal adjustment circuit 10 is configured to receive M first control signals and output L second control signals to the selector 20 , where L and M are both positive integers.

[0044] Optionally, M is a positive integer greater than 1, and L is a positive integer greater than M, for example, M=2, L=4. For ease of description, the M first control signals are recorded as LV <m:1>, where the first control signal is LV <1> , the second first control signal is LV <2> , the third first control signal is LV <3> , and so on, the Mth first control signal is LV <m>Similarly, the L second control signals are recorded as LVS <l:1>, where the first second control signal is LVS <1> , the second control signal is LVS <2> , the third second control signal is LVS <3> , and so on, the Lth second control signal is LVS <l>.

[0045] like Figure 4 As shown, the control signal adjustment circuit 10 can receive M first control signals LV provided by an external circuit. <m:1>and provide L second control signals LVS to MUX20 <l:1>Optionally, N is a positive integer greater than M, for example, N=3, and L is a positive integer greater than N, for example, L=N+1. In this case, the L second control signals LVS <l:1>Also known as LVS<N+1:1> .

[0046] The embodiment of the present application does not limit the circuit structure, implementation principle, etc. of the external circuit, and any M first control signals LV can be generated. <m:1>All circuits can be used as external circuits.

[0047] M first control signals LV <m:1>Used to indicate the reference voltage level. Taking M=2 as an example, assuming there are four levels of voltage, in order from low to high, the four levels are level 0, level 1, level 2, and level 3, and the voltages of the four levels are voltage 0, voltage 1, voltage 2, and voltage 3. <m:1>=00, used to indicate gear position 0. In this case, the reference voltage = voltage 0; LV <m:1>=01, used to indicate gear position 1. In this case, the reference voltage = voltage 1; LV <m:1>=10, used to indicate gear position 2. In this case, the reference voltage = voltage 2; LV <m:1>=11, used to indicate gear position 3. In this case, the reference voltage = voltage 3.

[0048] It is understandable that at different times, the M first control signals LV <m:1>Based on this, the M first control signals can collectively indicate the gear to increase the reference voltage, or collectively indicate the gear to decrease the reference voltage, or collectively indicate that the gear of the reference voltage remains unchanged. The reference voltage can be increased or decreased by at least one gear. For example, LV <m:1>When it changes from 00 to 01, the reference voltage increases by one level, LV <m:1>When it jumps from 11 to 00, the reference voltage decreases by three levels.

[0049] L second control signals LVS <l:1>It is also used to indicate the reference voltage level. Taking L=4 as an example, assuming there are four voltage levels, in order from low to high, the four levels are level 0, level 1, level 2, and level 3, and the voltages of the four levels are voltage 0, voltage 1, voltage 2, and voltage 3. <l:1>=0001, used to indicate gear position 0. In this case, the reference voltage = voltage 0; LVS <l:1>=0010, used to indicate gear position 1. In this case, the reference voltage = voltage 1; LVS <l:1>=0100, used to indicate gear position 2. In this case, the reference voltage = voltage 2; LVS <l:1>=1000, used to indicate gear position 3. In this case, the reference voltage = voltage 3.

[0050] It is understandable that at different times, the L second control signals LVS <l:1>The L second control signals may indicate the same or different gears. Based on this, the L second control signals may indicate the gear to increase the reference voltage, may indicate the gear to decrease the reference voltage, or may indicate that the gear of the reference voltage remains unchanged. The reference voltage may be increased or decreased by at least one gear. For example, LVS <l:1>When it changes from 0001 to 0010, the reference voltage increases by one level, and LVS <l:1>When it jumps from 1000 to 0001, the reference voltage decreases by three levels.

[0051] It should be noted that at the same time, M first control signals LV <m:1>and L second control signals LVS <l:1>Can indicate the same or different gears. For example, when LV <m:1>=11, when used to indicate gear position 3, the following situations may exist: 1. LVS <l:1>=0010, used to indicate gear position 1; 2, LVS <l:1>=0100, used to indicate gear position 2; 3, LVS <l:1>=1000, used to indicate gear position 3.

[0052] Wherein, when the M first control signals collectively indicate that the level of the reference voltage is increased by at least two levels at one time, the L second control signals collectively indicate that the reference voltage is increased by at least two levels over time. <m:1>When the reference voltage jumps from 00 to 11, it increases by three levels. In this case: First, the second control signal LVS <l:1>Jump from 0001 to 0010, so as to increase the reference voltage by one level first; then, the second control signal LVS <l:1>The second control signal LVS jumps from 0010 to 0100, thereby increasing the reference voltage by one level. <l:1>Jump from 0100 to 1000 to increase the reference voltage by one level.

[0053] Optionally, when the M first control signals indicate that the reference voltage level is increased by one level, the L second control signals indicate that the reference voltage level is increased by one level. When the M first control signals indicate that the reference voltage level is decreased by at least one level, the L second control signals indicate that the reference voltage level is decreased by at least one level all at once, or the L second control signals indicate that the reference voltage level is decreased by at least one level step by step.

[0054] In one possible implementation, Figure 4 As shown, the control signal conditioning circuit 10 includes a decoder 101, a hierarchical delay device 102, and an encoder 103. The hierarchical delay device 102 is connected to the decoder 101 and the encoder 103, and the encoder 103 is connected to the selector 20. Specifically, the output end of the decoder 101 is connected to the input end of the hierarchical delay device 102, the output end of the hierarchical delay device 102 is connected to the input end of the encoder 103, and the output end of the encoder 103 is connected to the input end of the MUX 20.

[0055] The decoder 101 is configured to receive M first control signals and output N third control signals to the hierarchical delay 102 , wherein the M first control signals and the N third control signals indicate the same information, and N is a positive integer greater than 2.

[0056] Optionally, N is a positive integer greater than M, for example, M=2, N=3. In an exemplary embodiment, N=2 M -1. For ease of description, the N third control signals are recorded as LVL <n:1>, where the first third control signal is LVL <1> , the second and third control signals are LVL <2> , the third control signal is LVL <3> , and so on, the Nth third control signal is LVL <n>.

[0057] N third control signals are recorded as LVL <n:1>Used to indicate the reference voltage level. Taking N=3 as an example, assuming there are four levels of voltage, in order from low to high, the four levels are level 0, level 1, level 2, and level 3, and the voltages of the four levels are voltage 0, voltage 1, voltage 2, and voltage 3. <n:1>=000, used to indicate gear position 0. In this case, the reference voltage = voltage 0; LVL <n:1>=001, used to indicate gear position 1. In this case, the reference voltage = voltage 1; LVL <n:1>=011, used to indicate gear position 2. In this case, the reference voltage = voltage 2; LVL <n:1>=111, used to indicate gear position 3. In this case, the reference voltage = voltage 3.

[0058] It should be noted that, at different times, N third control signals are recorded as LVL <n:1>Based on this, the N third control signals can indicate the gear to increase the reference voltage, the gear to decrease the reference voltage, or the gear to keep the reference voltage unchanged. The reference voltage can be increased or decreased by at least one gear. For example, LVL <n:1>When it changes from 011 to 111, the reference voltage increases by one level, LV <m:1>When it jumps from 111 to 000, the reference voltage decreases by three levels.

[0059] In addition, at the same time, M first control signals LV <m:1>and N third control signals LVL <n:1>Indicates the same gear. For example, when LV <m:1>=11, used to indicate gear position 3, LVL <n:1>=111, also used to indicate gear 3. The M first control signals indicate that the gear of the reference voltage is increased by at least one gear, and the N third control signals also indicate that the gear of the reference voltage is increased by at least one gear; the M first control signals indicate that the gear of the reference voltage is decreased by at least one gear, and the N third control signals also indicate that the gear of the reference voltage is decreased by at least one gear.

[0060] The input terminal of the decoder 101 receives M first control signals LV <m:1>, outputs N third control signals LVL to the hierarchical delay 102 <n:1>The way the first control signal is converted into the third control signal is the same as the way binary code is converted into thermometer code. In practical applications, a truth table can be set up, and the decoder 101 converts the binary code into thermometer code according to the truth table.

[0061] The present application embodiment does not limit the content of the truth table. For example, M=2, N=3, L=N+1=4, then the truth table can be as shown in Table 1 below:

[0062] Table 1

[0063] LV<2:1> LVL<3:1> LVS<4:1> Voltage range 00 000 0001 Gear 0 01 001 0010 Gear 1 10 011 0100 Gear 2 11 111 1000 Gear 3

[0064] For another example, M=3, N=7, L=N+1=8, then the truth table can be shown in Table 2 below:

[0065] Table 2

[0066] LV<3:1> LVL<7:1> LVS<8:1> Voltage range 000 0000000 00000001 Gear 0 001 0000001 00000010 Gear 1 010 0000011 00000100 Gear 2 011 0000111 00001000 Gear 3 100 0001111 00010000 Gear 4 101 0011111 00100000 Gear 5 110 0111111 01000000 Gear 6 111 1111111 10000000 Gear 7

[0067] The hierarchical delay device 102 is used to output the first fourth control signal to the encoder 103 according to the first third control signal, and output the i-th fourth control signal to the encoder 103 according to the i-th third control signal and the i-1-th fourth control signal, where i is any positive integer between 2 and N.

[0068] The input end of the hierarchical delay 102 receives N third control signals LVL <n:1>The output end of the hierarchical delay 102 provides N fourth control signals to the encoder 103. For ease of description, the N fourth control signals are recorded as LVD <n:1>, where the first fourth control signal is LVD <1> , the second fourth control signal is LVD <2> , the third and fourth control signals are LVD <3> , and so on, the Nth fourth control signal is LVD <n>.

[0069] Specifically, the hierarchical delay device 102 can be configured to generate a first third control signal LVL according to the first third control signal LVL. <1> , outputs the first fourth control signal LVD to the encoder 103 <1> ; According to the second third control signal LVL <2> and the 1st fourth control signal LVD <1> , outputs the second fourth control signal LVD to the encoder 103 <2> ; According to the third third control signal LVL <3> and the 2nd fourth control signal LVD <2> , outputs the third fourth control signal LVD to the encoder 103 <3> The same process is repeated until the Nth third control signal LVL is generated. <n>and the N-1th fourth control signal LVD <n-1>, outputs the Nth fourth control signal LVD to the encoder 103 <n>.

[0070] In an exemplary embodiment, the hierarchical delay unit 102 includes N delay units connected in series. Figure 5 As shown, the i-th delay unit A is used to determine the value of the third control signal LVL according to the i-th delay unit A. and the i-1th fourth control signal LVD <i-1>, outputs the i-th fourth control signal LVD to the encoder 103 Among them, in the i-1th fourth control signal LVD <i-1>and the i-th third control signal LVL When both have rising edges, the i-th fourth control signal LVD There is a delay in switching on the rising edge of .

[0071] Specifically, for N third control signals indicating that the level of the reference voltage is increased by at least one level, if the i-th third control signal LVL Switched from low level to high level, that is, the i-th third control signal LVL There is a rising edge, and the i-1th fourth control signal LVD <i-1>Also switches from low level to high level, i.e. the i-1th fourth control signal LVD <i-1>There is also a rising edge. In this case, the i-th fourth control signal LVD Switched from low level to high level, that is, the i-th fourth control signal LVD There is a rising edge, and the i-th fourth control signal LVD The switching time is related to the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>There is a certain time difference between the switching times. That is to say, the i-th fourth control signal belongs to delayed switching.

[0072] like Figure 5 As shown, the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>All are switched from low level to high level, that is, the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>There is a rising edge H1. In this case, the i-th fourth control signal LVD Switching from low level to high level with delay, that is, the ith fourth control signal LVD There is a rising edge H2 , and compared with the rising edge H1 , the rising edge H2 delays switching, so that there is a certain switching time difference between the rising edge H2 and the rising edge H1 .

[0073] In addition, for N third control signals indicating that the level of the reference voltage is reduced by at least one level, if any of the following conditions exists: 1. The i-th third control signal LVL Switched from low level to high level, the i-1th fourth control signal LVD <i-1>Switched from high level to low level; 2. The i-th third control signal LVL Switched from high level to low level, the i-1th fourth control signal LVD <i-1>Switched from low level to high level. In this case, the i-th fourth control signal LVD There is no level switching.

[0074] For N third control signals indicating that the level of the reference voltage is reduced by at least one level, if the i-th third control signal LVL Switched from high level to low level, the i-1th fourth control signal LVD <i-1>Switched from high level to low level. In this case, the i-th fourth control signal LVD Switched from high level to low level. Optionally, the i-th fourth control signal LVD It is not a delayed switch.

[0075] like Figure 5 As shown, the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>All are switched from high level to low level, that is, the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>There is a falling edge L1. In this case, the i-th fourth control signal LVD Switch from high level to low level immediately, that is, the i-th fourth control signal LVD There is a falling edge L2 , and there is no switching time difference between the falling edge L2 and the falling edge L1 .

[0076] In practical applications, any circuit that can delay the switching of the rising edge can be used as the i-th delay unit A in the embodiment of the present application. Figure 5 As shown, the i-th delay unit A includes a first logic gate 120 and a delay component B, and the first logic gate 120 is connected to the delay component B. Specifically, one input end of the first logic gate 120 is connected to the output end of the decoder 101, the other input end of the first logic gate 120 is connected to the output end of the (i-1)-th delay unit A, the output end of the first logic gate 120 is connected to the input end of the delay component B, and the output end of the delay component B is the output end of the i-th delay unit A.

[0077] It is understood that the circuit structure and implementation of the first delay unit A and the i-th delay unit A are similar. That is, the first delay unit A includes a first logic gate 120 and a delay component B, and the first logic gate 120 is connected to the delay component B. Since there is no output terminal of the (i-1)-th delay unit A, in this case, one input terminal of the first logic gate 120 is connected to the output terminal of the decoder 101, the other input terminal of the first logic gate 120 is connected to a logic high level, and the output terminal of the first logic gate 120 is connected to the input terminal of the delay component B. The output terminal of the delay component B is the output terminal of the first delay unit A.

[0078] The first logic gate 120 is used to output the first synthesis signal LVI to the delay component B according to the i-th third control signal and the i-1-th fourth control signal. .

[0079] The first logic gate 120 may include at least one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, and an XNOR gate. The specific type of the first logic gate 120 may be flexibly set according to the needs of the actual scenario. For example, Figure 5 As shown, the first logic gate 120 includes a NAND gate. The NAND gate has the characteristic of "all 1s are 0, and any 0 is 1", that is, when all inputs of the NAND gate are high, the output of the NAND gate is low, and when any input of the NAND gate is low, the output of the NAND gate is high.

[0080] In this example, the first logic gate 120 may receive the i-th third control signal LVL and the i-1th fourth control signal LVD <i-1>, providing the first composite signal LVI to the delay component B Taking the first logic gate 120 including a NAND gate as an example, based on the characteristics of the NAND gate, when the i-th third control signal LVL is high level, and the i-1th fourth control signal LVD <i-1>When the first composite signal LVI is also high, When the i-th third control signal LVL is high level, and the i-1th fourth control signal LVD <i-1>When the first composite signal LVI is low, When the i-th third control signal LVL is low level, and the i-1th fourth control signal LVD <i-1>When the first composite signal LVI is high, When the i-th third control signal LVL is low level, and the i-1th fourth control signal LVD <i-1>When the first composite signal LVI is also low, is high level.

[0081] In summary, if the i-th third control signal and the i-1-th fourth control signal both have rising edges (i.e., both switch from a low level to a high level), the first composite signal switches from a high level to a low level, i.e., the first composite signal has a falling edge. If the i-th third control signal and the i-1-th fourth control signal both have falling edges (i.e., both switch from a high level to a low level), the first composite signal switches from a low level to a high level, i.e., the first composite signal has a rising edge. If the i-th third control signal has a rising edge and the i-1-th fourth control signal has a falling edge, or if the i-th third control signal has a falling edge and the i-1-th fourth control signal has a rising edge, the first composite signal remains at a high level, i.e., the first composite signal has neither a rising edge nor a falling edge.

[0082] The delay component B is used to delay the first composite signal LVI according to the first composite signal LVI. , outputs the i-th fourth control signal to the encoder 103. Specifically, Figure 5 As shown, the delay component B receives the first composite signal LVI , outputs the i-th fourth control signal LVD to the encoder 103 .

[0083] In practical applications, the delay component B includes at least one delay module. When there are at least two delay modules, these delay modules are connected in series. The structure of the delay module can be flexibly configured according to the requirements of the application scenario. Any two delay modules can have the same or different structures. For example, the delay module can be a first module B1 or a second module B2, each of which will be described in detail below.

[0084] In implementation mode 1, when both the i-th third control signal and the i-1-th fourth control signal have rising edges, the first composite signal has a falling edge. In this case, the delay component B includes a first module B1. Figure 5 As shown, the delay component B (specifically, the first module B1 ) includes a first control subcomponent Z1 and a first electronic storage component Z2 , and the first control subcomponent Z1 and the first electronic storage component Z2 are connected.

[0085] The first control subassembly Z1 is used to control the first storage subassembly Z2 to charge according to the first current according to the falling edge of the first synthetic signal, and obtain the i-th fourth control signal with delayed switching on the rising edge.

[0086] It is understood that any device or circuit capable of storing electricity can be used as the first storage subassembly Z2. Similarly, any device or circuit capable of controlling the charging speed of the first storage subassembly Z2 can be used as the first control subassembly Z1. Figure 5 As shown, in the following, the specific implementation is described by taking the first storage subassembly Z2 including the first capacitor 123 and the first control subassembly Z1 including the first transistor 122 and the first current source 121 as an example.

[0087] The source of the first transistor 122 is connected to the first current source 121, the gate of the first transistor 122 is connected to the output end of the first logic gate 120, the drain of the first transistor 122 is connected to one end of the first capacitor 123, and the other end of the first capacitor 123 is grounded. In addition, the other end of the first current source 121 is connected to the power supply. Specifically, Figure 5 In the embodiment, the first transistor 122 is the transistor PM0, the first current source 121 is the current source IPB, and the first capacitor 123 is the capacitor C0.

[0088] A current source is a circuit element that can provide a constant current. The output current of a current source is unaffected by changes in load impedance. Ideally, the internal resistance of the current source is infinite. Therefore, the first current source 121 is configured to provide a first current to the source of the first transistor 122. The magnitude of the first current is not limited herein.

[0089] The first transistor 122 is used to provide a first current to the first capacitor 123 according to the first synthetic signal when N third control signals indicate that the reference voltage is increased by at least two levels and the i-th third control signal and the i-1-th fourth control signal are both switched from a low level to a high level.

[0090] The first transistor 122 is a PMOS transistor. When the actual voltage on the PMOS gate is lower than its threshold voltage, a current path is formed between the source and drain of the PMOS, and the source of the PMOS outputs a conduction current to the drain through this current path. Furthermore, the lower the actual voltage on the PMOS gate, the greater the conduction current; and the higher the actual voltage on the PMOS gate, the smaller the conduction current.

[0091] Based on the above content, for N third control signals LVL<N:1> Instructs to increase the reference voltage level by at least one level. If the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from low level to high level, the first composite signal LVI =The first transistor 122 is a PMOS transistor. Therefore, when a low level is input to the gate of the first transistor 122, a current path can be formed between the source and drain of the first transistor 122. In this case, the first current can flow through the first transistor 122, and based on this, the drain of the first transistor 122 provides the first current to the first capacitor 123.

[0092] For N third control signals LVL<N:1> Instructs to reduce the reference voltage level by at least one level, if the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from high level to low level. In this case, the first composite signal LVI Switched from low level to high level. If the i-th third control signal LVL Switched from high level to low level, the i-1th fourth control signal LVD <i-1>Switched from low level to high level; or, the i-th third control signal LVL Switched from low level to high level, the i-1th fourth control signal LVD <i-1>Switched from high level to low level, in both cases, the first composite signal LVI Since the first transistor 122 is a PMOS transistor, when a high level is input to the gate of the first transistor 122, no current path exists between the source and drain of the first transistor 122. In this case, the first current cannot flow through the first transistor 122, and therefore, the drain of the first transistor 122 does not provide the first current to the first capacitor 123.

[0093] On the basis that the drain of the first transistor 122 provides the first current to the first capacitor 123, the first capacitor 123 is used to charge according to the first current, and the level of the i-th fourth control signal is positively correlated with the amount of charge stored in the first capacitor 123. Specifically, when the first capacitor 123 is charged, the amount of charge stored in the first capacitor 123 will increase, resulting in the output voltage LVX of the first module B1. Increase. In actual application, the output voltage LVX Can be used as the i-th fourth control signal LVD , you can also set the output voltage LVX Input delay module, output the ith fourth control signal LVD through the delay module Finally, the i-th fourth control signal LVD is high level.

[0094] The first current provided by the first current source 121 charges the first capacitor 123, thereby controlling the charging speed of the first capacitor 123, thereby delaying the i-th fourth control signal LVD The time for switching from low level to high level makes the i-th fourth control signal LVD It has a relatively gentle rising edge, which achieves the effect of delaying the switching rising edge.

[0095] In an exemplary embodiment, when both the i-th third control signal and the i-1-th fourth control signal have falling edges, the first composite signal has a rising edge. Figure 5 As shown, the delay component B (specifically the first module B1) includes a second control subcomponent Z3 and a first electronic storage component Z2, and the second control subcomponent Z3 is connected to the first electronic storage component Z2.

[0096] The second control subassembly Z3 is used to control the discharge of the first electronic storage subassembly Z2 according to the rising edge of the first synthetic signal, and obtain the i-th fourth control signal of delayed switching or immediate switching on the falling edge.

[0097] It is understandable that any device or circuit capable of controlling the discharge of the first electronic storage component Z2 can be used as the second control subcomponent Z3. Figure 5 As shown, in the following, the specific implementation method is described by taking the first storage subassembly Z2 including the first capacitor 123 and the second control subassembly Z3 including the second transistor 124 as an example.

[0098] The source of the second transistor 124 is grounded, the gate of the second transistor 124 is connected to the output end of the first logic gate 120, and the drain of the second transistor 124 is connected to one end of the first capacitor 123. Figure 5 In the embodiment, the transistor NM0 is the second transistor 124. In addition, the drain of the first transistor 122 is connected to the drain of the second transistor 124.

[0099] The second transistor 124 is used to receive the second current generated by the discharge of the first capacitor 123 according to the first synthetic signal when N third control signals indicate a lowering gear of the reference voltage and the i-th third control signal and the i-1-th fourth control signal are both switched from a high level to a low level.

[0100] The second transistor 124 is an NMOS transistor. When the actual voltage on the NMOS gate is higher than its threshold voltage, a current path is formed between the source and drain of the NMOS, and the drain of the NMOS outputs a conduction current to the source through this current path. Furthermore, the higher the actual voltage on the NMOS gate, the greater the conduction current; and the lower the actual voltage on the NMOS gate, the smaller the conduction current.

[0101] Based on the above content, for N third control signals LVL<N:1> Instructs to increase the reference voltage level by at least one level. If the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from low level to high level, the first composite signal LVI Since the second transistor 124 is an NMOS, when a low level is input to the gate of the second transistor 124, no current path is formed between the source and drain of the second transistor 124. In this case, the first current cannot flow through the second transistor 124.

[0102] For N third control signals LVL<N:1> Instructs to reduce the reference voltage level by at least one level, if the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from high level to low level. In this case, the first composite signal LVI Switched from low level to high level. If the i-th third control signal LVL Switched from high level to low level, the i-1th fourth control signal LVD <i-1>Switched from low level to high level; or, the i-th third control signal LVL Switched from low level to high level, the i-1th fourth control signal LVD <i-1>Switched from high level to low level, in both cases, the first composite signal LVI Both maintain a high level. Since the second transistor 124 is an NMOS, when a high level is input to the gate of the second transistor 124, a current path exists between the source and drain of the second transistor 124. In this case, the first capacitor 123 can be discharged through the current path of the second transistor 124. The current during discharge is the second current, and the value of the second current is not limited here.

[0103] Since the first capacitor 123 is discharged, the amount of charge stored in the first capacitor 123 is reduced, resulting in the output voltage LVX of the first module B1 being In actual application, the output voltage LVX Can be used as the i-th fourth control signal LVD , you can also set the output voltage LVX Input delay module, output the ith fourth control signal LVD through the delay module Finally, the i-th fourth control signal LVD is low level.

[0104] Since the first capacitor 123 is not discharged by the current source to control the discharge speed, the first capacitor 123 can be discharged quickly, so that the i-th fourth control signal LVD It can quickly switch from high level to low level, that is, the i-th fourth control signal LVD It has a relatively steep falling edge, which achieves the effect of instant switching falling edge.

[0105] Optionally, the second control subassembly Z3 includes a second transistor 124 and a current source (not shown in the figure). One end of the current source is connected to the source of the second transistor 124, and the other end of the current source is grounded. Since the current source is used to provide a stable current, the second control subassembly Z3 can control the first storage subassembly Z2 to discharge according to the current provided by the current source when controlling the discharge of the first storage subassembly Z2, thereby controlling the discharge speed of the first storage subassembly Z2, so that the i-th fourth control signal LVD It can slowly switch from high level to low level, that is, the i-th fourth control signal LVD It has a relatively slow falling edge, which achieves the effect of delayed switching of the falling edge.

[0106] In implementation 2, when both the i-th third control signal and the i-1-th fourth control signal have rising edges, the first composite signal has a falling edge. In this case, the delay component includes a second module B2. Figure 5 As shown, the delay component B (specifically the second module B2 ) includes a third control subcomponent Z4 , a second storage subcomponent Z5 and a second logic gate 128 , and the second storage subcomponent Z5 is connected to the third control subcomponent Z4 and the second logic gate 128 .

[0107] Among them, the third control subcomponent Z4 is used to control the second electronic storage component to discharge according to the second current according to the falling edge of the first synthetic signal, so as to obtain the target voltage of the falling edge delayed switching; the second logic gate 128 is used to determine the i-th fourth control signal of the rising edge delayed switching according to the falling edge of the target voltage.

[0108] It is understandable that any device or circuit capable of storing electricity can be used as the second storage subassembly Z5. Similarly, any device or circuit capable of controlling the discharge of the second storage subassembly Z5 can be used as the third control subassembly Z4. Figure 5 As shown, in the following, the specific implementation method is explained by taking the second storage subassembly Z5 including the second capacitor 127 and the third control subassembly Z4 including the third transistor 125 and the second current source 126 as an example.

[0109] The source of the third transistor 125 is connected to one end of the second current source 126, the drain of the third transistor 125 is connected to one end of the second capacitor 127, the gate of the third transistor 125 is connected to the output end of the first logic gate 120, the other end of the second current source 126 is grounded, and the other end of the second capacitor 127 is grounded. Figure 5 In the embodiment, the third transistor 125 is the transistor NM1, the second current source 126 is the current source INB, and the second capacitor 127 is the capacitor C1.

[0110] The second current source 126 is configured to provide a third current to the source of the third transistor 125. The value of the third current is not limited herein.

[0111] The third transistor 125 is used to receive the third current generated by the discharge of the second capacitor 127 according to the first synthetic signal and the third current when N third control signals indicate that the reference voltage is increased by at least two levels and the i-th third control signal and the i-1-th fourth control signal are both switched from a low level to a high level.

[0112] The third transistor 125 is an NMOS.<N:1> Instructs to increase the reference voltage level by at least one level. If the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from low level to high level, the first composite signal LVI Since the first transistor 122 is an NMOS, when the gate of the third transistor 125 is input with a low level, no current path may be formed between the source and drain of the third transistor 125. In this case, the second capacitor 127 cannot be discharged through the current path.

[0113] For N third control signals LVL<N:1> Instructs to reduce the reference voltage level by at least one level, if the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from high level to low level. In this case, the first composite signal LVI Switched from low level to high level. If the i-th third control signal LVL Switched from high level to low level, the i-1th fourth control signal LVD <i-1>Switched from low level to high level; or, the i-th third control signal LVL Switched from low level to high level, the i-1th fourth control signal LVD <i-1>Switched from high level to low level, in both cases, the first composite signal LVI Since the third transistor 125 is an NMOS transistor, a current path exists between the source and drain of the third transistor 125 when a high level is input to the gate of the third transistor 125. In this case, the third current can flow through the third transistor 125 based on the current path, so that the second capacitor 127 can be discharged according to the third current through the third transistor 125.

[0114] The second logic gate 128 is configured to determine the level of the i-th fourth control signal according to the voltage provided by the second capacitor 127. The second logic gate 128 may include at least one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, and an XNOR gate.

[0115] Alternatively, as Figure 5 As shown, the second logic gate 128 comprises a NOT gate. The NOT gate has the characteristic of "1 equals 0, and 0 equals 1." That is, when the input signal to the NOT gate is low, the output is high; when the input signal to the NOT gate is high, the output is low.

[0116] When the second capacitor 127 is discharged, the amount of charge stored in the second capacitor 127 decreases, causing the drain voltage LVO of the third transistor 125 to increase. The drain voltage of the third transistor 125 is the voltage provided by the second capacitor 127. The input terminal of the second logic gate 128 receives the voltage LVO. , the second logic gate 128 includes a NOT gate, and the voltage LVO On the basis of the decrease, the output terminal of the second logic gate 128 outputs a high level.

[0117] In practical applications, the output voltage of the second logic gate 128 can be used as the i-th fourth control signal LVD Alternatively, the output voltage of the second logic gate 128 may be input to the delay module, and the delay module may output the ith fourth control signal LVD. Finally, the i-th fourth control signal LVD is high level.

[0118] The second current source 126 provides a third current so that the second capacitor 127 can discharge according to the third current, thereby controlling the discharge speed of the second capacitor 127 and delaying the i-th fourth control signal LVD. The time for switching from low level to high level makes the i-th fourth control signal LVD It has a relatively gentle rising edge, which achieves the effect of delaying the switching rising edge.

[0119] In an exemplary embodiment, when both the i-th third control signal and the i-1-th fourth control signal have falling edges, the first composite signal has a rising edge. Figure 5 As shown, the delay component B (specifically the second module B2 ) includes a fourth control subcomponent Z6 , a second storage subcomponent Z5 and a second logic gate 128 , and the second storage subcomponent Z5 is connected to the fourth control subcomponent Z6 and the second logic gate 128 .

[0120] Among them, the fourth control subcomponent Z6 is used to control the charging of the second electronic storage component Z5 according to the rising edge of the first synthetic signal, and obtain the target voltage of rising edge delayed switching or instant switching; the second logic gate 128 is used to determine the i-th fourth control signal of falling edge delayed switching or instant switching according to the rising edge of the target voltage.

[0121] It is understandable that any device or circuit capable of controlling the charging of the second storage subassembly Z5 can be used as the fourth control subassembly Z6. Figure 5 As shown, in the following, the specific implementation method is described by taking the second storage subassembly Z5 including the second capacitor 127 and the fourth control subassembly Z6 including the fourth transistor 129 as an example.

[0122] The gate of the fourth transistor 129 is connected to the output terminal of the first logic gate 120, the source of the fourth transistor 129 is connected to the power supply, and the drain of the fourth transistor 129 is connected to one end of the second capacitor 127. Figure 5 In the embodiment, the transistor PM1 is the fourth transistor 129. In addition, the drain of the fourth transistor 129 is connected to the drain of the third transistor 125.

[0123] The fourth transistor 129 is used to provide a fourth current to the second capacitor 127 according to the first synthetic signal when the N third control signals indicate a lowering of the reference voltage and the i-th third control signal and the i-1-th fourth control signal are both switched from a high level to a low level.

[0124] The second capacitor 127 is configured to be charged according to the fourth current.

[0125] The fourth transistor 129 is a PMOS transistor.<N:1> Instructs to increase the reference voltage level by at least one level. If the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from low level to high level, the first composite signal LVI =A low level. Since the fourth transistor 129 is a PMOS transistor, a current path can be formed between the source and drain of the fourth transistor 129 based on the low level input to the gate of the fourth transistor 129. In this case, the fourth current flows through the fourth transistor 129 through the current path and charges the second capacitor 127. The current during charging is the fourth current, and the value of the fourth current is not limited here.

[0126] For N third control signals LVL<N:1> Instructs to reduce the reference voltage level by at least one level, if the i-th third control signal LVL , the i-1th fourth control signal LVD <i-1>are switched from high level to low level. In this case, the first composite signal LVI Switched from low level to high level. If the i-th third control signal LVL Switched from high level to low level, the i-1th fourth control signal LVD <i-1>Switched from low level to high level; or, the i-th third control signal LVL Switched from low level to high level, the i-1th fourth control signal LVD <i-1>Switched from high level to low level, in both cases, the first composite signal LVI Since the fourth transistor 129 is a PMOS transistor, when the gate of the fourth transistor 129 is input with a high level, there is no current path between the source and drain of the fourth transistor 129. In this case, the second capacitor 127 cannot be charged.

[0127] As the second capacitor 127 is charged, the amount of charge stored in the second capacitor 127 increases, resulting in a voltage LVO. The second logic gate 128 includes a NOT gate, and the voltage LVO On the basis of rising, the output terminal of the second logic gate 128 outputs a low level.

[0128] In practical applications, the output voltage of the second logic gate 128 can be used as the i-th fourth control signal LVD , you can also set the output voltage LVX Input delay module, output the ith fourth control signal LVD through the delay module Finally, the i-th fourth control signal LVD is low level.

[0129] Since the second capacitor 127 is not charged by the current source to control the charging speed, the second capacitor 127 can be charged quickly, so that the i-th fourth control signal LVD It can quickly switch from high level to low level, that is, the i-th fourth control signal LVD It has a relatively steep falling edge, which achieves the effect of instant switching falling edge.

[0130] Optionally, the fourth control subassembly Z6 includes a fourth transistor 129 and a current source (not shown in the figure). One end of the current source is connected to the power supply, and the other end of the current source is connected to the source of the fourth transistor 129. Since the current source is used to provide a stable current, the fourth control subassembly Z6 can control the second storage subassembly Z5 to charge according to the current provided by the current source when controlling the charging of the second storage subassembly Z5, thereby controlling the charging speed of the second storage subassembly Z5, so that the i-th fourth control signal LVD It can slowly switch from high level to low level, that is, the i-th fourth control signal LVD It has a relatively slow falling edge, which achieves the effect of delayed switching of the falling edge.

[0131] Based on the above, the hierarchical delay device 102 includes N delay units A connected in series, and the i-th delay unit A includes a first logic gate 120 and at least one delay component B connected in series. The following uses two delay components B as an example to illustrate the implementation process of the i-th delay unit A.

[0132] In this example, since a large overshoot current problem will only occur when the reference voltage is switched from a low gear to a high gear when switching the gear of the reference voltage, due to practical considerations and circuit area, the i-th delay unit A only performs delay switching processing on the rising edge of the input signal, and does not perform delay switching processing on the falling edge of the input signal.

[0133] like Figure 5 As shown, the first logic gate 120 includes a NAND gate. One input end of the NAND gate is connected to the output end of the decoder 101 for receiving the third control signal LVL The other input of the NAND gate is connected to a logic high level or the output of the (i-1)th delay unit A. Regarding the case where the input of the NAND gate is connected to the output of the (i-1)th delay unit A, there are at least two possible implementation processes.

[0134] 1. The input end of the NAND gate is used to receive the i-1th fourth control signal LVD <i-1>The third control signal LVL and the i-1th fourth control signal LVD <i-1>, are switched from low level to high level, the output end of the NAND gate outputs the first composite signal LVI , and the first composite signal LVI Switched from high level to low level. = is low level, therefore, transistor PM0 is turned on, while transistor NM0 is not turned on. Based on this, current source IPB generates a first current, capacitor C0 is charged according to the first current, so that voltage LVX That is, the voltage LVX output by the delay component B1 With a relatively flat rising edge, a delay of one level is achieved. When the voltage is high, the transistor PM1 is not conducting, and the transistor NM1 is conducting. Based on this, the current source INB generates a third current, and the capacitor C1 discharges according to the third current, so that the voltage LVO Slowly decrease the voltage LVO The input is the NOT gate 128, and the NOT gate 128 outputs a slowly rising voltage. That is, the voltage LVD output by the delay component B2 It has a relatively flat rising edge and realizes a two-level delay.

[0135] 2. The input end of the NAND gate is used to receive the i-1th fourth control signal LVD <i-1>The third control signal LVL and the i-1th fourth control signal LVD <i-1>, are switched from high level to low level, the output end of the NAND gate outputs the first composite signal LVI , and the first composite signal LVI Switched from low level to high level. = is high, therefore, transistor PM0 is not conducting, while transistor NM0 is conducting. Based on this, since there is no current source regulation, capacitor C0 can be discharged quickly, making voltage LVX That is, the voltage LVX output by the delay component B1 Has a relatively steep falling edge. When the voltage LVX When the voltage is low, the transistor PM1 is turned on, and the transistor NM1 is not turned on. Based on this, since there is no current source regulation, the capacitor C1 can be charged quickly, so that the voltage LVO Rapidly rise. The voltage LVO The input is the NOT gate 128, and the NOT gate 128 outputs a rapidly decreasing voltage. That is, the voltage LVD output by the delay component B2 Has a relatively steep falling edge.

[0136] Voltage LVD Compared to voltage LVD <i-1>, only the rising edge is delayed by a fixed amount, while the falling edge is hardly delayed. By connecting N delay units A in series, the output voltage of each delay unit A is delayed only on the rising edge, while the falling edge is not delayed, compared to the output voltage of the previous delay unit A. Thus, the N delay units A together constitute an asynchronous hierarchical delay device. The hierarchical delay device is used to delay the rising edges of different third control signals by different amounts, while the delay amounts of two adjacent third control signals are the same.

[0137] The encoder 103 is configured to output L second control signals to the selector 20 according to the N third control signals and the N fourth control signals.

[0138] The encoder 103 is connected to the decoder 101 and is used to receive N third control signals LVL<N:1> The encoder 103 is also connected to the hierarchical delay device 102 for receiving N fourth control signals LVD<N:1> The encoder 103 is connected to the selector 20 and is used to output L second control signals LVS to the selector 20.<L:1> Wherein, L can be greater than N, less than N, or equal to N. For the convenience of description, in the following, L=N+1 is taken as an example, that is, the encoder 103 outputs N+1 second control signals LVS to the selector 20.<N+1:1> As an example, the implementation process of the encoder 103 is explained.

[0139] In this example, if Figure 6 As shown, the encoder 103 includes N first encoding units C and second encoding units D, and the second encoding unit D is connected to the N first encoding units C. Each first encoding unit C is connected to the decoder 101 and the hierarchical delay 102 .

[0140] The jth first coding unit C is used to provide the jth second composite signal to the second coding unit D according to the jth third control signal and the jth fourth control signal, where j is any positive integer from 1 to N.

[0141] The jth first coding unit C is connected to the decoder 101 and is used to receive the jth third control signal LVL <j>The jth first coding unit C is connected to the hierarchical delay 102 and is used to receive the jth fourth control signal LVD <j>The jth first encoding unit C is connected to the second encoding unit D, and is used to provide the jth second composite signal LVB to the second encoding unit D. <j>.

[0142] In an exemplary embodiment, as Figure 6 As shown, the j-th first coding unit C includes a third logic gate 131 and a buffer unit 132 , and the third logic gate 131 and the buffer unit 132 are connected.

[0143] The third logic gate 131 is configured to provide the jth third synthesized signal to the buffer unit 132 according to the jth third control signal and the jth fourth control signal.

[0144] One input terminal of the third logic gate 131 is connected to the decoder 101 for receiving the jth third control signal LVL <j>The other input terminal of the third logic gate 131 is connected to the hierarchical delay device 102 for receiving the j-th fourth control signal LVD <j>The output end of the third logic gate 131 is connected to the buffer unit 132, and is used to provide the j-th third composite signal LVA to the buffer unit 132. <j>.

[0145] The third logic gate 131 includes at least one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, and an XNOR gate. The specific type of the third logic gate 131 can be flexibly set according to the needs of the actual scenario. For example, the third logic gate 131 includes an AND gate. The AND gate has the characteristic of "all 1s are 1, and any 0 is 0." That is, if both input voltages of the AND gate are high, the output voltage of the AND gate is high. If both input voltages of the AND gate are low, or if one input voltage of the AND gate is high and the other input voltage is low, the output voltage of the AND gate is low.

[0146] Based on the above content, if the jth third control signal LVL <j>and the jth fourth control signal LVD <j>are both high, the third logic gate 131 provides the jth third composite signal LVA to the buffer unit 132 <j>, and the jth third composite signal LVA <j>If the jth third control signal LVL <j>and the jth fourth control signal LVD <j>are all low level, or the jth third control signal LVL <j>is high level, the jth fourth control signal LVD <j>is low level, or the jth third control signal LVL <j>is low level, the jth fourth control signal LVD <j>is high, the third logic gate 131 provides the jth third composite signal LVA to the buffer unit 132 <j>, and the jth third composite signal LVA <j>is low level.

[0147] The buffer unit 132 is configured to provide the jth second composite signal to the second encoding unit D according to the jth third composite signal.

[0148] The input end of the buffer unit 132 is connected to the output end of the third logic gate 131, and is used to receive the j-th third composite signal LVA. <j>The output end of the buffer unit 132 is connected to the input end of the second encoding unit D, and is used to provide the second encoding unit D with the j-th second composite signal LVB. <j>In the field of electronic technology, the buffer unit 132 is also called a circuit buffer, which is a component in the electronic circuit and is mainly used to enhance the stability of the signal, protect the circuit, level conversion, and enhance the driving ability of the signal. In this example, the buffer unit 132 is used to <j>The signal is shaped so that a rising edge with a slope becomes a vertical rising edge, and a falling edge with a slope becomes a vertical falling edge.

[0149] In practical applications, the j-th first coding unit C may include only the third logic gate 131. In this case, the output end of the third logic gate 131 is connected to the input end of the second coding unit D to provide the j-th second composite signal, i.e., the j-th third composite signal LVA, to the second coding unit D. <j>That is the jth second composite signal LVB <j>.

[0150] The second encoding unit D is configured to output L second control signals to the selector 20 according to the N second composite signals.

[0151] The input end of the second coding unit D is connected to the output end of the N first coding units C, and is used to receive the N second composite signals LVB<N:1> The output end of the second coding unit D is connected to the selector 20, and is used to output L second control signals LVS to the selector 20.<L:1> .

[0152] In an exemplary embodiment, as Figure 6 As shown, the second encoding unit D includes L fourth logic gates 133, where L is equal to the sum of N and 1. The first fourth logic gate 133 is connected to the first first encoding unit C, the kth fourth logic gate 133 is connected to the k-1th first encoding unit C and the kth first encoding unit C, and the Lth fourth logic gate 133 is connected to the Nth first encoding unit C, where k is any positive integer between 2 and N. In addition, the input end of the first fourth logic gate 133 is also connected to a high-level signal generating circuit 134, and the Lth fourth logic gate 133 is also connected to a low-level signal generating circuit 135.

[0153] Any fourth logic gate 133 includes at least one of an AND gate, an OR gate, a NOT gate, a NAND gate, a NOR gate, an XOR gate, and an XNOR gate. The specific type of the fourth logic gate 133 can be flexibly set according to the needs of the actual scenario. Exemplarily, the fourth logic gate 133 includes an XOR gate. The XOR gate has the characteristic of "same is 0, different is 1". That is, if both input voltages of the XOR gate are high or low, the output voltage of the XOR gate is low. If one input voltage of the XOR gate is high and the other input voltage is low, or if one input voltage of the XOR gate is low and the other input voltage is high, the output voltage of the XOR gate is high.

[0154] The first fourth logic gate 133 is used to output the first second control signal to the selector 20 according to the first second composite signal and the high level signal. On the basis that the first fourth logic gate 133 includes an exclusive OR gate, if the first second composite signal LVB <1> is high, the first fourth logic gate 133 outputs the first second control signal LVS to the selector 20 <1> , and the first second control signal LVS <1> If the first second composite signal LVB <1> is low, the first fourth logic gate 133 outputs the first second control signal LVS to the selector 20 <1> , and the first second control signal LVS <1> is high level.

[0155] The kth fourth logic gate 133 is used to output the kth second control signal to the selector 20 according to the k-1th second composite signal and the kth second composite signal. On the basis that the kth fourth logic gate 133 includes an XOR gate, if the k-1th second composite signal LVB <k-1>and the kth second composite signal LVB <k>are both high or both low, the kth fourth logic gate 133 outputs the kth second control signal LVS to the selector 20 <k>, and the kth second control signal LVS <k>If the k-1 second composite signal LVB <k-1>is low level, k second composite signals LVB <k>is high, or if the k-1 second composite signal LVB <k-1>is high level, k second composite signals LVB <k>is low, the kth fourth logic gate 133 outputs the kth second control signal LVS to the selector 20 <k>, and the kth second control signal LVS <k>is high level.

[0156] The Lth fourth logic gate 133 is configured to output the Lth second control signal to the selector 20 according to the Nth second combined signal and the low-level signal.

[0157] On the basis that the Lth fourth logic gate 133 includes an exclusive OR gate, if the Lth second composite signal LVB <l>is low, the Lth fourth logic gate 133 outputs the Lth second control signal LVS to the selector 20 <l>, and the Lth second control signal LVS <l>If the Lth second composite signal LVB <l>is high, the Lth fourth logic gate 133 outputs the Lth second control signal LVS to the selector 20 <l>, and the Lth second control signal LVS <l>is high level.

[0158] Based on the above, if Figure 6 As shown, the jth AND gate (ie, ANDj) receives the jth third control signal LVL <j>and the jth fourth control signal LVD <j>and provides the jth third composite signal LVA to the buffer unit 132 <j>Among them, the jth third control signal LVL <j>and the jth fourth control signal LVD <j>are all high level, then the jth third composite signal LVA <j>The jth third control signal LVL is also at a high level. <j>and the jth fourth control signal LVD <j>are all low level, or the jth third control signal LVL <j>is high level, the jth fourth control signal LVD <j>is low level, or the jth third control signal LVL <j>is low level, the jth fourth control signal LVD <j>is high, then the jth third composite signal LVA <j>is low level.

[0159] The buffer unit 132 is used to process the j-th third composite signal LVA <j>Reshape so that the jth third composite signal LVA <j>The falling edge of is not affected by the hierarchical delay 102, and the j-th second composite signal LVB is obtained. <j>.

[0160] The first XOR gate (ie XOR1) is used to generate the first second composite signal LVB <1> XOR processing is performed with the logic high level to obtain the first second control signal LVS <1> The second XOR gate (ie XOR2) is used to generate the first second composite signal LVB. <1> and the second composite signal LVB <2> Perform XOR processing to obtain the second control signal LVS <2> The third XOR gate (ie XOR3) is used to generate the second composite signal LVB. <2> and the third second composite signal LVB <3> Perform XOR processing to obtain the third second control signal LVS <3> This process is repeated until the Nth XOR gate (ie XORN) generates the N-1th second composite signal LVB. <n>and the Nth second composite signal LVB <n>Perform XOR processing to obtain the Nth second control signal LVS <n>In addition, the N+1th exclusive OR gate (ie XORN+1) generates the Nth second composite signal LVB. <n>XOR processing is performed with the logic low level to obtain the N+1th second control signal LVS<N+1> .

[0161] The selector 20 is used to receive at least three voltage levels. Under the control of L second control signals, the selector 20 sequentially selects a reference voltage from the at least three voltage levels and provides the sequentially selected reference voltage to the LDO 30. The reference voltage increases by at least two levels in a gear-by-grade manner as the selection time progresses.

[0162] like Figure 4 As shown, the selector 20 is MUX20, and the selector 20 is used to receive voltages of at least three gears. Assuming that the number of gears is L, the voltages of the L gears can be expressed as VREF<L:1> , when L=N+1, VREF<L:1> =VREF<N+1:1> Among them, the voltage of the first gear can be expressed as VREF <1> , the voltage of the second gear can be expressed as VREF <2> , the voltage of the third gear can be expressed as VREF <3> , and so on, the voltage of the L+1th gear can be expressed as VREF<L+1> .

[0163] Optionally, the input end of the selector 20 is connected to the output end of the BGR 40, and the BGR 40 is used to provide the selector 20 with L gear voltages VREF.<L:1> .

[0164] In addition, the selector 20 is also connected to the control signal adjustment circuit 10 for receiving L second control signals LVS.<L:1> . L second control signals LVS<L:1> It is used to indicate the gear of the reference voltage. Based on this, the selector 20 can select the gear according to L second control signals LVS.<L:1> , from the L position voltage VREF<L:1> Select a voltage of a gear from the L, and use the selected voltage as the reference voltage VBGR. For example, L second control signals LVS<L:1> Indicates the voltage VREF of the second gear <2> , then the reference voltage VBGR=the voltage VREF of the second gear <2> .

[0165] The selector 20 is connected to the LDO 30 and is used to provide a reference voltage VBGR to the LDO 30. The LDO 30 is used to output a supply voltage according to the selected reference voltages. The implementation of the LDO 30 has been described above and will not be repeated here.

[0166] Combining the above content and Figure 4 As shown in the gear adjustment circuit, in this example, when adjusting the voltage gear, it includes the following stages, such as Figure 7 shown.

[0167] 1. Startup phase. When the power supply voltage needs to be switched, the external circuit provides M first control signals LV to the decoder 101.<M:1> .

[0168] 2. Decoding stage. The decoder 101 converts the M first control signals LV<M:1> , converted from binary code to thermometer code, and N third control signals LVL are obtained<N:1> , optionally, N=2 M -1.

[0169] 3. Hierarchical delay stage: The hierarchical delay device 102 receives N third control signals LVL output by the decoder 101.<N:1> , respectively set the third control signal LVL of each bit The signal is sent to the delay unit of the corresponding bit, and different bits are separated in the time domain to obtain N fourth control signals LVD.<N:1> Among them, the third control signal LVL for any bit , only the rising edge is delayed and switched, and the falling edge is not delayed and switched. Optionally, the higher the bit position, the longer the delay, and the lower the bit position, the shorter the delay, and the delay difference between adjacent bits is a fixed delay difference.

[0170] 4. Encoding stage. The encoder 103 encodes N fourth control signals LVD<N:1> Encode to obtain N+1 second control signals LVS<N+1:1> , providing N+1 second control signals LVS to MUX20<N+1:1> .

[0171] 5. Selection stage. BGR10 provides N+1 gear voltage VREF to MUX20<N+1:1> MUX20 is based on N+1 second control signals LVS<N+1:1> , from the voltage VREF of N+1 gears<N+1:1> A voltage of a gear is selected from the output voltage, a reference voltage VBGR is obtained, and the reference voltage VBGR is provided to the LDO 30.

[0172] 6. Regulation stage: LDO30 receives the reference voltage VBGR and outputs the supply voltage VDDR.

[0173] In the above manner, for the case where the power supply voltage needs to be switched, if the first control signal LV<M:1> Indicates that the reference voltage VBGR increases by at least two levels, then: the decoder 101, the hierarchical delay 102 and the encoder 103 can<M:1> Processing is performed to obtain N+1 second control signals LVS<N+1:1> In terms of timing, N+1 second control signals LVS<N+1:1> This can be characterized by the following: the reference voltage VBGR before the increase is slowly increased step by step to the reference voltage VBGR after the increase. By slowly increasing the reference voltage, the large overshoot current generated by the LDO is reduced, thereby protecting the performance and stability of the circuit.

[0174] Specifically, taking M=2, N=3, L=N+1=4 as an example, combined with Figures 4 to 6 , and the truth table shown in Table 1 mentioned above, illustrate the detailed implementation process of the embodiment of the present application.

[0175] 1. Assuming that the first control signal LV<2:1> transitions from 00 to 11, the decoder 101 can determine that the third control signal LVL<3:1> transitions from 000 to 111 based on the truth table shown in Table 1. Furthermore, when the first control signal LV<2:1> is 00, the second control signal LVS<4:1> is 0001.

[0176] The hierarchical delayer 102 and the encoder 103 may perform the following steps:

[0177] (1) The NAND gate 120 receives the third control signal LVL <1> and logic high level. Since the third control signal LVL <1> From 0 to 1, therefore, the NAND gate 120 outputs the first composite signal LVI <1> , and the first composite signal LVI <1> When the first composite signal LVI changes from high level to low level, <1> When the voltage is low, a current path is formed between the source and drain of the first transistor 122, and the first capacitor 123 is charged based on the first current provided by the current source 121, so that the voltage LVX <1> Has a relatively gentle rising edge. When the voltage LVX <1> When the voltage LVO is high, there is a current path between the source and drain of the third transistor 125, and the second capacitor 127 can discharge according to the current provided by the current source 126 through the third transistor 125, so that the voltage LVO is <1> Has a relatively slow falling edge. Voltage LVO <1> After passing through the NOT gate 128, the fourth control signal LVD is output. <1> , and the fourth control signal LVD <1> Has a relatively slow rising edge. At this time, the third control signal LVL <1> is high level, the fourth control signal LVD <1> The third control signal LVL is also high. <2> has changed from 0 to 1, but the fourth control signal LVD <2> There is no time to jump, and it is still low level. Similarly, LVL <3> has changed from low level to high level, but the fourth control signal LVD <3> There is no time for the jump and it remains at a low level.

[0178] Therefore, the third control signal LVL <1> and the fourth control signal LVD <1> After passing through the AND gate AND1, a high level third synthetic signal LVA is obtained. <1> The third composite signal LVA <1> After being shaped by the buffer unit 132, a high-level second composite signal LVB is obtained. <1> The second composite signal LVB <1> And the logic high level input exclusive OR gate XOR1, get the low level second control signal LVS <1> The third control signal LVL <2> and the fourth control signal LVD <2> After passing through the AND gate AND2, a low-level third composite signal LVA is obtained. <2> The third composite signal LVA <2> After being shaped by the buffer unit 132, a low-level second composite signal LVB is obtained. <2> The second composite signal LVB <1> and the second composite signal LVB <2> Input the XOR gate XOR2 to obtain the high level second control signal LVS <2> The third control signal LVL <3> and the fourth control signal LVD <3> After passing through the AND gate AND3, a low-level third synthetic signal LVA is obtained. <3> The third composite signal LVA <3> After being shaped by the buffer unit 132, a low-level second composite signal LVB is obtained. <3> The second composite signal LVB <2> and the second composite signal LVB <3> Input the XOR gate XOR3 to obtain the second control signal LVS of low level <3> The second composite signal LVB <3> and the logic low level input XOR gate XOR4 to obtain the low level second control signal LVS <4> .

[0179] Finally, the second control signal LVS<4:1> jumps from 0001 to 0010. In this case, the selector 20 selects the reference voltage under the control of the second control signal LVS<4:1>, and the reference voltage jumps from level 0 to level 1.

[0180] (2) The NAND gate 120 receives the third control signal LVL <2> and the fourth control signal LVD <1> Since the third control signal LVL <2> From low level to high level, and the fourth control signal LVD <1> Also jumps from low level to high level, therefore, the NAND gate 120 outputs the first composite signal LVI <2> , and the first composite signal LVI <2> When the first composite signal LVI changes from high level to low level, <2> When the fourth control signal LVD is low, <2> Has a relatively slow rising edge. At this time, the third control signal LVL <1> is high level, the fourth control signal LVD <1> The third control signal LVL is high. <2> is high level, the fourth control signal LVD <2> LVL is high level. <3> has changed from 0 to 1, but the fourth control signal LVD <3> There is no time for the jump and it remains at a low level.

[0181] Therefore, the third control signal LVL <1> and the fourth control signal LVD <1> After passing through the AND gate AND1, a high level third synthetic signal LVA is obtained. <1> The third composite signal LVA <1> After being shaped by the buffer unit 132, a high-level second composite signal LVB is obtained. <1> The second composite signal LVB <1> And the logic high level input exclusive OR gate XOR1, get the low level second control signal LVS <1> The third control signal LVL <2> and the fourth control signal LVD <2> After passing through the AND gate AND2, a high level third synthetic signal LVA is obtained. <2> The third composite signal LVA <2> After being shaped by the buffer unit 132, a high-level second composite signal LVB is obtained. <2> The second composite signal LVB <1> and the second composite signal LVB <2> Input the XOR gate XOR2 to get the second control signal LVS of low level <2> The third control signal LVL <3> and the fourth control signal LVD <3> After passing through the AND gate AND3, a low-level third synthetic signal LVA is obtained. <3> The third composite signal LVA <3> After being shaped by the buffer unit 132, a low-level second composite signal LVB is obtained. <3> The second composite signal LVB <2> and the second composite signal LVB <3> Input the XOR gate XOR3 to obtain the high-level second control signal LVS <3> The second composite signal LVB <3> and the logic low level input XOR gate XOR4 to obtain the low level second control signal LVS <4> .

[0182] Finally, the second control signal LVS<4:1> changes from 0010 to 0100. In this case, the selector 20 selects the reference voltage under the control of the second control signal LVS<4:1>, and the reference voltage changes from level 1 to level 2.

[0183] (3) The NAND gate 120 receives the third control signal LVL <3> and the fourth control signal LVD <2> Since the third control signal LVL <3> From low level to high level, and the fourth control signal LVD <2> Also jumps from low level to high level, therefore, the NAND gate 120 outputs the first composite signal LVI <3> , and the first composite signal LVI <3> When the first composite signal LVI changes from high level to low level, <3> When the fourth control signal LVD is low, <3> Has a relatively slow rising edge. At this time, the third control signal LVL <1> LVL <2> LVL <3> Both are high level, the fourth control signal LVD <1> LVD <2> LVD <3> All are high level.

[0184] Therefore, the third control signal LVL <1> and the fourth control signal LVD <1> After passing through the AND gate AND1, a high level third synthetic signal LVA is obtained. <1> The third composite signal LVA <1> After being shaped by the buffer unit 132, a high-level second composite signal LVB is obtained. <1> The second composite signal LVB <1> And the logic high level input exclusive OR gate XOR1, get the low level second control signal LVS <1> The third control signal LVL <2> and the fourth control signal LVD <2> After passing through the AND gate AND2, a high level third synthetic signal LVA is obtained. <2> The third composite signal LVA <2> After being shaped by the buffer unit 132, a high-level second composite signal LVB is obtained. <2> The second composite signal LVB <1> and the second composite signal LVB <2> Input the XOR gate XOR2 to get the second control signal LVS of low level <2> The third control signal LVL <3> and the fourth control signal LVD <3> After passing through the AND gate AND3, a high level third synthetic signal LVA is obtained. <3> The third composite signal LVA <3> After being shaped by the buffer unit 132, a high-level second composite signal LVB is obtained. <3> The second composite signal LVB <2> and the second composite signal LVB <3> Input the XOR gate XOR3 to obtain the second control signal LVS of low level <3> The second composite signal LVB <3> and the logic low level input XOR gate XOR4 to obtain the high level second control signal LVS <4> .

[0185] Finally, the second control signal LVS<4:1> jumps from 0100 to 1000. In this case, the selector 20 selects the reference voltage under the control of the second control signal LVS<4:1>, and the reference voltage jumps from level 2 to level 3.

[0186] Through (1) to (3), it is achieved that when the first control signal LV<2:1> jumps from 00 to 11, that is, when the reference voltage indicated by the first control signal LV<2:1> jumps directly from gear 0 to gear 3, the second control signal LVS<4:1> first jumps from 0001 to 0010 to indicate that the reference voltage jumps from gear 0 to gear 1, then jumps from 0010 to 0100 to indicate that the reference voltage jumps from gear 1 to gear 2, and then jumps from 0100 to 1000 to indicate that the reference voltage jumps from gear 2 to gear 3, thereby achieving an increase in the reference voltage step by step.

[0187] like Figure 8 As shown, M=2, N=3, and L=N+1=4. Here, Ildo_old is a schematic curve of the current inside the LDO when the reference voltage is increased by at least two levels at once. Ildo_new is a schematic curve of the current inside the LDO when the reference voltage is increased by at least two levels step by step.

[0188] Please refer to the curve portion shown by label 801: When the first control signal LV<2:1> switches from 00 to 11, an overshoot current will occur in the LDO. Based on this, the third control signal LVL<3:1> jumps from 000 to 111. For the fourth control signal LVD<3:1>, initially LVD <1> Switch to high level, after a delay unit, LVD <2> Switch to high level, and after a delay unit, LVD <3> Switched to a high level, the second control signal LVS<4:1> switches from 0001 to 0010, 0100 and finally to 1000.

[0189] Comparing the Ildo_old and Ildo_new curves, we can see that if the reference voltage is increased by at least two levels at once, a large overshoot current will occur within the LDO, affecting circuit performance. However, in the embodiments of the present application, increasing the reference voltage by at least two levels in multiple steps, from a timing perspective, can effectively suppress the overshoot current generated within the LDO during a single transition. By increasing the switching time to gradually increase the reference voltage, the peak overshoot current is reduced, improving the operating stability of the DDIC and PMIC.

[0190] 2. Assuming that the first control signal LV<2:1> transitions from 11 to 00, the decoder 101 can determine, based on the truth table shown in Table 1, that the third control signal LVL<3:1> transitions from 111 to 000. Furthermore, when the first control signal LV<2:1> is 11, the second control signal LVS<4:1> is 1000.

[0191] The hierarchical delay device 102 may perform the following steps:

[0192] (1) The NAND gate 120 receives the third control signal LVL <1> and logic high level. Since the third control signal LVL <1> From 1 to 0, therefore, the NAND gate 120 outputs the first composite signal LVI <1> , and the first composite signal LVI <1> When the first composite signal LVI changes from low level to high level, <1> When the voltage is high, a current path is formed between the source and drain of the second transistor 124, and the first capacitor 123 is discharged quickly based on the current path of the second transistor 124, causing the voltage LVX to <1> Quickly switch from high level to low level. When the voltage LVX <1> When the voltage LVO is low, a current path is formed between the source and drain of the fourth transistor 129, and the second capacitor 127 is quickly charged based on the current path of the fourth transistor 129. <1> Quickly switch from low level to high level. Voltage LVO <1> After passing through the NOT gate 128, the fourth control signal LVD is output. <1> , and the fourth control signal LVD <1> Has a relatively steep falling edge. At this time, the third control signal LVL <1> is low level, the fourth control signal LVD <1> Also low level.

[0193] (2) The NAND gate 120 receives the third control signal LVL <2> and the fourth control signal LVD <1> Since the third control signal LVL <2> From high level to low level, and the fourth control signal LVD <1> Also jumps from high level to low level, therefore, the NAND gate 120 outputs the first composite signal LVI <2> , and the first composite signal LVI <2> When the first composite signal LVI changes from low level to high level, <2> When the fourth control signal LVD is high, <2> Has a relatively steep falling edge. At this time, the third control signal LVL <2> is low level, the fourth control signal LVD <2> is low level.

[0194] (3) The NAND gate 120 receives the third control signal LVL <3> and the fourth control signal LVD <2> Since the third control signal LVL <3> From high level to low level, and the fourth control signal LVD <2> Also jumps from high level to low level, therefore, the NAND gate 120 outputs the first composite signal LVI <3> , and the first composite signal LVI <3> When the first composite signal LVI changes from low level to high level, <3> When the fourth control signal LVD is high, <3> Has a relatively steep falling edge. At this time, the third control signal LVL <3> is low level, the fourth control signal LVD <3> Also low level.

[0195] The encoder 103 may perform the following steps:

[0196] The third control signal LVL <1> and the fourth control signal LVD <1> After passing through the AND gate AND1, a low-level third synthetic signal LVA is obtained. <1> The third composite signal LVA <1> After being shaped by the buffer unit 132, a low-level second composite signal LVB is obtained. <1> The second composite signal LVB <1> and the logic high level input XOR gate XOR1 to obtain the high level second control signal LVS <1> The third control signal LVL <2> and the fourth control signal LVD <2> After passing through the AND gate AND2, a low-level third composite signal LVA is obtained. <2> The third composite signal LVA <2> After being shaped by the buffer unit 132, a low-level second composite signal LVB is obtained. <2> The second composite signal LVB <1> and the second composite signal LVB <2> Input the XOR gate XOR2 to get the second control signal LVS of low level <2> The third control signal LVL <3> and the fourth control signal LVD <3> After passing through the AND gate AND3, a low-level third synthetic signal LVA is obtained. <3> The third composite signal LVA <3> After being shaped by the buffer unit 132, a low-level second composite signal LVB is obtained. <3> The second composite signal LVB <2> and the second composite signal LVB <3> Input the XOR gate XOR3 to obtain the second control signal LVS of low level <3> The second composite signal LVB <3> and the logic low level input XOR gate XOR4 to obtain the low level second control signal LVS <4> .

[0197] Finally, the second control signal LVS<4:1> jumps from 1000 to 0001. In this case, the selector 20 selects the reference voltage under the control of the second control signal LVS<4:1>, and the reference voltage jumps directly from level 3 to level 0.

[0198] Refer to the curve portion 802: When the first control signal LV<2:1> switches from 11 to 00, no overshoot current occurs within the LDO. Based on this, the third control signal LVL<3:1> jumps from 111 to 000. The fourth control signal LVD<3:1> jumps directly from 111 to 000, and the second control signal LVS<4:1> switches directly from 1000 to 0001. Comparing the Ildo_old and Ildo_new curves, it can be seen that when the reference voltage is reduced by at least one level, the current is reduced due to the internal feedback of the LDO. Therefore, the reference voltage can be reduced by at least one level at a time without affecting the normal operation of the circuit.

[0199] In the above circuit, the control signal conditioning circuit can receive M first control signals and output L second control signals to the selector. The selector can receive at least three voltage levels and, based on the L second control signals, select one voltage level from the at least three voltage levels to obtain a reference voltage, which is then provided to the LDO. Since the M first control signals instruct to increase the reference voltage level by at least two levels, the L second control signals instruct to increase the reference voltage level by at least two levels step by step, thus, the selector can increase the reference voltage multiple times, and each time the reference voltage is increased, the increased reference voltage is only increased by one level relative to the reference voltage before the increase.

[0200] Compared to increasing the reference voltage by at least two levels at once, increasing the reference voltage multiple times, each time by only one level, reduces the magnitude of the reference voltage increase. This reduces the peak overshoot current generated within the LDO as it outputs a supply voltage based on the reference voltage, thereby reducing the impact of the overshoot current on the circuit and improving circuit performance and lifespan.

[0201] In an exemplary embodiment, as Figure 9 As shown, an embodiment of the present application further provides a chip, which includes the gear adjustment circuit mentioned in the above embodiment.

[0202] In an exemplary embodiment, as Figure 10 As shown, an embodiment of the present application further provides an electronic device, which includes the chip mentioned in the above embodiment.

[0203] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0204] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0205] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application. < / n> < / n> < / n> < / n> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / l> < / l> < / l> < / l> < / l> < / l> < / k> < / k> < / k> < / k> < / k> < / k> < / k> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / n> < / n> < / n> < / n> < / l> < / m>

Claims

1. A gear adjustment circuit, characterized in that: The gear adjustment circuit includes a control signal adjustment circuit, a selector and a low voltage difference linear regulator, and the selector is connected to the control signal adjustment circuit and the low voltage difference linear regulator; The control signal conditioning circuit is configured to receive M first control signals and output L second control signals to the selector, where L and M are both positive integers, wherein when the M first control signals collectively instruct to increase the reference voltage by at least two levels at once, the L second control signals collectively instruct to increase the reference voltage by at least two levels over time; The selector is configured to receive voltages of at least three gears, and under the control of the L second control signals, sequentially select a reference voltage from the voltages of the at least three gears, and provide the sequentially selected reference voltages to the low-dropout linear regulator, wherein the reference voltage increases by at least two gears over time. The low voltage dropout linear regulator is used to output a supply voltage according to the reference voltages selected in sequence.

2. The gear adjustment circuit according to claim 1, characterized in that: The control signal adjustment circuit includes a decoder, a hierarchical delay device and an encoder, wherein the hierarchical delay device is connected to the decoder and the encoder, and the encoder is connected to the selector; The decoder is configured to receive the M first control signals and output N third control signals to the hierarchical delay device, wherein the M first control signals and the N third control signals indicate the same information, and N is a positive integer greater than 2; The hierarchical delay device is configured to output a first fourth control signal to the encoder according to the first third control signal, and output an i-th fourth control signal to the encoder according to the i-th third control signal and the i-1-th fourth control signal, where i is any positive integer ranging from 2 to N; The encoder is configured to output the L second control signals to the selector according to the N third control signals and the N fourth control signals.

3. The gear adjustment circuit according to claim 2, characterized in that: The hierarchical delay device includes N delay units connected in series, and the i-th delay unit is used to output the i-th fourth control signal to the encoder according to the i-th third control signal and the i-1-th fourth control signal; Wherein, when both the (i-1)th fourth control signal and the (i)th third control signal have rising edges, the rising edge of the (i)th fourth control signal has a delayed switching.

4. The gear adjustment circuit according to claim 3, characterized in that: The i-th delay unit includes a first logic gate and a delay component, and the first logic gate and the delay component are connected; The first logic gate is configured to output a first synthesized signal to the delay component according to the i-th third control signal and the (i-1)-th fourth control signal; The delay component is used to output the i-th fourth control signal to the encoder according to the first synthesized signal.

5. The gear adjustment circuit according to claim 4, characterized in that: When both the i-th third control signal and the i-1-th fourth control signal have rising edges, the first synthesized signal has a falling edge; the delay component includes a first control subassembly and a first storage subassembly, and the first control subassembly is connected to the first storage subassembly; The first control subassembly is used to control the first electronic storage component to charge according to the first current according to the falling edge of the first synthetic signal, and obtain the i-th fourth control signal with rising edge delayed switching.

6. The gear adjustment circuit according to claim 4, characterized in that: When both the i-th third control signal and the i-1-th fourth control signal have falling edges, the first synthesized signal has a rising edge; the delay component includes a second control subassembly and a first storage subassembly, and the second control subassembly is connected to the first storage subassembly; The second control subcomponent is used to control the discharge of the first electronic storage component according to the rising edge of the first synthetic signal, and obtain the i-th fourth control signal with delayed switching or immediate switching on the falling edge.

7. The gear adjustment circuit according to claim 4, characterized in that: When both the i-th third control signal and the (i-1)-th fourth control signal have rising edges, the first synthesized signal has a falling edge; the delay component includes a third control subcomponent, a second storage subcomponent, and a second logic gate, and the second storage subcomponent is connected to the third control subcomponent and the second logic gate; The third control subassembly is configured to control the second storage subassembly to discharge according to the second current according to the falling edge of the first synthetic signal, so as to obtain a target voltage for falling edge delayed switching; The second logic gate is used to determine the i-th fourth control signal for rising edge delayed switching according to the falling edge of the target voltage.

8. The gear adjustment circuit according to claim 4, characterized in that: When both the i-th third control signal and the i-1-th fourth control signal have falling edges, the first synthesized signal has a rising edge; the delay component includes a fourth control subassembly, a second storage subassembly, and a second logic gate, and the second storage subassembly is connected to the fourth control subassembly and the second logic gate; The fourth control subassembly is configured to control the charging of the second storage subassembly according to the rising edge of the first synthetic signal, so as to obtain the target voltage for delayed switching or immediate switching on the rising edge; The second logic gate is used to determine the i-th fourth control signal for falling edge delayed switching or immediate switching according to the rising edge of the target voltage.

9. The gear adjustment circuit according to any one of claims 2 to 8, characterized in that: The encoder includes N first encoding units and second encoding units, and the second encoding units are connected to the N first encoding units; a j-th first encoding unit, configured to provide a j-th second composite signal to the second encoding unit according to the j-th third control signal and the j-th fourth control signal, where j is any positive integer from 1 to N; The second encoding unit is configured to output the L second control signals to the selector according to the N second composite signals.

10. The gear adjustment circuit according to claim 9, characterized in that: The j-th first encoding unit includes a third logic gate and a buffer unit, and the third logic gate is connected to the buffer unit; The third logic gate is configured to provide a j-th third composite signal to the buffer unit according to the j-th third control signal and the j-th fourth control signal; The buffer unit is configured to provide the jth second composite signal to the second encoding unit based on the jth third composite signal.

11. The gear adjustment circuit according to claim 9, characterized in that: The second coding unit includes L fourth logic gates, where L is equal to the sum of N and 1, the first fourth logic gate is connected to the first first coding unit, the kth fourth logic gate is connected to the k-1th first coding unit and the kth first coding unit, and the Lth fourth logic gate is connected to the Nth first coding unit, where k is any positive integer from 2 to N; The first fourth logic gate is used to output a first second control signal to the selector according to the first second composite signal and the high-level signal; The kth fourth logic gate is configured to output a kth second control signal to the selector according to the k-1th second composite signal and the kth second composite signal; The Lth fourth logic gate is used to output the Lth second control signal to the selector according to the Nth second composite signal and the low-level signal.

12. A chip, characterized in that: The chip includes the gear adjustment circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that: The electronic device comprises the chip according to claim 12.

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