Reconfigurable electric tuning frequency hopping filter and multi-objective optimization control method thereof

Abstract

The invention belongs to the technical field of filters, and particularly relates to a reconfigurable electric tuning frequency hopping filter and a multi-target optimization control method thereof.The filter comprises an MCU module, a resonance circuit module, a pre-distortion module and a signal receiving and transmitting module, the MCU module is provided with two main control CPUs and used for radio frequency signal processing, parameter control and communication coordination, address codes are calculated through the main control CPUs, and the signal receiving and transmitting module is used for receiving and transmitting signals. Radio frequency signal processing is set to be straight-through processing or filtering processing, a C-V curve and tuning voltage-frequency response of a variable capacitance diode are measured, a nonlinear model is established, and the non-linear model is used for radio frequency signal preprocessing of the MCU module, sending the radio frequency signal to the pre-distortion module or outputting the radio frequency signal after straight-through processing through parameter control of the MCU module. According to the invention, non-linear compensation can be carried out on signals with different frequencies in advance, and then the signals are distributed to corresponding resonance circuits through a digital chip in an address code calculation mode, so that the out-of-band rejection performance is improved, and distortion is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of filters, and in particular relates to a reconfigurable electrically tunable frequency hopping filter and a multi-objective optimization control method thereof. Background Art

[0002] Reconfigurable electronically tunable filters are capable of changing their center frequency, bandwidth, or filtering characteristics, primarily through electronic control rather than mechanical adjustment. They are key components in advanced electronic systems such as 5G / 6G communications and smart radar, and their performance directly impacts the flexibility and adaptability of the entire system.

[0003] In wireless communications, bandwidth reconfiguration mainly relies on digitally controlled frequency-hopping filters. For example, China has invented an ultra-wideband, broadband, reconfigurable, full-band, high-speed frequency-hopping transceiver with announcement number CN116318228B. It combines digitally controlled frequency-hopping filters, electrically adjustable filters, a wide-band, high-linearity power amplifier, and high-speed frequency-hopping frequency combination technology to achieve significant improvements in widening the operating frequency band, wide-band signal interference, broadband noise blocking, and resistance to blocking interference.

[0004] For digitally controlled frequency-hopping filters, varactor diodes are primarily used for automatic tuning, frequency modulation, and phase modulation in high-frequency circuits. Their out-of-band rejection performance relies solely on their own high quality factor, i.e., models with a smaller Q value varying with the bias signal. Consequently, there are few means for external optimization. Therefore, the present invention proposes a reconfigurable, electrically tunable frequency-hopping filter that utilizes auxiliary circuits to improve out-of-band rejection performance and reduce distortion, as well as a multi-objective optimization control method for the filter. Summary of the Invention

[0005] The purpose of the present invention is to provide a reconfigurable electrically tunable frequency hopping filter and a multi-objective optimization control method thereof, which can pre-nonlinearly compensate for signals of different frequencies and then distribute them to corresponding resonant circuits by address code calculation through a digital chip, thereby improving out-of-band suppression performance and reducing distortion.

[0006] The technical solutions adopted by the present invention are as follows: Reconfigurable electrically tunable frequency hopping filter, including: MCU module, which is equipped with two main control CPUs for RF signal processing, parameter control and communication coordination; The resonant circuit module calculates the address code through the main control CPU and sets the radio frequency signal processing to direct processing or filtering processing; A pre-distortion module measures the CV curve and tuning voltage-frequency response of the varactor diode and establishes a nonlinear model for RF signal preprocessing of the MCU module; The signal transceiver module sends the radio frequency signal to the pre-distortion module, or outputs the radio frequency signal after direct processing through the parameter control of the MCU module.

[0007] As an optional solution, the predistortion module includes: Digital predistorter, based on FPGA or DSP, generates predistorted signals in the digital domain; The DAC unit is used to output the predistortion signal to the bias end of the resonant circuit module.

[0008] As an optional solution, the address code calculated by the main control CPU includes a 10-bit parallel binary code, which is A9 to A0 in sequence and is compatible with CMOS and TTL levels; Among them, A9~A8 are frequency band selection codes, and A7~A0 are intra-segment address codes.

[0009] As an optional solution, the resonant circuit module includes: The first filter digital chip, when the frequency band control A9=0, A8=0, the frequency band is selected as 225~400MHz; The second filter digital chip, when the frequency band control A9=0, A8=1, the frequency band selection is 400~678MHz; For the third filtering digital chip, when the frequency band control A9=1 and A8=0, the frequency band is selected as 108~174MHz.

[0010] As an optional solution, the first digital filtering chip, the second digital filtering chip, and the third digital filtering chip are all connected in parallel with an inductor, a capacitor, and a varactor diode.

[0011] As an optional solution, the first main control CPU is connected in series with capacitors C1, C3, C5, C6, C8, C9, C13, C14, C17, and C19.

[0012] As an optional solution, the second main control CPU is connected in series with capacitors C2, C4, C7, C7, C9, C10, C11, C12, C15, C16, C18, and C20.

[0013] As an alternative, the CV curve of the varactor diode of the nonlinear model is derived from the depletion layer capacitance formula, considering the capacitance at zero bias voltage. , junction potential , gradient coefficient m.

[0014] As an optional solution, the signal transceiver module includes an RX branch, a TX branch, a 1022 branch, a 2240 branch, and a 4067 branch.

[0015] A multi-objective optimization control method for a reconfigurable electrically tunable frequency hopping filter includes the following steps: Step 1: Measure the CV curve and tuning voltage-frequency response of the varactor diode and establish a nonlinear model; Step 2: Receive the RF signal, calculate the address code through the main control CPU, set the RF signal processing to direct processing, send it to the signal transceiver module for output, or set the RF signal to filter processing; Step 3: Sending the RF signal filtered in step 2 to a predistortion module for static nonlinear compensation; Step 4: Send the RF signal compensated in step 3 to the resonant circuit module for filtering and then output via the signal transceiver module.

[0016] The technical effects achieved by the present invention are: The present invention uses an auxiliary circuit to generate a pre-distortion signal in the digital domain, measures the CV curve and tuning voltage-frequency response of the varactor diode, establishes a nonlinear model, and pre-injects distortion opposite to the nonlinear characteristics of the varactor diode into the input signal, thereby offsetting the nonlinear effect at the output end. The signal is then distributed to the corresponding resonant circuit through address code calculation, thereby improving out-of-band suppression performance and reducing distortion.

[0017] In the process of nonlinear characteristic modeling, the present invention designs a predistorter by using the depletion layer capacitance formula, nonlinear expansion, mathematical expression of transfer function and modeling method of nonlinear transfer function, so as to provide a theoretical basis for nonlinear compensation of the filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 1 is a circuit diagram of the first master control CPU in the first embodiment of the present invention; Figure 2 is a diagram of the second master CPU in the first embodiment of the present invention; Figure 3 is a circuit diagram of the first filtering digital chip in the first embodiment of the present invention; Figure 4 is a circuit diagram of the second filtering digital chip in the first embodiment of the present invention; Figure 5 is a circuit diagram of the third filtering digital chip in the first embodiment of the present invention; Figure 6 This is a circuit diagram of a resonant circuit attached to the first filtering digital chip in the first embodiment of the present invention; Figure 7 This is a circuit diagram of a resonant circuit belonging to the second filtering digital chip in the first embodiment of the present invention; Figure 8 This is a circuit diagram of a resonant circuit belonging to the third filtering digital chip in the first embodiment of the present invention; Figure 9 is a system block diagram of a reconfigurable electrically tunable frequency hopping filter in embodiment 1 of the present invention; Figure 10 Schematic diagram of address code allocation in embodiment 1 of the present invention; Figure 11 It is a flow chart of the multi-objective optimization control method in embodiment 2 of the present invention. DETAILED DESCRIPTION

[0019] In order to make the purpose and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the following examples. It should be understood that the following text is only used to describe one or more specific embodiments of the present invention and does not strictly limit the scope of protection of the present invention.

[0020] Example 1: like Figures 1-10 As shown, the reconfigurable electrically tunable frequency hopping filter includes a PCB circuit board and an MCU module, a resonant circuit module, a predistortion module, and a signal transceiver module mounted on the PCB circuit board. When working, the signal transceiver module receives the radio frequency signal, calculates the address code through the main control CPU of the MCU module, sets the radio frequency signal processing to pass-through processing or filtering processing, and performs compensation through the nonlinear model established by the predistortion module to complete the preprocessing. The signal is then filtered through the resonant circuit module and converted into a radio frequency signal of a suitable frequency band, which is finally output by the signal transceiver module.

[0021] Among them, the PCB circuit board can be encapsulated in a metal shell to isolate external interference signals, and to be waterproof and dustproof, leaving a signal transfer bus interface.

[0022] Refer to the attached Figure 1 、 Figure 2 and Figure 9 ,This embodiment uses two main control CPUs to form a dual-channel filtering structure, both equipped with RX branch, TX branch, 1022 branch, 2240 branch, and 4067 branch; Among them, 1022 branches, 2240 branches, and 4067 branches are divided into IN interfaces and OUT interfaces. Figure 1 and Figure 2 The OUT interface is used for direct output, the IN interface is used for direct input, the RF connector model is SMP-J, and the low-frequency connector model is STMM-107-01-FD.

[0023] Refer to the attached Figure 1 ,The first main control CPU is connected in series with capacitors C1, C3, C5, C6, C8, C9, C13, C14, C17, and C19, which are used for signal processing, parameter control, and communication coordination of RF signal input.

[0024] Refer to the attached Figure 2 ,The second main control CPU is connected in series with capacitors C2, C4, C7, C7, C9, C10, C11, C12, C15, C16, C18, and C20, which are used for signal processing, parameter control, and communication coordination of RF signal output.

[0025] Refer to the attached Figure 1 and Figure 2 , the first master CPU and the second master CPU are both written with the algorithm for calculating the address code, as follows: Address code to be tuned = 50 in, is the center frequency to be tuned within the segment, is the lowest frequency in the segment, is the highest frequency in the segment, 250 is the total number of insertions in the segment, and the calculation structure uses rounding to the nearest integer; See also Figure 10 , the address code contains 10-bit parallel binary code, which is A9 to A0, compatible with CMOS and TTL levels; Among them, A9~A8 are frequency band selection codes, and A7~A0 are intra-band address codes; When the frequency band control A9=0, A8=0, the frequency band is selected as 225~400MHz, and you can choose Figure 3 The first filtering digital chip and its subordinate resonant circuit shown perform filtering; When the frequency band control A9=0, A8=1, the frequency band is selected as 400~678MHz, and the following options can be selected: Figure 4 The second filtering digital chip and its subordinate resonant circuit are shown to perform filtering; When the frequency band control A9=1, A8=0, the frequency band is selected as 108~174MHz, and the following options can be selected: Figure 5 The third filtering digital chip and its subordinate resonant circuit are shown to perform filtering; The subordinate resonant circuits and frequency bands corresponding to the above three filtering digital chips are not limited to the above three frequency bands and can be adaptively adjusted according to user needs.

[0026] Refer to the attached Figure 3Pin 1 of the first filtering digital chip is connected to pin 13 of the first master CPU and pin 12 of the second master CPU. The slave resonant circuit is connected in parallel with capacitors C31, C32, C33, C34, C35, C46, C47, C48, C49, C50, C61, C62, C63, C64, C65, C76, C77, C78, C79, and C80, and is also connected in parallel with varactor diodes D21, D22, D23, D24, D25, D26, D27, D28, D29, D30, D51, D52, D53, D54, D55, D56, D57, D58, D59, and D60. The capacitance values of these capacitors are adjusted by reverse bias, thereby changing the resonant frequency. When the reverse bias increases, the capacitance value decreases and the resonant frequency decreases; otherwise, it increases.

[0027] Refer to the attached Figure 4 Pin 1 of the second filtering digital chip is connected to pin 13 of the first master CPU and pin 12 of the second master CPU, and the slave resonant circuit is connected in parallel with capacitors C91, C92, C93, C94, C95, C106, C107, C108, C109, C110, C121, C122, C123, C124, C125, C136, C137, C138, C139, and C140, and Varactor diodes D81, D82, D83, D84, D85, D86, D87, D88, D89, D90, D111, D112, D113, D114, D115, D116, D117, D118, D119, and D120 are connected in series. The capacitance of these capacitors is adjusted by reverse bias, thereby changing the resonant frequency. When the reverse bias increases, the capacitance decreases and the resonant frequency decreases; otherwise, it increases.

[0028] Refer to the attached Figure 5 Pin 1 of the third filtering digital chip is connected to pin 13 of the first master CPU and pin 12 of the second master CPU. The slave resonant circuit is connected in parallel with capacitors C151, C152, C153, C154, C155, C166, C167, C168, C169, C170, C171, C172, C173, C174, C175, C196, C197, C198, C199, and C200. Varactor diodes D141, D142, D143, D144, D145, D146, D147, D148, D149, D150, D171, D172, D173, D174, D175, D176, D177, D178, D179, and D180 adjust the capacitance of these capacitors by reverse bias, thereby changing the resonant frequency; when the reverse bias increases, the capacitance decreases and the resonant frequency decreases; otherwise, it increases.

[0029] The three subordinate resonant circuits described above use a multi-stage varactor diode tuning circuit (such as a cascade tuning circuit) to improve overall selectivity through segmented tuning.

[0030] Varactor diodes are primarily used for automatic tuning, frequency modulation, and phase modulation in high-frequency circuits. Their out-of-band rejection performance generally relies on their inherent high quality factor, meaning that their Q value varies slightly with the bias signal. External optimization methods are limited. Therefore, this embodiment utilizes auxiliary circuits to improve out-of-band rejection performance and reduce distortion. The following components are employed: A digital predistorter, based on an FPGA or DSP, generates a predistorted signal in the digital domain, measures the CV curve and tuning voltage-frequency response of the varactor diode, and establishes a nonlinear model for RF signal preprocessing of the MCU module; The DAC unit is electrically connected to the digital predistorter, the RX branch, the TX branch, and the three filtering digital chips, and is used to output the predistortion signal to the bias ends of the three subordinate resonant circuits.

[0031] Predistortion technology pre-injects distortion opposite to the nonlinear characteristics of the varactor diode into the input signal, thereby offsetting the nonlinear effect at the output. The implementation steps are as follows: (1) Nonlinear characteristic modeling Measure the CV curve and tuning voltage-frequency response of varactor diodes and establish nonlinear models (such as polynomial models, Volterra series, or lookup tables); For example, the capacitance-voltage relationship can be modeled as:

[0032] in, Characterize nonlinear terms; (2) Predistorter design Design an inverse nonlinear function to make the combination of predistorter and varactor diode close to linear; If the nonlinear transfer function of the varactor diode is H( ), the transfer function of the predistorter G ( ) should meet the following requirements: ≈k·v Where k is a constant, and the predistortion parameters can be dynamically updated through an iterative algorithm (such as LMS adaptive filtering); (3) Hardware implementation FPGA / DSP processing: Generate predistortion signal in digital domain, see Figure 9 , output to the bias terminal of the varactor diode through the DAC; (4) Calibration and feedback; The output spectrum is monitored in real time, and the predistortion parameters are adjusted through a feedback loop (such as PID control).

[0033] Nonlinearity sources of varactor diodes: The capacitance-voltage (CV) characteristic of a varactor diode is determined by the variation of the depletion layer width of the PN junction or Schottky junction with voltage. Its nonlinear nature comes from: (5) Depletion layer capacitance formula For a reverse biased PN junction, the capacitance C( ) and voltage The relationship is: =

[0034] in, The capacitance at zero bias, is the junction potential, m is the gradient coefficient; (6) Nonlinear expansion Will At the working point Taylor expansion at , we get the nonlinear transfer function:

[0035] Among them, the high-order terms ( 、 ) causes harmonic and intermodulation distortion; (7) Mathematical expression of transfer function Capacitance-voltage relationship (CV characteristics): Directly describe the effect of bias voltage v on capacitance C:

[0036] Linear approximation, under small signal conditions ( ∅), can be simplified to: ( ) Among them, the quadratic term and higher-order terms characterize nonlinearity; Tuning frequency-voltage relationship In a VCO (voltage controlled oscillator), the tuning frequency of the varactor diode The relationship with capacitance is:

[0037] The transfer function becomes:

[0038] Nonlinear expansion: Assumptions m=0.5 (mutation knot), after expansion:

[0039] Among them, the nonlinearity is mainly caused by Item leading; (8) Modeling method of nonlinear transfer function Polynomial Model: Suitable for small signal analysis. H Expressed as:

[0040] Among them, the coefficient extraction is performed by fitting the polynomial coefficients through the measured CV curve (e.g., the least squares method); Piecewise linear model: In the large signal range, the CV curve is linearized in segments, and each segment is approximated with a different slope:

[0041] (9) Measurement method of nonlinear transfer function The network analyzer sweeps the frequency to measure the S parameters under different bias voltages and extract the capacitance value. ; Or use a spectrum analyzer to test, input a single-frequency / dual-frequency signal, and observe the harmonics and intermodulation products in the output spectrum; Or use an LCR meter to perform a DC bias sweep and directly measure the CV curve (pay attention to high-frequency effects).

[0042] Example 2: like Figure 11 As shown, the multi-objective optimization control method is applicable to the reconfigurable electrically tunable frequency hopping filter of embodiment 1, and includes the following steps: Step 1: Measure the CV curve and tuning voltage-frequency response of the varactor diode and establish a nonlinear model; Step 2: Receive the RF signal, calculate the address code through the main control CPU, set the RF signal processing to direct processing, send it to the signal transceiver module for output, or set the RF signal to filter processing; The algorithm for calculating the address code is as follows: Address code to be tuned = 50 in, is the center frequency to be tuned within the segment, is the lowest frequency in the segment, is the highest frequency in the segment, 250 is the total number of insertions in the segment, and the calculation structure uses rounding to the nearest integer; See also Figure 10, the address code contains 10-bit parallel binary code, which is A9 to A0, compatible with CMOS and TTL levels; Among them, A9~A8 are frequency band selection codes, and A7~A0 are intra-band address codes; When the frequency band control A9=0, A8=0, the frequency band is selected as 225~400MHz, using Figure 3 The first filtering digital chip and its subordinate resonant circuit shown perform filtering; When the frequency band control A9=0, A8=1, the frequency band is selected as 400~678MHz, using Figure 4 The second filtering digital chip and its subordinate resonant circuit are shown to perform filtering; When the frequency band control A9=1, A8=0, the frequency band is selected as 108~174MHz, using Figure 5 The third filtering digital chip and its subordinate resonant circuit are shown to perform filtering; Step 3: Send the RF signal filtered in step 2 to the predistortion module, and use static nonlinear compensation to perform nonlinear characteristic modeling and predistortion on the three frequency bands in step 2, and the two are processed together to complete the compensation; Step 4: Send the RF signal compensated in step 3 to the resonant circuit module for filtering and then output via the signal transceiver module.

[0043] The foregoing merely represents optional embodiments of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained herein shall, unless otherwise specified or limited, be implemented in accordance with conventional means in the art.

Claims

1. Reconfigurable electrically tunable frequency hopping filter, characterized in that: include: MCU module, which is equipped with two main control CPUs for RF signal processing, parameter control and communication coordination; The resonant circuit module calculates the address code through the main control CPU and sets the radio frequency signal processing to direct processing or filtering processing; A pre-distortion module measures the CV curve and tuning voltage-frequency response of the varactor diode and establishes a nonlinear model for RF signal preprocessing of the MCU module; The signal transceiver module sends the radio frequency signal to the pre-distortion module, or outputs the radio frequency signal after direct processing through the parameter control of the MCU module.

2. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The predistortion module includes: Digital predistorter, based on FPGA or DSP, generates predistorted signals in the digital domain; The DAC unit is used to output the predistortion signal to the bias end of the resonant circuit module.

3. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The address code calculated by the main control CPU includes 10-bit parallel binary code, which is A9 to A0 in sequence and is compatible with CMOS and TTL levels; Among them, A9~A8 are frequency band selection codes, and A7~A0 are intra-segment address codes.

4. The reconfigurable electrically tunable frequency hopping filter according to claim 3, wherein: The resonant circuit module includes: The first filter digital chip, when the frequency band control A9=0, A8=0, the frequency band is selected as 225~400MHz; The second filter digital chip, when the frequency band control A9=0, A8=1, the frequency band selection is 400~678MHz; For the third filtering digital chip, when the frequency band control A9=1 and A8=0, the frequency band is selected as 108~174MHz.

5. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The first digital filtering chip, the second digital filtering chip, and the third digital filtering chip are all connected in parallel with an inductor, a capacitor, and a varactor diode.

6. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The first main control CPU is connected in series with capacitors C1, C3, C5, C6, C8, C9, C13, C14, C17, and C19.

7. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The second main control CPU is connected in series with capacitors C2, C4, C7, C7, C9, C10, C11, C12, C15, C16, C18, and C20.

8. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The CV curve of the varactor diode of the nonlinear model is derived from the depletion layer capacitance formula, considering the capacitance at zero bias voltage. , junction potential , gradient coefficient m.

9. The reconfigurable electrically tunable frequency hopping filter according to claim 1, wherein: The signal transceiver module includes an RX branch, a TX branch, a 1022 branch, a 2240 branch, and a 4067 branch.

10. A multi-objective optimization control method for a reconfigurable electrically tunable frequency hopping filter, applied to the reconfigurable electrically tunable frequency hopping filter according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1: Measure the CV curve and tuning voltage-frequency response of the varactor diode and establish a nonlinear model; Step 2: Receive the RF signal, calculate the address code through the main control CPU, set the RF signal processing to direct processing, send it to the signal transceiver module for output, or set the RF signal to filter processing; Step 3: Sending the RF signal filtered in step 2 to a predistortion module for static nonlinear compensation; Step 4: Send the RF signal compensated in step 3 to the resonant circuit module for filtering and then output via the signal transceiver module.

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