Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a multi-layer storage unit located on a substrate; each layer of storage units comprises a plurality of storage units which are distributed at intervals along a first direction and a second direction which are parallel to the substrate; the memory unit comprises a transistor, and the transistor comprises a semiconductor layer, a gate electrode at least partially surrounding the semiconductor layer and a gate insulating layer located between the semiconductor layer and the gate electrode; the semiconductor layer extends along a second direction parallel to the substrate, and the first direction intersects with the second direction; and the connecting part extends along the first direction, and the gate electrodes of the transistors of the plurality of memory cells distributed at intervals along the first direction are connected through the connecting part. According to the semiconductor device provided by the embodiment of the invention, relatively high storage density can be realized.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing accordingly, so that slight differences in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The semiconductor device can achieve a higher storage density.

[0006] An embodiment of the present application provides a semiconductor device, comprising: a multi-layer memory cell located on a substrate;

[0007] Each layer of the memory cells includes a plurality of memory cells spaced apart along a first direction and a second direction parallel to the substrate, wherein the first direction intersects the second direction; the memory cells include transistors, each transistor including a semiconductor layer, a gate electrode at least partially surrounding the semiconductor layer, and a gate insulating layer located between the semiconductor layer and the gate electrode; the semiconductor layer extends along the second direction;

[0008] The connecting portion extends along the first direction, wherein gate electrodes of transistors of a plurality of memory cells spaced apart and distributed along the first direction are connected via the connecting portion.

[0009] In some embodiments, the gate insulating layer includes a ferroelectric material.

[0010] In some embodiments, the connecting portion has two end surfaces connected to the gate electrode, and each of the end surfaces is in contact with an outer sidewall of an adjacent gate electrode.

[0011] In some embodiments, the gate electrode extends in the second direction and both ends of the gate electrode extend at least to an outer contour of the connecting portion.

[0012] In some embodiments, the connecting portion and the gate electrode are made of different materials; or

[0013] The connection portion is made of the same material as the gate electrode.

[0014] In some embodiments, the semiconductor device further includes a bit line and a common electrode layer spaced apart in the second direction; the semiconductor layer extends in the second direction and has two end surfaces, the two end surfaces of the semiconductor layer are respectively connected to the bit line and the common electrode layer, and the common electrode layer is connected to the reference signal terminal;

[0015] The bit line extends in a direction perpendicular to the substrate and is connected to one end surface of the semiconductor layer of the transistors of a column of the memory cells located in different layers.

[0016] In some embodiments, the common electrode layer extends along a direction perpendicular to the substrate and the first direction and is connected to one end of each semiconductor layer of each stacked memory cell arranged along the first direction.

[0017] In some embodiments, the semiconductor device further includes a first bit line and a second bit line spaced apart in a second direction; the semiconductor layer extends in the second direction and has two end surfaces, and the two end surfaces of the semiconductor layer are respectively connected to the first bit line and the second bit line;

[0018] The first bit line and the second bit line extend in a direction perpendicular to the substrate and are connected to two end surfaces of the semiconductor layer of transistors of a column of the memory cells located in different layers.

[0019] In some embodiments, the gate insulation layer extends onto two opposite sidewalls of the bit line along the second direction.

[0020] In some embodiments, the semiconductor device is a Nor Flash memory.

[0021] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0022] Providing a substrate, and alternately depositing a predetermined gate electrode layer and a first insulating layer on the substrate to obtain a stacked structure, wherein the predetermined gate electrode layer is a dielectric layer or a conductive layer;

[0023] Performing patterned etching on the stack structure to form a plurality of trenches in the stack structure, wherein the plurality of trenches extend along a first direction parallel to the substrate and are spaced apart in a second direction parallel to the substrate, wherein the first direction intersects the second direction; and between two adjacent trenches in the second direction, a connection region extending along the first direction and a gate region extending along the second direction are included;

[0024] Removing the gate region of each predetermined gate electrode layer and retaining the connection region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches, sequentially forming a gate electrode, a gate insulating layer, and a semiconductor layer within the gate hole; and forming a plurality of spaced-apart bit lines within one of the two adjacent trenches, the plurality of bit lines extending in a direction perpendicular to the substrate and spaced-apart in the first direction;

[0025] The retained connection region is the conductive layer, which contacts the gate electrode; or the retained connection region is the dielectric layer, and the method further includes replacing the dielectric layer with a conductive layer, which contacts the gate electrode.

[0026] In some embodiments, the stacked structure is patterned and etched to form a plurality of trenches in the stacked structure, and the connection region extending along the first direction and the gate region extending along the second direction between two adjacent trenches in the second direction include:

[0027] Performing patterned etching on the stack structure to successively form a plurality of through holes and a plurality of trenches in the stack structure, wherein the plurality of through holes extend in a direction perpendicular to the substrate and are spaced apart; and forming a second insulating layer in the through holes;

[0028] Two adjacent trenches expose the second insulating layer of each through hole; the area between two adjacent second insulating layers in the first direction is the gate area, and the area between two adjacent second insulating layers in the second direction is the connecting area.

[0029] In some embodiments, removing the gate region in each of the predetermined gate electrode layers and retaining the connection region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches, and forming a gate electrode in the gate hole includes:

[0030] Removing the gate region in each of the preset gate electrode layers and retaining the connecting region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches;

[0031] Depositing a gate electrode layer and a sacrificial layer in sequence in the gate hole and the trench;

[0032] The gate electrode layer and the sacrificial layer in the two adjacent trenches are removed, and the gate electrode layer in the gate hole is retained as the gate electrode.

[0033] In some embodiments, sequentially depositing a gate insulating layer and a semiconductor layer in the gate hole includes:

[0034] Depositing the gate insulating layer and the semiconductor layer in sequence in the trench and the gate hole and filling them with insulating material;

[0035] removing the semiconductor layer and insulating material in the trench, retaining the semiconductor layer and insulating material in the gate hole, and retaining the gate insulating layer in the trench and the gate hole;

[0036] Wherein, the gate insulating layer includes ferroelectric material.

[0037] In some embodiments, forming a plurality of bit lines spaced apart in one of two adjacent trenches, wherein the plurality of bit lines extend in a direction perpendicular to the substrate and are spaced apart in the first direction, comprises:

[0038] A conductive material is deposited in one of the two trenches, and a film layer formed by the conductive material is disconnected in the first direction to form the plurality of bit lines. An insulating material is filled between two adjacent bit lines for insulation.

[0039] In some embodiments, the manufacturing method further comprises: depositing and filling a conductive material in another of the two trenches as a common electrode layer, wherein the common electrode layer is connected to one end of the semiconductor layer and to a reference signal terminal;

[0040] The common electrode layer is simultaneously connected to the semiconductor layers of the memory cells adjacent to each other in the second direction.

[0041] In some embodiments, the plurality of bit lines are used as first bit lines;

[0042] The manufacturing method also includes: depositing and filling a conductive material in the other of the two trenches, disconnecting the film layer formed by the conductive material in the first direction to form a second bit line, and the first bit line and the second bit line respectively connect the two ends of the semiconductor layer of the transistor of the memory cell.

[0043] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the embodiment of the present application, or includes a semiconductor device obtained by the method for manufacturing the semiconductor device provided in the embodiment of the present application.

[0044] The semiconductor device of the embodiment of the present application is a three-dimensional (3D) structure, thus achieving a higher storage density and a lower bit cost. Moreover, the manufacturing method of the semiconductor device of the embodiment of the present application is simple, and a semiconductor device with stable performance can be easily obtained.

[0045] Other features and advantages of the present application will be described in the following description, and in part will become more apparent from the description, or understood by practicing the present application. The purposes and advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0047] Figure 1A A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to the substrate and passing through a gate electrode and a connection portion;

[0048] Figure 1B for Figure 1A The semiconductor device shown is along Figure 1A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0049] Figure 1C for Figure 1A The semiconductor device shown is along Figure 1A A schematic cross-sectional view of the BB section perpendicular to the substrate;

[0050] Figure 1D A circuit connection diagram of a semiconductor device according to an exemplary embodiment of the present application;

[0051] Figure 2A A schematic cross-sectional view of another semiconductor device according to an exemplary embodiment of the present application, taken along a cross section parallel to the substrate and passing through a gate electrode and a connection portion;

[0052] Figure 2B A circuit connection diagram of another semiconductor device according to an exemplary embodiment of the present application;

[0053] Figure 3 is the polarization curve of the ferroelectric material;

[0054] Figure 4 A current-voltage curve of a ferroelectric field effect transistor of a semiconductor device according to an exemplary embodiment of the present application during data reading;

[0055] Figure 5 A process flow chart of a method for manufacturing a semiconductor device provided for an exemplary embodiment of the present application;

[0056] Figure 6A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a stacked structure;

[0057] Figure 6B for Figure 6A The semiconductor structure shown is along Figure 6A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0058] Figure 7A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after a second insulating layer is filled in a through hole;

[0059] Figure 7B for Figure 7A The semiconductor structure shown is along Figure 7A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0060] Figure 8A A schematic cross-sectional view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to a substrate and passing through a predetermined gate electrode layer after forming a trench;

[0061] Figure 8B for Figure 8A The semiconductor structure shown is along Figure 8A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0062] Figure 9A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a groove;

[0063] Figure 9B for Figure 9A The semiconductor structure shown is along Figure 9A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0064] Figure 9C for Figure 9A The semiconductor structure shown is along Figure 9A A schematic cross-sectional view of the BB section perpendicular to the substrate;

[0065] Figure 10A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after a groove is filled with a sacrificial layer;

[0066] Figure 10B for Figure 10A The semiconductor structure shown is along Figure 10A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0067] Figure 10C for Figure 10A The semiconductor structure shown is along Figure 10A A schematic cross-sectional view of the BB section perpendicular to the substrate;

[0068] Figure 11A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after removing a gate electrode layer and a sacrificial layer in a trench;

[0069] Figure 11B for Figure 11A The semiconductor structure shown is along Figure 11A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0070] Figure 12A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after removing a sacrificial layer;

[0071] Figure 12B for Figure 12A The semiconductor structure shown is along Figure 12A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0072] Figure 12C for Figure 12A The semiconductor structure shown is along Figure 12A A schematic cross-sectional view of the BB section perpendicular to the substrate;

[0073] Figure 13A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after a groove is filled with an insulating material;

[0074] Figure 13B for Figure 13A The semiconductor structure shown is along Figure 13A A schematic cross-sectional view of the AA section perpendicular to the substrate;

[0075] Figure 13C for Figure 13A The semiconductor structure shown is along Figure 13A A schematic cross-sectional view of the BB section perpendicular to the substrate;

[0076] Figure 14A A top view of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after removing the semiconductor layer and the insulating material in the trench;

[0077] Figure 14B for Figure 14A The semiconductor structure shown is along Figure 14A Schematic cross-sectional view of the AA section perpendicular to the substrate.

[0078] The meanings of the various symbols in the accompanying drawings are:

[0079] 10-substrate; 11-preset gate electrode layer; 111-connection region; 112-gate region; 12-first insulating layer; 13-second insulating layer; 14-sacrificial layer; 15-insulating material; 20-transistor; 21-first electrode; 22-second electrode; 23-semiconductor layer; 24-gate electrode; 24'-gate electrode layer; 25-gate insulating layer; 26-connection; 30-common electrode layer; BL-bit line; WL-word line; 51-trench; 52-gate hole; K-through hole. DETAILED DESCRIPTION

[0080] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0081] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.

[0082] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments and may also be other shapes and sizes. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present application are not limited to the shapes or values shown in the drawings.

[0083] The sizes and proportions of the various film layers or components in the drawings of this application can be used as a reference in actual processes and are exemplary embodiments of the present invention. However, the drawings are not intended to be limiting. For example, the width-to-length ratio of the semiconductor layer, the thickness of the various film layers, and the spacing between them can be adjusted based on actual needs.

[0084] The ordinal numbers such as “first” and “second” in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0085] In this application, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on this application. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in the disclosure are not limited and may be appropriately replaced according to the circumstances.

[0086] In this application, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0087] In this application, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0088] In this application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may be interchanged. Therefore, in this application, unless otherwise specified, the terms "source electrode" and "drain electrode" may be interchanged.

[0089] In this application, "electrical connection" or "connection" includes situations where components are connected together through an element with some electrical function, such as electrical signal connection (coupling connection, such as coupled to), or physical direct connection. There is no particular limitation on the "element with some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0090] In this application, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0091] In this application, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0092] The phrase "A and B are disposed in the same layer" in this application means that A and B are distributed on the same horizontal plane, or, although not on the same horizontal plane, are located in different areas of the same support surface. In one embodiment, A and B are formed simultaneously through the same patterning process on the same film layer.

[0093] In the embodiments of this application, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, if A and B are formed from the same material into a single film layer and are simultaneously connected through the same patterning process, or if B is directly grown on A via epitaxial growth, the two materials may not be identical.

[0094] The substrate in the embodiment of the present application can be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed. The device involved in the inventive structure of the embodiment of the present application is arranged on the main surface of the supporting structure.

[0095] In this application, the term "separated distribution" can be understood as a separate, independent distribution. Separation can be achieved by physical structural disconnection or electrical disconnection. For example, the semiconductor layer between the active channels of two transistors is modified to achieve insulation to achieve electrical separation between the two channels.

[0096] An embodiment of the present application provides a semiconductor device. Figure 1A A schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application, taken on a cross section parallel to the substrate and passing through a gate electrode and a connection portion; Figure 1B for Figure 1A The semiconductor device shown is along Figure 1A A schematic cross-sectional view of the AA section perpendicular to the substrate; Figure 1C for Figure 1A The semiconductor device shown is along Figure 1A Schematic cross-sectional view of the BB section perpendicular to the substrate.

[0097] like Figures 1A to 1C As shown, the semiconductor device of the embodiment of the present application includes: a substrate 10 and a multi-layer memory cell, a gate electrode 24 and a connection portion 26 between the gate electrodes located on the substrate 10;

[0098] The multi-layer memory cells are stacked and distributed along a direction perpendicular to the substrate 10, and each layer of the memory cells includes a plurality of memory cells spaced apart and distributed along a first direction parallel to the substrate; the memory cells include transistors 20, which include a laterally extending cylindrical (solid) or annular (hollow) semiconductor layer 23, an annular gate electrode 24 at least partially surrounding an outer sidewall of the semiconductor layer 23, and an annular gate insulating layer 25 located between the semiconductor layer 23 and the gate electrode 24; the cylindrical or annular semiconductor layer 23 extends along a second direction parallel to the substrate 10, and the first direction intersects the second direction;

[0099] The longitudinal section of the semiconductor layer 23 in the first direction ( Figure 1A BB direction) is the cylindrical (solid) or annular (hollow).

[0100] The semiconductor device includes a semiconductor device along the first direction (eg, Figure 1A Gate electrodes 24 of transistors of a plurality of memory cells spaced apart (in the X direction shown) and connecting portions 26 connected to the gate electrodes 24, the connecting portions 26 extending along the first direction being a solid structure, and in some embodiments also being a hollow structure with an end portion near the gate electrode 24, the end portion being connected to the gate electrode 24;

[0101] The connection portion 26 and the gate electrode 24 connected thereto are in contact connection and are not formed in a single process.

[0102] The semiconductor device of the embodiment of the present application stacks and distributes the memory cells in a direction perpendicular to the substrate to form a three-dimensional (3D) structure, thereby achieving a higher storage density and a lower bit cost.

[0103] In some embodiments of the present application, the gate insulating layer includes a ferroelectric material, and the transistor is a ferroelectric transistor. The semiconductor device of the embodiment of the present application uses a gate insulating layer of a ferroelectric material having ferroelectric properties, and can achieve 1-bit storage without an additional capacitor. In some embodiments, the gate insulating layer can be a single layer, and the single layer can include a ferroelectric material layer. In some embodiments, the gate insulating layer can be multilayer, and at least one of the multilayer film layers includes a ferroelectric material layer.

[0104] In some embodiments of the present application, the first direction may be as follows Figure 1A The X direction shown, the second direction can be as follows Figure 1A Y direction shown.

[0105] In some embodiments of the present application, the connecting portion has two end surfaces connected to the gate electrode, and each end surface contacts the outer sidewall of the adjacent gate electrode. For example, the entire area of each end surface contacts the outer sidewall of the adjacent gate electrode. Exemplarily, the shape of the end surface can be square, rectangular, circular, etc. The entire area of each end surface of the connecting portion contacts the sidewall of the gate electrode, which can avoid a virtual connection between the connecting portion and the gate electrode.

[0106] In some embodiments of the present application, Figure 1A As shown, the gate electrode 24 extends in the second direction and both ends of the gate electrode 24 extend at least to the outer contour of the connecting portion 26, which is a contour line extending along the first direction. In some embodiments, both ends of the gate electrode 24 extend beyond a certain area of the outer contour of the connecting portion 26, thereby increasing the control area of the channel and improving device performance. In some embodiments, both ends of the gate electrode 24 extend to both ends of the semiconductor layer, and the length of the gate electrode in the second direction is the same as the length of the semiconductor layer in the second direction. In some embodiments, the gate electrode and the semiconductor layer have the same shape, the semiconductor layer is formed in various areas of the inner sidewall of the gate electrode, and the two are insulated by a gate insulating layer. In some embodiments, the length of the gate electrode in the second direction is less than the length of the semiconductor layer in the second direction. During the manufacturing process, the semiconductor layer is first formed in the gate electrode, and then the film layer of the gate electrode covering the semiconductor layer near the end area is etched away.

[0107] In some embodiments of the present application, the gate electrode 24 extends in the second direction and both ends of the gate electrode 24 extend at least to the outer contour of the connecting portion 26. It can be understood that the size of the connecting portion in the second direction is less than or equal to the size of the gate electrode in the second direction. Figure 1A As shown, a dimension W1 of the connection portion 26 in the second direction is smaller than a dimension W2 of the gate electrode 24 in the second direction.

[0108] The connection portion 26 and the gate electrode 24 of the semiconductor device in the embodiment of the present application have different sizes in the second direction, and the sizes of the connection portion 26 and the gate electrode 24 can be designed separately as needed.

[0109] In some embodiments, the gate electrode in the second direction is etched back so that the size of the gate electrode in the second direction is equal to the size of the connecting portion 26 in the second direction, thereby reducing the coupling capacitance between the gate electrode or the connecting portion and the bit line.

[0110] In some embodiments of the present application, the material of the connecting portion and the gate electrode may be the same or different.

[0111] In some embodiments of the present application, Figure 1A and Figure 1BAs shown, the semiconductor device further includes a bit line BL, which extends in a direction perpendicular to the substrate 10 and is connected to one end surface of the semiconductor layer 23 of the transistor 20 of a column of the memory cells located in different layers.

[0112] In some embodiments of the present application, Figure 1B As shown, the transistor 20 may further include a first electrode 21 and a second electrode 22 , with the semiconductor layer 23 located between the first electrode 21 and the second electrode 22 ; the first electrode 21 and / or the second electrode 22 extend in a direction perpendicular to the substrate 10 .

[0113] Figure 1D FIG. 1 is a circuit connection diagram of a semiconductor device according to an exemplary embodiment of the present application. Figure 1D As shown, in some embodiments of the present application, each memory cell includes a ferroelectric transistor, the gate of which is connected to the word line, one of the source and the drain is connected to the bit line, and the other is connected to a reference signal terminal (such as a ground terminal).

[0114] The first electrodes 21 of the transistors 20 of the memory cells in a column located at different layers are connected to the same bit line BL.

[0115] In some embodiments of the present application, Figure 1B As shown, the first electrode 21 and the bit line BL connected thereto may be an integrated structure.

[0116] In some embodiments of the present application, Figure 1D As shown, the transistors 20 of the multi-layer memory cell may be distributed in an array in the first direction and the second direction.

[0117] In some embodiments of the present application, Figure 1B As shown, the semiconductor device may further include a common electrode layer 30, which is spaced apart from the bit line BL in the second direction; the semiconductor layer 23 extends in the second direction and has two end faces, the two end faces of the semiconductor layer 23 are respectively connected to the bit line BL and the common electrode layer 30, and the common electrode layer 30 is connected to the reference signal end.

[0118] The common electrode layer 30 extends along a direction perpendicular to the substrate 10 and the first direction, and is connected to one end of each semiconductor layer 23 of each stacked memory cell arranged along the first direction; the common electrode layer 30 is shared between two adjacent memory cells in the second direction.

[0119] In some embodiments of the present application, Figure 1B As shown, the second electrodes 22 of the transistors 20 of the memory cells in a column located at different layers are connected to the same common electrode layer 30 .

[0120] In some embodiments of the present application, Figure 1B As shown, the second electrode 22 and the common electrode layer 30 connected thereto may be an integrated structure.

[0121] Figure 2A A schematic cross-sectional view of another semiconductor device according to an exemplary embodiment of the present application, taken along a cross section parallel to the substrate and passing through a gate electrode and a connection portion; Figure 2A The semiconductor device shown is along Figure 2A The cross-sectional diagram on the AA section perpendicular to the substrate in FIG. Figure 1B Same, along Figure 2A The cross-sectional diagram of the BB section perpendicular to the substrate is shown in FIG. Figure 1C same; Figure 2B Another semiconductor device ( Figure 2A Schematic diagram of circuit connection).

[0122] like Figure 2A As shown, in some embodiments of the present application, each memory cell includes a ferroelectric transistor, a gate of the ferroelectric transistor is connected to the word line, one of the source and the drain is connected to the first bit line, and the other is connected to the second bit line.

[0123] The first and second bit lines in the two-dimensional memory array at the same layer are not shared, while the stacked memory cells at different layers share the first and second bit lines.

[0124] like Figure 2B The bit lines BL include a first bit line BL1 and a second bit line BL2; the first electrodes 21 of the transistors 20 of a column of the memory cells stacked vertically at different layers are connected to the same first bit line BL1, and the second electrodes 22 of the transistors 20 of a column of the memory cells stacked vertically at different layers are connected to the same second bit line BL2.

[0125] In some embodiments of the present application, the first electrode 21 and the first bit line BL1 connected thereto are an integrated structure, and the second electrode 22 and the second bit line BL2 connected thereto are an integrated structure.

[0126] It can be understood that the first electrode and the second electrode are conductive layers that are in contact with the semiconductor layer and are integrated with the bit line.

[0127] In some embodiments of the present application, the gate insulation layer 25 extends to two side walls of the bit line BL opposite to each other along the second direction, but there is no gate insulation layer covering the gate hole area, ensuring that the bit line, the first bit line and the second bit line are in contact with the semiconductor layer in the gate hole area.

[0128] In some embodiments of the present application, after the gate electrode and the connection portion are formed and before the semiconductor layer is formed, a gate insulating layer is formed on the inner sidewalls of the gate electrode and the outer sidewalls of the connection portion exposed in the trench. In this case, the gate insulating layer is formed within the gate hole region. This can prevent the gate electrode or the connection portion from contacting the bit line.

[0129] In some embodiments of the present application, the transistor 20 is a ferroelectric field effect transistor. For example, the ferroelectric field effect transistor can be formed by using a gate insulating layer 25 having ferroelectric properties. Figure 3 is the polarization curve of ferroelectric material. Figure 3 As shown in FIG, the polarization curve of the ferroelectric material has a "hysteresis loop". Therefore, a gate insulating layer 25 having ferroelectric properties is used, for example, Hf X Zr 1- X O2 exhibits polarization hysteresis characteristics and has two different polarization directions, which can be used for 1-bit storage.

[0130] Figure 4 The current-voltage curve of the ferroelectric field effect transistor of the semiconductor device of the exemplary embodiment of the present application during data reading; wherein, "0" represents the current-voltage curve when reading data "0", and "1" represents the current-voltage curve when reading data "1"; the horizontal axis V GS Represents the voltage applied to the word line WL, the vertical axis I D Indicates the current flowing through the transistor; V R Indicates the set voltage value applied to the word line WL during the data reading phase. Figure 4 It can be seen that when the voltage value V is set R Under the same circumstances, the current of the transistor when reading data "1" is greater than the current when reading data "0".

[0131] like Figure 4 As shown, the semiconductor device of the embodiment of the present application adopts a ferroelectric field effect transistor. For data "1" and "0", the transistor will display two lines with an offset threshold voltage V th The current-voltage (I D -V GS ) curve, and these two states can be obtained by applying a sufficiently large positive or negative voltage to the gate. The voltage value V R Read out stored information.

[0132] In some embodiments of the present application, a channel between the first electrode and the second electrode of one of the transistors may be a horizontal channel.

[0133] In an embodiment of the present application, the gate electrode 24 at least partially surrounds the semiconductor layer 23. Here, surrounding can be understood as partially surrounding or fully surrounding. In some embodiments, the surrounding can be fully surrounding, that is, at least the entire side wall of the semiconductor layer 23 is surrounded by the gate electrode 24, and the gate electrode 24 after surrounding is a closed ring. In some embodiments, the surrounding can be partially surrounding, that is, part of the side wall of the semiconductor layer 23 is surrounded by the gate electrode 24, and the cross-section after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent gate electrodes 24. For example, the opposite side surfaces of the semiconductor layer 23 are surrounded by the gate electrode 24, and the cross-section of the gate electrode 24 is a ring with two openings.

[0134] In the present application, the material of the semiconductor layer may be a material such as silicon or polysilicon with a band gap smaller than 1.65 eV, or a wide band gap material such as a metal oxide material with a band gap larger than 1.65 eV.

[0135] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen and silicon, or contain other small amounts of doping elements.

[0136] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW O, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. Materials such as the above can be used as long as the leakage current of the transistor can meet the requirements. The specific adjustment can be made according to the actual situation.

[0137] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15A to 10 -18 A, thereby improving the working performance of dynamic memory.

[0138] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0139] For example, the material of the bit line can be selected from any one or more metal materials having similar properties, such as tungsten, molybdenum, and cobalt. The bit line can have a single-layer or multi-layer structure, for example, a multi-layer structure formed of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0140] In some embodiments of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0141] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it may be a metal alloy containing the aforementioned metals;

[0142] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0143] Of course, it can also be polysilicon material; it can also be conductive material doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0144] In some embodiments of the present application, the material of the gate insulating layer may include one or more layers of a dielectric material having ferroelectric properties. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0145] In some embodiments, the material of the gate insulating layer includes hafnium and oxygen, and may also include any one or more of silicon, aluminum, lanthanum, zirconium, etc. For example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), Hf X Zr 1-X In some other embodiments, the material of the gate insulating layer may include a traditional ferroelectric material, such as lead zirconate, bismuth ferrite, etc.

[0146] In some embodiments of the present application, the semiconductor device may be a 3D memory, such as a 3D NOR Flash memory, a 3D DRAM, or the like. The 3D memory may have a structure such as 1TOC. A storage cell in a 3D NOR Flash memory includes only one ferroelectric transistor.

[0147] An embodiment of the present application further provides a method for manufacturing the semiconductor device of the embodiment of the present application, comprising: forming the gate electrode and the connecting portion respectively in different process steps.

[0148] Figure 5 The process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application is as follows. Figure 5 As shown, the method for manufacturing a semiconductor device according to an embodiment of the present application includes:

[0149] Providing a substrate, and alternately depositing a predetermined gate electrode layer and a first insulating layer on the substrate to obtain a stacked structure, wherein the predetermined gate electrode layer is a dielectric layer or a conductive layer;

[0150] Performing patterned etching on the stack structure to form a plurality of trenches in the stack structure, wherein the plurality of trenches extend along a first direction parallel to the substrate and are spaced apart in a second direction parallel to the substrate, wherein the first direction intersects the second direction; and between two adjacent trenches in the second direction, a connection region extending along the first direction and a gate region extending along the second direction are included;

[0151] Removing the gate region of each predetermined gate electrode layer and retaining the connection region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches, sequentially forming a gate electrode, a gate insulating layer, and a semiconductor layer within the gate hole; and forming a plurality of spaced-apart bit lines within one of the two adjacent trenches, the plurality of bit lines extending in a direction perpendicular to the substrate and spaced-apart in the first direction;

[0152] The retained connection region is the conductive layer, which contacts the gate electrode; or the retained connection region is the dielectric layer, and the method further includes replacing the dielectric layer with a conductive layer, which contacts the gate electrode.

[0153] Exemplarily, the gate insulating layer includes a ferroelectric material.

[0154] The key processes of the manufacturing method of the embodiment of the present application can be completed in one step, thereby further reducing process costs and thermal budget. In addition, although the manufacturing method forms the connecting portion and the gate electrode in two steps, the gate electrode is deposited at the end of the connecting portion, and the gate electrode and the connecting portion are closely connected.

[0155] In some embodiments of the present application, the stacked structure is patterned and etched to form a plurality of trenches in the stacked structure, and the connection region extending along the first direction and the gate region extending along the second direction between two adjacent trenches in the second direction include:

[0156] Performing patterned etching on the stacked structure to successively form a plurality of through holes and a plurality of trenches in the stacked structure, wherein the plurality of through holes extend in a direction perpendicular to the substrate and are spaced apart; and forming a second insulating layer in the through holes;

[0157] Two adjacent trenches expose the second insulating layer of each through hole; the area between two adjacent second insulating layers in the first direction is the gate area, and the area between two adjacent second insulating layers in the second direction is the connecting area.

[0158] The purpose of the through hole is to fill the isolation layer for isolation, so the shape of the through hole can be a rectangular hole extending in the first direction, and the filled isolation layer is a film layer structure extending along a direction perpendicular to the substrate and the first direction.

[0159] In some embodiments of the present application, removing the gate portion region in each of the predetermined gate electrode layers and retaining the connection portion region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches, and forming a gate electrode in the gate hole includes:

[0160] Removing the gate region in each of the preset gate electrode layers and retaining the connecting region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches;

[0161] depositing a gate electrode layer and a sacrificial layer in sequence in the gate hole and the trench;

[0162] The gate electrode layer and the sacrificial layer in the two adjacent trenches are removed, the sacrificial layer in the gate hole is removed, and the gate electrode layer in the gate hole is retained as the gate electrode.

[0163] In some embodiments of the present application, sequentially depositing a gate insulating layer and a semiconductor layer in the gate hole includes:

[0164] Depositing the gate insulating layer and the semiconductor layer in the trench and the gate hole in sequence and filling at least the gate hole with insulating material;

[0165] removing the semiconductor layer and insulating material within the trench, retaining the semiconductor layer and insulating material within the gate hole, and retaining the gate insulating layer within the trench and the gate hole, wherein the gate insulating layer covers all areas within the trench, including an area between two adjacent gate holes in a direction perpendicular to the substrate, but does not cover the semiconductor layer and insulating material within the gate hole;

[0166] The gate insulating layer includes a ferroelectric material, and the gate insulating layer is in contact with the gate electrode.

[0167] In some embodiments of the present application, forming a plurality of bit lines spaced apart in one of two adjacent trenches, wherein the plurality of bit lines extend in a direction perpendicular to the substrate and are spaced apart in the first direction, comprises:

[0168] A conductive material is deposited in one of the two trenches, and a film layer formed by the conductive material is disconnected in the first direction to form the plurality of bit lines. An insulating material is filled between two adjacent bit lines for insulation.

[0169] In some embodiments of the present application, the manufacturing method further includes: depositing and filling a conductive material in the other of the two trenches as a common electrode layer, wherein the common electrode layer is connected to one end of the semiconductor layer and to a reference signal terminal;

[0170] The common electrode layer is simultaneously connected to the semiconductor layers of the memory cells adjacent to each other in the second direction.

[0171] In some embodiments of the present application, a conductive material is deposited in one of the two trenches, and the film layer formed by the conductive material is disconnected in the first direction to form the multiple bit lines, and the multiple bit lines are used as the first bit lines; the manufacturing method also includes: depositing and filling a conductive material in the other of the two trenches, and disconnecting the film layer formed by the conductive material in the first direction to form a second bit line, and the first bit line and the second bit line are respectively connected to the two ends of the semiconductor layer of the transistor of the storage unit.

[0172] The semiconductor device provided by the exemplary embodiment of the present application can be obtained by the manufacturing method provided by the exemplary embodiment of the present application as described above.

[0173] The technical solution of the embodiment of the present application is further explained below through the manufacturing process of the semiconductor device of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.

[0174] like 6A to 14B and Figures 1A to 1C As shown, in an exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0175] S10: providing a substrate 10, and alternately depositing a predetermined gate electrode layer 11 and a first insulating layer 12 on the substrate 10 to obtain a stacked structure, wherein, under the same etching conditions, the predetermined gate electrode layer 11 and the first insulating layer 12 have different etching selectivities, such as Figure 6A and Figure 6B Wherein, the preset gate electrode layer is a dielectric layer or a conductive layer.

[0176] In some embodiments of the present application, the preset gate electrode layer 11 may be a conductive layer, and the material of the conductive layer may be any one or more of the following different types of materials:

[0177] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it may be a metal alloy containing the aforementioned metals;

[0178] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as metal oxide materials with high conductivity such as indium tin oxide ITO, indium zinc oxide IZO, indium oxide InO; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN).

[0179] In other embodiments, the preset gate electrode layer 11 can be an insulating layer (i.e., a dielectric layer). In this case, the materials of the preset gate electrode layer 11 and the first insulating layer 12 can each independently be a low-K dielectric material, i.e., a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing film layers, etc., but the materials of the preset gate electrode layer 11 and the first insulating layer 12 are different, so that when one of the preset gate electrode layer 11 and the first insulating layer 12 is subsequently etched and removed, they can have different etching rates, thereby removing the insulating layer that is desired to be removed.

[0180] Figure 6A The stacked structure shown includes three preset gate electrode layers 11 and three first insulating layers 12, which is only an example. In other embodiments, the stacked structure may include more or fewer layers of preset gate electrode layers 11 and first insulating layers 12 arranged alternately.

[0181] In some embodiments of the present application, step S10 may further include: forming a hard mask HM on the top surface of the stack structure, such as Figure 6A and Figure 6B shown.

[0182] S20: Etching the stacked structure in a direction toward the substrate 10 to form a plurality of through holes K penetrating through each predetermined gate electrode layer 11 and spaced apart in the stacked structure, and filling the through holes K with a second insulating layer 13, as shown in FIG. Figure 7A and Figure 7B shown.

[0183] In some embodiments of the present application, the through hole K may be perpendicular to the substrate 10. The plurality of through holes K may be arrayed in a first direction and a second direction, wherein the first direction intersects the second direction. For example, the first direction and the second direction may be perpendicular to each other. For another example, the first direction may be as follows: Figure 7A The X direction shown, the second direction can be as follows Figure 7A Y direction shown.

[0184] In some embodiments of the present application, the material of the second insulating layer 13 can be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) or other silicon-containing film layers.

[0185] S30: Etching the stacked structure in a direction toward the substrate 10 to form a plurality of trenches 51 penetrating through each predetermined gate electrode layer 11 and spaced apart in the stacked structure. The trenches 51 extend along the first direction and are spaced apart in the second direction. Figure 8A and Figure 8B shown.

[0186] like Figure 8A As shown, the trenches 51 can be located between the through holes K, and two adjacent rows of through holes K can be spaced apart in the second direction between two adjacent trenches 51. The second insulating layer 13 in the through holes K between two adjacent trenches 51 separates the predetermined gate electrode layer 11 into a plurality of gate regions 112 extending along the second direction and a plurality of connection regions 111 connecting two adjacent gate regions 112. The locations of the connection regions 111 will be used to form the connecting portion 26 later, and the locations of the gate regions 112 will be used to form the gate electrodes of the transistors later.

[0187] In some embodiments of the present application, the trench 51 may be perpendicular to the substrate 10 .

[0188] In some embodiments of the present application, Figure 8A and Figure 8B As shown, the trench 51 may expose the second insulating layer 13 in the through holes K on both sides thereof.

[0189] In this embodiment, the through hole K is formed first and then the groove 51 is formed. In other embodiments, the groove 51 may be formed first and then the through hole K is formed.

[0190] S40: etching and removing the gate region 112 in each preset gate electrode layer 11 and retaining the connecting region 111, to obtain a gate hole 52 extending along the second direction and communicating with two adjacent trenches 51, the gate hole 52 communicating with the trench 51, as shown in FIG. Figures 9A to 9C shown.

[0191] In some embodiments of the present application, wet etching may be used to remove a portion of the predetermined gate electrode layer 11 .

[0192] S50: depositing a gate electrode layer 24' on the inner wall of the gate hole and the trench 51, and filling the gate hole and the trench 51 with a sacrificial layer 14, as shown in FIG. Figures 10A to 10C shown.

[0193] S60: etching and removing the gate electrode layer 24' and the sacrificial layer 14 in the trench 51, and retaining the gate electrode layer 24' and the sacrificial layer 14 in the gate hole, as shown in FIG. Figure 11A and Figure 11B shown. Figure 11A The semiconductor structure shown is along Figure 11A The cross-sectional diagram of the BB section perpendicular to the substrate is shown in FIG. Figure 10C same.

[0194] S70: etching and removing the sacrificial layer 14, such as 12A to 12C shown.

[0195] In some embodiments of the present application, wet etching may be used to remove the sacrificial layer 14 .

[0196] S80: depositing the gate insulating layer 25 and the semiconductor layer 23 on the exposed inner walls of the gate hole and the trench 51 in sequence, and filling the gate hole and the trench 51 with the insulating material 15, as shown in FIG. 13A to 13C shown.

[0197] In some embodiments of the present application, the insulating material 15 may be a low-K dielectric material, that is, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing film layers.

[0198] S90: etching and removing the semiconductor layer 23 and the insulating material 15 in the trench 51, such as Figure 14A and Figure 14B shown. Figure 14A The semiconductor structure shown is along Figure 14A The cross-sectional diagram of the BB section perpendicular to the substrate is shown in FIG. Figure 13C same.

[0199] S100: Deposit conductive material in the groove 51, form the conductive material of one of the two adjacent grooves 51 into a common electrode layer 30, disconnect the film layer formed by the conductive material in the other groove 51 in the first direction, and form a plurality of bit lines BL extending toward the substrate 10. The two adjacent bit lines BL can be insulated by filling the insulating material 15.

[0200] If the preset gate electrode layer 11 deposited in step S10 is a conductive layer, the connection region 111 of the preset gate electrode layer 11 can be used as the connection portion 26. The word line WL in the logic circuit can include the connection portion 26 and the gate electrode 24 connected thereto. After completing step S100, the following can be obtained: Figures 1A to 1C The semiconductor device shown.

[0201] If the predetermined gate electrode layer 11 deposited in step S10 is an insulating layer, after step S100, the method for manufacturing the semiconductor device further includes:

[0202] S110: etching and removing the preset gate electrode layer 11, depositing a conductive material in the space vacated after removing the preset gate electrode layer 11 to form a connecting portion 26 extending along the first direction, and connecting the gate electrodes 24 of a row of memory cells to the connecting portion 26, to obtain the following: Figures 1A to 1C This step is a common process method and will not be described in detail here.

[0203] The common electrode layer 30 is shared as the first electrode 21, and the bit line BL is shared as the second electrode 22. The first electrode 21, the second electrode 22, the semiconductor layer 23 between the first electrode 21 and the second electrode 22, the gate electrode 24 surrounding the semiconductor layer, and the gate insulating layer 25 located between the semiconductor layer 23 and the gate electrode 24 constitute the transistor 20.

[0204] In another embodiment, for Figure 2A The semiconductor device shown can be obtained by the following manufacturing method:

[0205] Steps S10' to S90' are the same as steps S10 to S90;

[0206] S100': Deposit a conductive material in the trench 51, and disconnect the film formed by the conductive material in the first direction to form a plurality of bit lines BL extending toward the substrate 10. Adjacent bit lines BL may be insulated from each other by filling with insulating material 15. The bit line BL in one of the two adjacent trenches 51 is defined as a first bit line BL1, and the bit line BL in the other trench 51 is defined as a second bit line BL2.

[0207] If the preset gate electrode layer 11 deposited in step S10' is a conductive layer, the preset gate electrode layer 11 can be formed into a gate electrode and a connecting portion connecting the gate electrode. After completing step S100', the following can be obtained: Figure 2A The semiconductor device shown.

[0208] If the predetermined gate electrode layer 11 deposited in step S10′ is an insulating layer, after step S100′, the method for manufacturing the semiconductor device further includes:

[0209] S110': etching and removing the preset gate electrode layer 11, and depositing a conductive material in the space vacated after removing the preset gate electrode layer 11 to form a connecting portion 26 extending along the first direction, so as to obtain Figure 2A This step is a common process method and will not be described in detail here.

[0210] An embodiment of the present application further provides an electronic device, which includes the semiconductor device provided in the above embodiment of the present application.

[0211] In some embodiments of the present application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0212] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

[0213] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a multi-layer memory cell located on a substrate; Each layer of the memory cells includes a plurality of memory cells spaced apart along a first direction and a second direction parallel to the substrate, wherein the first direction intersects the second direction; the memory cells include transistors, each of which includes a semiconductor layer, a gate electrode at least partially surrounding the semiconductor layer, and a gate insulating layer located between the semiconductor layer and the gate electrode; The semiconductor layer extends along the second direction; The connecting portion extends along the first direction, wherein gate electrodes of transistors of a plurality of memory cells spaced apart and distributed along the first direction are connected via the connecting portion.

2. The semiconductor device according to claim 1, wherein in, The gate insulating layer includes a ferroelectric material.

3. The semiconductor device according to claim 1, wherein The connection portion has two end surfaces connected to the gate electrode, and each of the end surfaces is in contact with an outer sidewall of an adjacent gate electrode.

4. The semiconductor device according to claim 1, wherein The gate electrode extends in the second direction, and both ends of the gate electrode extend at least to an outer contour of the connecting portion.

5. The semiconductor device according to claim 1, wherein The connection portion and the gate electrode are made of different materials; or The connection portion is made of the same material as the gate electrode.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor layer further includes bit lines and a common electrode layer spaced apart in the second direction; the semiconductor layer extends in the second direction and has two end surfaces, the two end surfaces of the semiconductor layer are respectively connected to the bit lines and the common electrode layer, and the common electrode layer is connected to the reference signal terminal; The bit line extends in a direction perpendicular to the substrate and is connected to one end surface of the semiconductor layer of the transistors of a column of the memory cells located in different layers.

7. The semiconductor device according to claim 6, wherein: The common electrode layer extends along a direction perpendicular to the substrate and the first direction and is connected to one end of each semiconductor layer of each stacked memory cell arranged along the first direction.

8. The semiconductor device according to any one of claims 1 to 5, wherein: The semiconductor layer further comprises a first bit line and a second bit line spaced apart in a second direction; the semiconductor layer extends in the second direction and has two end surfaces, and the two end surfaces of the semiconductor layer are connected to the first bit line and the second bit line respectively; The first bit line and the second bit line extend in a direction perpendicular to the substrate and are connected to two end surfaces of the semiconductor layer of transistors of a column of the memory cells located in different layers.

9. The semiconductor device according to claim 6, wherein: The gate insulating layer extends onto two sidewalls of the bit line that are opposite to each other along the second direction.

10. The semiconductor device according to claim 1, wherein The semiconductor device is a Nor Flash memory.

11. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, and alternately depositing a predetermined gate electrode layer and a first insulating layer on the substrate to obtain a stacked structure, wherein the predetermined gate electrode layer is a dielectric layer or a conductive layer; Performing patterned etching on the stack structure to form a plurality of trenches in the stack structure, wherein the plurality of trenches extend along a first direction parallel to the substrate and are spaced apart in a second direction parallel to the substrate, wherein the first direction intersects the second direction; and between two adjacent trenches in the second direction, a connection region extending along the first direction and a gate region extending along the second direction are included; Removing the gate region of each predetermined gate electrode layer and retaining the connection region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches, sequentially forming a gate electrode, a gate insulating layer, and a semiconductor layer within the gate hole; and forming a plurality of spaced-apart bit lines within one of the two adjacent trenches, the plurality of bit lines extending in a direction perpendicular to the substrate and spaced-apart in the first direction; The retained connection region is the conductive layer, which contacts the gate electrode; or the retained connection region is the dielectric layer, and the method further includes replacing the dielectric layer with a conductive layer, which contacts the gate electrode.

12. The manufacturing method according to claim 11, characterized in that: The stack structure is patterned and etched to form a plurality of trenches in the stack structure, wherein a connection region extending along the first direction and a gate region extending along the second direction between two adjacent trenches include: Performing patterned etching on the stack structure to successively form a plurality of through holes and a plurality of trenches in the stack structure, wherein the plurality of through holes extend in a direction perpendicular to the substrate and are spaced apart; and forming a second insulating layer in the through holes; Two adjacent trenches expose the second insulating layer of each through hole; the area between two adjacent second insulating layers in the first direction is the gate area, and the area between two adjacent second insulating layers in the second direction is the connecting area.

13. The manufacturing method according to claim 11, characterized in that: The step of removing the gate region in each of the preset gate electrode layers and retaining the connecting region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches, and forming a gate electrode in the gate hole comprises: Removing the gate region in each of the preset gate electrode layers and retaining the connecting region to obtain a gate hole extending along the second direction and communicating with the two adjacent trenches; Depositing a gate electrode layer and a sacrificial layer in sequence in the gate hole and the trench; The gate electrode layer and the sacrificial layer in the two adjacent trenches are removed, and the gate electrode layer in the gate hole is retained as the gate electrode.

14. The manufacturing method according to claim 13, characterized in that: Sequentially depositing a gate insulating layer and a semiconductor layer in the gate hole comprises: Depositing the gate insulating layer and the semiconductor layer in sequence in the trench and the gate hole and filling them with insulating material; removing the semiconductor layer and insulating material in the trench, retaining the semiconductor layer and insulating material in the gate hole, and retaining the gate insulating layer in the trench and the gate hole; Wherein, the gate insulating layer includes ferroelectric material.

15. The manufacturing method according to claim 11, characterized in that: The step of forming a plurality of bit lines distributed at intervals in one of two adjacent trenches, wherein the plurality of bit lines extend in a direction perpendicular to the substrate and are distributed at intervals in the first direction, comprises: A conductive material is deposited in one of the two trenches, and a film layer formed by the conductive material is disconnected in the first direction to form the plurality of bit lines. An insulating material is filled between two adjacent bit lines for insulation.

16. The manufacturing method according to claim 15, characterized in that: Also includes: Depositing and filling a conductive material in the other of the two trenches as a common electrode layer, wherein the common electrode layer is connected to one end of the semiconductor layer and to a reference signal terminal; The common electrode layer is simultaneously connected to the semiconductor layers of the memory cells adjacent to each other in the second direction.

17. The manufacturing method according to claim 15, characterized in that: using the plurality of bit lines as first bit lines; The manufacturing method also includes: depositing and filling a conductive material in the other of the two trenches, disconnecting the film layer formed by the conductive material in the first direction to form a second bit line, and the first bit line and the second bit line respectively connect the two ends of the semiconductor layer of the transistor of the memory cell.

18. An electronic device, characterized in that: The method comprises the semiconductor device according to any one of claims 1 to 10, or comprises a semiconductor device obtained by the manufacturing method according to any one of claims 11 to 17.

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