Preparation method of low-temperature drift polycrystalline silicon resistor
By forming a polysilicon layer on the silicon substrate and performing an ion implantation process, a low-temperature drift polysilicon resistor is formed, which solves the problem of temperature drift of the polysilicon resistor and improves the stability and accuracy of the circuit.
Patent Information
- Application Number
- CN202510589074.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-08
- Publication Date
- 2025-08-05
AI Technical Summary
The existing polysilicon resistors have a large drift when temperature changes, which affects the accuracy and reliability of the circuit. The existing compensation method is costly and has limited effect.
The doped region is formed by forming a polysilicon layer on the silicon substrate and performing two ion implantation processes. After removing part of the doped region, a dielectric layer and a metal layer are formed thereon, forming a low-temperature floating polysilicon resistor.
Without increasing process difficulty, the temperature coefficient of the polysilicon resistance is reduced, the application requirements of low-temperature drifts are met, and the stability of the circuit is improved.
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Figure CN120435013A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor device manufacturing, in particular to a method for preparing a low-temperature drift polysilicon resistor. Background Art
[0002] In the field of electronics, polysilicon resistors are widely used in various electronic devices such as integrated circuits due to their excellent performance. However, existing polysilicon resistors suffer from significant temperature drift in actual use.
[0003] With the continuous advancement of electronic technology and increasing performance requirements, the stability requirements for resistors are becoming increasingly stringent. Temperature changes can cause significant fluctuations in the resistance value of polysilicon resistors, significantly affecting the accuracy and reliability of circuits. For example, in some high-precision measuring instruments and communications equipment, resistor temperature drift can lead to increased measurement errors or distortion of communication signals.
[0004] Currently, complex compensation circuits or specialized material processing methods are often used to address the temperature drift of polysilicon resistors. However, these methods are often costly, have limited effectiveness, and may increase circuit complexity and design difficulty. Therefore, a new method for preparing low-temperature drift polysilicon resistors is urgently needed to meet the needs of evolving electronic technology and improve the performance and stability of electronic devices. Summary of the Invention
[0005] The object of the present invention is to provide a method for preparing a low-temperature drift polysilicon resistor, comprising the following steps:
[0006] S1: providing a silicon substrate, and forming a first dielectric layer and a polysilicon layer on the silicon substrate.
[0007] S2: performing two ion implantation processes on the polysilicon layer to form a first polysilicon doping region and a second polysilicon doping region.
[0008] S3: removing a portion of the first polysilicon doping region and a portion of the second polysilicon doping region.
[0009] S4: forming a second dielectric layer on the first polysilicon doping region, the second polysilicon doping region, and the first dielectric layer not covered by the first polysilicon doping region and the second polysilicon doping region.
[0010] S5: removing a portion of the second dielectric layer.
[0011] S6: forming a metal layer on the second dielectric layer, so that the metal layer is in contact with the first dielectric layer, the first polysilicon doped region, and the second polysilicon doped region respectively.
[0012] Furthermore, the polysilicon layer in S1 is a layer of polycrystalline grown once, or two layers of polycrystalline grown twice under different conditions.
[0013] Furthermore, the steps of performing two ion implantation processes on the polysilicon layer include:
[0014] S201: forming a first mask layer on the polysilicon layer.
[0015] S202: removing a portion of the first mask layer, and forming a first polysilicon doping region on the upper surface of the polysilicon layer without the mask layer by ion implantation.
[0016] S203: removing all the first mask layers and forming a second mask layer on the polysilicon layer.
[0017] S204: removing a portion of the second mask layer, and forming a second polysilicon doped region in the unmasked layer by ion implantation.
[0018] S205: removing all the second mask layers.
[0019] S206: performing annealing treatment on the first polysilicon doping region and the second polysilicon doping region.
[0020] Furthermore, the ratio of the number of polysilicon resistor blocks formed by the first polysilicon doping region and the second polysilicon doping region is 1:1, 1:N or N:1.
[0021] Furthermore, the first polysilicon doping region is an N-type polysilicon doping region or a P-type polysilicon doping region.
[0022] Furthermore, the second polysilicon doping region is an N-type polysilicon doping region or a P-type polysilicon doping region.
[0023] Furthermore, the portion of the first polysilicon doping region removed in S3 includes an edge of the first polysilicon doping region and a connection with the second polysilicon doping region.
[0024] The portion of the second polysilicon doping region removed in S3 includes the edge of the second polysilicon doping region and the connection with the first polysilicon doping region.
[0025] Furthermore, in step S4, a second dielectric layer is formed on the polysilicon layer by a deposition or oxidation process.
[0026] Furthermore, in step S5, the step of removing part of the second dielectric layer includes etching the second dielectric layer at the connection between the first polysilicon doping region and the second polysilicon doping region, and the second dielectric layer above the edge polysilicon layer.
[0027] Furthermore, in step S6, the step of forming a metal layer on the second dielectric layer is: depositing a metal layer on the second dielectric layer, etching excess metal, forming metal lead ends, and obtaining a combination form of polysilicon resistors, thereby realizing the preparation of low-temperature drift polycrystalline resistors.
[0028] The technical effect of the present invention is unquestionable. The present invention proposes a method for preparing a low-temperature drift polysilicon resistor, which can realize a combination form of polysilicon resistors without significantly increasing the process difficulty and complexity, thereby reducing the temperature coefficient of the polysilicon resistor and ultimately meeting the application requirements of the low-temperature drift polysilicon resistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 The present invention is a flowchart of a method for preparing a low-temperature drift polysilicon resistor.
[0030] Figure 2-Figure 8 Schematic diagram of the semiconductor structure in each step of the embodiment of the present invention.
[0031] Description of reference numerals:
[0032] 100 - silicon substrate; 101 - first dielectric layer; 102 - polysilicon layer; 102a - first polysilicon doping region; 102b - second polysilicon doping region; 103 - first mask layer; 104 - second mask layer; 105 - second dielectric layer; 106 - metal layer. DETAILED DESCRIPTION
[0033] The present invention will be further described below with reference to the following examples, but it should not be understood that the scope of the present invention is limited to the following examples. Without departing from the above technical ideas of the present invention, various substitutions and modifications can be made according to common technical knowledge and customary means in the art, and all should be included in the scope of protection of the present invention.
[0034] Example 1:
[0035] See also Figures 1-8 A method for preparing a low-temperature drift polysilicon resistor comprises the following steps:
[0036] S1: providing a silicon substrate 100 , and forming a first dielectric layer 101 and a polysilicon layer 102 on the silicon substrate 100 .
[0037] S2: performing two ion implantation processes on the polysilicon layer 102 to form a first polysilicon doping region 102 a and a second polysilicon doping region 102 b .
[0038] S3: removing a portion of the first polysilicon doping region 102a and a portion of the second polysilicon doping region 102b.
[0039] S4: forming a second dielectric layer 105 on the first and second polysilicon doping regions 102a and 102b, and the first dielectric layer 101 not covered by the first and second polysilicon doping regions 102a and 102b.
[0040] S5: removing a portion of the second dielectric layer 105 .
[0041] S6: forming a metal layer 106 on the second dielectric layer 105 so that the metal layer 106 is in contact with the first dielectric layer 101 , the first polysilicon doping region 102 a , and the second polysilicon doping region 102 b , respectively.
[0042] The polysilicon layer in S1 is a layer of polycrystalline grown once, or two layers of polycrystalline grown twice under different conditions (different growth processes and environmental conditions).
[0043] The steps of performing two ion implantation processes on the polysilicon layer 102 include:
[0044] S201 : forming a first mask layer 103 on the polysilicon layer.
[0045] S202: removing a portion of the first mask layer 103 and forming a first polysilicon doped region 102a on the upper surface of the polysilicon layer 102 where there is no mask layer by ion implantation.
[0046] S203 : removing all of the first mask layer 103 and forming a second mask layer 104 on the polysilicon layer 102 .
[0047] S204: removing a portion of the second mask layer, and forming a second polysilicon doped region 102b in the unmasked layer by ion implantation.
[0048] S205 : removing all the second mask layers 104 .
[0049] S206: performing annealing treatment on the first polysilicon doping region 102a and the second polysilicon doping region 102b.
[0050] The ratio of the number of polysilicon resistor blocks formed by the first polysilicon doping region and the second polysilicon doping region is 1:1, 1:N or N:1.
[0051] The first polysilicon doping region is an N-type polysilicon doping region or a P-type polysilicon doping region.
[0052] The second polysilicon doping region is an N-type polysilicon doping region or a P-type polysilicon doping region.
[0053] The portion of the first polysilicon doping region 102a removed in S3 includes the edge of the first polysilicon doping region 102a and the connection with the second polysilicon doping region 102b.
[0054] The portion of the second polysilicon doping region 102b removed in S3 includes the edge of the second polysilicon doping region 102b and the connection with the first polysilicon doping region 102a.
[0055] In step S4, a second dielectric layer is formed on the polysilicon layer by a deposition or oxidation process.
[0056] In step S5 , the step of removing part of the second dielectric layer 105 includes etching the second dielectric layer 105 at the connection between the first polysilicon doping region and the second polysilicon doping region, and the second dielectric layer 105 above the edge polysilicon layer.
[0057] In step S6, the step of forming the metal layer 106 on the second dielectric layer 105 is as follows: depositing the metal layer 106 on the second dielectric layer 105, etching excess metal to form metal lead terminals, and obtaining a combination form of polysilicon resistors, thereby realizing the preparation of low-temperature drift polycrystalline resistors.
[0058] Example 2:
[0059] A method for preparing a low-temperature drift polysilicon resistor comprises the following steps:
[0060] S1: providing a silicon substrate 100 , and forming a first dielectric layer 101 and a polysilicon layer 102 on the silicon substrate 100 .
[0061] S2: performing two ion implantation processes on the polysilicon layer 102 to form a first polysilicon doping region 102 a and a second polysilicon doping region 102 b .
[0062] S3: removing a portion of the first polysilicon doping region 102a and a portion of the second polysilicon doping region 102b.
[0063] S4: forming a second dielectric layer 105 on the first and second polysilicon doping regions 102a and 102b, and the first dielectric layer 101 not covered by the first and second polysilicon doping regions 102a and 102b.
[0064] S5: removing a portion of the second dielectric layer 105 .
[0065] S6: forming a metal layer 106 on the second dielectric layer 105 so that the metal layer 106 is in contact with the first dielectric layer 101 , the first polysilicon doping region 102 a , and the second polysilicon doping region 102 b , respectively.
[0066] Example 3:
[0067] A method for preparing a low-temperature drift polysilicon resistor, with the same technical content as Example 2, further, the polysilicon layer in S1 is a layer of polycrystalline grown once, or two layers of polycrystalline grown twice under different conditions.
[0068] Example 4:
[0069] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of embodiments 2-3, further comprising the steps of performing two ion implantation processes on the polysilicon layer 102 respectively:
[0070] S201 : forming a first mask layer 103 on the polysilicon layer.
[0071] S202: removing a portion of the first mask layer 103 and forming a first polysilicon doped region 102a on the upper surface of the polysilicon layer 102 where there is no mask layer by ion implantation.
[0072] S203 : removing all of the first mask layer 103 and forming a second mask layer 104 on the polysilicon layer 102 .
[0073] S204: removing a portion of the second mask layer, and forming a second polysilicon doped region 102b in the unmasked layer by ion implantation.
[0074] S205 : removing all the second mask layers 104 .
[0075] S206: performing annealing treatment on the first polysilicon doping region 102a and the second polysilicon doping region 102b.
[0076] Example 5:
[0077] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of Examples 2-4, further comprising: a ratio of the number of polysilicon resistor blocks formed by the first polysilicon doping region and the second polysilicon doping region being 1:1, 1:N, or N:1.
[0078] Example 6:
[0079] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of Examples 2-5, further, the first polysilicon doping region is an N-type polysilicon doping region, or a P-type polysilicon doping region.
[0080] Example 7:
[0081] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of Examples 2-6, further, the second polysilicon doping region is an N-type polysilicon doping region, or a P-type polysilicon doping region.
[0082] Example 8:
[0083] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of Examples 2-7, further, the portion of the first polysilicon doped region 102a removed in S3 includes the edge of the first polysilicon doped region 102a and the connection with the second polysilicon doped region 102b.
[0084] The portion of the second polysilicon doping region 102b removed in S3 includes the edge of the second polysilicon doping region 102b and the connection with the first polysilicon doping region 102a.
[0085] Example 9:
[0086] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of embodiments 2-8, further, in step S4, a second dielectric layer is formed on the polysilicon layer by a deposition or oxidation process.
[0087] Example 10:
[0088] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of Examples 2-9, further comprising: in step S5, the step of removing a portion of the second dielectric layer 105 comprises etching the second dielectric layer 105 located at the connection between the first polysilicon doped region and the second polysilicon doped region, and the second dielectric layer 105 located above the edge polysilicon layer.
[0089] Example 11:
[0090] A method for preparing a low-temperature drift polysilicon resistor, the technical content of which is the same as any one of Examples 2-10. Furthermore, in step S6, the step of forming a metal layer 106 on the second dielectric layer 105 comprises: depositing the metal layer 106 on the second dielectric layer 105, etching excess metal to form metal lead terminals, and obtaining a combination form of a polysilicon resistor, thereby realizing the preparation of a low-temperature drift polysilicon resistor.
[0091] Example 12:
[0092] A method for preparing a low-temperature drift polysilicon resistor, comprising the following steps:
[0093] S1: providing a silicon substrate, and forming a first dielectric layer and a polysilicon layer on the silicon substrate;
[0094] S2: performing two ion implantation processes on the polysilicon layer to form a first polysilicon doping region and a second polysilicon doping region;
[0095] S3: removing part of the polysilicon layer;
[0096] S4: forming a second dielectric layer on the polysilicon layer;
[0097] S5: removing a portion of the second dielectric layer;
[0098] S6: forming a metal layer on the second dielectric layer.
[0099] The following is combined with Figure 2-Figure 8 , specifically describe the preparation method of the low-temperature drift polysilicon resistor:
[0100] S1: Please refer to Figure 2 , providing a silicon substrate 100, and forming a first dielectric layer 101 and a polysilicon layer 102 on the silicon substrate.
[0101] Among them, see Figure 2 The silicon substrate 100 may be made of single crystal silicon or other substrate materials such as silicon-on-insulator (SOI). The first dielectric layer 101 may be silicon oxide grown by thermal oxidation, or silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride formed by chemical vapor deposition. The polycrystalline silicon layer 102 is used to form a polycrystalline silicon resistor and may be a single layer of polycrystalline grown in one go, or two layers of polycrystalline grown in two different growth conditions.
[0102] S2: Please refer to Figure 3 and Figure 4 , perform two ion implantation processes on the polysilicon layer 102 to form a first polysilicon doping region 102a and a second polysilicon doping region 102b. This step may include the following sub-steps:
[0103] S201: forming a first mask layer 103 on the polysilicon layer 102, wherein the first mask layer 103 may be a hard mask or a photoresist;
[0104] S202: removing a portion of the first mask layer 103, and forming a first polysilicon doped region 102a in the unmasked layer by ion implantation. The first polysilicon doped region may be an N-type (including phosphorus or arsenic) polysilicon doped region or a P-type (including boron or boron fluoride) polysilicon doped region.
[0105] S203: removing all the first mask layers 103 and forming a second mask layer 104 on the polysilicon layer 102 and the first polysilicon doped region 102a. The second mask layer 104 may be a hard mask or a photoresist.
[0106] S204: removing a portion of the second mask layer 104, and forming a second polysilicon doping region 102b in the mask-free layer by ion implantation. The second polysilicon doping region may be an N-type (including phosphorus or arsenic) polysilicon doping region, or a P-type (including boron or boron fluoride) polysilicon doping region. Furthermore, the ratio of the number of polysilicon resistor blocks formed by the first polysilicon doping region 102a and the second polysilicon doping region 102b may be 1:1, 1:N, or N:1.
[0107] S205: removing all the second mask layers 104;
[0108] S206: performing annealing treatment on the polysilicon doped regions 102a and 102b.
[0109] S3: See Figure 5 , removing part of the polysilicon doped regions 102a and 102b;
[0110] See also Figure 5 In step three S3, the portions of the polysilicon doped regions 102a and 102b removed are the connection and edges of the polysilicon doped regions 102a and 102b, and a dry etching process is used to remove the portions of the polysilicon doped regions 102a and 102b.
[0111] S4: Please refer to Figure 6 , forming a second dielectric layer 105 on the polysilicon doped regions 102a and 102b;
[0112] See also Figure 6 The second dielectric layer 105 may be silicon oxide grown by thermal oxidation, or silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride formed by chemical vapor deposition.
[0113] S5: See Figure 7 , removing part of the second dielectric layer 105;
[0114] For further information, see Figure 7 , remove part of the second dielectric layer 105, and etch the second dielectric layer 105 at the connection between the polysilicon doped regions 102a and 102b and the second dielectric layer 105 above the edge polysilicon doped regions 102a and 102b.
[0115] S6: See Figure 8 , a metal layer 106 is formed on the second dielectric layer 105 .
[0116] A metal layer 106 is deposited on the second dielectric layer 105 , and excess metal is etched to form metal lead-out terminals, ultimately obtaining a combination of polysilicon resistors, thereby realizing a low-temperature drift polysilicon resistor.
[0117] In summary, this embodiment proposes a method for preparing a low-temperature drift polysilicon resistor, which can realize a combination form of polysilicon resistors without significantly increasing the process difficulty and complexity, thereby reducing the temperature coefficient of the polysilicon resistor and ultimately meeting the application requirements of the low-temperature drift polysilicon resistor.
[0118] The above embodiments are merely descriptions of preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art based on the above disclosures shall fall within the scope of protection of the claims.
Claims
1. A method for preparing a low-temperature drift polysilicon resistor, characterized in that: The following steps are involved: S1: providing a silicon substrate (100), and forming a first dielectric layer (101) and a polysilicon layer (102) on the silicon substrate (100). S2: performing two ion implantation processes on the polysilicon layer (102) to form a first polysilicon doping region (102a) and a second polysilicon doping region (102b); S3: removing a portion of the first polysilicon doping region (102a) and a portion of the second polysilicon doping region (102b); S4: forming a second dielectric layer (105) on the first polysilicon doping region (102a) and the second polysilicon doping region (102b), and on the first dielectric layer (101) not covered by the first polysilicon doping region (102a) and the second polysilicon doping region (102b); S5: removing a portion of the second dielectric layer (105); S6: forming a metal layer (106) on the second dielectric layer (105), so that the metal layer (106) is in contact with the first dielectric layer (101), the first polysilicon doped region (102a), and the second polysilicon doped region (102b), respectively.
2. The method for preparing a low-temperature drift polysilicon resistor according to claim 1, wherein: The polysilicon layer in S1 is a layer of polycrystalline grown once, or two layers of polycrystalline grown twice under different conditions.
3. The method for preparing a low-temperature drift polysilicon resistor according to claim 1, wherein: The steps of performing two ion implantation processes on the polysilicon layer (102) include: S201: forming a first mask layer (103) on the polysilicon layer; S202: removing a portion of the first mask layer (103), and forming a first polysilicon doping region (102a) on the upper surface of the polysilicon layer (102) without the mask layer by ion implantation; S203: removing all of the first mask layer (103), and forming a second mask layer (104) on the polysilicon layer (102); S204: removing a portion of the second mask layer, and forming a second polysilicon doped region (102b) in the unmasked layer by ion implantation; S205: removing all the second mask layers (104); S206: performing annealing treatment on the first polysilicon doping region (102a) and the second polysilicon doping region (102b).
4. The method for preparing a low-temperature drift polysilicon resistor according to claim 3, wherein: The ratio of the number of polysilicon resistor blocks formed by the first polysilicon doping region and the second polysilicon doping region is 1:1, 1:N or N:
1.
5. The method for preparing a low-temperature drift polysilicon resistor according to claim 3, characterized in that: The first polysilicon doping region is an N-type polysilicon doping region or a P-type polysilicon doping region.
6. The method for preparing a low-temperature drift polysilicon resistor according to claim 3, characterized in that: The second polysilicon doping region is an N-type polysilicon doping region or a P-type polysilicon doping region.
7. The method for preparing a low-temperature drift polysilicon resistor according to claim 1, characterized in that: The portion of the first polysilicon doped region (102a) removed in S3 includes the edge of the first polysilicon doped region (102a) and the connection with the second polysilicon doped region (102b); The portion of the second polysilicon doping region (102b) removed in S3 includes the edge of the second polysilicon doping region (102b) and the connection with the first polysilicon doping region (102a).
8. The method for preparing a low-temperature drift polysilicon resistor according to claim 1, characterized in that: In step S4, a second dielectric layer is formed on the polysilicon layer by a deposition or oxidation process.
9. The method for preparing a low-temperature drift polysilicon resistor according to claim 1, wherein: In step S5, the step of removing part of the second dielectric layer (105) is: etching the second dielectric layer (105) located at the connection between the first polysilicon doping region and the second polysilicon doping region, and the second dielectric layer (105) located above the edge polysilicon layer.
10. The method for preparing a low-temperature drift polysilicon resistor according to claim 1, characterized in that: In step S6, the step of forming a metal layer (106) on the second dielectric layer (105) is as follows: depositing the metal layer (106) on the second dielectric layer (105), etching excess metal, forming metal lead ends, and obtaining a combination form of a polysilicon resistor, thereby realizing the preparation of a low-temperature drift polycrystalline resistor.