Thin film transistor array substrate and display device including same

Abstract

The invention discloses a thin film transistor array substrate and a display device including the same. The thin film transistor array substrate includes a buffer layer disposed over a substrate, and a thin film transistor. Parasitic capacitance is minimized by minimizing a region where the gate electrode overlaps the conductive region. Breakdown characteristics of a thin film transistor are improved by minimizing an overlapping region and improving thickness uniformity of a gate insulating layer. Resolution and performance of a display device are improved by reducing a size of a thin film transistor disposed in the display device while improving characteristics of the thin film transistor. And process steps and masks are reduced. And the process optimization is realized. The resistance of the gate electrode is reduced, the switching speed of the thin film transistor is improved, and the power loss is reduced, thereby contributing to low power consumption.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0017211, filed on February 5, 2024, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Embodiments relate to a thin film transistor array substrate and a display device including the thin film transistor array substrate. Background Art

[0004] With the development of the information society, demands for various types of display devices for displaying images are increasing, and recently a series of display devices have been put into use, such as liquid crystal display (LCD) devices, plasma display devices, and organic light emitting diode display devices.

[0005] A large number of thin film transistors are provided on a display panel, which is a core component of a display device, to drive the display panel. For example, in order to drive the light-emitting elements of an organic light-emitting display device, a driving thin film transistor and a switching thin film transistor are provided on the display panel. Summary of the Invention

[0006] Various aspects provide a thin film transistor array substrate and a display device including the thin film transistor array substrate, in which parasitic capacitance between a gate electrode and a conductive region of a thin film transistor can be minimized and breakdown characteristics of the thin film transistor can be improved.

[0007] Also provided are a thin film transistor array substrate and a display device including the thin film transistor array substrate, wherein the resolution and performance of the display device can be improved.

[0008] The purpose of the present disclosure is not limited to the foregoing description, and a person skilled in the art in the technical field to which the present disclosure belongs will clearly understand other purposes not explicitly disclosed herein based on the description provided below.

[0009] According to an embodiment, a thin film transistor array substrate includes: a buffer layer disposed above a substrate and including an opening region exposing a portion of the substrate, and a first inclined surface having an inverted tapered shape and exposed through the opening region; and a first thin film transistor. The first thin film transistor includes: a first active pattern including: a first channel region including a first portion disposed above the first inclined surface of the buffer layer and a second portion disposed above the top surface of the substrate below the first inclined surface of the buffer layer; a first conductive region disposed above the top surface of the buffer layer; and a second conductive region disposed above the top surface of the substrate; a first gate insulating layer including a first inclined portion disposed above the first portion of the first channel region and a first horizontal portion disposed above the second portion of the first channel region; and a first gate electrode disposed above the first inclined portion and the first horizontal portion of the first gate insulating layer and overlapping the first channel region.

[0010] According to an embodiment, a display device includes: a circuit element layer disposed over a substrate; and a light-emitting element disposed over the circuit element layer. The circuit element layer includes: a buffer layer disposed over the substrate and including an opening region exposing a portion of the substrate, and a first inclined surface having an inverted tapered shape and exposed through the opening region; and a first thin-film transistor. The first thin-film transistor includes: a first active pattern including: a first channel region including a first portion disposed over the first inclined surface of the buffer layer and a second portion disposed over the top surface of the substrate below the first inclined surface of the buffer layer; a first conductive region disposed over the top surface of the buffer layer; and a second conductive region disposed over the top surface of the substrate; a first gate insulating layer including a first inclined surface portion disposed over the first portion of the first channel region and a first horizontal surface portion disposed over the second portion of the first channel region; and a first gate electrode disposed over the first inclined surface portion and the first horizontal surface portion of the first gate insulating layer and overlapping the first channel region.

[0011] According to embodiments, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, in which parasitic capacitance can be reduced by minimizing an area where a gate electrode overlaps a conductive region.

[0012] According to an embodiment, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein the breakdown characteristics of the thin film transistor can be improved by minimizing the area where the gate electrode overlaps the conductive region and improving the thickness uniformity of the gate insulating layer.

[0013] According to an embodiment, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein the resolution and performance of the display device can be improved by reducing the size of thin film transistors provided in the display device while improving the characteristics of the thin film transistors.

[0014] According to embodiments, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein the number of process steps and the number of masks can be reduced by simultaneously forming vertical thin film transistors and coplanar thin film transistors, thereby achieving a process optimization effect.

[0015] According to an embodiment, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein, by forming a gate connection electrode connected to the gate electrode, the resistance of the gate electrode can be reduced, the switching speed of the thin film transistor can be improved, and the power loss occurring during the switching process can be reduced, thereby contributing to low power consumption.

[0016] The effects of the present disclosure are not limited to the foregoing description, and those skilled in the art to which the present disclosure pertains will clearly understand other effects not explicitly disclosed herein based on the description provided below. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a plan view showing a thin film transistor array substrate according to an embodiment;

[0019] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA';

[0020] Figure 3 It is along Figure 1 A cross-sectional view taken along line BB';

[0021] Figure 4 and Figure 5 each showing a gate electrode of a thin film transistor according to some embodiments;

[0022] Figure 6 is a plan view showing a thin film transistor array substrate according to an embodiment;

[0023] Figure 7 It is along Figure 6 A cross-sectional view taken along line CC' in FIG.

[0024] Figure 8 It is along Figure 6A cross-sectional view taken along line D-D';

[0025] Figure 9 shows a schematic configuration of a system of a display device according to an embodiment;

[0026] Figure 10 is a cross-sectional view showing a display device according to an embodiment;

[0027] Figure 11 is a plan view showing a circuit element layer of a display device according to an embodiment;

[0028] Figure 12 It is along Figure 11 A cross-sectional view taken along line EE' in FIG.

[0029] Figures 13A to 19B is a cross-sectional view illustrating a method of manufacturing a circuit element layer of a display device according to an embodiment. DETAILED DESCRIPTION

[0030] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and the same reference numerals may be used to designate the same or similar components even if they are shown in different drawings. In addition, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter of some embodiments of the invention quite unclear. Terms such as "comprising", "having", "including", "consisting of", and "formed of" as used herein are generally intended to allow for the addition of other components unless these terms are used with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0031] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present invention. Each of these terms is not used to limit the nature, order, sequence, or number of the elements, but is only used to distinguish the corresponding element from other elements.

[0032] When referring to a first element being “connected or coupled to,” “contacting or overlapping,” etc. a second element, it should be understood that not only the first element may be “directly connected or coupled to,” or “directly contacting or overlapping,” but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled to,” “contacting or overlapping,” etc., each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled to,” “contacting or overlapping,” etc., each other.

[0033] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a process or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms “directly” or “immediately” are used together.

[0034] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerances or error ranges that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully includes all meanings of the term "can".

[0035] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a plan view showing a thin film transistor array substrate according to an embodiment, Figure 2 It is along Figure 1 A cross-sectional view taken along line AA' in FIG. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB' in FIG.

[0037] Now refer to Figures 1 to 3 A buffer layer 20 may be disposed over the substrate 10 , and the buffer layer 20 may have an open region OP exposing a portion of the substrate 10 .

[0038] The open region OP may expose the inclined surface 20S of the buffer layer 20. The width of the open region OP may increase in a direction toward the substrate 10. The inclined surface 20S may have an inverse tapered shape.

[0039] A thin film transistor TR1 may be disposed above a region of the buffer layer 20 including the inclined surface 20S. The thin film transistor TR1 may be a vertical thin film transistor. The thin film transistor TR1 may include an active pattern 31 , a gate insulating layer 41 , and a gate electrode 51 .

[0040] The active pattern 31 may be disposed above the inclined surface 20S of the buffer layer 20 and may extend to the top surface of the buffer layer 20 adjacent to the inclined surface 20S of the buffer layer 20 and to the top surface of the substrate 10. From a plan view, the active pattern 31 may pass through the inclined surface 20S of the buffer layer 20. The active pattern 31 may pass through the inclined surface 20S of the buffer layer 20 in the X-axis direction X of the XY plane, but is not limited thereto.

[0041] The active pattern 31 may be formed by an atomic layer deposition (ALD) process having excellent step coverage and may be disposed as a thin film along the slope 20S of the buffer layer 20 , the top surface of the buffer layer 20 , and the top surface of the substrate 10 .

[0042] The active pattern 31 may be formed of an oxide semiconductor. The oxide semiconductor may include an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and an oxide thereof. More specifically, the oxide semiconductor may include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), and the like.

[0043] The active pattern 31 may include a channel region 31A, a first conductive region 31B, and a second conductive region 31C.

[0044] The channel region 31A may have semiconductor properties. The channel region 31A may be formed of, for example, an oxide semiconductor. The first conductive region 31B and the second conductive region 31C may be regions where the oxide semiconductor has been made conductive by exposure to an etching gas used in the etching process for forming the gate insulating layer 41.

[0045] The channel region 31A may be disposed above the inclined surface 20S of the buffer layer 20. In addition, the channel region 31A may be disposed above the top surface of the substrate 10 below the inclined surface 20S of the buffer layer 20. The channel region 31A may include a first portion 31Aa disposed above the inclined surface 20S of the buffer layer 20 and a second portion 31Ab disposed above the top surface of the substrate 10.

[0046] The channel width W of the thin film transistor TR1 ch The size of may be equal to the width W of the channel region 31A in the Y-axis direction Y. The channel length L of the thin film transistor TR1 ch It can be defined as shown in the following formula 1.

[0047] [Formula 1]

[0048]

[0049] Here, B THK is the thickness of the buffer layer 20, T L B is the length of the second portion 31Ab of the channel region 31A in the X-axis direction X. THK and T L The size can be set so that the channel length L of the thin film transistor TR1 ch is the target value.

[0050] The first conductive region 31B may be disposed on the top surface of the buffer layer 20 on one side of the channel region 31A. The second conductive region 31C may be disposed on the top surface of the substrate 10 on the other side of the channel region 31A. One of the first conductive region 31B and the second conductive region 31C may be the source region of the thin film transistor TR1, and the other may be the drain region of the thin film transistor TR1.

[0051] A portion of the first conductive region 31B may overlap the inclined surface 20S of the buffer layer 20. The second conductive region 31C may not overlap the inclined surface 20S of the buffer layer 20. The first conductive region 31B and the second conductive region 31C may be spaced apart from each other in a horizontal direction parallel to the top surface of the substrate 10.

[0052] The gate insulating layer 41 may be disposed above the channel region 31 A. The gate insulating layer 41 may expose the first conductive region 31B and the second conductive region 31C.

[0053] The gate insulating layer 41 may include a slope portion 41A, a horizontal portion 41B, and an extension portion 41C.

[0054] The inclined surface portion 41A of the gate insulating layer 41 may be disposed above the first portion 31A of the channel region 31A to cover the first portion 31A of the channel region 31A. The inclined surface portion 41A of the gate insulating layer 41 may extend to the inclined surface 20S of the buffer layer 20 on the opposite side of the channel region 31A to cover the inclined surface 20S of the buffer layer 20.

[0055] A portion of the inclined surface portion 41A of the gate insulating layer 41 may be in direct contact with the first portion 31Aa of the channel region 31A, and another portion of the inclined surface portion 41A of the gate insulating layer 41 may be in direct contact with the inclined surface 20S of the buffer layer 20. A portion of the top portion of the inclined surface portion 41A of the gate insulating layer 41 may be in direct contact with the side surface of the first conductive region 31B.

[0056] The horizontal portion 41B of the gate insulating layer 41 may be disposed above the second portion 31Ab of the channel region 31A to cover the second portion 31Ab of the channel region 31A. The horizontal portion 41B of the gate insulating layer 41 may extend to the substrate 10 on the opposite side of the channel region 31A to cover the top surface of the substrate 10 below the inclined portion 41A of the gate insulating layer 41.

[0057] A portion of the horizontal portion 41B of the gate insulating layer 41 may be in direct contact with the second portion 31Ab of the channel region 31A, and another portion of the horizontal portion 41B of the gate insulating layer 41 may be in direct contact with the top surface of the substrate 10 .

[0058] The extension portion 41C of the gate insulating layer 41 may be disposed over the top surface of the buffer layer 20 around the open region OP and may extend to the open region OP to be connected to the slope portion 41A of the gate insulating layer 41 .

[0059] The gate insulating layer 41 can be formed by an ALD process. Since the gate insulating layer 41 is formed by an ALD process with excellent step coverage, the gate insulating layer 41 can have a uniform thickness. Therefore, by preventing the gate insulating layer 41 from being formed too thinly at vulnerable points such as corners, the breakdown characteristics of the thin film transistor TR1 can be improved.

[0060] The gate electrode 51 and the gate connection electrode 54 may be disposed under the slope portion 41A of the gate insulating layer 41. The gate electrode 51 and the gate connection electrode 54 may be connected to each other.

[0061] The gate electrode 51 may be disposed over a portion of the inclined portion 41A of the gate insulating layer 41 that is in direct contact with the first portion 31Aa of the channel region 31A, and over a portion of the horizontal portion 41B of the gate insulating layer 41 that is in direct contact with the second portion 31Ab of the channel region 31A. The gate electrode 51 may overlap the channel region 31A of the active pattern 31.

[0062] The gate connection electrode 54 may be disposed over another portion of the inclined surface portion 41A of the gate insulating layer 41 that is in direct contact with the inclined surface 20S of the buffer layer 20, and over another portion of the horizontal portion 41B of the gate insulating layer 41 that is in direct contact with the top surface of the substrate 10. The gate connection electrode 54 may not overlap with the active pattern 31.

[0063] A gate connection line 55 may be disposed over the extension portion 41C of the gate insulating layer 41. The gate connection line 55 may extend to the open region OP to be connected to the gate connection electrode 54. The gate connection line 55 may not overlap the active pattern 31.

[0064] The gate electrode 51, the gate connection electrode 54, and the gate connection line 55 may be formed of the same material. The gate electrode 51, the gate connection electrode 54, and the gate connection line 55 may be implemented using various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), an alloy of one or more thereof, or a multilayer thereof, but is not limited thereto.

[0065] The gate electrode 51 , the gate connection electrode 54 , and the gate connection line 55 may be formed by forming a gate electrode layer, forming a mask pattern covering a portion of the periphery of the opening region OP, and etching the gate electrode layer using the mask pattern as an etching mask.

[0066] During the etching process, the gate electrode layer covered by the slope portion 41A of the gate insulating layer 41 may remain unetched, thereby forming the gate electrode 51 and the gate connection electrode 54. During the etching process, the gate electrode layer covered by the mask pattern may remain unetched, thereby forming the gate connection line 55.

[0067] The gate electrode 51 may have an inner surface contacting the slope portion 41A and the horizontal portion 41B of the gate insulating layer 41 and an outer surface 51S opposite to the inner surface.

[0068] As described above, a portion of the top portion of the slope portion 41A of the gate insulating layer 41 may contact a side surface of the first conductive region 31B. An outer surface 51S of the gate electrode 51 may be vertically aligned with a portion of the top portion of the slope portion 41A of the gate insulating layer 41.

[0069] A portion of the first conductive region 31B may be self-aligned with the inclined portion 41A of the gate insulating layer 41. A portion of the second conductive region 31C may be self-aligned with the horizontal portion 41B of the gate insulating layer 41. The first conductive region 31B may not overlap with the gate electrode 51, or only a portion of the first conductive region 31B may overlap with the gate electrode 51. The second conductive region 31C may not overlap with the gate electrode 51.

[0070] By disposing the gate electrode 51 above the gate insulating layer 41 and configuring the first conductive region 31B and the second conductive region 31C to be self-aligned with the gate insulating layer 41, the area where the first conductive region 31B and the second conductive region 31C overlap with the gate electrode 51 can be minimized. Therefore, the parasitic capacitance between the gate electrode 51 and the first conductive region 31B and the second conductive region 31C can be minimized, and the breakdown characteristics of the thin film transistor TR1 can be improved.

[0071] An insulating layer 60 may be disposed over the buffer layer 20 to cover the active pattern 31, the gate insulating layer 41, the gate electrode 51, the gate connection electrode 54, and the gate connection line 55. The insulating layer 60 may have a first contact hole CH1 exposing the first conductive region 31B and a second contact hole CH2 exposing the second conductive region 31C.

[0072] The first electrode 71 and the second electrode 72 may be disposed on the insulating layer 60. The first electrode 71 may be connected to the first conductive region 31B through a first contact hole CH1. The second electrode 72 may be connected to the second conductive region 31C through a second contact hole CH2.

[0073] Figure 2 The outer surface 51S of the gate electrode 51 is shown as being vertically aligned with the top portion of the slope portion 41A of the gate insulating layer 41, but is not limited thereto. The shape of the outer surface 51S of the gate electrode 51 may vary depending on the thickness of the gate electrode layer, the processing conditions of the process for etching the gate electrode layer, etc.

[0074] Figure 4 and Figure 5 Each shows a gate electrode of a thin film transistor according to some embodiments.

[0075] Reference Figure 4 , the outer surface 51S of the gate electrode 51 may have a regular tapered shape.

[0076] As described above, the gate electrode 51 can be formed by forming a gate electrode layer and etching the gate electrode layer through an etching process. The gate electrode layer provided under the slope portion 41A of the gate insulating layer 41 can be covered by the slope portion 41A so as not to be removed in the etching process and to remain, thereby forming the gate electrode 51.

[0077] The outer surface 51S of the gate electrode 51 is a surface formed by the above-mentioned etching process. Due to process factors, the gate electrode layer may be etched into an inclined shape rather than a vertical shape, so that the outer surface 51S of the gate electrode 51 has a tapered shape. In this case, the outer surface 51S of the gate electrode 51 may protrude beyond (or be higher than) the top portion of the inclined surface portion 41A of the gate insulating layer 41.

[0078] Reference Figure 5 , the outer surface 51S of the gate electrode 51 may have a curvature corresponding to the surface shapes of the inclined portion 41A and the horizontal portion 41B of the gate insulating layer 41 .

[0079] During the formation of the gate electrode layer, the gate electrode layer may not completely fill the space below the inclined surface portion 41A of the gate insulating layer 41, and may be formed along the curved surfaces of the inclined surface portion 41A and the horizontal portion 41B of the gate insulating layer 41. In this case, the outer surface 51S of the gate electrode 51 may have a curve corresponding to the surface shape of the inclined surface portion 41A and the horizontal portion 41B of the gate insulating layer 41.

[0080] Figure 6 is a plan view showing a thin film transistor array substrate according to an embodiment, Figure 7 It is along Figure 6 The cross-sectional view taken along line CC' in FIG. Figure 8 It is along Figure 6 A cross-sectional view taken along line D-D' in FIG.

[0081] Reference Figures 6 to 8 A buffer layer 20 having an open area OP exposing a portion of the substrate 10 may be disposed over the substrate 10 .

[0082] The inclined surfaces 20S1, 20S2, 20S3, and 20S4 of the buffer layer 20 may be exposed through the open area OP. The inclined surfaces 20S1, 20S2, 20S3, and 20S4 of the buffer layer 20 may include a first inclined surface 20S1 and a second inclined surface 20S2 facing each other in the X-axis direction X of the XY plane, and a third inclined surface 20S3 and a fourth inclined surface 20S4 facing each other in the Y-axis direction Y of the XY plane. The width of the open area OP may increase in a direction toward the substrate 10. The first inclined surface 20S1, the second inclined surface 20S2, the third inclined surface 20S3, and the fourth inclined surface 20S4 of the buffer layer 20 may have an inverted tapered shape.

[0083] In the present disclosure, the first inclined surface 20S1 and the second inclined surface 20S2 of the buffer layer 20 face each other in the X-axis direction X, and the third inclined surface 20S3 and the fourth inclined surface 20S4 of the buffer layer 20 face each other in the Y-axis direction Y, but this is not intended to be limiting. The first inclined surface 20S1 and the second inclined surface 20S2 of the buffer layer 20 may face each other in a first direction, and the third inclined surface 20S3 and the fourth inclined surface 20S4 of the buffer layer 20 may face each other in a second direction intersecting with the first direction.

[0084] The first thin film transistor TR1 may be disposed above a region including the first inclined surface 20S1 of the buffer layer 20. The second thin film transistor TR2 may be disposed above a region including the second inclined surface 20S2 of the buffer layer 20. The first and second thin film transistors TR1 and TR2 may be vertical thin film transistors.

[0085] The first active pattern 31' may be continuously disposed over the top surface of the buffer layer 20 adjacent to the first inclined surface 20S1 of the buffer layer 20, over the first inclined surface 20S1 of the buffer layer 20, over the top surface of the substrate 10 between the first inclined surface 20S1 and the second inclined surface 20S2 of the buffer layer 20, over the second inclined surface 20S2 of the buffer layer 20, and over the top surface of the buffer layer 20 adjacent to the second inclined surface 20S2 of the buffer layer 20. In a plan view, the first active pattern 31' may pass through the first inclined surface 20S1 and the second inclined surface 20S2 of the buffer layer 20 in the X-axis direction X.

[0086] The first active pattern 31 ′ may be provided as a thin film along the surface curvatures of the first and second inclined surfaces 20S1 and 20S2 of the buffer layer 20 , the top surface of the buffer layer 20 , and the top surface of the substrate 10 .

[0087] The first active pattern 31 ′ may be formed of an oxide semiconductor and may include a first channel region 31A, a first conductive region 31B, a second conductive region 31C, a second channel region 31D, and a third conductive region 31E.

[0088] The first channel region 31A and the second channel region 31D may have semiconductor characteristics. The first channel region 31A and the second channel region 31D may be formed of, for example, an oxide semiconductor. The first conductive region 31B, the second conductive region 31C, and the third conductive region 31E may be regions where the oxide semiconductor is made conductive by exposure to an etching gas used in the etching process for forming the first gate insulating layer 41'.

[0089] The first channel region 31A may be disposed above the first inclined surface 20S1 of the buffer layer 20. Furthermore, the first channel region 31A may be disposed above the top surface of the substrate 10 below the first inclined surface 20S1 of the buffer layer 20. The first channel region 31A may include a first portion 31Aa disposed above the first inclined surface 20S1 of the buffer layer 20 and a second portion 31Ab disposed above the top surface of the substrate 10.

[0090] The second channel region 31B may be disposed above the second inclined surface 20S2 of the buffer layer 20. The second channel region 31B may also be disposed above the top surface of the substrate 10 below the second inclined surface 20S2 of the buffer layer 20. The second channel region 31B may include a third portion 31Ba disposed above the second inclined surface 20S2 of the buffer layer 20 and a fourth portion 31Bb disposed above the top surface of the substrate 10.

[0091] The first conductive region 31B may be disposed on the top surface of the buffer layer 20 on one side of the first channel region 31A. The second conductive region 31C may be disposed on the top surface of the substrate 10 between the other side of the first channel region 31A and one side of the second channel region 31B. The third conductive region 31E may be disposed on the top surface of the buffer layer 20 on the other side of the second channel region 31D.

[0092] The first conductive region 31B and the second conductive region 31C may be disposed on opposite sides of the first channel region 31A in the X-axis direction X. The second conductive region 31C and the third conductive region 31E may be disposed on opposite sides of the second channel region 31D in the X-axis direction X. The second conductive region 31C may be disposed between the first channel region 31A and the second channel region 31D in the X-axis direction X.

[0093] One of the first conductive region 31B and the second conductive region 31C may be the source region of the first thin film transistor TR1, and the other may be the drain region of the first thin film transistor TR1. One of the second conductive region 31C and the third conductive region 31E may be the source region of the second thin film transistor TR2, and the other may be the drain region of the second thin film transistor TR2. The first thin film transistor TR1 and the second thin film transistor TR2 may share the second conductive region 31C.

[0094] The first conductive region 31B may overlap with the first inclined surface 20S1 of the buffer layer 20. The third conductive region 31E may overlap with the second inclined surface 20S2 of the buffer layer 20. The second conductive region 31C may not overlap with any of the inclined surfaces 20S1, 20S2, 20S3, and 20S4 of the buffer layer 20. The first conductive region 31B, the second conductive region 31C, and the third conductive region 31E may be spaced apart from each other in a horizontal direction parallel to the top surface of the substrate 10.

[0095] The first gate insulating layer 41' may be disposed over the first channel region 31A and the second channel region 31D. The first gate insulating layer 41' may expose the first conductive region 31B, the second conductive region 31C, and the third conductive region 31E.

[0096] The first gate insulating layer 41' may include a first inclined surface portion 41A-1', a second inclined surface portion 41A-2', a third inclined surface portion 41A-3', and a fourth inclined surface portion 41A-4', and a first horizontal portion 41B-1', a second horizontal portion 41B-2', a third horizontal portion 41B-3', and a fourth horizontal portion 41B-4'. The first gate insulating layer 41' may further include an extension portion 41C.

[0097] The first inclined surface portion 41A-1' of the first gate insulating layer 41' may cover the first portion 31Aa of the first channel region 31A. The first inclined surface portion 41A-1' of the first gate insulating layer 41' may extend to the first inclined surface 20S1 of the buffer layer 20 on the opposite side of the first channel region 31A to cover the first inclined surface 20S1 of the buffer layer 20.

[0098] A portion of the first inclined surface portion 41A-1' of the first gate insulating layer 41' may be in direct contact with the first portion 31Aa of the first channel region 31A, and another portion of the first inclined surface portion 41A-1' of the first gate insulating layer 41' may be in direct contact with the first inclined surface 20S1 of the buffer layer 20. A portion of a top portion of the first inclined surface portion 41A-1' of the first gate insulating layer 41' may be in direct contact with a side surface of the first conductive region 31B.

[0099] The first horizontal portion 41B-1' of the first gate insulating layer 41' may cover the second portion 31Ab of the first channel region 31A. The first horizontal portion 41B-1' of the first gate insulating layer 41' may extend to the top surface of the substrate 10 to cover the top surface of the substrate 10 below the first inclined portion 41A-1' of the first gate insulating layer 41'.

[0100] A portion of the first horizontal portion 41B- 1 ′ of the first gate insulating layer 41 ′ may directly contact the second portion 31Ab of the first channel region 31A, and another portion of the first horizontal portion 41B- 1 ′ of the first gate insulating layer 41 ′ may directly contact the top surface of the substrate 10 .

[0101] The second slope portion 41A-2' of the first gate insulating layer 41' may cover the third portion 31Da of the second channel region 31D. The second slope portion 41A-2' of the first gate insulating layer 41' may extend to the second slope 20S2 of the buffer layer 20 on the opposite side of the second channel region 31D to cover the second slope 20S2 of the buffer layer 20.

[0102] A portion of the second inclined surface portion 41A-2' of the first gate insulating layer 41' may be in direct contact with the third portion 31Da of the second channel region 31D, and another portion of the second inclined surface portion 41A-2' of the first gate insulating layer 41' may be in direct contact with the second inclined surface 20S2 of the buffer layer 20. A portion of the top portion of the second inclined surface portion 41A-2' of the first gate insulating layer 41' may be in direct contact with the side surface of the third conductive region 31E.

[0103] The second horizontal portion 41B-2' of the first gate insulating layer 41' may cover the fourth portion 31Db of the second channel region 31D. The second horizontal portion 41B-2' of the first gate insulating layer 41' may extend to the top surface of the substrate 10 to cover the top surface of the substrate 10 below the second inclined portion 41A-2' of the first gate insulating layer 41'.

[0104] A portion of the second horizontal portion 41B- 2 ′ of the first gate insulating layer 41 ′ may directly contact the fourth portion 31Db of the second channel region 31D, and another portion of the second horizontal portion 41B- 2 ′ of the first gate insulating layer 41 ′ may directly contact the top surface of the substrate 10 .

[0105] The third slope portion 41A- 3 ′ of the first gate insulating layer 41 ′ may cover the third slope 20S3 of the buffer layer 20 . The third slope portion 41A- 3 ′ of the first gate insulating layer 41 ′ may be in direct contact with the third slope 20S3 of the buffer layer 20 .

[0106] The third horizontal portion 41B-3' of the first gate insulating layer 41' may cover the top surface of the substrate 10 below the third inclined portion 41A-3'. The third horizontal portion 41B-3' of the first gate insulating layer 41' may directly contact the top surface of the substrate 20 below the third inclined portion 41A-3' of the first gate insulating layer 41'.

[0107] The fourth slope portion 41A- 4 ′ of the first gate insulating layer 41 ′ may cover the fourth slope 20S4 of the buffer layer 20 . The fourth slope portion 41A- 4 ′ of the first gate insulating layer 41 ′ may be in direct contact with the fourth slope 20S4 of the buffer layer 20 .

[0108] The fourth horizontal portion 41B-4' of the first gate insulating layer 41' may cover the top surface of the substrate 10 below the fourth inclined portion 41A-4' of the first gate insulating layer 41'. The fourth horizontal portion 41B-4' of the first gate insulating layer 41' may directly contact the top surface of the substrate 10 below the fourth inclined portion 41A-4' of the first gate insulating layer 41'.

[0109] The extension portion 41C of the first gate insulating layer 41' may be disposed above the top surface of the buffer layer 20 around the opening region OP and may extend to the opening region OP to connect to the third inclined surface portion 41A-3' of the first gate insulating layer 41'. In the present disclosure, the extension portion 41C of the first gate insulating layer 41' is connected to the third inclined surface portion 41A-3' of the first gate insulating layer 41', but is not limited thereto. The extension portion 41C of the first gate insulating layer 41' may be connected to at least one of the first inclined surface portion 41A-1', the second inclined surface portion 41A-2', the third inclined surface portion 41A-3', and the fourth inclined surface portion 41A-4' of the first gate insulating layer 41'.

[0110] The first gate insulating layer 41 ′ may be formed by an ALD process. Since the first gate insulating layer 41 ′ is formed by an ALD process having good step coverage, the first gate insulating layer 41 ′ may have a uniform thickness.

[0111] The first and second gate electrodes 51 and 52 and the gate connection electrode 54 may be disposed under the first, second, third, and fourth slope portions 41A- 1 ′, 41A- 2 ′, 41A- 3 ′, and 41A- 4 ′ of the first gate insulating layer 41 ′.

[0112] The first gate electrode 51 may be disposed over a portion of the first inclined portion 41A-1′ of the first gate insulating layer 41′ that is in direct contact with the first portion 31Aa of the first channel region 31A. Furthermore, the first gate electrode 51 may be disposed over a portion of the first horizontal portion 41B-1′ of the first gate insulating layer 41′ that is in direct contact with the second portion 31Ab of the first channel region 31A. The first gate electrode 51 may overlap the first channel region 31A.

[0113] The second gate electrode 52 may be disposed over a portion of the second inclined portion 41A-2' of the first gate insulating layer 41' that is in direct contact with the third portion 31Da of the second channel region 31D. Additionally, the second gate electrode 52 may be disposed over a portion of the second horizontal portion 41B-2' of the first gate insulating layer 41' that is in direct contact with the fourth portion 31Db of the second channel region 31D. The second gate electrode 52 may overlap the second channel region 31D.

[0114] The gate connection electrode 54 may be disposed over another portion of the first inclined surface portion 41A-1' of the first gate insulating layer 41' that is in direct contact with the first inclined surface 20S1 of the buffer layer 20. The gate connection electrode 54 may be disposed over another portion of the first horizontal portion 41B-1' of the first gate insulating layer 41' that is in direct contact with the top surface of the substrate 10. The gate connection electrode 54 may be disposed over another portion of the second inclined surface portion 41A-2' of the first gate insulating layer 41' that is in direct contact with the second inclined surface 20S2 of the buffer layer 20. The gate connection electrode 54 may be disposed over another portion of the second horizontal portion 41B-2' of the first gate insulating layer 41' that is in direct contact with the top surface of the substrate 10. The gate connection electrode 54 may be disposed over the third inclined surface portion 41A-3', the third horizontal portion 41B-3', the fourth inclined surface portion 41A-4', and the fourth horizontal portion 41B-4' of the first gate insulating layer 41'.

[0115] The gate connection line 55 may be disposed above the extension portion 41C of the first gate insulating layer 41'. The gate connection line 55 may extend to the open area OP to be connected to the gate connection electrode 54. The gate connection line 55 may not overlap the active pattern 31'.

[0116] The first gate electrode 51 and the second gate electrode 52, the gate connection electrode 54 and the gate connection line 55 may be formed of the same material. The first gate electrode 51 and the second gate electrode 52, the gate connection electrode 54 and the gate connection line 55 may be implemented using various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) or copper (Cu), alloys of one or more thereof, or multilayers thereof, but are not limited thereto.

[0117] The gate connection electrode 54 may be commonly connected to the first gate electrode 51 and the second gate electrode 52. In this case, the first gate electrode 51 and the second gate electrode 52 may be connected to each other through the gate connection electrode 54.

[0118] In the present disclosure, the gate connection electrode 54 is commonly connected to the first gate electrode 51 and the second gate electrode 52, but this is not intended to be limiting. The gate connection electrode 54 may also be individually connected to each of the first gate electrode 51 and the second gate electrode 52. In this case, the first gate electrode 51 and the second gate electrode 52 may be electrically isolated.

[0119] The first and second gate electrodes 51 and 52 , the gate connection electrode 54 and the gate connection line 55 can be formed by forming a gate electrode layer, forming a mask pattern covering a portion around the opening area OP, and etching the gate electrode layer using the mask pattern as an etching mask.

[0120] During the etching process, the gate electrode layer shielded by the first bevel portion 41A-1′, the second bevel portion 41A-2′, the third bevel portion 41A-3′, and the fourth bevel portion 41A-4′ of the first gate insulating layer 41′ may remain unetched to form the first and second gate electrodes 51 and 52 and the gate connection electrode 54. During the etching process, the gate electrode layer covered by the mask pattern may remain unetched to form the gate connection line 55.

[0121] The first thin film transistor TR1 may include a first gate electrode 51, a first slope portion 41A-1' and a first horizontal portion 41B-1' of a first gate insulating layer 41' below the first gate electrode 51, a first channel region 31A of a first active pattern 31', and first and second conductive regions 31B and 31C.

[0122] The second thin film transistor TR2 may include a second gate electrode 52, a second inclined portion 41A-2′ and a second horizontal portion 41B-2′ of the first gate insulating layer 41′ below the second gate electrode 52, a second channel region 31D of the first active pattern 31′, and second and third conductive regions 31C and 31E of the first active pattern 31′.

[0123] A portion of the first conductive region 31B may be self-aligned with the first inclined portion 41A-1' of the first gate insulating layer 41'. A portion of the second conductive region 31C may be self-aligned with the first horizontal portion 41B-1' of the first gate insulating layer 41', and another portion of the second conductive region 31C may be self-aligned with the second horizontal portion 41B-2' of the first gate insulating layer 41'. A portion of the third conductive region 31E may be self-aligned with the second inclined portion 41A-2' of the first gate insulating layer 41'.

[0124] The first conductive region 31B may not overlap with the first gate electrode 51, or only a portion of the first conductive region 31B may overlap with the first gate electrode 51. The third conductive region 31E may not overlap with the second gate electrode 52, or only a portion of the third conductive region 31E may overlap with the second gate electrode 52. The second conductive region 31C may not overlap with the first gate electrode 51 or the second gate electrode 52.

[0125] By disposing the first gate electrode 51 above the first inclined portion 41A-1' and the first horizontal portion 41B-1' of the first gate insulating layer 41', and configuring the first conductive region 31B and the second conductive region 31C to be self-aligned with the first inclined portion 41A-1' and the first horizontal portion 41B-1' of the first gate insulating layer 41', the area where the first conductive region 31B and the second conductive region 31C overlap with the first gate electrode 51 can be minimized. Therefore, the parasitic capacitance between the first gate electrode 51 and the first conductive region 31B and the second conductive region 31C can be minimized, and the breakdown characteristics of the first thin film transistor TR1 can be improved.

[0126] Similarly, by disposing the second gate electrode 52 above the second inclined portion 41A-2′ and the second horizontal portion 41B-2′ of the first gate insulating layer 41′, and configuring the second conductive region 31C and the third conductive region 31E to be self-aligned with the second inclined portion 41A-2′ and the second horizontal portion 41B-2′ of the first gate insulating layer 41′, the area where the second conductive region 31C and the third conductive region 31E overlap with the second gate electrode 52 can be minimized. Therefore, the parasitic capacitance between the second gate electrode 52 and the second conductive region 31C and the third conductive region 31E can be minimized, and the breakdown characteristics of the second thin film transistor TR2 can be improved.

[0127] An insulating layer 60 may be disposed over the buffer layer 20 to cover the first active pattern 31', the first gate insulating layer 41', the first and second gate electrodes 51 and 52, the gate connection electrode 54, and the gate connection line 55. The insulating layer 60 may have a first contact hole CH1 exposing the first conductive region 31B, a second contact hole CH2 exposing the second conductive region 31C, and a third contact hole CH3 exposing the third conductive region 31E.

[0128] The first electrode 71 , the second electrode 72 , and the third electrode 73 may be disposed over the insulating layer 60 .

[0129] The first electrode 71 may be connected to the first conductive region 31B through the first contact hole CH1, the second electrode 72 may be connected to the second conductive region 31C through the second contact hole CH2, and the third electrode 73 may be connected to the third conductive region 31E through the third contact hole CH3.

[0130] Figure 9 A schematic configuration of a system of a display device according to an embodiment is shown.

[0131] Reference Figure 9According to an embodiment, the display device 100 includes a display panel 110. In addition, the display device 100 includes a driver circuit for driving various signal lines and the like provided on the display panel 110. The driving circuit system may include a gate driver circuit 120, a data driver circuit 130, a controller 140, and the like.

[0132] The display panel 110 includes a display area A / A and a non-display area N / A outside the display area A / A. A plurality of sub-pixels SP are provided in the display area A / A of the display panel 110. A plurality of gate lines GL extending in a first direction (e.g., a column direction or a row direction) and a plurality of data lines DL extending in a second direction intersecting the first direction may be provided on the display panel 110, and the sub-pixels SP may be provided in the region where the gate lines GL and the data lines DL intersect.

[0133] The gate driver circuit 120 may generate a gate signal and output the gate signal to a plurality of gate lines GL. Figure 9 As shown, the gate driver circuit 120 may be provided in the non-display area N / A of the display panel 110. That is, the display device 100 may be a gate-in-panel (GIP) display device.

[0134] Although not shown, the gate driver circuit 120 may be formed separately from the display panel 110 and connected to the display panel 110 by a tape automated packaging (TAB) method, or connected to a bonding pad on the display panel 110 by a chip on glass (COG) method or a chip on plastic (COP) method, or may be implemented and connected to the display panel 110 by a chip on film (COF) method.

[0135] The data driver circuit 130 may output data signals (also referred to as "data voltages") corresponding to video or image signals to the plurality of data lines DL. The data driver circuit 130 may include one or more source driver integrated circuits. For example, each source driver integrated circuit may be connected to the display panel 110 using a TAB method, connected to a bonding pad on the display panel 110 using a COG method or a COP method, or implemented and connected to the display panel 110 using a COF method.

[0136] exist Figure 9 , the data driver circuit 130 is shown as a component separate from the display panel 110, but the data driver circuit 130 may be configured as an intra-panel type in which the data driver circuit 130 is integrally formed with the display panel 110. The data driver circuit 130 may be provided in a non-display area N / A of the display panel 110.

[0137] The controller 140 may convert input image data (or video data) input from an external host (not shown) into a data signal format used by the data driver circuit 130 and provide the converted image data to the data driver circuit 130 .

[0138] Each of the sub-pixels SP may include a light emitting element ED and a pixel driver circuit for driving the light emitting element ED. The pixel driver circuit may include a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0139] The light emitting element ED may be, for example, an organic light emitting diode (OLED), a light emitting diode (LED) based on an inorganic material, or a quantum dot light emitting element which is a self-luminous semiconductor crystal.

[0140] According to an embodiment, when the display device 100 is an OLED display, each sub-pixel SP may include a self-luminous OLED as a light-emitting element. According to an embodiment, when the display device 100 is a quantum dot display, each sub-pixel SP may include a light-emitting element formed of quantum dots, which are self-luminous semiconductor crystals. According to an embodiment, when the display device 100 is a micro-LED display, each sub-pixel SP may include a self-luminous micro-light-emitting diode (micro-LED) based on an inorganic material as a light-emitting element.

[0141] The drive transistor DRT is a transistor for driving the light-emitting element ED by controlling the current flowing to the light-emitting element ED, and may include a first node N1, a second node N2, a third node N3, etc. The first node N1 may be a source node or a drain node and is electrically connected to the anode electrode AE of the light-emitting element ED. The second node N2 may be a gate node and is electrically connected to the source node or the drain node of the scan transistor SCT. The third node N3 may be a drain node or a source node and is connected to a drive voltage line DVL, through which a drive voltage EVDD is supplied.

[0142] The scan transistor SCT can control the connection between the data line DL and the second node N2 of the drive transistor DRT. The scan transistor SCT can connect the second node N2 of the drive transistor DRT to the corresponding data line DL among the plurality of data lines DL in response to a scan signal SCAN provided to the scan line SCL (i.e., a type of gate line GL). The scan transistor SCT can transmit the data voltage Vdata to the second node N2, which is the gate node of the drive transistor DRT, in response to the scan signal SCAN.

[0143] The storage capacitor Cst may be connected to the first node N1 and the second node N2 of the driving transistor DRT and maintain the voltage of the second node N2 for a predetermined period of time.

[0144] For example, each sub-pixel SP may have Figure 9 The 2T1C structure shown includes two transistors DRT and SCT and a single capacitor Cst, but is not limited thereto. In some cases, each sub-pixel SP may further include one or more transistors and / or one or more capacitors.

[0145] Figure 10 is a cross-sectional view showing a display device according to an embodiment, Figure 11 is a plan view showing a circuit element layer of a display device according to an embodiment, Figure 12 It is along Figure 11 A cross-sectional view taken along line EE' in FIG.

[0146] Now refer to Figure 10 According to an embodiment, the display device may include a circuit element layer 1 disposed over a substrate 10 and a light emitting element 90 disposed on the circuit element layer 1 .

[0147] The substrate 10 may include various materials having flexible or bendable properties. For example, the substrate 10 may include glass, metal, or a polymer resin. In addition, the substrate 10 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 10 may be modified in various ways, such as having a multilayer structure including two layers each including the above-mentioned polymer resin and a barrier layer including an inorganic material (e.g., silicon oxide, silicon nitride, or silicon oxynitride) disposed between the layers.

[0148] Although not shown, an additional auxiliary film (not shown) such as a barrier film, a blocking film, and / or a buffer film may be provided over the substrate 10. The auxiliary film may smooth the top surface and prevent the penetration of impurities. The auxiliary film may be formed of an inorganic insulating material and may be formed into a single-layer structure or a double-layer structure (or a monolayer structure or a bilayer structure). The auxiliary film may prevent the first active pattern 31' and the second active pattern 32 (see FIG. 1 ). Figure 12 ) are contaminated by impurities from the substrate 10, thereby protecting the first active pattern 31' and the second active pattern 32 while improving the interface characteristics thereof.

[0149] The circuit element layer 1 may include the above reference Figures 1 to 5 The first thin film transistor TR1 described above. The circuit element layer 1 may include Figures 6 to 8The first thin film transistor TR1 and the second thin film transistor TR2 are described. In addition, or in another example, the circuit element layer 1 may further include a third thin film transistor TR3.

[0150] The first thin film transistor TR1, the second thin film transistor TR2, and the third thin film transistor TR3 may be transistors included in a sub-pixel. For example, the first thin film transistor TR1 or the second thin film transistor TR2 may be a switching transistor, and the third thin film transistor TR3 may be a driving transistor, but this is not intended to be limiting.

[0151] Reference Figure 11 and Figure 12 , the third thin film transistor TR3 may include a second active pattern 32, a second gate insulating layer 42, and a third gate electrode 53. The third thin film transistor TR3 may have a coplanar structure.

[0152] The second active pattern 32 may be disposed over the top surface of the buffer layer 20. The second active pattern 32 may include an oxide semiconductor.

[0153] The second active pattern 32 may include a third channel region 32A, and a fourth conductive region 32B and a fifth conductive region 32C on opposite sides of the third channel region 32A. The third channel region 32A may have semiconductor properties. The third channel region 32A may be formed of a semiconductor, such as an intrinsic oxide semiconductor. The fourth conductive region 32B and the fifth conductive region 32C may be regions where the oxide semiconductor has been made conductive by exposure to an etching gas used in the etching process for forming the second gate insulating layer 42. One of the fourth conductive region 32B and the fifth conductive region 32C may be the source region of the third thin-film transistor TR3, and the other may be the drain region of the third thin-film transistor TR3.

[0154] The second gate insulating layer 42 may be disposed over the third channel region 32A. The second gate insulating layer 42 may cover the third channel region 32A and expose the fourth conductive region 32B and the fifth conductive region 32C. The third gate electrode 53 may be disposed over the second gate insulating layer 42.

[0155] The circuit element layer 1 may further include a bottom shielding metal pattern 12 disposed above the substrate 10. The bottom shielding metal pattern 12 may be disposed in a region corresponding to the third thin film transistor TR3. The bottom shielding metal pattern 12 may include molybdenum (Mo). The bottom shielding metal pattern 12 may prevent potential generation on the surface of the substrate 10 and light from entering from the outside.

[0156] The circuit element layer 1 may include an insulating layer 60. The insulating layer 60 may be disposed over the buffer layer 20 and may cover the first to third thin film transistors TR1, TR2, and TR3.

[0157] The insulating layer 60 may be provided with a first contact hole CH1, a second contact hole CH2, a third contact hole CH3, a fourth contact hole CH4 and a fifth contact hole CH5 exposing the first conductive region 31B, the second conductive region 31C, the third conductive region 31E, the fourth conductive region 32B and the fifth conductive region 32C, respectively.

[0158] A first electrode 71, a second electrode 72, a third electrode 73, a fourth electrode 74, and a fifth electrode 75 may be disposed above the insulating layer 60. The first electrode 71 may be connected to the first conductive region 31B via a first contact hole CH1. The second electrode 72 may be connected to the second conductive region 31C via a second contact hole CH2. The third electrode 73 may be connected to the third conductive region 31E via a third contact hole CH3. The fourth electrode 74 may be connected to the fourth conductive region 32B via a fourth contact hole CH4. The fifth electrode 75 may be connected to the fifth conductive region 32C via a fifth contact hole CH5.

[0159] Refer again Figure 10 A passivation layer 80 may be provided over the insulating layer 60 to cover the first, second, third, fourth, and fifth electrodes 71, 72, 73, 74, and 75. A sixth contact hole CH6 exposing the fifth electrode 75 to the passivation layer 80 may be provided.

[0160] The light emitting element 90 may be disposed over the passivation layer 80 .

[0161] The light emitting element 90 may include a pixel electrode 91, a light emitting layer 92, and a common electrode 93. The pixel electrode 91 may be disposed above the passivation layer 80 and connected to the fifth electrode 75 through a sixth contact hole CH6.

[0162] The bank 82 may be disposed over the passivation layer 80. The bank 82 may have a hole H exposing the pixel electrode 91. The light emitting element 90 may be formed in a region exposed by the hole H. The bank 82 may include an organic material such as polyimide or hexamethyldisiloxane (HMDSO).

[0163] The light emitting layer 92 may be disposed over the pixel electrode 91 exposed through the hole H of the bank 82. The light emitting layer 92 may cover the side surface of the bank 82 exposed through the hole H and the top surface of the bank 82.

[0164] The light emitting layer 92 may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light emitting layer 92 may be a low molecular weight organic material or a high molecular weight organic material.

[0165] In addition, or in another example, the first functional layer and the second functional layer may be selectively disposed below and above the light emitting layer 92. The first functional layer may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0166] The common electrode 93 may be disposed on the light emitting layer 92 .

[0167] Figures 13A to 19B : is a cross-sectional view showing a method of manufacturing a circuit element layer of a display device according to an embodiment. Figures 13A to 19A Shown with Figure 11 The cross section corresponding to the line E-E' in Figures 13B to 19B Shown with Figure 11 The cross section corresponding to the line F-F' in .

[0168] Reference Figure 13A and Figure 13B , a bottom shield metal pattern 12 may be formed over the substrate 10 , and a buffer layer 20 may be formed to cover the bottom shield metal pattern 12 .

[0169] Although not shown, an additional auxiliary film (not shown) such as a barrier film, a blocking film, and / or a buffer film may be disposed over the substrate 10 .

[0170] A bottom shield metal pattern 12 may be formed in the third thin film transistor region.

[0171] The buffer layer 20 may include, but is not limited to, a single layer formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), or a multilayer of silicon nitride (SiNx) and silicon oxide (SiOx).

[0172] Reference Figure 14A and Figure 14B , an open region OP may be formed in the buffer layer 20 .

[0173] A first mask pattern PR1 may be formed over the buffer layer 20 to expose portions of the first and second thin film transistor regions of the buffer layer 20, and the buffer layer 20 may be etched using the first mask pattern PR1 as an etching mask to form an open region OP. The etching process may be implemented as a wet etching process.

[0174] The inclined surfaces 20S1, 20S2, 20S3, and 20S4 of the buffer layer 20 may be exposed through the open region OP. The inclined surfaces 20S1, 20S2, 20S3, and 20S4 may include a first inclined surface 20S1 and a second inclined surface 20S2 facing each other in the X-axis direction, and a third inclined surface 20S3 and a fourth inclined surface 20S4 facing each other in the Y-axis direction. The width of the open region OP may increase in a direction toward the substrate 10. The first inclined surface 20S1, the second inclined surface 20S2, the third inclined surface 20S3, and the fourth inclined surface 20S4 may have an inverted tapered shape.

[0175] The first mask pattern PR1 may be formed of a photoresist, and the first mask pattern PR1 remaining after forming the open area OP may be removed by a strip process.

[0176] Reference Figure 15A and Figure 15B An active layer may be formed and patterned to form first active patterns 31' in the first and second thin film transistor regions. During the formation of the first active pattern 31', a second active pattern 32 may be formed in the third thin film transistor region. The first and second active patterns 31', 32 may be formed simultaneously.

[0177] The first active pattern 31' may be continuously disposed over the top surface of the buffer layer 20 adjacent to the first inclined surface 20S1, the first inclined surface 20S1, the top surface of the substrate 10 between the first inclined surface 20S1 and the second inclined surface 20S2, the second inclined surface 20S2, and the top surface of the buffer layer 20 adjacent to the second inclined surface 20S2. The second active pattern 32 may be formed over the top surface of the buffer layer 20.

[0178] The active layer may be formed by an ALD process. Since the active layer is formed using an ALD process having excellent step coverage, the first active pattern 31' and the second active pattern 32 may be formed with a uniform thickness along the surface curvatures of the first and second inclined surfaces 20S1 and 20S2, the top surface of the buffer layer 20, and the top surface of the substrate 10.

[0179] Reference Figure 16A and Figure 16B A gate insulating layer 40 may be formed over the first active pattern 31' and the second active pattern 32, the first inclined surface 20S1, the second inclined surface 20S2, the third inclined surface 20S3 and the fourth inclined surface 20S4 of the buffer layer 20, the top surface of the buffer layer 20 and the top surface of the substrate 10, and a gate electrode layer 50 may be formed over the gate insulating layer 40.

[0180] The gate insulating layer 40 may be formed of silicon oxide (SiO 2 ). However, the gate insulating layer 40 is not limited thereto and may be formed of an inorganic insulating material other than silicon oxide (SiO 2 ) and may have a single layer structure or a double layer structure.

[0181] The gate electrode layer 50 may be formed of a metal material and may have a single-layer structure or a double-layer structure. The gate electrode layer 50 may be implemented using various metal materials such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), an alloy of one or more of these, or a multilayer thereof, but is not limited thereto.

[0182] Reference Figure 17A and Figure 17B , a second mask pattern PR2 may be formed over the gate electrode layer 50, and the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53, the gate connection electrode 54, and the gate connection line 55 may be formed by etching the gate electrode layer 50 using the second mask pattern PR2 as an etching mask. The first gate electrode 51, the second gate electrode 52, and the third gate electrode 53, the gate connection electrode 54, and the gate connection line 55 may be formed at once.

[0183] The second mask pattern PR2 may expose the open region OP and cover a portion of the gate electrode layer 50 around the open region OP. In addition, the second mask pattern PR2 may cover a portion of the third thin film transistor region.

[0184] The first gate electrode 51, the second gate electrode 52 and the gate connecting electrode 54 can be formed by the remaining portion of the gate electrode layer 50, which is covered by the inclined surface portion of the first gate insulating layer 41' arranged above the first inclined surface 20S1, the second inclined surface 20S2, the third inclined surface 20S3 and the fourth inclined surface 20S4 of the buffer layer 20 and is not removed in the above-mentioned etching process.

[0185] The third gate electrode 53 may be formed by the remaining portion of the gate electrode layer 50 in the third thin film transistor region, which is covered by the second mask pattern PR2 and is not removed during the etching process. The gate connection line 55 may be formed by the remaining portion of the gate electrode layer 50 around the opening region OP, which is covered by the second mask pattern PR2 and is not removed during the etching process.

[0186] The second mask pattern PR2 may be formed of a photoresist, and the second mask pattern PR2 remaining after forming the first, second, and third gate electrodes 51, 52, and 53, the gate connection electrode 54, and the gate connection line 55 may be removed by a stripping process.

[0187] Reference Figure 18A and Figure 18B The gate insulating layer 40 exposed by the first and second gate electrodes 51 and 52 and the gate connection electrode 54 may be removed by an etching process to form a first and second gate insulating layer 41 ′ and 42 . The first and second gate insulating layers 41 ′ and 42 may be formed at once.

[0188] The etching process can be implemented as a dry etching process. During the dry etching process, the first active pattern 31' and the second active pattern 32, except for the portions covered by the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53, can be made conductive by exposure to an etching gas. As a result, the first conductive region 31B, the second conductive region 31C, and the third conductive region 31E can be formed in the first active pattern 31', and the fourth conductive region 32B and the fifth conductive region 32C can be formed in the second active pattern 32. The first conductive region 31B, the second conductive region 31C, the third conductive region 31E, the fourth conductive region 32B, and the fifth conductive region 32C can be formed at one time.

[0189] Reference Figure 19A and Figure 19B An insulating film 60 covering the first active pattern 31 ′ and the second active pattern 32 , the first gate insulating layer 41 ′ and the second gate insulating layer 42 , the first gate electrode 51 , the second gate electrode 52 and the third gate electrode 53 , the gate connecting electrode 54 and the gate connecting line 55 may be formed over the buffer layer 20 .

[0190] Thereafter, a first contact hole CH1 exposing the first conductive region 31B, a second contact hole CH2 exposing the second conductive region 31C, and a third contact hole CH3 exposing the third conductive region 31E may be formed in the insulating film 60 by a photolithography process. In addition, a fourth contact hole CH4 exposing the fourth conductive region 32B and a fifth contact hole CH5 exposing the fifth conductive region 32C may be formed.

[0191] Thereafter, a metal layer may be formed to cover the insulating film 60 and fill the first, second, third, fourth, and fifth contact holes CH1, CH2, CH3, CH4, and CH5, and the metal layer may be patterned to form first, second, third, fourth, and fifth contact plugs 71, 72, 73, 74, and 75, the first to fifth contact plugs 71-75 being connected to the first, second, third, fourth, and fifth conductive regions 31B, 31C, 31E, 32B, and 32C through the first, second, third, fourth, and fifth contact holes CH1, CH2, CH3, CH4, and CH5, respectively.

[0192] The thin film transistor array substrate and the display device including the thin film transistor array substrate according to the embodiments described above may be briefly reviewed as follows.

[0193] According to an embodiment, a thin film transistor array substrate may include: a buffer layer disposed over a substrate and including an opening region exposing a portion of the substrate, and a first inclined surface having an inverted tapered shape and exposed through the opening region; and a first thin film transistor. The first thin film transistor may include: a first active pattern including: a first channel region including a first portion disposed over the first inclined surface of the buffer layer and a second portion disposed over the top surface of the substrate below the first inclined surface of the buffer layer; a first conductive region disposed over the top surface of the buffer layer; and a second conductive region disposed over the top surface of the substrate; a first gate insulating layer including a first inclined portion disposed over the first portion of the first channel region and a first horizontal portion disposed over the second portion of the first channel region; and a first gate electrode disposed over the first inclined portion and the first horizontal portion of the first gate insulating layer and overlapping the first channel region.

[0194] According to an embodiment, a portion of the first conductive region may be self-aligned with the first slope portion of the first gate insulating layer, and a portion of the second conductive region may be self-aligned with the first horizontal portion of the first gate insulating layer.

[0195] According to an embodiment, the second conductive region may not overlap with the first gate electrode.

[0196] According to an embodiment, the first conductive region may overlap with the first inclined surface of the buffer layer, and the second conductive region may not overlap with the first inclined surface of the buffer layer.

[0197] According to an embodiment, the first conductive region and the second conductive region may be spaced apart from each other in a direction parallel to the top surface of the substrate.

[0198] According to an embodiment, a top portion of the first slope portion of the first gate insulating layer may be in contact with a side surface of the first conductive region.

[0199] According to an embodiment, the first gate electrode may include an inner surface contacting the first inclined portion and the first horizontal portion of the first gate insulating layer, and an outer surface opposite to the inner surface, and the outer surface of the first gate electrode may be aligned perpendicular to the top portion of the first inclined portion of the first gate insulating layer.

[0200] According to an embodiment, the first gate electrode may include an inner surface contacting the first inclined portion and the first horizontal portion of the first gate insulating layer, and an outer surface opposite to the inner surface, and the outer surface of the first gate electrode may protrude beyond a top portion of the first inclined portion of the first gate insulating layer.

[0201] According to an embodiment, the first gate electrode may include an inner surface contacting the first slope portion and the first horizontal portion of the first gate insulating layer, and an outer surface opposite to the inner surface, and the outer surface of the first gate electrode may have a tapered shape.

[0202] According to an embodiment, the first gate electrode may include an inner surface contacting the first inclined surface portion and the first horizontal portion of the first gate insulating layer, and an outer surface opposite to the inner surface. The outer surface of the first gate electrode may have a curvature corresponding to the surface shape of the first inclined surface portion and the first horizontal portion of the first gate insulating layer.

[0203] According to an embodiment, a portion of the first inclined surface portion of the first gate insulating layer may be in direct contact with the first portion of the first channel region, and another portion of the first inclined surface portion of the first gate insulating layer may be in direct contact with the first inclined surface of the buffer layer. A portion of the first horizontal portion of the first gate insulating layer may be in direct contact with the second portion of the first channel region, and another portion of the first horizontal portion of the first gate insulating layer may be in direct contact with the top surface of the substrate.

[0204] According to an embodiment, the thin film transistor array substrate may further include a gate connection electrode connected to the first gate electrode. The gate connection electrode may be disposed above another portion of the first inclined portion of the first gate insulating layer and another portion of the first horizontal portion of the first gate insulating layer.

[0205] According to an embodiment, the gate connection electrode may be formed of the same material as the first gate electrode.

[0206] According to an embodiment, the gate connection electrode may cover the first gate insulating layer above the first inclined surface of the buffer layer.

[0207] According to an embodiment, the buffer layer may further include a second inclined surface exposed by the opening region, the second inclined surface facing the first inclined surface in the first direction and having an inverted tapered shape. The thin film transistor array substrate may further include a second thin film transistor disposed above the region including the second inclined surface of the buffer layer and sharing the second conductive region with the first thin film transistor.

[0208] According to an embodiment, the first active pattern may further include: a second channel region, the second channel region including a third portion disposed above the second inclined surface of the buffer layer and a fourth portion disposed above the top surface of the substrate below the second inclined surface of the buffer layer; and a third conductive region disposed above the top surface of the buffer layer. The first gate insulating layer may further include a second inclined surface portion disposed above the third portion of the second channel region and a second horizontal portion disposed above the fourth portion of the second channel region. The second thin-film transistor may include: the second channel region, the second conductive region, and the third conductive region of the first active pattern; the second inclined surface portion and the second horizontal portion of the first gate insulating layer; and a second gate electrode disposed above the second inclined surface portion and the second horizontal portion of the first gate insulating layer and overlapping the second channel region.

[0209] According to an embodiment, a portion of the first conductive region can be self-aligned with the first inclined portion of the first gate insulating layer, a portion of the second conductive region can be self-aligned with the first horizontal portion of the first gate insulating layer, another portion of the second conductive region can be self-aligned with the second horizontal portion of the first gate insulating layer, and a portion of the third conductive region can be self-aligned with the second inclined portion of the first gate insulating layer.

[0210] According to an embodiment, the second conductive region may not overlap with the first gate electrode or the second gate electrode.

[0211] According to an embodiment, the first conductive region may overlap the first slope of the buffer layer, the third conductive region may overlap the second slope of the buffer layer, and the second conductive region may not overlap the first or second slope of the buffer layer.

[0212] According to an embodiment, the first conductive region, the second conductive region, and the third conductive region may be spaced apart from each other in a direction parallel to the top surface of the substrate.

[0213] According to an embodiment, a portion of the first bevel portion of the first gate insulating layer may be in direct contact with the first portion of the first channel region, and another portion of the first bevel portion of the first gate insulating layer may be in direct contact with the first bevel of the buffer layer. A portion of the first horizontal portion of the first gate insulating layer may be in direct contact with the second portion of the first channel region, and another portion of the first horizontal portion of the first gate insulating layer may be in direct contact with the top surface of the substrate. A portion of the second bevel portion of the first gate insulating layer may be in direct contact with the third portion of the second channel region, and another portion of the second bevel portion of the first gate insulating layer may be in direct contact with the second bevel of the buffer layer. A portion of the second horizontal portion of the first gate insulating layer may be in direct contact with the fourth portion of the second channel region, and another portion of the second horizontal portion of the first gate insulating layer may be in direct contact with the top surface of the substrate.

[0214] According to an embodiment, the buffer layer may further include a third inclined surface and a fourth inclined surface exposed by the opening region, the third inclined surface and the fourth inclined surface facing each other in a second direction intersecting the first direction and having an inverted tapered shape. The first gate insulating layer may further include a third inclined surface portion disposed above the third inclined surface of the buffer layer, a third horizontal portion disposed above the substrate below the third inclined surface portion, a fourth inclined surface portion disposed above the fourth inclined surface of the buffer layer, and a fourth horizontal portion disposed above the substrate below the fourth inclined surface portion.

[0215] According to an embodiment, the thin film transistor array substrate may further include a gate connection electrode connected to the first gate electrode and the second gate electrode. The gate connection electrode may be disposed above another portion of the first inclined portion of the first gate insulating layer, another portion of the first horizontal portion of the first gate insulating layer, another portion of the second inclined portion of the first gate insulating layer, another portion of the second horizontal portion of the first gate insulating layer, the third inclined portion of the first gate insulating layer, the third horizontal portion of the first gate insulating layer, the fourth inclined portion of the first gate insulating layer, and the fourth horizontal portion of the first gate insulating layer.

[0216] According to an embodiment, the gate connection electrode may be formed of the same material as the first gate electrode and the second gate electrode.

[0217] According to an embodiment, the thin film transistor array substrate may include a gate connection line disposed over the buffer layer and connected to the gate connection electrode.

[0218] According to an embodiment, the first gate insulating layer may further include an extension portion disposed between the buffer layer and the gate connection line.

[0219] According to an embodiment, the gate link line may not overlap with the first active pattern.

[0220] According to an embodiment, a display device may include: a circuit element layer disposed over a substrate; and a light-emitting element disposed over the circuit element layer. The circuit element layer may include: a buffer layer disposed over the substrate and including an opening region exposing a portion of the substrate, and a first inclined surface having an inverted tapered shape and exposed through the opening region; and a first thin film transistor. The first thin film transistor may include: a first active pattern including: a first channel region including a first portion disposed over the first inclined surface of the buffer layer and a second portion disposed over the top surface of the substrate below the first inclined surface of the buffer layer; a first conductive region disposed over the top surface of the buffer layer; and a second conductive region disposed over the top surface of the substrate; a first gate insulating layer including a first inclined surface portion disposed over the first portion of the first channel region and a first horizontal surface portion disposed over the second portion of the first channel region; and a first gate electrode disposed over the first inclined surface portion and the first horizontal surface portion of the first gate insulating layer and overlapping the first channel region.

[0221] According to an embodiment, a portion of the first conductive region may be self-aligned with the first slope portion of the first gate insulating layer, and a portion of the second conductive region may be self-aligned with the first horizontal portion of the first gate insulating layer.

[0222] According to an embodiment, the second conductive region may not overlap with the first gate electrode.

[0223] According to an embodiment, the first conductive region may overlap with the first inclined surface of the buffer layer, and the second conductive region may not overlap with the first inclined surface of the buffer layer.

[0224] According to an embodiment, the buffer layer may further include a second inclined surface exposed by the opening region, the second inclined surface facing the first inclined surface in the first direction and having an inverted tapered shape. The circuit element layer may further include a second thin film transistor disposed above the region including the second inclined surface of the buffer layer and sharing the second conductive region with the first thin film transistor.

[0225] According to an embodiment, the first active pattern may further include: a second channel region including a third portion disposed above the second inclined surface of the buffer layer, and a fourth portion disposed above the top surface of the substrate below the second inclined surface of the buffer layer and connected to the second conductive region; and a third conductive region disposed above the top surface of the buffer layer. The first gate insulating layer may further include a second inclined surface portion disposed above the third portion of the second channel region and a second horizontal surface portion disposed above the fourth portion of the second channel region. The second thin film transistor may include: the second channel region, the second conductive region, and the third conductive region of the first active pattern; the second inclined surface portion and the second horizontal surface portion of the first gate insulating layer; and a second gate electrode disposed above the second inclined surface portion and the second horizontal surface portion of the first gate insulating layer and overlapping the second channel region.

[0226] According to an embodiment, a portion of the first conductive region may be self-aligned with the first inclined portion of the first gate insulating layer. A portion of the second conductive region may be self-aligned with the first horizontal portion of the first gate insulating layer. Another portion of the second conductive region may be self-aligned with the second horizontal portion of the first gate insulating layer. A portion of the third conductive region may be self-aligned with the second inclined portion of the first gate insulating layer.

[0227] According to an embodiment, the second conductive region may not overlap with the first gate electrode or the second gate electrode.

[0228] According to an embodiment, the first conductive region may overlap the first slope of the buffer layer, the third conductive region may overlap the second slope of the buffer layer, and the second conductive region may not overlap the first or second slope of the buffer layer.

[0229] According to an embodiment, the first conductive region, the second conductive region, and the third conductive region may be spaced apart from each other in a direction parallel to the top surface of the substrate.

[0230] According to an embodiment, the display device may further include a third thin film transistor disposed above the buffer layer. The third thin film transistor may include: a second active pattern disposed above the buffer layer; a second gate insulating layer disposed above the second active pattern; and a second gate electrode disposed above a portion of the second gate insulating layer.

[0231] According to embodiments, using at least one of the above structures, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein parasitic capacitance can be reduced by minimizing the area where the gate electrode overlaps the conductive region.

[0232] According to an embodiment, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein the breakdown characteristics of the thin film transistor can be improved by minimizing the area where the gate electrode overlaps the conductive region and improving the thickness uniformity of the gate insulating layer.

[0233] According to an embodiment, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein the resolution and performance of the display device can be improved by reducing the size of thin film transistors provided in the display device while improving the characteristics of the thin film transistors.

[0234] According to embodiments, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein the number of process steps and the number of masks can be reduced by simultaneously forming vertical thin film transistors and coplanar thin film transistors, thereby achieving a process optimization effect.

[0235] According to an embodiment, a thin film transistor array substrate and a display device including the thin film transistor array substrate can be provided, wherein, by forming a gate connection electrode connected to the gate electrode, the resistance of the gate electrode can be reduced, the switching speed of the thin film transistor can be improved, and the power loss occurring during the switching process can be reduced, thereby contributing to low power consumption.

[0236] The above description has been presented to enable those skilled in the art to implement and use the technical concepts of the present invention, and has been provided in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. The above description and accompanying drawings provide examples of the technical concepts of the present invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present invention.

Claims

1. A thin film transistor array substrate, comprising: substrate; a buffer layer disposed above the substrate and including an opening region exposing a portion of the substrate and a first inclined surface having an inverted tapered shape and exposed through the opening region; as well as a first thin film transistor, Wherein, the first thin film transistor includes: a first active pattern, the first active pattern comprising: a first channel region, the first channel region comprising a first portion disposed above the first inclined surface of the buffer layer and a second portion disposed above the top surface of the substrate below the first inclined surface of the buffer layer; a first conductive region disposed above the top surface of the buffer layer; and a second conductive region disposed above the top surface of the substrate; a first gate insulating layer including a first inclined portion disposed above a first portion of the first channel region and a first horizontal portion disposed above a second portion of the first channel region; and A first gate electrode is disposed above the first inclined portion and the first horizontal portion of the first gate insulating layer and overlaps the first channel region.

2. The thin film transistor array substrate according to claim 1, wherein: A portion of the first conductive region is self-aligned with a first slope portion of the first gate insulating layer, and A portion of the second conductive region is self-aligned with the first horizontal portion of the first gate insulating layer.

3. The thin film transistor array substrate according to claim 1, wherein: The second conductive region does not overlap with the first gate electrode.

4. The thin film transistor array substrate according to claim 1, wherein: The first conductive region overlaps with the first inclined surface of the buffer layer, and the second conductive region does not overlap with the first inclined surface of the buffer layer.

5. The thin film transistor array substrate according to claim 1, wherein: The first conductive region and the second conductive region are spaced apart from each other in a direction parallel to a top surface of the substrate.

6. The thin film transistor array substrate according to claim 1, wherein: A top portion of the first inclined portion of the first gate insulating layer contacts a side surface of the first conductive region.

7. The thin film transistor array substrate according to claim 6, wherein: The first gate electrode includes an inner surface and an outer surface opposite to the inner surface, the inner surface is in contact with the first inclined portion and the first horizontal portion of the first gate insulating layer, and An outer surface of the first gate electrode is aligned perpendicular to a top portion of the first slope portion of the first gate insulating layer.

8. The thin film transistor array substrate according to claim 6, wherein: The first gate electrode includes an inner surface and an outer surface opposite to the inner surface, the inner surface is in contact with the first inclined portion and the first horizontal portion of the first gate insulating layer, and An outer surface of the first gate electrode protrudes beyond a top portion of the first slope portion of the first gate insulating layer.

9. The thin film transistor array substrate according to claim 6, wherein: The first gate electrode includes an inner surface and an outer surface opposite to the inner surface, the inner surface is in contact with the first inclined portion and the first horizontal portion of the first gate insulating layer, and An outer surface of the first gate electrode has a tapered shape.

10. The thin film transistor array substrate according to claim 1, wherein: The first gate electrode includes an inner surface and an outer surface opposite to the inner surface, the inner surface is in contact with the first inclined portion and the first horizontal portion of the first gate insulating layer, and An outer surface of the first gate electrode has a curvature corresponding to surface shapes of the first inclined portion and the first horizontal portion of the first gate insulating layer.

11. The thin film transistor array substrate according to claim 1, wherein: A portion of the first inclined surface portion of the first gate insulating layer is in direct contact with the first portion of the first channel region, and another portion of the first inclined surface portion of the first gate insulating layer is in direct contact with the first inclined surface of the buffer layer, and A portion of the first horizontal portion of the first gate insulating layer is in direct contact with the second portion of the first channel region, and another portion of the first horizontal portion of the first gate insulating layer is in direct contact with the top surface of the substrate.

12. The thin film transistor array substrate according to claim 11, further comprising a gate connection electrode connected to the first gate electrode, in, The gate connection electrode is disposed over another portion of the first inclined portion of the first gate insulating layer and another portion of the first horizontal portion of the first gate insulating layer.

13. The thin film transistor array substrate according to claim 12, wherein: The gate connection electrode is formed of the same material as that of the first gate electrode.

14. The thin film transistor array substrate according to claim 12, wherein: The gate connecting electrode covers the first gate insulating layer above the first inclined surface of the buffer layer.

15. The thin film transistor array substrate according to claim 1, wherein: The buffer layer further includes a second inclined surface exposed through the opening region, the second inclined surface facing the first inclined surface in the first direction and having an inverted tapered shape. The thin film transistor array substrate further includes a second thin film transistor, which is disposed above a region including the second inclined surface of the buffer layer and shares the second conductive region with the first thin film transistor.

16. The thin film transistor array substrate according to claim 15, wherein: The first active pattern further includes: a second channel region including a third portion disposed above the second inclined surface of the buffer layer and a fourth portion disposed above the top surface of the substrate below the second inclined surface of the buffer layer; and a third conductive region disposed above the top surface of the buffer layer. The first gate insulating layer further includes a second inclined portion disposed above the third portion of the second channel region and a second horizontal portion disposed above the fourth portion of the second channel region, and The second thin film transistor includes: a second channel region, a second conductive region, and a third conductive region of the first active pattern; a second inclined portion and a second horizontal portion of the first gate insulating layer; and A second gate electrode is disposed above the second inclined portion and the second horizontal portion of the first gate insulating layer and overlaps the second channel region.

17. The thin film transistor array substrate according to claim 16, wherein: A portion of the first conductive region is self-aligned with a first inclined portion of the first gate insulating layer, A portion of the second conductive region is self-aligned with a first horizontal portion of the first gate insulating layer, Another portion of the second conductive region is self-aligned with the second horizontal portion of the first gate insulating layer, and A portion of the third conductive region is self-aligned with the second inclined portion of the first gate insulating layer.

18. The thin film transistor array substrate according to claim 16, wherein: The second conductive region does not overlap with the first gate electrode or the second gate electrode.

19. The thin film transistor array substrate according to claim 16, wherein: The first conductive region overlaps with the first inclined surface of the buffer layer, The third conductive region overlaps with the second inclined surface of the buffer layer, and The second conductive region does not overlap with the first inclined surface or the second inclined surface of the buffer layer.

20. The thin film transistor array substrate according to claim 16, wherein: The first conductive region, the second conductive region, and the third conductive region are spaced apart from each other in a direction parallel to a top surface of the substrate.

21. The thin film transistor array substrate according to claim 16, wherein: A portion of the first inclined surface portion of the first gate insulating layer is in direct contact with a first portion of the first channel region, and another portion of the first inclined surface portion of the first gate insulating layer is in direct contact with a first inclined surface of the buffer layer. A portion of the first horizontal portion of the first gate insulating layer is in direct contact with the second portion of the first channel region, and another portion of the first horizontal portion of the first gate insulating layer is in direct contact with the top surface of the substrate, A portion of the second inclined surface portion of the first gate insulating layer is in direct contact with the third portion of the second channel region, and another portion of the second inclined surface portion of the first gate insulating layer is in direct contact with the second inclined surface of the buffer layer, and A portion of the second horizontal portion of the first gate insulating layer is in direct contact with a fourth portion of the second channel region, and another portion of the second horizontal portion of the first gate insulating layer is in direct contact with a top surface of the substrate.

22. The thin film transistor array substrate according to claim 21, wherein: The buffer layer further includes a third inclined surface and a fourth inclined surface exposed through the opening region, the third inclined surface and the fourth inclined surface facing each other in a second direction intersecting the first direction and having an inverted tapered shape, and The first gate insulating layer also includes a third inclined surface portion arranged above the third inclined surface of the buffer layer, a third horizontal portion arranged above the substrate below the third inclined surface portion, a fourth inclined surface portion arranged above the fourth inclined surface of the buffer layer, and a fourth horizontal portion arranged above the substrate below the fourth inclined surface portion.

23. The thin film transistor array substrate according to claim 22, further comprising a gate connection electrode connected to the first gate electrode and the second gate electrode, in, The gate connecting electrode is arranged above another part of the first inclined portion of the first gate insulating layer, another part of the first horizontal portion of the first gate insulating layer, another part of the second inclined portion of the first gate insulating layer, another part of the second horizontal portion of the first gate insulating layer, the third inclined portion of the first gate insulating layer, the third horizontal portion of the first gate insulating layer, the fourth inclined portion of the first gate insulating layer and the fourth horizontal portion of the first gate insulating layer.

24. The thin film transistor array substrate according to claim 23, wherein: The gate connection electrode is formed of the same material as the first gate electrode and the second gate electrode. 25 . The thin film transistor array substrate according to claim 23 , further comprising a gate connection line disposed over the buffer layer and connected to the gate connection electrode.

26. The thin film transistor array substrate according to claim 25, wherein: The first gate insulating layer further includes an extension portion disposed between the buffer layer and the gate connection line.

27. The thin film transistor array substrate according to claim 25, wherein: The gate connection line does not overlap with the first active pattern.

28. A display device comprising: substrate; a circuit element layer disposed above the substrate; as well as a light emitting element disposed above the circuit element layer, Wherein, the circuit element layer includes: a buffer layer disposed over the substrate and including an opening region exposing a portion of the substrate and a first inclined surface having an inverted tapered shape and exposed through the opening region; and a first thin film transistor, Wherein, the first thin film transistor includes: a first active pattern, the first active pattern comprising: a first channel region, the first channel region comprising a first portion disposed above the first inclined surface of the buffer layer and a second portion disposed above the top surface of the substrate below the first inclined surface of the buffer layer; a first conductive region disposed above the top surface of the buffer layer; and a second conductive region disposed above the top surface of the substrate; a first gate insulating layer including a first inclined portion disposed above a first portion of the first channel region and a first horizontal portion disposed above a second portion of the first channel region; and A first gate electrode is disposed above the first inclined portion and the first horizontal portion of the first gate insulating layer and overlaps the first channel region.

29. The display device according to claim 28, wherein A portion of the first conductive region is self-aligned with a first slope portion of the first gate insulating layer, and A portion of the second conductive region is self-aligned with the first horizontal portion of the first gate insulating layer.

30. The display device according to claim 28, wherein The second conductive region does not overlap with the first gate electrode.

31. The display device according to claim 28, wherein The first conductive region overlaps with the first inclined surface of the buffer layer, and the second conductive region does not overlap with the first inclined surface of the buffer layer.

32. The display device according to claim 28, wherein The buffer layer further includes a second inclined surface exposed through the opening region, the second inclined surface facing the first inclined surface in the first direction and having an inverted tapered shape, and The circuit element layer further includes a second thin film transistor, which is disposed above a region including the second inclined surface of the buffer layer and shares the second conductive region with the first thin film transistor.

33. The display device according to claim 32, wherein: The first active pattern further includes: a second channel region, the second channel region including a third portion and a fourth portion, the third portion being disposed above the second inclined surface of the buffer layer, the fourth portion being disposed below the second inclined surface of the buffer layer and above the top surface of the substrate and connected to the second conductive region; and a third conductive region disposed above the top surface of the buffer layer. The first gate insulating layer further includes a second inclined portion disposed above the third portion of the second channel region and a second horizontal portion disposed above the fourth portion of the second channel region, and The second thin film transistor includes: a second channel region, a second conductive region, and a third conductive region of the first active pattern; a second inclined portion and a second horizontal portion of the first gate insulating layer; and A second gate electrode is disposed above the second inclined portion and the second horizontal portion of the first gate insulating layer and overlaps the second channel region.

34. The display device according to claim 33, wherein A portion of the first conductive region is self-aligned with a first inclined portion of the first gate insulating layer. A portion of the second conductive region is self-aligned with a first horizontal portion of the first gate insulating layer, Another portion of the second conductive region is self-aligned with the second horizontal portion of the first gate insulating layer, and A portion of the third conductive region is self-aligned with the second inclined portion of the first gate insulating layer.

35. The display device according to claim 33, wherein: The second conductive region does not overlap with the first gate electrode or the second gate electrode.

36. The display device according to claim 33, wherein: The first conductive region overlaps with the first inclined surface of the buffer layer, The third conductive region overlaps with the second inclined surface of the buffer layer, and The second conductive region does not overlap with the first inclined surface or the second inclined surface of the buffer layer.

37. The display device according to claim 33, wherein: The first conductive region, the second conductive region, and the third conductive region are spaced apart from each other in a direction parallel to a top surface of the substrate.

38. The display device according to claim 33, further comprising a third thin film transistor disposed above the buffer layer, in, The third thin film transistor includes: a second active pattern disposed above the buffer layer; a second gate insulating layer disposed over the second active pattern; and A second gate electrode is disposed over a portion of the second gate insulating layer.

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