External contact defect analysis method, storage medium and terminal

Abstract

The invention discloses an external contact defect analysis method, a storage medium and a terminal. The method comprises the following steps: providing a plurality of chips to be tested; providing at least one test structure, wherein each test structure is provided with a plurality of probes; obtaining a mapping table, wherein the mapping table comprises the position, the electrical parameter and the test threshold range of each probe; comparing the real test value of each probe in each test with the corresponding test threshold range in the mapping table; counting the number of times that the real test value of each probe of each test structure is not in the corresponding test threshold range; when the number of times that the real test value of any probe PinX is not located in the corresponding test threshold range is abnormal, it is judged that the probe of the test structure has the external contact defect, specific parameter abnormity can be efficiently analyzed, and the tedious process of manually pulling and processing data is omitted. And the position of the probe with abnormal external contact can be accurately positioned according to the mapping table, so that the downtime troubleshooting time is effectively shortened, and the test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to an external contact defect analysis method, a storage medium and a terminal. Background Art

[0002] The entire chip manufacturing process includes numerous process steps, such as photolithography, etching, and deposition in the fab, as well as bonding, placement, and encapsulation in the packaging plant. Each process step can lead to manufacturing defects, resulting in changes in the chip's electrical or functional parameters. These defects can only be identified through testing, so wafers manufactured in the fab undergo CP testing to select qualified die for subsequent packaging. Similarly, some qualified die will inevitably be damaged during the packaging process, causing parameter drift. Therefore, after chip packaging, a final test, also known as FT testing, is required before the chip is manufactured into a module.

[0003] However, there are still many problems in the existing technology during the CP / FT test process. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide an external contact defect analysis method, a storage medium and a terminal to reduce downtime troubleshooting time and lower testing costs.

[0005] In order to solve the above problems, the present invention provides an external contact defect analysis method, comprising: providing a wafer to be tested, wherein the wafer to be tested has a plurality of chips to be tested; providing a test board, wherein the test board has at least one test structure, each of the test structures has a plurality of probes, and each of the test structures is used to test one chip to be tested at a time; obtaining a mapping table, wherein the mapping table includes the position of each probe, the electrical parameters corresponding to the test of the probes at different positions, and the test threshold range of each electrical parameter; the test board sequentially tests each chip to be tested in the wafer to be tested, and records the value of each test structure at each test. The true test value of each probe; comparing the true test value of each probe in each test with the corresponding test threshold range in the mapping table; after several test processes, counting the number of times the true test value of each probe in each test structure is not within the corresponding test threshold range; comparing the number of times the true test values of the probes at the same position in each test structure are not within the corresponding test threshold range, when there is an abnormal number of times the true test value of any probe PinX is not within the corresponding test threshold range, it is judged that the probe of the test structure has an external contact defect.

[0006] Optionally, when the number of test structures on the test board is greater than one, the method for determining whether the probe of the test structure has an external contact defect includes: if the number of times the true test value of any probe PinX in any one of the test structures SiteX is not within the corresponding test threshold range is the largest, and the difference between the number of times the true test value of the probe at the same position in each of the remaining test structures is not within the corresponding test threshold range is greater than a second threshold, then it is determined that the probe PinX of the test structure SiteX has an external contact defect.

[0007] Optionally, after determining that the probe of the test structure has an external contact defect, the method further includes: repairing or replacing the probe PinX of the test structure SiteX.

[0008] Optionally, if the actual test value of any probe PinX in any test structure SiteX is not within the corresponding test threshold range, the chip to be tested corresponding to the test is marked to generate a defect map.

[0009] Optionally, when the number of test structures on the test board is 1, the method for determining whether the probe of the test structure has an external contact defect includes: if the number of times the actual test value of any one of the probes PinX in the test structure is not within the corresponding test threshold range is greater than a first threshold, then it is determined that the probe PinX of the test structure has an external contact defect.

[0010] Optionally, after determining that the probe of the test structure has an external contact defect, the method further includes: repairing or replacing the probe PinX of the test structure.

[0011] Optionally, if the actual test value of any one of the probes PinX in the test structure is not within the corresponding test threshold range, the chip to be tested corresponding to the test is marked to generate a defect map.

[0012] Optionally, before testing each of the chips to be tested, the method further includes: setting a priority for each of the electrical parameters; and the failure parameters displayed by the chips to be tested marked in the defect map are the electrical parameters with higher priorities.

[0013] Correspondingly, the technical solution of the present invention further provides a storage medium on which computer instructions are stored, characterized in that when the computer instructions are executed, the steps of the method described in any of the above technical solutions are executed.

[0014] Correspondingly, the technical solution of the present invention also provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and is characterized in that when the processor runs the computer instructions, it executes the steps of the method described in any of the above technical solutions.

[0015] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0016] In the external contact defect analysis method of the present invention, the actual test value of each probe during each test is compared with the corresponding test threshold range in the mapping table. The number of times each probe's actual test value falls outside the corresponding test threshold range after a number of tests is counted for each test structure, effectively analyzing specific parameter anomalies and eliminating the tedious process of manually extracting and processing data. Furthermore, the location of the probe with the external contact anomaly can be accurately located based on the mapping table, effectively reducing downtime troubleshooting, improving production capacity, and eliminating the costly operation of replacing all probes, effectively reducing testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of an external contact defect analysis method according to an embodiment of the present invention;

[0018] Figures 2 to 7 It is a structural schematic diagram of each step of an external contact defect analysis method in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] As described in the background art, there are still many problems in the prior art during CP / FT testing, which will be described in detail below with reference to the accompanying drawings.

[0020] During chip CP / FT testing on a tester, there are typically multiple connections between the chip and the tester, primarily relying on cable interfaces and probe contact to achieve circuit continuity and signal transmission between the tester and the chip. This is especially true during final testing, where probe contact is often used to connect the chip's pads (bond pads / bumps) to the test system. As the number of probe contact pads increases, the probe tip often accumulates some pad metal or insulating material, or wears out, leading to false measurements. If these faults cannot be located and corrected promptly, a large number of qualified products will be classified as defective and scrapped.

[0021] Yield monitoring systems or yield management systems (YMS) typically pull offline data for yield analysis. Yield engineers, drawing on their experience, can roughly pinpoint external causes, such as machine issues, or internal issues, such as process failures, and then provide feedback to relevant departments for resolution. However, for anomalies caused by external contact, it's difficult to pinpoint a specific probe, meaning the exact location of the faulty probe is impossible. Current solutions involve lengthy downtime for troubleshooting or simply replacing all test probes.

[0022] However, the time-consuming solution of troubleshooting downtime seriously affects production capacity, while the cost of directly replacing all the test probes is extremely high (generally, the probes are gold-plated).

[0023] On this basis, the present invention provides a method, storage medium, and terminal for analyzing external contact defects. By comparing the actual test value of each probe during each test with the corresponding test threshold range in the mapping table, and counting the number of times each probe's actual test value falls outside the corresponding test threshold range after several tests of each test structure, the present invention can efficiently analyze specific parameter anomalies, eliminating the tedious process of manually pulling and processing data. Furthermore, the location of the probe with the external contact anomaly can be accurately located based on the mapping table, effectively saving downtime troubleshooting and improving production capacity. It also eliminates the high-cost operation of replacing all the probes, effectively reducing testing costs.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Figure 1 4 is a flow chart of an external contact defect analysis method in an embodiment of the present invention.

[0026] Please refer to Figure 1 , the external contact defect analysis method includes:

[0027] Step S101, providing a wafer to be tested, wherein the wafer to be tested has a plurality of chips to be tested;

[0028] Step S102, providing a test board, wherein the test board has at least one test structure, each of the test structures has a plurality of probes, and each of the test structures is used to test one chip to be tested at a time;

[0029] Step S103, obtaining a mapping table, wherein the mapping table includes the position of each probe, the electrical parameters tested corresponding to the probes at different positions, and the test threshold range of each electrical parameter;

[0030] Step S104, the test board sequentially tests each chip to be tested in the wafer to be tested, and records the actual test value of each probe of each test structure during each test;

[0031] Step S105 , comparing the actual test value of each probe during each test with the corresponding test threshold range in the mapping table;

[0032] Step S106, after several times of the test processing, counting the number of times the true test value of each probe of each test structure is not within the corresponding test threshold range;

[0033] Step S107, comparing the number of times the true test value of the probe at the same position in each of the test structures is not within the corresponding test threshold range. When there is an abnormal number of times the true test value of any probe PinX is not within the corresponding test threshold range, it is determined that the probe of the test structure has an external contact defect.

[0034] Each step of the external contact defect analysis method will be described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 7 It is a structural schematic diagram of each step of an external contact defect analysis method in an embodiment of the present invention.

[0036] Please refer to Figure 2 , a wafer to be tested 100 is provided, wherein the wafer to be tested 100 has a plurality of chips to be tested 101 .

[0037] It should be noted that, in this embodiment, the plurality of chips to be tested 101 may be in a state after the wafer to be tested 100 is divided, or may be in a state before the wafer to be tested 100 is divided.

[0038] For example, when performing CP (Chip Probing) testing on several of the chips to be tested 101, several of the chips to be tested 101 are in a state where the wafer to be tested 100 has not been split; and when performing FT (Final Test) testing on several of the chips to be tested 101, several of the chips to be tested 101 may be in a state where the wafer to be tested 100 has been split, or may be in a state where the wafer to be tested 100 has not been split.

[0039] Please refer to Figure 3A test board 200 is provided, wherein the test board 200 has at least one test structure 201 , each of the test structures 201 has a plurality of probes 202 , and each of the test structures 201 is used to test one chip to be tested 101 at a time.

[0040] In this embodiment, it is taken as an example that the test board 200 has four test structures 201 .

[0041] In other embodiments, the test board may also have only one test structure 201 .

[0042] In this embodiment, the position of each probe 202 (Pin) in each test structure 201 has a corresponding mark.

[0043] Please refer to Figure 4 , obtaining a mapping table 300, wherein the mapping table 300 includes the position of each of the probes 202, the electrical parameters corresponding to the tests of the probes 202 at different positions, and the test threshold range of each of the electrical parameters.

[0044] It should be noted that in this embodiment, the electrical parameters corresponding to the tests of the probes 202 at different positions in the mapping table 300 need to be verified experimentally. Generally, a single probe 202 affects a single electrical parameter, or multiple probes 202 affect the same electrical parameter. The test threshold range of each electrical parameter in the mapping table 300 can be obtained based on the reference range specified in the product specification.

[0045] In this embodiment, the mapping table 300 is obtained through experimental verification, which facilitates timely indexing and searching after the probe 202 is subsequently determined to have contacted an abnormality, avoiding the repetitive work of checking all contact abnormalities each time, lowering the professional knowledge threshold of maintenance personnel, and solidifying it into the mapping table 300 can also avoid the technical difference maintenance costs caused by personnel flow.

[0046] Please refer to Figure 5 The test board 200 sequentially tests each chip 101 in the wafer 100 and records the actual test value of each probe 202 of each test structure 201 during each test.

[0047] It should be noted that in this embodiment, since the number of the test structures 201 in the test board 200 is much smaller than the number of the chips to be tested 101 in the wafer to be tested 100, multiple tests are required to ensure that all the chips to be tested 101 are tested. Since the overall arrangement of the chips to be tested 101 in the wafer to be tested 100 is circular, it is not possible to ensure that all the test structures 201 in the test board 200 are used in each test. In order to ensure that the number of times each test structure 201 in the test board 200 is used remains uniform after all the chips to be tested 101 are tested, it is necessary to plan the test path reasonably.

[0048] Please refer to Figure 6 , the actual test value of each probe 202 during each test is compared with the corresponding test threshold range in the mapping table 300 .

[0049] In this embodiment, the number of the test structures 201 of the test board 200 is greater than one. If the actual test value of any probe 202PinX in any test structure 201SiteX is not within the corresponding test threshold range, the corresponding chip to be tested 101 will be marked to generate a defect map 400.

[0050] In this embodiment, before testing each of the chips to be tested 101 , the process further includes: setting a priority for each of the electrical parameters; and the failure parameters displayed by the chips to be tested 101 marked in the defect map 400 are the electrical parameters with higher priorities.

[0051] For example, in a specific embodiment, the test structure 201 detects that both the electrical parameters DVDD and AVDD of a chip under test 101 fail. When the abnormal parameter of DVDD is defined with a high priority, the defect map 400 will eventually display that the failed telecommunications parameter of the chip under test 101 is DVDD, in order to facilitate the location of the electrical parameter of the chip under test 101 that ultimately fails at that position.

[0052] In other embodiments, when there is one test structure on the test board, if the actual test value of any one of the probes 202PinX in the test structure is not within the corresponding test threshold range, the corresponding chip to be tested will be marked to generate a defect map; accordingly, before testing each chip to be tested, it also includes: setting the priority of each electrical parameter; the failure parameter displayed by the chip to be tested marked in the defect map is the electrical parameter with a higher priority.

[0053] Please refer to Figure 7 After several test processes, the number of times that the true test value of each probe 202 of each test structure 201 is not within the corresponding test threshold range is counted.

[0054] In this embodiment, in order to prevent the remaining failed electrical parameters from being obscured due to the priority definition, and to provide data support for the subsequent precise positioning of the location of the external contact defect, it is necessary to count the number of times that the actual test value of each probe 202 of each test structure 201 in the original data is not within the corresponding test threshold range. For example, if the electrical parameters AVDD and DVDD tested by a chip 101 to be tested both fail, it is necessary to count the number of DVDD and AVDD as 1 each.

[0055] Please continue to refer to Figure 7 , compare the number of times the true test value of the probe 202 at the same position in each test structure 201 is not within the corresponding test threshold range. When the number of times the true test value of any probe 202PinX is not within the corresponding test threshold range is abnormal, it is determined that the probe 202 of the test structure 201 has an external contact defect.

[0056] In this embodiment, by comparing the actual test value of each probe 202 during each test with the corresponding test threshold range in the mapping table 300, and counting the number of times the actual test value of each probe 202 for each test structure 201 is outside the corresponding test threshold range after several tests, specific parameter anomalies can be efficiently analyzed, eliminating the tedious process of manually pulling and processing data. Moreover, the location of the probe 202 with external contact anomaly can be accurately located based on the mapping table 300, effectively saving time for downtime troubleshooting, improving production capacity, and eliminating the high-cost operation of replacing all the probes 202, effectively reducing testing costs.

[0057] In this embodiment, the number of the test structures 201 of the test board 200 is greater than one, and the method for determining whether the probe 202 of the test structure 201 has an external contact defect includes: if the number of times the true test value of any probe 202PinX in any one of the test structures 201SiteX is not within the corresponding test threshold range is the largest, and the difference between the number of times the true test value of the probe 202 at the same position in each of the remaining test structures 201 is not within the corresponding test threshold range is greater than a second threshold, then it is determined that the probe 202PinX of the test structure 201SiteX has an external contact defect.

[0058] Please continue to refer to Figure 7 In a specific embodiment, if the number of times the true test value of the probe 202Pin1 in the test structure 201Site3 is not within the corresponding test threshold range is the largest, and the difference between the number of times the true test value of the probe 202 at the same position in each of the remaining test structures 201 is not within the corresponding test threshold range is greater than a second threshold (e.g., the second threshold is 5), then the probe 202Pin1 in the test structure 201Site3 may have an external contact defect. This is because when a probe 202 in a certain test structure 201 has an external contact defect, when testing the chip to be tested 101, the corresponding probe 202 will basically have a contact problem, thereby causing the true test value of the test to be abnormal. Therefore, the number of times the true test value is not within the corresponding test threshold range will also be the largest, and will also be significantly higher than the number of times the true test value of the probe 202 at the same position in each of the remaining test structures 201 is not within the corresponding test threshold range.

[0059] In this embodiment, the comparison between the actual test values of the probes 202 at the same position in each of the test structures 201 can be presented in the form of a histogram, a broken line graph, etc., for more intuitive display.

[0060] In this embodiment, after determining that the probe 202 of the test structure 201 has an external contact defect, the method further includes: repairing or replacing the probe 202PinX of the test structure 201SiteX; accordingly, if the number of times the true test value of any probe 202PinX in any one of the test structures 201SiteX is not within the corresponding test threshold range is the largest, and the difference between the number of times the true test value of the probe 202 at the same position in each of the remaining test structures 201 is not within the corresponding test threshold range is less than a second threshold, then it is determined that the probe 202 of the test structure 201 does not have an external contact defect. At this time, it is necessary to feedback the problem to the process department to check the problem in the process, or continue testing.

[0061] In other embodiments, when the number of test structures on the test board is one, a method for determining whether the probe 202 of the test structure has an external contact defect includes: if the number of times the true test value of any probe 202PinX in the test structure is not within the corresponding test threshold range is greater than a first threshold, then determining that the probe 202PinX in the test structure has an external contact defect. For example, in a specific embodiment, if the number of times the true test value of probe 202Pin1 in the test structure is not within the corresponding test threshold range is greater than a first threshold (e.g., the first threshold is 10), then determining that the probe 202Pin1 in the test structure has an external contact defect. This is because there is only one test structure on the test board and no comparison is required between different test structures, so only one larger first threshold needs to be set. Correspondingly, after determining that the probe 202 of the test structure has an external contact defect, the method further includes: repairing or replacing the probe 202PinX in the test structure. Correspondingly, if the number of times that the actual test value of any probe 202PinX in the test structure is not within the corresponding test threshold range is less than the first threshold, it is judged that there is no external contact defect in the probe 202 of the test structure. At this time, the problem needs to be fed back to the process department to check the problems in the process or continue the test.

[0062] Correspondingly, an embodiment of the present invention further provides a storage medium on which computer instructions are stored, characterized in that when the computer instructions are executed, the steps of the method described in any of the above embodiments are executed.

[0063] Correspondingly, an embodiment of the present invention also provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and is characterized in that when the processor runs the computer instructions, it executes the steps of the method described in any of the above embodiments.

[0064] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for analyzing external contact defects, characterized in that: include: Providing a wafer to be tested, wherein the wafer to be tested has a plurality of chips to be tested; Providing a test board, wherein the test board has at least one test structure, each of the test structures has a plurality of probes, and each of the test structures is used to test one chip to be tested at a time; Obtaining a mapping table, the mapping table including the position of each probe, the electrical parameters tested corresponding to the probes at different positions, and a test threshold range of each electrical parameter; The test board sequentially tests each chip to be tested in the wafer to be tested, and records the actual test value of each probe of each test structure during each test; Comparing the actual test value of each probe during each test with the corresponding test threshold range in the mapping table; After a number of test processes, counting the number of times the true test value of each probe of each test structure is not within the corresponding test threshold range; Compare the number of times the true test value of the probe at the same position in each of the test structures is not within the corresponding test threshold range. When there is an abnormal number of times the true test value of any probe PinX is not within the corresponding test threshold range, it is determined that the probe of the test structure has an external contact defect.

2. The external contact defect analysis method according to claim 1, wherein: When the number of test structures on the test board is greater than one, the method for determining whether the probe of the test structure has an external contact defect includes: if the number of times the true test value of any probe PinX in any one of the test structures SiteX is not within the corresponding test threshold range is the largest, and the difference between the number of times the true test value of the probe at the same position in each of the remaining test structures is not within the corresponding test threshold range is greater than a second threshold, then it is determined that the probe PinX of the test structure SiteX has an external contact defect.

3. The external contact defect analysis method according to claim 2, wherein: After determining that the probe of the test structure has an external contact defect, the method further includes: repairing or replacing the probe PinX of the test structure SiteX.

4. The external contact defect analysis method according to claim 2, wherein: If the actual test value of any probe PinX in any test structure SiteX is not within the corresponding test threshold range, the chip to be tested corresponding to the test is marked to generate a defect map.

5. The external contact defect analysis method according to claim 1, wherein: When the number of test structures on the test board is 1, the method for determining whether the probe of the test structure has an external contact defect includes: if the number of times the true test value of any one of the probes PinX in the test structure is not within the corresponding test threshold range is greater than a first threshold, then it is determined that the probe PinX of the test structure has an external contact defect.

6. The external contact defect analysis method according to claim 5, wherein: After determining that the probe of the test structure has an external contact defect, the method further includes: repairing or replacing the probe PinX of the test structure.

7. The external contact defect analysis method according to claim 5, wherein: If the actual test value of any one of the probes PinX in the test structure is not within the corresponding test threshold range, the chip to be tested corresponding to the test is marked to generate a defect map.

8. The external contact defect analysis method according to claim 4 or 7, wherein: Before testing each of the chips to be tested, the method further includes: setting a priority for each of the electrical parameters; and the failure parameters displayed by the chips to be tested marked in the defect map are the electrical parameters with higher priorities.

9. A storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed, the steps of the method according to any one of claims 1 to 8 are executed.

10. A terminal comprising a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, characterized in that: When the processor executes the computer instructions, the steps of the method according to any one of claims 1 to 8 are performed.

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