Wafer electromigration test structure and test method

Abstract

The invention discloses a wafer electromigration test structure and test method, and belongs to the technical field of chips. The wafer electromigration test structure comprises N electromigration test circuits and a test power supply, each electromigration test circuit comprises a test wire and a plurality of test electrodes connected with the test wire, and the test wires in each electromigration test structure are the same; the N electromigration test circuits or the N-1 electromigration test circuits are provided with heat dissipation structures thermally coupled with the test lines; the test power supply is configured to provide the same test current density for each test line; wherein each electromigration test circuit has different heat dissipation efficiency; under the condition that the number of the heat dissipation structures is multiple, the heat dissipation structures have different heat dissipation efficiencies. Multiple groups of test circuits can be tested under the same test current density, contributions of two acceleration factors of temperature and current density to the electromigration failure life of the test structure are accurately distinguished, no extra temperature gradient is introduced to the test structure, and the test result is reliable.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a wafer electromigration test structure and test method. Background Art

[0002] Common electromigration test methods include packaging test method and wafer-level isothermal test method. Although the packaging test method has high precision, it requires metal-ceramic packaging of the device under test, which is costly and has a long cycle. The traditional wafer-level isothermal electromigration test method applies a large current to the metal wire and uses Joule heat to heat the metal wire, causing the metal wire to fail prematurely. The wafer-level isothermal electromigration test method does not require chip cutting and packaging, and the acceleration current is large, so the test efficiency is high, but the defects are also obvious. Since the ambient temperature is constant during the test, the metal wire is heated by the test current. Therefore, it cannot accurately distinguish the contribution of the two acceleration factors, temperature and current density, to the electromigration failure life, and cannot accurately solve the Black equation, the empirical formula for electromigration failure life.

[0003] To improve this problem, a circuit is usually embedded in the substrate to assist in heating to control the temperature of the test circuit during electromigration testing. However, this complicates the test circuit and reduces the accuracy of the test results. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a wafer electromigration test structure and test method. By superimposing a heat dissipation array on the electromigration test circuit, the contribution of two acceleration factors, temperature and current density, to the electromigration failure lifetime can be tested without introducing additional temperature gradients.

[0005] In a first aspect, the present application provides a wafer electromigration test structure, which includes:

[0006] N electromigration test circuits, where the electromigration test circuits include test lines and test electrodes connected to the test lines, and the test lines in each electromigration test structure are identical; N at least partially electromigration test circuits or N-1 electromigration test circuits are provided with a heat dissipation structure, where the heat dissipation structure is thermally coupled to the test lines, where N is an integer greater than or equal to 2;

[0007] a test power supply connected to the test lines in each electromigration test circuit and configured to provide the same test current density to each test line;

[0008] Wherein, each electromigration test circuit has a different heat dissipation efficiency; in the case where there are multiple heat dissipation structures, each heat dissipation structure has a different heat dissipation efficiency.

[0009] According to one embodiment of the present application, the heat dissipation structure includes a first structure, and the first structure includes:

[0010] The insulating thermal conductive array is laid on the side of the test line. The portion of the insulating thermal conductive array located on the same side of the test line is continuous or in a discontinuous fin shape.

[0011] According to one embodiment of the present application, the heat dissipation structure includes a second structure, and the second structure includes:

[0012] Insulated thermal conductive array,

[0013] A plurality of heat-conducting columns, wherein the first ends of the heat-conducting columns are connected to the insulating heat-conducting array, and the second ends of the heat-conducting columns are connected to the top metal layer of the wafer.

[0014] According to an embodiment of the present application, the plurality of heat dissipation structures are different from each other in at least one of material, size, and position.

[0015] In a second aspect, the present application provides a testing method, which is applied to the aforementioned wafer electromigration test structure, and the testing method includes:

[0016] Providing multiple test groups, each test group including at least one electromigration test circuit, each electromigration test circuit in the same test group having the same heat dissipation efficiency, and at least some of the test groups having different heat dissipation efficiencies;

[0017] Continuously applying a constant current of the same amplitude to multiple test groups in the first test set to obtain a test line temperature and a failure time corresponding to each test group, wherein the multiple test groups in the first test set have different heat dissipation efficiencies;

[0018] The temperature acceleration factor corresponding to the electromigration failure life empirical formula of the electromigration test circuit is determined according to the test line temperature corresponding to each test group and each failure time.

[0019] According to one embodiment of the present application, the process of obtaining the expiration time corresponding to each test group includes:

[0020] When a constant current is continuously applied to each test group and each electromigration test circuit in each test group has a relatively stable voltage value, timing is started;

[0021] When the variation range of the relatively stable voltage value exceeds the reference value, the timing is stopped to obtain the failure time corresponding to each test group.

[0022] According to one embodiment of the present application, when the variation range of the relatively stable voltage value exceeds the reference value, the timing is stopped to obtain the failure time corresponding to each test group, including:

[0023] When the variation of the relatively stable voltage value exceeds the reference value, the timing is stopped to obtain the failure time corresponding to each electromigration test circuit;

[0024] The log-normal distribution mean of each failure time data set in the same test group is used as the failure time corresponding to each test group.

[0025] According to one embodiment of the present application, the process of obtaining the test line temperature corresponding to each test group includes:

[0026] Determine the test line resistance corresponding to each test group based on the relatively stable voltage value and constant current;

[0027] The test line temperature corresponding to the test line resistance is determined based on the reference resistance temperature coefficient of the electromigration test line in each test group.

[0028] According to one embodiment of the present application, before continuously applying a constant current of the same amplitude to multiple test groups in the first test set and obtaining the test line temperature and failure time corresponding to each test group, the method further includes:

[0029] Place each test group at different test ambient temperatures to perform resistance tests and obtain the test line resistance;

[0030] A linear fit is performed based on different test environment temperatures and the resistance of each test line to obtain the reference resistance temperature coefficient corresponding to each test group.

[0031] According to one embodiment of the present application, after providing multiple test groups, the method further includes:

[0032] continuously applying constant currents of different amplitudes to multiple test groups in the second test set to obtain a failure time corresponding to each test group, wherein the multiple test groups in the second test set have the same heat dissipation efficiency;

[0033] The current acceleration factor corresponding to the electromigration failure life empirical formula of the electromigration test circuit is determined according to the constant current corresponding to each test group and each failure time.

[0034] According to the wafer electromigration test structure and test method of the present application, a heat dissipation array is superimposed on the electromigration test circuit. When a large current density is applied to the test circuit, the actual temperature of the test circuit stabilizes at different levels due to different heat dissipation efficiencies. In this way, multiple groups of test circuits can be tested under the same test current density, and the contributions of the two acceleration factors, temperature and current density, to the electromigration failure life of the test structure can be accurately distinguished. No additional temperature gradient is introduced on the test structure, and the test results are reliable.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 This is one of the structural schematic diagrams of the electromigration test circuit provided in the embodiments of the present application;

[0038] Figure 2 This is the second structural diagram of the electromigration test circuit provided in the embodiment of the present application;

[0039] Figure 3 This is the third structural diagram of the electromigration test circuit provided in the embodiment of the present application;

[0040] Figure 4 This is one of the flow charts of the testing method provided in the embodiment of the present application;

[0041] Figure 5 This is the second flow chart of the testing method provided in the embodiment of the present application.

[0042] Reference numerals:

[0043] Test line M, heat dissipation structure 10, insulating heat conductive array 11, heat conductive column 12, first and second loading electrodes F1-F2, first and second sensing electrodes S1-S2. DETAILED DESCRIPTION

[0044] Embodiments of the present application are described in detail below, with examples of the embodiments illustrated in the accompanying drawings. In the accompanying drawings, the sizes of layers, regions, and components, as well as their relative sizes, may be exaggerated for clarity. Throughout, the same or similar reference numerals represent the same or similar components or components having the same or similar functions. The embodiments described below with reference to the accompanying drawings are illustrative and intended only to explain the present application, and are not to be construed as limiting the present application.

[0045] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that while the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Thus, without departing from the teachings of the present disclosure, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Furthermore, when a second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present disclosure.

[0046] Throughout this specification, terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0047] In the related art, in order to distinguish the contributions of temperature and current density, two acceleration factors, to electromigration failure lifetime in wafer-level isothermal electromigration testing, a circuit embedded in the substrate to assist in heating is often used to control the temperature of the test circuit during electromigration testing. However, this method complicates the test circuit. Furthermore, due to the poor thermal conductivity of the substrate silicon material and the close proximity of the embedded heater to the test metal lines (both within the silicon wafer), large temperature gradients can easily form within the test structure, causing premature failure in high-temperature areas and thus affecting the reliability of the test results.

[0048] The present application proposes a wafer electromigration test structure and test method. By superimposing a heat dissipation array on a conventional wafer-level isothermal electromigration test circuit, the thermal resistance coefficient of the test circuit is changed. When a large current density is applied to the test circuit, the actual temperature of the test metal wire is stabilized at different levels due to the different materials and positions of the heat dissipation array. The actual temperature of the metal wire can be accurately solved by the resistance temperature coefficient of the metal wire. Under the same test current density, by solving the actual test temperature of several groups of electromigration test structures with different heat dissipation arrays and statistics on the failure life, the electromigration temperature acceleration coefficient of the structure to be tested is solved, and the contribution of the two acceleration factors, temperature and current density, to the electromigration failure life of the test structure is accurately distinguished. The electromigration test method has a simple test circuit, does not introduce additional temperature gradients on the test structure, and has reliable test results.

[0049] Reference Figure 1 、 Figure 2 and Figure 3 , respectively show the structure of an electromigration test circuit, an embodiment of the present application provides a wafer electromigration test structure. Figures 1 to 3 The wafer electromigration test structure provided in this application is described.

[0050] In this embodiment, the wafer electromigration test structure includes N electromigration test circuits, the electromigration test circuit includes a test line M and multiple test electrodes and a test power supply (not shown in the figure) connected to the test line, and the test line M in each electromigration test structure is the same; N electromigration test circuits or N-1 electromigration test circuits are provided with a heat dissipation structure 10, the heat dissipation structure 10 is thermally coupled with the test line M, and N is an integer greater than or equal to 2; the test power supply is connected to the test line M in each electromigration test circuit, and is configured to provide the same test current density to each test line M; wherein, each electromigration test circuit has a different heat dissipation efficiency; when the number of heat dissipation structures 10 is multiple, each heat dissipation structure 10 has a different heat dissipation efficiency.

[0051] The electromigration test circuit is formed on the wafer; for example, it can be formed in the scribe line area of the wafer, without affecting the layout of the chips on the wafer. One electromigration test circuit can be formed on a wafer, or multiple electromigration test circuits can be formed on the wafer. When multiple electromigration test circuits are formed on a wafer, each electromigration test circuit can be provided with a different heat dissipation structure 10, or no heat dissipation structure 10 can be provided.

[0052] As an example, the test electrodes may include a first loading electrode F1 , a second loading electrode F2 , a first sensing electrode S1 , and a second sensing electrode S2 .

[0053] The first loading electrode F1 and the second loading electrode F2 are used to apply a voltage or current to the test line M. For example, the power output node of the test power supply can be connected to the first loading electrode F1, and the second loading electrode F2 can be connected to the ground node. Of course, the reverse is also possible. The first sensing electrode S1 and the second sensing electrode S2 are used to detect voltage or current. For example, the first sensing electrode S1 and the second sensing electrode S2 are connected to the two detection ports of a voltmeter or ammeter.

[0054] The test lines M and test nodes are made of the same metal material, such as copper, aluminum, or silver. The electromigration test circuits are made of the same material as the metal lines inside the chips on the wafer to ensure the validity of the test results.

[0055] The heat dissipation structure 10 is used to dissipate heat from the test lines M. Its heat dissipation efficiency is determined by its specific structure, and different heat dissipation structures 10 have different heat dissipation efficiencies. N electromigration test lines or N-1 electromigration test lines can be equipped with different heat dissipation structures 10, resulting in different heat dissipation efficiencies for each electromigration test line. This allows each test line M to have a different temperature under the same applied current, without causing premature failure of the test line M.

[0056] like Figure 2 As shown, in some embodiments, the heat dissipation structure 10 includes a first structure, which includes an insulating thermal conductive array 11, which is laid on the side of the test line M. The portion of the insulating thermal conductive array 11 located on the same side of the test line M is continuous or in the shape of discontinuous fins.

[0057] The insulating thermal conductive array 11 can be made of insulating thermal conductive materials such as SiN (silicon nitride), SiC (silicon carbide), AlN (aluminum nitride), or GaN (gallium nitride). The insulating thermal conductive array 11 is laid flat on both sides of the test line M, and the test line M transfers heat to the insulating thermal conductive array 11 to reduce the temperature of the test line M. The insulating thermal conductive array 11 can also be in the form of continuous fins to improve the heat dissipation efficiency of the insulating thermal conductive array 11 itself, thereby improving the heat dissipation effect on the test line M.

[0058] In other examples, the first structure can form heat dissipation structures 10 with different heat dissipation efficiencies by adjusting the material, size, and position of the insulating heat-conducting array 11. The size can refer to the coverage area of the insulating heat-conducting array 11, and the position can refer to the arrangement orientation or relative distance of the insulating heat-conducting array 11 relative to the test line M.

[0059] like Figure 3 As shown, in some embodiments, the heat dissipation structure 10 includes a second structure, which includes an insulating heat-conducting array 11 and a plurality of heat-conducting columns 12, wherein the first ends of the heat-conducting columns 12 are connected to the insulating heat-conducting array 11, and the second ends of the heat-conducting columns are connected to the top metal of the wafer.

[0060] The heat dissipation structure 10 in this embodiment is based on the first structure and has a heat conducting column 12. The heat conducting column 12 can transfer the heat dissipation structure 10 to the top metal layer. The material of the heat conducting column 12 can be W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), or Cr (chromium).

[0061] Therefore, the heat dissipation structure 10 with the second structure has a higher heat dissipation effect than the heat dissipation structure 10 with the first structure, accelerates the heat conduction efficiency, and further reduces the temperature of the test line M. When the same current is applied, the temperature of the test line M thermally coupled with the second structure will be lower than the temperature of the test line M thermally coupled with the first structure.

[0062] In other examples, the second structure can also be formed into heat dissipation structures 10 with different heat dissipation efficiencies by adjusting the materials, sizes, and positions of the insulating heat-conducting array 11 and the heat-conducting pillars 12. The adjustment of the insulating heat-conducting array 11 can refer to the above, the size of the heat-conducting pillars 12 can refer to the size of their cross-sections, and the position of the heat-conducting pillars 12 can refer to their positions relative to the insulating heat-conducting array 11.

[0063] As an example, the multiple electromigration test circuits may include a test structure A, a test structure B, and a test structure C. The test structure A may be configured as follows: Figure 1 The electromigration test circuit shown in FIG. 1 does not have a heat dissipation structure 10; the test structure B may be configured as follows: Figure 2 The electromigration test circuit shown in FIG. 1 is provided with a heat dissipation structure 10 adopting a first structure; the test structure C can adopt a heat dissipation structure 10 adopting a first structure; Figure 3 The electromigration test circuit shown is provided with a heat dissipation structure 10 of the second structure. When the same current is applied to the three test structures, the test line temperature of test structure A is higher than the test line temperature of test structure B, and the test line temperature of test structure B is higher than the test line temperature of test structure C.

[0064] Reference Figure 4 , Figure 4 A test method flow is shown. An embodiment of the present application further proposes a test method. In this embodiment, the test method is applied to the aforementioned wafer electromigration test structure. The test method includes steps 10, 20, and 30.

[0065] Step 10: providing a plurality of test groups, each test group including at least one electromigration test circuit, wherein each electromigration test circuit in the same test group has the same heat dissipation efficiency, and at least some of the test groups have different heat dissipation efficiencies;

[0066] Step 20: continuously applying a constant current of the same amplitude to the multiple test groups in the first test set to obtain a test line temperature and failure time corresponding to each test group, wherein the multiple test groups in the first test set have different heat dissipation efficiencies;

[0067] Step 30: Determine a temperature acceleration factor corresponding to an empirical formula for electromigration failure life of the electromigration test circuit according to the test line temperature and failure time corresponding to each test group.

[0068] It is understandable that to improve test accuracy, a larger number of samples are required for each test structure. For example, multiple electromigration test circuits without heat dissipation structures 10 can be considered a test group; or multiple electromigration test circuits with the same heat dissipation structure 10 can be considered a test group. Different test groups have different heat dissipation structures 10, resulting in different heat dissipation efficiencies. The number of test structures within a test group can be 30, 50, etc., and this embodiment does not impose any limit on the number.

[0069] To facilitate illustration of the testing method of this embodiment, the following description uses as an example a first test set that may include three test groups, with test group A having test structure A, test group B having test structure B, and test group C having test structure C. The specific descriptions of the three test structures can refer to the above descriptions. Of course, the number of test groups may be other, and the test structures used may also be other types.

[0070] The test line temperature refers to the temperature of the test line M when the test current is applied. Since the test structure B and the test structure C are provided with a heat dissipation structure 10, the test line temperature TA corresponding to the test structure A is greater than the test line temperature TB corresponding to the test structure B, and the test line temperature TB corresponding to the test structure B is greater than the test line temperature TC corresponding to the test structure C.

[0071] Time-to-failure (TTFA) refers to the time that test lead M maintains normal resistance under the applied test current. When the same current is applied to test lead M, the voltage before and after failure varies significantly. The time-to-failure for test structure A is expressed as TTFA, the time-to-failure for test structure B as TTFB, and the time-to-failure for test structure C as TTFC.

[0072] Linear fitting is performed with TA, TB and TC as independent variables, TTFA, TTFB and TTFC as dependent variables, and the slope of the straight line is used as the temperature acceleration factor corresponding to the empirical formula of electromigration failure life.

[0073] In some embodiments, the process of obtaining the failure time corresponding to each test group includes: starting timing when a constant current is continuously applied to each test group and each electromigration test circuit in each test group has a relatively stable voltage value; when the change amplitude of the relatively stable voltage value exceeds a reference value, ending timing to obtain the failure time corresponding to each test group.

[0074] In this embodiment, a voltmeter can be connected to the sensing node of the electromigration test circuit. When the voltmeter reading is stable, it indicates that the electromigration test circuit has a relatively stable voltage value. At this point, a timer is started until the voltmeter reading increases and exceeds a reference value. The timer is the failure time. The reference value can be 10% or 20%, etc., and this embodiment is not limited to this.

[0075] In some embodiments, when the change amplitude of the relatively stable voltage value exceeds the reference value, the timing is stopped to obtain the failure time corresponding to each test group, including: when the change amplitude of the relatively stable voltage value exceeds the reference value, the timing is stopped to obtain the failure time corresponding to each electromigration test circuit; the log-normal distribution average value of each failure time data set in the same test group is used as the failure time corresponding to each test group.

[0076] In this embodiment, each test group contains multiple test structures, and the corresponding failure time for each test structure is generally different. For example, a test group may include 30 test structures A. The failure times within this test group can be expressed as TTFA-1 to TTFA-30. Thus, by taking the lognormal distribution average of the 30 data points, the failure time TTFA corresponding to this test group is obtained.

[0077] In some embodiments, the process of obtaining the test line temperature corresponding to each test group includes: determining the test line resistance corresponding to each test group based on a relatively stable voltage value and a constant current; and determining the test line temperature corresponding to the test line resistance based on a reference resistance temperature coefficient of the electromigration test circuit in each test group.

[0078] Test lead resistance R = V / I, where V is the relatively stable voltage and I is the constant current. The reference resistance temperature coefficient (RTC) represents the conversion coefficient between the resistance of the test lead M and its temperature, and can be determined through testing. Multiplying the test lead resistance R by the RTC yields the test lead temperature.

[0079] In some embodiments, before continuously applying a constant current of the same amplitude to multiple test groups in the first test set to obtain the test line temperature and failure time corresponding to each test group, it also includes: placing each test group at a different test environment temperature to perform a resistance test to obtain the test line resistance; performing linear fitting based on the different test environment temperatures and the resistance of each test line to obtain the reference resistance temperature coefficient corresponding to each test group.

[0080] This embodiment measures the resistance of a test structure at different temperatures to obtain a reference resistance temperature coefficient. For example, the test structure can be placed at temperatures T1, T2, and T3. By connecting a test line M to a power source, the resistance is calculated by determining the voltage and current on the test line M. This yields resistance R1 for temperature T1, resistance R2 for temperature T2, and resistance R3 for temperature T3. The data is then fitted, and the reference resistance temperature coefficient can be determined based on the slope of the fitted line.

[0081] Reference Figure 5 , Figure 5 FIG. 4 is a flow chart of a testing method. In some embodiments, after providing a plurality of test groups, steps 40 and 50 are further included.

[0082] Step 40: Continuously apply constant currents of different amplitudes to the multiple test groups in the second test set to obtain a failure time corresponding to each test group, and the multiple test groups in the second test set have the same heat dissipation efficiency;

[0083] Step 50: Determine a current acceleration factor corresponding to an empirical formula for electromigration failure life of the electromigration test circuit according to the constant current and failure time corresponding to each test group.

[0084] In this embodiment, by applying different test currents to the same test structure to test the failure time, a current acceleration factor can be fitted, thereby combining the current acceleration factor and the temperature acceleration factor to solve the empirical formula for electromigration failure life.

[0085] As an example, the second test set may include three test groups A1, A2, and A3, each of which has a test structure A. That is, under the same test current, the temperature of each test line M in the test groups A1, A2, and A3 is the same. During the test, a constant current I1 is applied to the test group A1, and the failure time TTFA1 is obtained by test; a constant current I2 is applied to the test group A2, and the failure time TTFA2 is obtained by test; a constant current I3 is applied to the test group A3, and the failure time TTFA3 is obtained by test. Linear fitting is performed with I1, I2, and I3 as independent variables and TTFA1, TTFA2, and TTFA3 as dependent variables, and the slope of the straight line is used as the current acceleration factor corresponding to the empirical formula for electromigration failure life.

[0086] One embodiment of the present application also proposes a test process that combines the technical solutions in the above embodiments to improve test efficiency and test accuracy. The test structures A, B, and C involved in this embodiment can be specifically referred to above. The test process is as follows:

[0087] Test step a: Place the wafer-level electromigration sample to be tested on a three-temperature probe station. Measure the resistance of test structures A, B, and C by setting different probe station temperatures, and obtain the resistance temperature coefficient by fitting. This step may include the following stages:

[0088] Stage 1: Set the probe station temperature to T1 (e.g., -25°C). Connect the voltage source to port F1 of test structure A and ground to port F2. Measure the loop current I1. Connect a voltmeter to ports S1 and S2, recording the voltage reading as V1. Sweep the voltage at port F1 from 0V to 0.1V, ensuring that I1 does not exceed 0.1mA. If this exceeds 0.1mA, reduce the voltage sweep range at port F1. Calculate the metal wire resistance R1 = V1 / I1. Take the average value of R1 during the stable period and record it as the resistance MR1 of test structure A at temperature T1.

[0089] Phase 2: Set the probe station temperature to T2 (e.g., 25°C). Connect the voltage source to port F1 of test structure A and ground port F2. Measure the loop current, I2, by connecting a voltmeter to ports S1 and S2, recording the voltage reading as V2. Sweep the voltage at port F1 from 0V to 0.1V, ensuring that I2 does not exceed 0.1mA. If this exceeds the value, reduce the voltage sweep range at port F1. The metal wire resistance, R2, then equals V2 / I2. The average value of R2 during the stable period is recorded as the resistance, MR2, of test structure A at temperature T2.

[0090] The third stage: Set the probe station temperature to T3 (for example, 75°C), connect the F1 port of the test structure A to the voltage source, and the F2 port to the ground, and measure the loop current I3 at the same time. Connect a voltmeter to the S1 and S2 ports, record the voltage reading as V3, and scan the F1 port voltage from 0V to 0.1V, while making I3 not exceed 0.1mA. If it exceeds, reduce the F1 port scanning voltage range, then the metal wire resistance R3 = V3 / I3, and take the average value of R3 in the stable section and record it as the resistance MR3 of the test structure A at the temperature T3.

[0091] Stage 4: Perform a linear fit using the three temperatures T1, T2, and T3 as independent variables and the measured MR1, MR2, and MR3 as dependent variables. The slope of the line is recorded as the temperature coefficient of resistance (TCR_A) of test structure A. Repeat the above process for test structures B and C, respectively, to determine their temperature coefficients of resistance (TCR_B) and TCR_C.

[0092] Test step b: Prepare 30 test samples of test structure A. Apply a constant current Istress1 (e.g., 10 mA) to terminal F1, ground terminal F2, and connect a voltmeter to terminals S1 and S2. Start timing when the voltmeter reading stabilizes, and read the voltage display value Vstress_A1. The resistance value of test structure A under Istress1 is Rstress_A1 = Vstress_A1 / Istress1. Substitute the TCR_A measured in the previous step to calculate the metal wire temperature Tstress_A1 under test current Istress1. Continue applying constant current Istress1 until the voltmeter reading increases by more than 10%, and read the failure time A1-TTF-1. Repeat the above test on 30 samples, record a set of failure times A1-TTF-1 to A1-TTF-30 for test structure A, and calculate the lognormal distribution mean value A1-TTF-t50 of this set of data.

[0093] Test step c: Prepare 30 test samples of test structure A. Apply a constant current Istress2 (e.g., 15 mA) to terminal F1. Connect terminal F2 to ground, and connect terminals S1 and S2 to a voltmeter. When the voltmeter reading stabilizes, start timing and read the voltmeter reading Vstress_A2. The resistance of test structure A at Istress2 is Rstress_A2 = Vstress_A2 / Istress2. Substitute the TCR_A measured in the previous step to calculate the metal wire temperature Tstress_A2 at test current Istress2. Continue applying constant current Istress2 until the voltmeter reading increases by more than 10%. Read the failure time A2-TTF-1. Repeat the above test on 30 samples, record a set of failure times A2-TTF-1 to A2-TTF-30 for test structure A, and calculate the lognormal distribution mean A2-TTF-t50 of this data set.

[0094] Test step d: Prepare 30 test samples of test structure A. Apply a constant current Istress3 (e.g., 20 mA) to terminal F1, ground terminal F2, and connect a voltmeter to terminals S1 and S2. When the voltmeter reading stabilizes, start timing and read the voltmeter reading Vstress_A3. The resistance value of test structure A under Istress3 is Rstress_A3 = Vstress_A3 / Istress3. Substitute the TCR_A measured in the previous step to calculate the metal wire temperature Tstress_A3 under the test current Istress3. Continue applying the constant current Istress3 until the voltmeter reading increases by more than 10%, and read the failure time A3-TTF-1. Repeat the above test on 30 samples, record a set of failure times A3-TTF-1 to A3-TTF-30 for test structure A, and calculate the log-normal distribution mean value A3-TTF-t50 of this set of data.

[0095] Test step e: Prepare 30 test samples of test structure B, and apply a constant current Istress1 (e.g., 10 mA) to the F1 port. Connect the F2 terminal to the ground, and connect the S1 and S2 terminals to a voltmeter. When the voltmeter reading stabilizes, start timing and read the voltage display value Vstress_B1. The resistance value of the test structure B under Istress1 is Rstress_B1 = Vstress_B1 / Istress1. Substitute the TCR_B measured in the previous step to calculate the metal wire temperature Tstress_B1 under the test current Istress1. Continue to apply the constant current Istress1 until the voltmeter reading increases by more than 10%, and read the failure time B1-TTF-1. Repeat the above test on 30 samples, record a group of failure lives B1-TTF-1 to B1-TTF-30 of the test structure B, and calculate the log-normal distribution mean value B1-TTF-t50 of this group of data.

[0096] Test step f: Prepare 30 test samples of test structure C. Apply a constant current Istress1 (e.g., 10 mA) to terminal F1. Connect terminal F2 to ground and connect terminals S1 and S2 to a voltmeter. When the voltmeter reading stabilizes, start timing and read the voltmeter reading Vstress_C1. The resistance value of test structure C at Istress1 is Rstress_C1 = Vstress_C1 / Istress1. Substitute the TCR_C measured in the previous step to calculate the metal wire temperature Tstress_C1 at test current Istress1. Continue applying constant current Istress1 until the voltmeter reading increases by more than 10%. Read the failure time C1-TTF-1. Repeat the above test on 30 samples, record a set of failure times C1-TTF-1 to C1-TTF-30 for test structure C, and calculate the lognormal distribution mean C1-TTF-t50 of this data set.

[0097] Test step g: Use Istress1, Istress2 and Istress3 as independent variables and the logarithmic values of A1-TTF-t50, A2-TTF-t50 and A3-TTF-t50 as dependent variables for linear fitting. The slope of the straight line is the current acceleration factor in the Black equation, an empirical formula for electromigration failure life.

[0098] Test step f: Perform a linear fit using Tstress_A1, Tstress_B1, and Tstress_C1 as independent variables and the logarithmic values of A1-TTF-t50, B1-TTF-t50, and C1-TTF-t50 as dependent variables. This is the temperature acceleration factor in the Black equation, an empirical formula for electromigration failure life.

[0099] In this document, the terms "comprises", "includes" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0100] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A wafer electromigration test structure, characterized in that: The wafer electromigration test structure includes: N electromigration test circuits, each electromigration test circuit comprising a test line and a test electrode connected to the test line, the test lines in each electromigration test structure being identical; N electromigration test circuits or N-1 electromigration test circuits being provided with a heat dissipation structure, the heat dissipation structure being thermally coupled to the test line, where N is an integer greater than or equal to 2; a test power supply connected to the test lines in each of the electromigration test circuits and configured to provide the same test current density to each of the test lines; Wherein, each of the electromigration test circuits has a different heat dissipation efficiency; when there are multiple heat dissipation structures, each of the heat dissipation structures has a different heat dissipation efficiency.

2. The wafer electromigration test structure according to claim 1, wherein: The heat dissipation structure includes a first structure, and the first structure includes: The insulating heat-conducting array is laid on the side of the test line. The portion of the insulating heat-conducting array located on the same side of the test line is continuous or discontinuous fin-shaped.

3. The wafer electromigration test structure according to claim 2, wherein: The heat dissipation structure includes a second structure, and the second structure includes: The insulating thermal conductive array, A plurality of heat-conducting pillars are provided, wherein a first end of each heat-conducting pillar is connected to the insulating heat-conducting array, and a second end of each heat-conducting pillar is connected to the top metal layer of the wafer.

4. The wafer electromigration test structure according to any one of claims 1 to 3, characterized in that: The plurality of heat dissipation structures are different from each other in at least one of material, size and position.

5. A testing method, characterized in that: Applied to the wafer electromigration test structure according to any one of claims 1 to 4, the test method comprises: Providing a plurality of test groups, each test group including at least one electromigration test circuit, each electromigration test circuit in the same test group having the same heat dissipation efficiency, and at least some of the test groups having different heat dissipation efficiencies; continuously applying a constant current of the same amplitude to the plurality of test groups in the first test set to obtain a test line temperature and a failure time corresponding to each test group, wherein the plurality of test groups in the first test set have different heat dissipation efficiencies; A temperature acceleration factor corresponding to an empirical formula for electromigration failure life of the electromigration test circuit is determined according to the test line temperature corresponding to each test group and each failure time.

6. The testing method according to claim 5, characterized in that: The process of obtaining the expiration time corresponding to each test group includes: When the constant current is continuously applied to each test group and each electromigration test circuit in each test group has a relatively stable voltage value, starting timing; When the variation range of the relatively stable voltage value exceeds a reference value, the timing is stopped to obtain the failure time corresponding to each of the test groups.

7. The testing method according to claim 6, characterized in that: When the variation of the relatively stable voltage value exceeds a reference value, the timing is stopped to obtain the failure time corresponding to each of the test groups, including: When the variation of the relatively stable voltage value exceeds a reference value, the timing is stopped to obtain the failure time corresponding to each electromigration test circuit; The log-normal distribution average value of each failure time data set in the same test group is used as the failure time corresponding to each test group.

8. The testing method according to claim 6, wherein: The process of obtaining the test line temperature corresponding to each test group includes: determining the test line resistance corresponding to each of the test groups according to the relatively stable voltage value and the constant current; The test line temperature corresponding to the test line resistance is determined based on the reference resistance temperature coefficient of the electromigration test circuit in each of the test groups.

9. The testing method according to claim 8, characterized in that: Before continuously applying a constant current of the same amplitude to the plurality of test groups in the first test set and obtaining the test line temperature and failure time corresponding to each test group, the method further includes: Placing each test group at different test environment temperatures to perform resistance testing to obtain test line resistance; A linear fitting is performed according to the different test environment temperatures and the resistance of each test line to obtain a reference resistance temperature coefficient corresponding to each test group.

10. The testing method according to any one of claims 5 to 9, characterized in that: After providing multiple test groups, the method further includes: continuously applying constant currents of different amplitudes to the plurality of test groups in the second test set to obtain a failure time corresponding to each of the test groups, wherein the plurality of test groups in the second test set have the same heat dissipation efficiency; A current acceleration factor corresponding to an empirical formula for electromigration failure life of the electromigration test circuit is determined according to the constant current corresponding to each test group and each failure time.

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