Chip detection system and method based on ATE and real-installation integration

Abstract

The invention belongs to the technical field of chip testing, and discloses a chip detection system and method based on ATE and on-board integration, electrical connection is established through a chip interface unit and a to-be-tested chip, the chip interface unit comprises an adaptive clamp and a connection circuit board, a precision contact array is arranged in the adaptive clamp, and the precision contact array is connected with the connection circuit board. The connection module is used for realizing reliable connection between a to-be-tested chip and a connection circuit board; the detection analysis unit executes a plurality of different types of detection programs of the to-be-detected chip and collects detection data; and the result processing unit is used for receiving, integrating and processing the detection data acquired by the detection analysis unit and generating a detection report. By means of the mode, the defects of single ATE test and real installation test are overcome, and the test fault coverage rate is increased.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing system and method based on ATE and actual assembly integration. Background Art

[0002] As the core chip for dual-tone multi-frequency (DTMF) encoding and decoding, the MT8880's performance directly impacts the signal resolution accuracy and anti-interference capabilities of communications equipment. Traditional testing methods rely primarily on discrete instruments such as signal generators and spectrum analyzers, manually verifying the chip's DTMF signal generation, receiver sensitivity, and decoding capabilities. This results in long test cycles and incomplete parameter coverage, particularly under complex operating conditions such as dynamic load changes and temperature drift. While existing automated test equipment (ATE) has improved some testing efficiency through scripting, low fault test coverage remains a concern.

[0003] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of the present invention is to provide a chip detection system and method based on ATE and actual assembly integration, aiming to solve the technical problem of low fault test coverage.

[0005] To achieve the above objectives, the present invention provides a chip detection system based on ATE and actual assembly integration, the chip detection system based on ATE and actual assembly integration comprising: a chip interface unit, a detection and analysis unit, and a result processing unit, wherein the chip interface unit is electrically connected to the detection and analysis unit and the result processing unit;

[0006] The chip interface unit is used to establish an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connection circuit board. The adapter fixture is provided with a precision contact array for achieving reliable connection between the chip under test and the connection circuit board.

[0007] The detection and analysis unit is used to execute various types of detection programs on the chip to be tested and collect detection data;

[0008] The result processing unit is used to receive, integrate and process the detection data collected by the detection and analysis unit, and generate a detection report. The result processing unit is constructed using a high-performance computer and equipped with dedicated data processing software to collect and analyze the detection data in real time.

[0009] In some embodiments, the detection and analysis unit includes at least: ATE automatic detection equipment, a spectrum analyzer, a bit error detector, a waveform observer and a modulation signal generator. The ATE automatic detection equipment is used to run the chip test program and control the entire detection process; the spectrum analyzer is used to analyze the spectrum characteristics of the chip; the bit error detector is used to detect the bit error situation of the chip during signal transmission; the waveform observer is used to observe the output waveform of the chip; and the modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

[0010] In some embodiments, the ATE automatic detection equipment is used to perform program startup self-test during the system initialization phase to check the hardware and software status of the ATE equipment to ensure the normal operation of the equipment, and during the chip testability design verification phase, including boundary scan testing and functional verification testing, to verify whether the internal structure and function of the chip are normal.

[0011] In some embodiments, the testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing.

[0012] In some embodiments, the connectivity test is to establish a hardware connection between the chip to be tested and the test equipment through an adapter, purchase a matching test locking seat according to the packaging process of the chip to be tested, design a PCB board, and perform a connectivity test after the locking seat is welded to ensure that the electrical connection between the chip and the test equipment is reliable; the functional test is to use a signal generator to generate a standard DTMF signal, connect it to the input end of the chip to be tested, introduce the DTMF signal, and use an oscilloscope to record the output of the chip to be tested to ensure that each number is correctly decoded; the performance test is to perform a basic performance test at room temperature, record the decoding delay and accuracy, gradually change the operating temperature, and increase it from a first preset temperature to a second preset temperature, and press The decoding test is performed at preset temperature intervals, and the decoding stability and accuracy are recorded. The power supply voltage test is to increase the voltage from a first preset voltage to a second preset voltage according to a preset voltage level through an adjustable power supply, and record the chip's decoding ability of DTMF signals under different voltages, wherein the DTMF signal strength is kept unchanged during the test. The anti-interference test is to apply noise while the signal generator outputs the DTMF signal, record the changes in the decoding of the chip under test, so as to test the stability under different interference levels and record the error rate of the decoded signal. The long-term reliability test is to place the chip under test in a preset environment and test it for a preset time to determine whether the function of the chip under test is normal and whether the decoding ability is affected.

[0013] In addition, to achieve the above-mentioned objectives, the present invention further proposes a chip detection method based on ATE and actual assembly integration. The chip detection method based on ATE and actual assembly integration is applied to the chip detection system based on ATE and actual assembly integration as described above, and the method comprises:

[0014] The chip interface unit establishes an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connection circuit board. The adapter fixture is provided with a precision contact array for achieving reliable connection between the chip under test and the connection circuit board.

[0015] The detection and analysis unit executes various types of detection procedures on the chip to be tested and collects detection data;

[0016] The result processing unit receives, integrates and processes the test data collected by the detection and analysis unit, and generates a test report. The result processing unit is constructed using a high-performance computer and equipped with dedicated data processing software to collect and analyze the test data in real time.

[0017] In some embodiments, the detection and analysis unit includes at least: ATE automatic detection equipment, a spectrum analyzer, a bit error detector, a waveform observer and a modulation signal generator. The ATE automatic detection equipment is used to run the chip test program and control the entire detection process; the spectrum analyzer is used to analyze the spectrum characteristics of the chip; the bit error detector is used to detect the bit error situation of the chip during signal transmission; the waveform observer is used to observe the output waveform of the chip; and the modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

[0018] In some embodiments, the method further comprises:

[0019] During the system initialization phase, ATE automatic detection equipment executes program startup self-test to check the hardware and software status of the ATE equipment to ensure the normal operation of the equipment. During the chip testability design verification phase, boundary scan testing and functional verification testing are performed to verify whether the internal structure and function of the chip are normal.

[0020] In some embodiments, the testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing.

[0021] In some embodiments, the connectivity test is to establish a hardware connection between the chip to be tested and the test equipment through an adapter, purchase a matching test locking seat according to the packaging process of the chip to be tested, design a PCB board, and perform a connectivity test after the locking seat is welded to ensure that the electrical connection between the chip and the test equipment is reliable; the functional test is to use a signal generator to generate a standard DTMF signal, connect it to the input end of the chip to be tested, introduce the DTMF signal, and use an oscilloscope to record the output of the chip to be tested to ensure that each number is correctly decoded; the performance test is to perform a basic performance test at room temperature, record the decoding delay and accuracy, gradually change the operating temperature, and increase it from a first preset temperature to a second preset temperature, and press The decoding test is performed at preset temperature intervals, and the decoding stability and accuracy are recorded. The power supply voltage test is to increase the voltage from a first preset voltage to a second preset voltage according to a preset voltage level through an adjustable power supply, and record the chip's decoding ability of DTMF signals under different voltages, wherein the DTMF signal strength is kept unchanged during the test. The anti-interference test is to apply noise while the signal generator outputs the DTMF signal, record the changes in the decoding of the chip under test, so as to test the stability under different interference levels and record the error rate of the decoded signal. The long-term reliability test is to place the chip under test in a preset environment and test it for a preset time to determine whether the function of the chip under test is normal and whether the decoding ability is affected.

[0022] The present invention establishes an electrical connection with the chip under test through a chip interface unit. The chip interface unit includes an adapter fixture and a connection circuit board. The adapter fixture is internally provided with a precision contact array for reliably connecting the chip under test to the connection circuit board. A detection and analysis unit executes multiple different types of detection procedures for the chip under test and collects test data. A result processing unit receives, integrates, and processes the test data collected by the detection and analysis unit and generates a test report. This approach overcomes the shortcomings of single ATE testing and on-site testing, and improves test fault coverage. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a structural block diagram of a first embodiment of a chip detection system based on ATE and assembly integration according to the present invention;

[0024] Figure 2 It is a flow chart of the first embodiment of the chip detection method based on ATE and assembly integration of the present invention.

[0025] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0026] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0027] The embodiment of the present invention provides a chip detection system based on ATE and actual assembly integration, referring to Figure 1 , Figure 1 This is a structural block diagram of a first embodiment of a chip detection system based on ATE and assembly integration of the present invention.

[0028] In this embodiment, the chip detection system based on ATE and assembly integration includes a chip interface unit, a detection and analysis unit, and a result processing unit, wherein the chip interface unit is electrically connected to the detection and analysis unit and the result processing unit.

[0029] In a specific implementation, the chip interface unit is used to establish an electrical connection with the chip to be tested. The chip interface unit includes an adapter fixture and a connecting circuit board. The adapter fixture is provided with a precision contact array to achieve reliable connection between the chip to be tested and the connecting circuit board. The detection and analysis unit is used to execute various types of detection programs for the chip to be tested and collect detection data; the result processing unit is used to receive, integrate and process the detection data collected by the detection and analysis unit and generate a detection report, wherein the result processing unit is constructed using a high-performance computer and equipped with dedicated data processing software to collect and analyze detection data in real time. The detection and analysis unit includes at least: ATE automatic detection equipment, a spectrum analyzer, an error detector, a waveform observer and a modulation signal generator. The ATE automatic detection equipment is used to run the chip test program and control the entire detection process; the spectrum analyzer is used to analyze the spectrum characteristics of the chip; the error detector is used to detect the error situation of the chip during signal transmission; the waveform observer is used to observe the output waveform of the chip; and the modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

[0030] It should be noted that the overall testing process of this technical solution involves assembling the chip under test to the interface unit; executing the complete test procedure through the detection and analysis unit, simultaneously collecting DC operating parameters and AC characteristic parameters; and generating a standardized test report by integrating the test process data, DC parameters, and AC parameters at the data processing terminal. The circuit architecture in this technical solution integrates automated test equipment (ATE) modules with system-in-package (SiP) testing technology to establish a two-dimensional verification system during the chip testing process: microsystem functional simulation and AC / DC parameter measurement are completed on the ATE platform, while chip-level functional verification is achieved in the SiP installation environment. This hybrid testing strategy effectively integrates the technical advantages of ATE modular testing and system-level installation verification, forming a complementary test architecture that significantly improves the defect detection rate (FDR) to industry-leading levels. Specifically, the circuit innovatively utilizes an ATE programmable test interface to accurately obtain the electrical characteristic parameters of the microsystem's I / O ports, covering key indicators such as connection integrity, static power distribution, drive strength threshold, and dynamic timing response, while simultaneously supporting power consumption spectrum analysis under multiple operating modes. Empirical research has shown that this solution reduces test cycles by approximately 40% and overall costs by 35% compared to traditional single-mode test processes, demonstrating significant engineering application value. By integrating ATE test systems with microsystem physical verification methods, system functionality and AC / DC parameter testing can be completed simultaneously during chip testing. This fusion solution effectively integrates the advantages of ATE automated testing and prototype verification technologies, not only overcoming the limitations of a single test mode but also significantly enhancing comprehensive fault detection capabilities. Compared to existing technologies, the advantages and positive effects of this new testing method lie in its ability to complete the test process in a shorter time and achieving significantly better test accuracy than traditional step-by-step testing solutions.

[0031] In practical applications, the adapter is used to connect the device under test (DUT) to the system. The adapter then connects the test channels, DPS, AGND, and control relays to the adapter, which then connects to the device under test via the adapter's sockets. For example, the MT8880 chip under test uses an interface unit connected to the test unit. The MT8880 chip test unit establishes a signal transmission channel with the result output unit. The MT8880 chip test unit consists of integrated circuit automatic test equipment (ATE), a spectrum analyzer, a bit error detector, a waveform acquisition unit, and a signal modulation source. Each instrument is electrically connected to the DUT via the interface unit. The ATE system runs the chip test program, while other equipment simultaneously collects the chip's AC and DC characteristic parameters during the test. The result output unit integrates the test program execution data and related parameter indicators. During testing, the MT8880 chip interface pins are connected to the ATE equipment's digital system adapter.

[0032] The detection process corresponding to the above-mentioned ATE automatic detection equipment is divided into two stages. Specifically, in the system initialization stage, the execution program starts the self-test, checks the hardware and software status of the ATE equipment, and ensures the normal operation of the equipment; and in the chip testability design verification stage, including boundary scan testing and functional verification testing, it is used to verify whether the internal structure and function of the chip are normal.

[0033] Furthermore, the detection and analysis unit performs a variety of different types of test procedures including connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing. Specifically, the connectivity test is to establish a hardware connection between the chip to be tested and the test equipment through an adapter, purchase a matching test locking seat according to the packaging process of the chip to be tested, design a PCB board, and perform a connectivity test after the locking seat is welded to ensure that the electrical connection between the chip and the test equipment is reliable; the functional test is to use a signal generator to generate a standard DTMF signal, connect it to the input end of the chip to be tested, introduce the DTMF signal, and use an oscilloscope to record the output of the chip to be tested to ensure that each number is correctly decoded; the performance test is to perform a basic performance test at room temperature, record the decoding delay and accuracy, gradually change the operating temperature, and increase it from the first preset temperature to the second preset temperature, and according to the preset The decoding test is performed at temperature intervals, and the decoding stability and accuracy are recorded. The power supply voltage test is performed by increasing the voltage from a first preset voltage to a second preset voltage according to a preset voltage level through an adjustable power supply, and recording the chip's decoding ability for DTMF signals under different voltages, wherein the DTMF signal strength is kept unchanged during the test. The anti-interference test is performed by applying noise while the signal generator outputs the DTMF signal, recording the changes in the decoding of the chip under test, so as to test the stability under different interference levels and record the error rate of the decoded signal. The long-term reliability test is performed by placing the chip under test in a preset environment and testing it for a preset time to determine whether the function of the chip under test is normal and whether the decoding ability is affected.

[0034] It should be noted that during the connectivity test, the hardware connection between the device under test and the test equipment is established using an adapter. A matching test locking socket is purchased based on the packaging process used during the test. The PCB is designed according to the test system interface board schematic. Finally, the locking socket is soldered and the connectivity test is performed. For functional testing, a standard DTMF signal is used, such as 1234567890*#. During performance testing, the first preset temperature can be set to -20°C, the second preset temperature can be set to 70°C, and the preset temperature interval can be set to 10°C. This means that decoding tests are performed every 10°C from -20°C to 70°C to observe decoding stability and accuracy. During power supply voltage testing, the first preset voltage can be set to 4.5V, the second preset voltage can be set to 5.5V, and the preset voltage level can be set to 0.5V. This means that the chip's decoding capabilities at different voltages are recorded at 0.5V intervals from 4.5V to 5.5V. For anti-interference testing, the noise applied can be a 1kHz sine wave. In the long-term reliability test, the preset environment can be a high temperature and high humidity environment, for example, an environment with a temperature of 60°C to 85°C and a humidity greater than 85%, and the preset duration can be set to 72 hours. It should be understood that the above parameter settings are only examples and are not intended to limit this embodiment, and can be adjusted accordingly based on actual conditions.

[0035] This embodiment establishes an electrical connection with the chip under test through a chip interface unit, which includes an adapter fixture and a connection circuit board. The adapter fixture is internally provided with a precision contact array for reliably connecting the chip under test to the connection circuit board. The detection and analysis unit executes various types of detection procedures for the chip under test and collects test data. The result processing unit receives, integrates, and processes the test data collected by the detection and analysis unit and generates a test report. This approach overcomes the shortcomings of single ATE testing and on-site testing, and improves test fault coverage.

[0036] Reference Figure 2 , Figure 2 It is a flow chart of the first embodiment of the chip detection method based on ATE and assembly integration of the present invention.

[0037] like Figure 2 As shown, the chip detection method based on ATE and actual assembly integration proposed in the embodiment of the present invention includes:

[0038] Step S10: The chip interface unit establishes an electrical connection with the chip to be tested.

[0039] Step S20: The detection and analysis unit executes various types of detection programs on the chip to be tested and collects detection data.

[0040] Step S30: The result processing unit receives, integrates and processes the detection data collected by the detection and analysis unit, and generates a detection report.

[0041] This embodiment establishes an electrical connection with the chip under test through a chip interface unit, which includes an adapter fixture and a connection circuit board. The adapter fixture is internally provided with a precision contact array for reliably connecting the chip under test to the connection circuit board. The detection and analysis unit executes various types of detection procedures for the chip under test and collects test data. The result processing unit receives, integrates, and processes the test data collected by the detection and analysis unit and generates a test report. This approach overcomes the shortcomings of single ATE testing and on-site testing, and improves test fault coverage.

[0042] In some embodiments, the detection and analysis unit includes at least: ATE automatic detection equipment, a spectrum analyzer, a bit error detector, a waveform observer and a modulation signal generator. The ATE automatic detection equipment is used to run the chip test program and control the entire detection process; the spectrum analyzer is used to analyze the spectrum characteristics of the chip; the bit error detector is used to detect the bit error situation of the chip during signal transmission; the waveform observer is used to observe the output waveform of the chip; and the modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

[0043] In some embodiments, the method further comprises:

[0044] During the system initialization phase, ATE automatic detection equipment executes program startup self-test to check the hardware and software status of the ATE equipment to ensure the normal operation of the equipment. During the chip testability design verification phase, boundary scan testing and functional verification testing are performed to verify whether the internal structure and function of the chip are normal.

[0045] In some embodiments, the testing procedure includes connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing.

[0046] In some embodiments, the connectivity test is to establish a hardware connection between the chip to be tested and the test equipment through an adapter, purchase a matching test locking seat according to the packaging process of the chip to be tested, design a PCB board, and perform a connectivity test after the locking seat is welded to ensure that the electrical connection between the chip and the test equipment is reliable; the functional test is to use a signal generator to generate a standard DTMF signal, connect it to the input end of the chip to be tested, introduce the DTMF signal, and use an oscilloscope to record the output of the chip to be tested to ensure that each number is correctly decoded; the performance test is to perform a basic performance test at room temperature, record the decoding delay and accuracy, gradually change the operating temperature, and increase it from a first preset temperature to a second preset temperature, and press The decoding test is performed at preset temperature intervals, and the decoding stability and accuracy are recorded. The power supply voltage test is to increase the voltage from a first preset voltage to a second preset voltage according to a preset voltage level through an adjustable power supply, and record the chip's decoding ability of DTMF signals under different voltages, wherein the DTMF signal strength is kept unchanged during the test. The anti-interference test is to apply noise while the signal generator outputs the DTMF signal, record the changes in the decoding of the chip under test, so as to test the stability under different interference levels and record the error rate of the decoded signal. The long-term reliability test is to place the chip under test in a preset environment and test it for a preset time to determine whether the function of the chip under test is normal and whether the decoding ability is affected.

[0047] An embodiment of the present application also provides a chip detection device based on ATE and actual installation integration, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus, and the memory is used to store the chip detection program based on ATE and actual installation integration; the processor is used to implement the above-mentioned chip detection method based on ATE and actual installation integration when executing the program stored in the memory.

[0048] The communication bus mentioned in the aforementioned chip testing equipment based on ATE and integrated assembly can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. This communication bus can be divided into an address bus, a data bus, and a control bus.

[0049] The communication interface is used for communication between the above-mentioned chip detection equipment based on ATE and actual assembly integration and other equipment.

[0050] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage. Alternatively, the memory may be at least one storage device located remote from the processor.

[0051] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0052] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0053] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0054] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0055] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

[0056] It should be understood that the above is only an example and does not constitute any limitation to the technical solution of the present invention. In specific applications, those skilled in the art can make settings as needed, and the present invention does not impose any limitation on this.

[0057] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of the present invention. In practical applications, technicians in this field can select part or all of it according to actual needs to achieve the purpose of the embodiment scheme, and no limitation is made here.

[0058] In addition, for technical details not fully described in this embodiment, please refer to the chip detection method based on ATE and actual assembly integration provided in any embodiment of the present invention, and will not be repeated here.

[0059] In addition, it should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0060] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0061] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, or of course by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as a read-only memory (ROM) / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0062] The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

[0063] It is understandable that the system provided by the embodiment of the present invention corresponds to the method provided by the embodiment of the present invention, and the explanation, examples and beneficial effects of the relevant contents can refer to the corresponding parts of the above method.

Claims

1. A chip detection system based on ATE and actual assembly integration, characterized in that: The chip detection system based on ATE and actual assembly integration includes: a chip interface unit, a detection and analysis unit, and a result processing unit, wherein the chip interface unit is electrically connected to the detection and analysis unit and the result processing unit; The chip interface unit is used to establish an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connection circuit board. The adapter fixture is provided with a precision contact array for achieving reliable connection between the chip under test and the connection circuit board. The detection and analysis unit is used to execute various types of detection programs on the chip to be tested and collect detection data; The result processing unit is used to receive, integrate and process the detection data collected by the detection and analysis unit, and generate a detection report. The result processing unit is constructed using a high-performance computer and equipped with dedicated data processing software to collect and analyze the detection data in real time.

2. The chip detection system based on ATE and actual assembly integration as claimed in claim 1, characterized in that: The detection and analysis unit includes at least: ATE automatic detection equipment, a spectrum analyzer, a bit error detector, a waveform observer, and a modulation signal generator. The ATE automatic detection equipment is used to run the chip test program and control the entire detection process; the spectrum analyzer is used to analyze the spectrum characteristics of the chip; the bit error detector is used to detect bit errors in the chip during signal transmission; the waveform observer is used to observe the output waveform of the chip; and the modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

3. The chip detection system based on ATE and actual assembly integration as claimed in claim 2, characterized in that: The ATE automatic detection equipment is used to perform program startup self-test during the system initialization phase to check the hardware and software status of the ATE equipment to ensure the normal operation of the equipment, and during the chip testability design verification phase, including boundary scan testing and functional verification testing, to verify whether the internal structure and function of the chip are normal.

4. The chip detection system based on ATE and assembly integration as claimed in claim 1, characterized in that: The testing procedures include connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing.

5. The chip detection system based on ATE and assembly integration as claimed in claim 4, characterized in that: The connectivity test is to establish a hardware connection between the chip to be tested and the test equipment through an adapter, purchase a matching test locking seat according to the packaging process of the chip to be tested, design a PCB board, and perform a connectivity test after the locking seat is welded to ensure that the electrical connection between the chip and the test equipment is reliable; the functional test is to use a signal generator to generate a standard DTMF signal, connect it to the input end of the chip to be tested, introduce the DTMF signal, and use an oscilloscope to record the output of the chip to be tested to ensure that each number is correctly decoded; the performance test is to perform a basic performance test at room temperature, record the decoding delay and accuracy, gradually change the operating temperature, increase it from a first preset temperature to a second preset temperature, and perform a test according to the preset temperature. The decoding test is performed at regular intervals to record the decoding stability and accuracy; the power supply voltage test is to increase the voltage from a first preset voltage to a second preset voltage according to a preset voltage gear through an adjustable power supply, and record the chip's decoding ability of DTMF signals under different voltages, wherein the DTMF signal strength is kept unchanged during the test; the anti-interference test is to apply noise while the signal generator outputs the DTMF signal, record the changes in the decoding of the chip under test, so as to test the stability under different interference levels, and record the error rate of the decoded signal; the long-term reliability test is to place the chip under test in a preset environment and test it for a preset time, and then determine whether the function of the chip under test is normal and whether the decoding ability is affected.

6. A chip detection method based on ATE and actual assembly integration, characterized in that: The chip detection method based on ATE and actual assembly integration is applied to the chip detection system based on ATE and actual assembly integration as described in any one of claims 1 to 5, and the method includes: The chip interface unit establishes an electrical connection with the chip under test. The chip interface unit includes an adapter fixture and a connection circuit board. The adapter fixture is provided with a precision contact array for achieving reliable connection between the chip under test and the connection circuit board. The detection and analysis unit executes various types of detection procedures on the chip to be tested and collects detection data; The result processing unit receives, integrates and processes the test data collected by the detection and analysis unit, and generates a test report. The result processing unit is constructed using a high-performance computer and equipped with dedicated data processing software to collect and analyze the test data in real time.

7. The chip detection method based on ATE and assembly integration as claimed in claim 6, characterized in that: The detection and analysis unit includes at least: ATE automatic detection equipment, a spectrum analyzer, a bit error detector, a waveform observer, and a modulation signal generator. The ATE automatic detection equipment is used to run the chip test program and control the entire detection process; the spectrum analyzer is used to analyze the spectrum characteristics of the chip; the bit error detector is used to detect bit errors in the chip during signal transmission; the waveform observer is used to observe the output waveform of the chip; and the modulation signal generator is used to generate a modulation signal to test the modulation and demodulation capabilities of the chip.

8. The chip detection method based on ATE and assembly integration as claimed in claim 7, characterized in that: The method further comprises: During the system initialization phase, ATE automatic detection equipment executes program startup self-test to check the hardware and software status of the ATE equipment to ensure the normal operation of the equipment. During the chip testability design verification phase, boundary scan testing and functional verification testing are performed to verify whether the internal structure and function of the chip are normal.

9. The chip detection method based on ATE and assembly integration as claimed in claim 6, characterized in that: The testing procedures include connectivity testing, functional testing, performance testing, power supply voltage testing, anti-interference testing, and long-term reliability testing.

10. The chip detection method based on ATE and assembly integration as claimed in claim 9, characterized in that: The connectivity test is to establish a hardware connection between the chip to be tested and the test equipment through an adapter, purchase a matching test locking seat according to the packaging process of the chip to be tested, design a PCB board, and perform a connectivity test after the locking seat is welded to ensure that the electrical connection between the chip and the test equipment is reliable; the functional test is to use a signal generator to generate a standard DTMF signal, connect it to the input end of the chip to be tested, introduce the DTMF signal, and use an oscilloscope to record the output of the chip to be tested to ensure that each number is correctly decoded; the performance test is to perform a basic performance test at room temperature, record the decoding delay and accuracy, gradually change the operating temperature, increase it from a first preset temperature to a second preset temperature, and perform a test according to the preset temperature. The decoding test is performed at regular intervals to record the decoding stability and accuracy; the power supply voltage test is to increase the voltage from a first preset voltage to a second preset voltage according to a preset voltage gear through an adjustable power supply, and record the chip's decoding ability of DTMF signals under different voltages, wherein the DTMF signal strength is kept unchanged during the test; the anti-interference test is to apply noise while the signal generator outputs the DTMF signal, record the changes in the decoding of the chip under test, so as to test the stability under different interference levels, and record the error rate of the decoded signal; the long-term reliability test is to place the chip under test in a preset environment and test it for a preset time, and then determine whether the function of the chip under test is normal and whether the decoding ability is affected.

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