Method and system for testing stability of output voltage of mainboard power supply

Abstract

The invention provides a mainboard power supply output voltage stability test method and system, and the method comprises the steps: generating a dynamic stepped load current based on a load demand parameter and a limit working condition defined by a hardware specification when a mainboard operates in a preset multi-mode switching state, and setting a first synchronization window before each step switching moment, setting a second synchronization window after the step switching time, collecting voltage waveform data, inputting the voltage waveform data into a preset filtering algorithm, extracting an overshoot amplitude and recovery time, constructing an asymmetric coupling model, and taking a difference value between the overshoot amplitude and a preset fluctuation range as a first stability index; the ratio of the recovery time to the response time threshold value is used as a second stability index, nonlinear weight distribution of the two indexes in multiple step intervals is calculated, a stability grade judgment result is generated in combination with a circuit board wiring impedance characteristic library, and the test compatibility of high-density mainboard multi-phase power supply and high-frequency devices is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of motherboard testing technology, and more particularly to a method and system for testing the stability of a motherboard power supply output voltage. Background Art

[0002] As motherboard power supply designs evolve toward higher density, multi-mode switching, and higher frequencies, the voltage stability of power supply systems under transient load shocks is becoming increasingly prominent. This is especially true for motherboards equipped with multi-phase parallel power supplies, GaN power devices, and high-speed digital circuits. Output voltage overshoot and recovery time are susceptible to multiple factors, including PCB wiring impedance, switching noise coupling, and dynamic load timing misalignment.

[0003] Current mainstream testing solutions often use fixed loads or simple step-type loads to simulate power supply transient conditions, evaluating voltage stability through threshold comparison or linear weighted models. For example, after acquiring the voltage waveform using a general-purpose oscilloscope, a low-pass filter is used to separate noise and extract overshoot parameters, or power loop simulation software is used to predict recovery time. Some solutions attempt to incorporate PCB impedance parameters for stability correction, but these typically employ a linear superposition evaluation method that combines a static impedance database with electrical performance indicators.

[0004] However, existing solutions have significant limitations. First, traditional step loads cannot accurately simulate the dynamic current changes under multi-mode switching of the motherboard, and the parasitic inductance effect causes step waveform distortion, making it difficult to reproduce the actual extreme operating conditions. Second, the general filtering algorithm is unable to separate the spectral overlap area of digital switching noise and the inherent response of the power supply, and the overshoot amplitude extraction error exceeds the standard value. Third, the linear evaluation model ignores the dynamic coupling relationship between power supply topology parameters (such as output capacitor ESR and phase margin) and transient indicators, resulting in inaccurate weight distribution, and does not incorporate the suppressive effect of PCB wiring impedance on high-frequency oscillation. The final judgment result deviates from the measured failure mode by more than the preset value. These defects seriously restrict the reliability verification accuracy of high-density motherboard power supplies. Summary of the Invention

[0005] The embodiments of the present application provide a method and system for testing the output voltage stability of a motherboard power supply, which are used to solve the problems of dynamic load simulation distortion, insufficient noise suppression capability and static stability evaluation model in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a method for testing the output voltage stability of a motherboard power supply, comprising:

[0007] When the motherboard is operating in a preset multi-mode switching state, a dynamic step load current is generated by a nonlinear compensation load generator based on the load demand parameters fed back by the power management chip of the motherboard and the extreme operating conditions defined in the hardware specification of the motherboard;

[0008] A first synchronization window is set before each step switching moment of the dynamic step load current, and a second synchronization window is set after the step switching moment, and a phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to acquire voltage waveform data;

[0009] Inputting the voltage waveform data into a preset filtering algorithm to separate the inherent response of the power management chip from the switching noise of the digital circuit to extract the overshoot amplitude and recovery time;

[0010] An asymmetric coupling model is constructed based on characteristic parameters of the power supply topology of the motherboard, a difference between the overshoot amplitude and a preset fluctuation range is used as a first stability indicator, a ratio of the recovery time to a response time threshold is used as a second stability indicator, and a nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals is calculated using the asymmetric coupling model;

[0011] Combined with the circuit board wiring impedance characteristic library of the mainboard, a stability level determination result of the power supply output voltage is output.

[0012] Optionally, an asymmetric coupling model is constructed based on characteristic parameters of the power supply topology structure of the motherboard, a difference between the overshoot amplitude and a preset fluctuation range is used as a first stability indicator, and a ratio of the recovery time to a response time threshold is used as a second stability indicator. The asymmetric coupling model is used to calculate a nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals, including:

[0013] Based on the power topology type defined in the hardware specification of the motherboard, selecting a basic model architecture corresponding to the power topology type, wherein the basic model architecture includes: a coupling relationship equation of the output capacitor equivalent series resistance, the feedback loop phase margin, and the rise time of the switching device;

[0014] Decomposing the output capacitor equivalent series resistance value, the feedback loop phase margin value, and the switching device rise time value in the power topology characteristic parameters of the mainboard, performing impedance dimension normalization on the output capacitor equivalent series resistance value to generate a first standardized parameter, performing angle-time conversion on the feedback loop phase margin value to generate a second standardized parameter, and performing time dimension normalization on the switching device rise time value to generate a third standardized parameter;

[0015] Inputting the first standardized parameter, the second standardized parameter, and the third standardized parameter into a preset orthogonal experiment configuration module, and using multi-factor variance analysis to determine initial weighting coefficients of the output capacitor equivalent series resistance value, the feedback loop phase margin value, and the switching device rise time value in the basic model architecture;

[0016] Calculating a dynamic compensation factor of the basic model architecture according to the step amplitude and step interval duration of the dynamic stepped load current, and inputting the initial weighting coefficient and the dynamic compensation factor into the coupling relationship equation to generate an asymmetric coupling model;

[0017] Inputting the difference between the overshoot amplitude and the preset fluctuation range into the asymmetric coupling model, and calculating the reference value of the first stability indicator using the coupling relationship equation; inputting the ratio of the recovery time to the response time threshold into the asymmetric coupling model, and calculating the reference value of the second stability indicator using the coupling relationship equation;

[0018] According to the step amplitude of the dynamic step load current and the dynamic compensation factor, the weight distribution ratio of the initial weight coefficient in the asymmetric coupling model is adjusted to generate a nonlinear weight distribution.

[0019] Optionally, calculating a dynamic compensation factor of the basic model architecture according to the step amplitude and step interval duration of the dynamic stepped load current, and inputting the initial weighting coefficient and the dynamic compensation factor into the coupling relationship equation to generate an asymmetric coupling model, including:

[0020] Obtaining a current step amplitude nominal value and a reciprocal of a current step interval duration of the dynamic step load current, calculating a product of the current step amplitude nominal value and the reciprocal to generate an initial step change rate, performing logarithmic processing on the initial step change rate and the third normalized parameter to generate a first compensation coefficient;

[0021] extracting a phase distribution difference value of the dynamic stepped load current in the multi-phase parallel power supply architecture based on real-time load feedback parameters of the power management chip of the motherboard, and multiplying the phase distribution difference value by the first compensation coefficient to generate a phase correction factor;

[0022] adding the phase correction factor to the initial step change rate to generate a composite step change rate, inputting the composite step change rate into a high-frequency response curve of a switching device of the basic model architecture, extracting a gain compensation term corresponding to the composite step change rate, performing a convolution operation on the gain compensation term and the first normalization parameter to generate an impedance dynamic weight, and performing polarity matching on the impedance dynamic weight and the second normalization parameter to generate a loop stability correction value;

[0023] According to the percentage by which the step amplitude of the dynamic step load current exceeds the nominal value of the hardware specification, the amplitude attenuation factor of the initial weighting coefficient is calculated, the amplitude attenuation factor is multiplied by the initial weighting coefficient to generate a dynamic adjustment weighting coefficient, and the dynamically adjusted weighting coefficient, the gain compensation term and the impedance dynamic weight are input into the coupling relationship equation to generate the asymmetric coupling model.

[0024] Optionally, outputting a stability level determination result of the power supply output voltage in combination with a circuit board wiring impedance characteristic library of the mainboard includes:

[0025] Extracting the impedance values of multi-layer traces connected to the power output terminal of the mainboard, the coupling capacitance values of adjacent signal layers, and the length of the reference plane return path from the circuit board wiring impedance characteristic library to generate an impedance distribution vector;

[0026] Calculate impedance matching between the multi-layer trace impedance value in the impedance distribution vector and the output capacitor equivalent series resistance value in the asymmetric coupling model to generate an impedance compensation factor;

[0027] Inputting the reference value of the first stability index and the reference value of the second stability index into a time-frequency domain converter, and decomposing the reference value of the first stability index and the reference value of the second stability index within a step interval of the dynamic step load current into a low-frequency component and a high-frequency oscillation component;

[0028] Calculating a high-frequency resonance energy density based on the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer, and performing a weighted summation of the high-frequency resonance energy density and the impedance compensation factor to generate a resonance suppression score;

[0029] The low-frequency component is input into the asymmetric coupling model, and the weight ratio of the low-frequency component is redistributed through the nonlinear weight distribution to generate a steady-state offset score. According to the stability level mapping table defined in the hardware specification of the motherboard, the resonance suppression score and the steady-state offset score are input into a composite judgment function to generate a stability level judgment result of the power supply output voltage.

[0030] Optionally, calculating a high-frequency resonance energy density according to the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer, and performing a weighted summation of the high-frequency resonance energy density and the impedance compensation factor to generate a resonance suppression score includes:

[0031] Inputting the high-frequency oscillation component into a pre-built resonant frequency band separator and extracting a target oscillation frequency band corresponding to an odd-order harmonic of the switching frequency of the power topology structure of the mainboard;

[0032] Calculating an average amplitude of the target oscillation frequency band within the dynamic stepped load current step interval, and multiplying the average amplitude by the adjacent signal layer coupling capacitance value to generate an initial resonant energy density;

[0033] Extracting a skin effect attenuation coefficient corresponding to the reference plane return path length from the circuit board wiring impedance characteristic library, and performing an inverse proportional operation on the skin effect attenuation coefficient and the initial resonant energy density to generate a corrected resonant energy density;

[0034] Calculating the phase dispersion of the target oscillation frequency band according to the phase switching interval of the power management chip of the motherboard in the multi-phase parallel power supply architecture, and performing a convolution process on the phase dispersion and the corrected resonant energy density to generate a high-frequency resonant energy density;

[0035] The high-frequency resonance energy density and the impedance compensation factor are input into a dynamic weight allocator, and the weight ratio of the impedance compensation factor is adjusted according to the step amplitude nominal value of the dynamic step load current to generate a resonance suppression score.

[0036] Optionally, a first synchronization window is set before each step switching moment of the dynamic step load current, and a second synchronization window is set after the step switching moment, and a phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to acquire voltage waveform data, including:

[0037] parsing the step start time and the step amplitude nominal value in the step mark signal of the dynamic step load current, and calculating the ratio of the step amplitude nominal value to the maximum output current of the power management chip of the mainboard to generate a window reference width;

[0038] Divide the window reference width into a plurality of sampling intervals synchronized with the switching cycle according to the switching frequency of the power topology of the mainboard, and extend the initial boundary of the first synchronization window in the reverse direction by two switching cycles before the step start time, and extend the initial boundary of the second synchronization window in the forward direction by three switching cycles after the step start time;

[0039] Extracting a clock jitter parameter of the phase-locked trigger module and a trigger delay parameter of the high-precision oscilloscope, inputting a difference between the clock jitter parameter and the trigger delay parameter into a phase error compensation algorithm to generate a first window boundary correction amount and a second window boundary correction amount;

[0040] Superimposing the first window boundary correction amount on the initial boundary of the first synchronization window to generate a final boundary of the first synchronization window, and superimposing the second window boundary correction amount on the initial boundary of the second synchronization window to generate a final boundary of the second synchronization window, wherein the starting time of the final boundary is synchronized with the rising edge of the step mark signal at a sub-microsecond level;

[0041] Pre-trigger sampling is performed within the final boundary of the first synchronization window to obtain a reference voltage waveform before the step switching, and post-trigger sampling is performed within the final boundary of the second synchronization window to obtain a transient voltage waveform after the step switching. The reference voltage waveform and the transient voltage waveform are input into a differential amplifier for common-mode noise suppression to generate voltage waveform data.

[0042] Optionally, the voltage waveform data is input into a preset filtering algorithm to separate the inherent response of the power management chip and the switching noise of the digital circuit to extract the overshoot amplitude and recovery time, including:

[0043] Based on the clock frequency distribution characteristics of the digital circuit of the motherboard, the fundamental frequency component of the periodic switching noise is extracted from the voltage waveform data to generate a noise baseline template;

[0044] Inputting the voltage waveform data and the noise baseline template into an empirical mode decomposer, and using an adaptive decomposition algorithm to separate the intrinsic mode function components containing the inherent response of the power management chip;

[0045] Inputting the intrinsic mode function components into a waveform reconstructor, screening effective harmonic components according to integer multiples of the switching frequency of the power topology structure of the mainboard, and generating a denoised power supply intrinsic response waveform;

[0046] In the inherent response waveform of the power supply, a voltage mutation point corresponding to the step switching moment of the dynamic step load current is located, and an overshoot detection window is generated by tracing back a first preset time length based on the voltage mutation point, and a recovery detection window is generated by tracing back a second preset time length;

[0047] In the overshoot detection window, the difference between the peak voltage and the steady-state voltage of the power supply inherent response waveform is calculated to generate the overshoot amplitude. In the recovery detection window, the time required for the power supply inherent response waveform to decay from the peak voltage to a preset range value of the steady-state voltage is calculated to generate the recovery time.

[0048] In a second aspect, an embodiment of the present application provides a motherboard power supply output voltage stability testing system, comprising:

[0049] a generating module for generating a dynamic stepped load current through a nonlinear compensation load generator based on load demand parameters fed back by a power management chip of the motherboard and extreme operating conditions defined in the hardware specification of the motherboard when the motherboard operates in a preset multi-mode switching state;

[0050] a setting module, configured to set a first synchronization window before each step switching moment of the dynamic stepped load current, and set a second synchronization window after the step switching moment, and synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal using a phase-locked trigger module to acquire voltage waveform data;

[0051] a separation module, configured to input the voltage waveform data into a preset filtering algorithm, separate the inherent response of the power management chip from the switching noise of the digital circuit, and extract the overshoot amplitude and recovery time;

[0052] a calculation module, configured to construct an asymmetric coupling model based on characteristic parameters of the power supply topology of the motherboard, use a difference between the overshoot amplitude and a preset fluctuation range as a first stability indicator, and a ratio of the recovery time to a response time threshold as a second stability indicator, and calculate a nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals using the asymmetric coupling model;

[0053] The output module is used to output the stability level determination result of the power supply output voltage in combination with the circuit board wiring impedance characteristic library of the mainboard.

[0054] In a third aspect, an embodiment of the present application provides a computing device comprising a processor and a memory, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute a motherboard power supply output voltage stability testing method as described in any one of the first aspects.

[0055] In a fourth aspect, an embodiment of the present application provides a computer storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement a method for testing the output voltage stability of a motherboard power supply as described in any one of the first aspects.

[0056] In an embodiment of the present application, when the motherboard operates in a preset multi-mode switching state, a dynamic step load current is generated by a nonlinear compensation load generator based on load demand parameters fed back by the motherboard's power management chip and the extreme operating conditions defined in the motherboard's hardware specification. A first synchronization window is set before each step switching moment of the dynamic step load current, and a second synchronization window is set after the step switching moment. A phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to acquire voltage waveform data. The voltage waveform data is input into a preset filtering algorithm to separate the inherent response of the power management chip from the switching noise of the digital circuit to extract the overshoot amplitude and recovery time. An asymmetric coupling model is constructed based on the characteristic parameters of the power topology structure of the motherboard. The difference between the overshoot amplitude and the preset fluctuation range is used as a first stability indicator, and the ratio of the recovery time to the response time threshold is used as a second stability indicator. The asymmetric coupling model is used to calculate the nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals. Combined with the circuit board wiring impedance characteristic library of the motherboard, a stability level determination result of the power supply output voltage is output.

[0057] The technical solution of this application generates a dynamic stepped load current through a nonlinear compensation load generator to accurately simulate the transient load impact in the multi-mode switching scenario of the motherboard; adopts a dual-window synchronous acquisition and filtering algorithm to effectively separate the inherent response of the power supply and the switching noise of the digital circuit, and improves the detection accuracy of the overshoot amplitude and recovery time; constructs an asymmetric coupling model to integrate the power supply topology parameters and dynamic load conditions, and combines the circuit board wiring impedance characteristic library to quantify the high-frequency resonance suppression effect, thereby achieving physical interpretability of the stability level determination and expanding the test compatibility of high-density motherboard multi-phase power supply and high-frequency devices.

[0058] Furthermore, an asymmetric coupling model is established through parameter standardization and dynamic compensation factors, and the sensitivity weights of the power supply topology parameters are quantified by combining orthogonal experimental configuration and multi-factor analysis. The nonlinear weight distribution is dynamically adjusted to adapt to different load step characteristics. The response characteristics of switching devices and the high-frequency load impact mechanism are integrated to suppress the interference of high-frequency resonance on stability evaluation, forming a closed-loop optimization link between hardware design specifications and test data, thereby improving the reliability and scenario adaptability of the stability evaluation of high-frequency power supply systems.

[0059] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0061] Figure 1 A flowchart of a method for testing the stability of a motherboard power supply output voltage provided by an embodiment of the present application;

[0062] Figure 2 A schematic diagram of the structure of a motherboard power supply output voltage stability test system provided in an embodiment of the present application;

[0063] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0065] In some of the processes described in the specification and claims of this application and the above-mentioned figures, multiple operations that appear in a specific order are included, but it should be clearly understood that these operations may not be executed in the order in which they appear in this document or may be executed in parallel. The serial numbers of the operations, such as 101, 102, etc., are only used to distinguish between different operations, and the serial numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this document are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to being different types.

[0066] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0067] Figure 1 A flowchart of a method for testing the stability of a motherboard power supply output voltage is provided in an embodiment of the present application. Figure 1 As shown, the method includes:

[0068] Step 101, when the motherboard is operating in a preset multi-mode switching state, a dynamic step load current is generated by a nonlinear compensation load generator based on load demand parameters fed back by a power management chip of the motherboard and the extreme operating conditions defined in the hardware specification of the motherboard;

[0069] In this step, the dynamic step load current refers to a current signal with step-like characteristics, generated by a nonlinearly compensated load generator. The step amplitude and duration are dynamically adjusted based on the real-time feedback parameters of the motherboard's power management chip and the extreme operating conditions defined in the hardware specification. This is used to simulate the transient load changes of the motherboard during multi-mode switching. A nonlinearly compensated load generator is a device that corrects load current waveform distortion in real time, compensating for parasitic inductance and back electromotive force interference to ensure that the step current switching rate and waveform accuracy meet test requirements.

[0070] In this embodiment, a nonlinear compensation load generator generates a dynamic step-type load current based on the load demand parameters fed back by the motherboard power management chip and the extreme operating conditions defined in the hardware specification. The specific process includes parsing the load demand parameters and extreme operating conditions to calculate the initial step amplitude; dividing the time slice according to the switching frequency of the power topology to generate a step current template; extracting the output capacitor equivalent series resistance value and the power loop response delay time to calculate the parasitic inductance compensation amount and the back electromotive force suppression time; and superimposing the compensation current waveform on the step current template to generate a corrected dynamic step-type load current.

[0071] For example, in a motherboard test, the power management chip feedback shows that the current load demand is 50A, and the peak current threshold defined in the hardware specification is 100A. The nonlinear compensation load generator first calculates the initial step amplitude as 50A (50A / 100A), and divides the mode duration into multiple time slices according to the switching frequency to generate a 50A step current template. Then, the output capacitor ESR and loop delay time (2μs) are extracted, the parasitic inductance compensation amount is calculated to be 0.1V·s, and the reverse electromotive force suppression time is 4μs. Finally, a corrected dynamic step load current is generated to simulate the transient working condition of the motherboard switching from low load mode to high load mode. Step 102, set a first synchronization window before each step switching moment of the dynamic step load current, and set a second synchronization window after the step switching moment, and use the phase-locked trigger module to synchronize the acquisition timing of the high-precision oscilloscope with the load switching signal to collect voltage waveform data;

[0072] In this step, dual-window synchronous acquisition involves setting a first synchronization window and a second synchronization window before and after each step switching moment of the dynamic step load current. A phase-locked trigger module is used to strictly synchronize the high-precision oscilloscope acquisition timing with the load switching signal, ensuring the timing accuracy of the voltage waveform data. The phase-locked trigger module eliminates clock jitter and trigger delay variations. It uses a frequency-adaptive calibration algorithm to compensate for phase offset in multi-phase power supply architectures, ensuring sub-microsecond synchronization of the acquisition window with the load switching signal.

[0073] In this embodiment, a first synchronization window is set before each step switching moment of a dynamic step load current, and a second synchronization window is set after the switching moment. A phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal. The specific process includes: parsing the step start time and nominal step amplitude in the step marker signal to calculate the window reference width; dividing the sampling interval according to the power topology switching frequency to generate the initial window boundary; extracting clock jitter parameters and trigger delay parameters to calculate the window boundary correction; adding these corrections to generate the final window boundary, performing pre-trigger and post-trigger sampling, and acquiring the reference voltage waveform and transient voltage waveform.

[0074] For example, in the above-mentioned motherboard test scenario, the step start time of the dynamic step load current is t = 10μs, and the nominal step amplitude is 50A. The sampling interval is divided according to the switching frequency to generate the initial boundaries of the first synchronization window (t = 8μs to t = 10μs) and the second synchronization window. The clock jitter parameter (0.1μs) and trigger delay parameter (0.2μs) are extracted, and the window boundary correction amount is calculated to be 0.1μs, and finally the first synchronization window (t = 7.9μs to t = 10μs) and the second synchronization window (t = 10μs to t = 13.1μs) are generated. The reference voltage waveform and transient voltage waveform are collected within the window for subsequent noise separation and stability analysis.

[0075] Step 103: Input the voltage waveform data into a preset filtering algorithm to separate the inherent response of the power management chip and the switching noise of the digital circuit to extract the overshoot amplitude and recovery time;

[0076] In this step, a pre-set filtering algorithm, a signal processing algorithm based on empirical mode decomposition (EMD) and a clock frequency baseline template, is used to separate the intrinsic response of the power management chip from the switching noise of the digital circuit from the voltage waveform data, extracting the overshoot amplitude and recovery time. EMD is an adaptive signal decomposition method that accurately separates noise from the valid signal by extracting the intrinsic mode function components.

[0077] In this embodiment, voltage waveform data is fed into a pre-set filtering algorithm to separate the intrinsic response of the power management chip from the switching noise of the digital circuit. The specific process includes extracting a noise baseline template based on the frequency distribution characteristics of the digital circuit clock; separating the intrinsic mode function components and residual high-frequency noise components using an empirical mode decomposer; filtering the effective harmonic components to reconstruct the denoised intrinsic response waveform of the power supply; locating the voltage mutation point at the step switching moment to generate the overshoot detection window and the recovery detection window; and calculating the overshoot amplitude and recovery time.

[0078] For example, in the motherboard test described above, the voltage waveform data contains digital circuit switching noise and the inherent power supply response signal. The preset filtering algorithm first extracts a 100MHz noise baseline template and uses an empirical mode decomposer to separate the intrinsic mode function components and residual high-frequency noise components. The voltage mutation point is located at the step switching instant t = 10μs, and overshoot and recovery detection windows are generated. The overshoot amplitude is calculated to be 0.5V, and the recovery time is calculated to be 3μs.

[0079] Step 104: constructing an asymmetric coupling model based on characteristic parameters of the power topology of the motherboard, using the difference between the overshoot amplitude and a preset fluctuation range as a first stability indicator, and the ratio of the recovery time to the response time threshold as a second stability indicator, and calculating the nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals using the asymmetric coupling model;

[0080] In this step, the asymmetric coupling model is a stability evaluation model that integrates power supply topology parameters and dynamic load conditions. It calculates the overshoot amplitude difference and recovery time ratio through nonlinear weight distribution to quantify the transient response characteristics of the power supply output voltage.

[0081] In this embodiment, an asymmetric coupling model is constructed based on the characteristic parameters of the motherboard's power topology to calculate the first stability index. The specific process includes selecting a basic model architecture corresponding to the power topology type; decomposing the output capacitor ESR value, phase margin value, and switch rise time value to generate standardized parameters; determining the initial weighting coefficient through the orthogonal experiment configuration module; calculating the dynamic compensation factor and generating the asymmetric coupling model; inputting the overshoot amplitude difference and recovery time ratio to calculate the stability index baseline value; and adjusting the weight distribution ratio to generate a nonlinear weight distribution.

[0082] For example, in the aforementioned motherboard test, the basic model architecture corresponding to the multi-phase parallel power supply architecture was selected, and the output capacitor ESR value, phase margin value (45°), and switch rise time value were decomposed to generate standardized parameters. The initial weighting coefficient (ESR: 0.4, phase margin: 0.3, switch rise time: 0.3) was determined through the orthogonal experiment configuration module, and the dynamic compensation factor was calculated as 0.2 to generate an asymmetric coupling model. The overshoot amplitude difference (0.5V) and recovery time ratio (1.5) were input, the stability index baseline value was calculated, and the weight distribution ratio was adjusted to generate a nonlinear weight distribution.

[0083] Step 105: outputting a stability level determination result of the power supply output voltage in combination with a circuit board wiring impedance characteristic library of the mainboard;

[0084] In this step, the PCB wiring impedance characteristic library is a database containing parameters such as multi-layer trace impedance, coupling capacitance, and return path length, which is used to quantify the PCB layout's suppression effect on high-frequency resonance.

[0085] In this embodiment, a stability level determination result for the power supply output voltage is generated by combining a circuit board wiring impedance characteristic library. The specific process includes: extracting multi-layer trace impedance values, coupling capacitance values, and return path lengths to generate an impedance distribution vector; calculating an impedance compensation factor; decomposing the baseline value of the stability indicator using a time-frequency domain converter; calculating the high-frequency resonant energy density and steady-state offset score; and inputting the composite determination function to generate the stability level determination result.

[0086] For example, in the motherboard test described above, the impedance values of multi-layer traces, coupling capacitance values, and return path lengths were extracted to generate an impedance distribution vector. The impedance compensation factor was calculated to be 0.8. Using a time-frequency converter to decompose the stability index baseline, the high-frequency resonant energy density was calculated to be 0.2, and the steady-state excursion score was 0.9. This input into the composite judgment function yielded an "Excellent" stability rating.

[0087] In summary, this embodiment uses a nonlinear compensation load generator to accurately simulate dynamic step load current, combines dual-window synchronous acquisition with a phase-locked trigger module to improve the timing accuracy of voltage waveform data, and uses a preset filtering algorithm to efficiently separate the inherent response of the power supply from the switching noise of the digital circuit, significantly improving the detection accuracy of the overshoot amplitude and recovery time. By constructing an asymmetric coupling model to integrate the power supply topology parameters and dynamic load conditions, the nonlinear weight distribution of the stability index is quantified, and the high-frequency resonance suppression effect is quantified in combination with the circuit board wiring impedance characteristic library, the physical interpretability and scenario adaptability of the stability level determination are achieved, providing a high-precision and high-efficiency transient response verification method for high-performance motherboard power supply design.

[0088] In motherboard testing, traditional linear models cannot accurately reflect the dynamic coupling relationship between power topology parameters and transient response indicators, resulting in a large deviation between stability evaluation results and measured failure modes. In addition, the static weight distribution method is difficult to adapt to transient response changes under different load step characteristics. Based on this, in some embodiments, according to step 104, an asymmetric coupling model is constructed according to the characteristic parameters of the power topology structure of the motherboard, and the difference between the overshoot amplitude and the preset fluctuation range is used as the first stability indicator, and the ratio of the recovery time to the response time threshold is used as the second stability indicator. The asymmetric coupling model is used to calculate the nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals, including:

[0089] Step 201: Based on the power topology type defined in the hardware specification of the motherboard, a basic model architecture corresponding to the power topology type is selected, wherein the basic model architecture includes: a coupling relationship equation of the output capacitor equivalent series resistance, the feedback loop phase margin, and the rise time of the switching device;

[0090] In this step, the basic model architecture is a mathematical model framework built based on the power supply topology type (such as Buck circuit and multiphase parallel architecture) defined in the motherboard hardware specification. Its core is the coupling relationship equation between the output capacitor equivalent series resistance (ESR), the feedback loop phase margin, and the rise time of the switching device. This architecture provides the theoretical basis and calculation framework for the subsequent construction of the asymmetric coupling model.

[0091] In this embodiment, the corresponding basic model architecture is selected based on the power topology type defined in the motherboard hardware specification. For example, for a multi-phase parallel power supply architecture, the basic model architecture includes coupling equations for output capacitor ESR, phase margin, and switch device rise time. The specific process includes parsing the power topology type in the hardware specification, matching it with a predefined model architecture library, and extracting the parameter definitions and calculation rules for the coupling equations.

[0092] Step 202: Decompose the output capacitor equivalent series resistance value, the feedback loop phase margin value, and the switching device rise time value from the power topology characteristic parameters of the motherboard, perform impedance dimension normalization on the output capacitor equivalent series resistance value to generate a first standardized parameter, perform angle-time conversion on the feedback loop phase margin value to generate a second standardized parameter, and perform time dimension normalization on the switching device rise time value to generate a third standardized parameter.

[0093] In this step, standardized parameters refer to standardized variables generated by dimensional unification and normalization of the characteristic parameters of the power topology structure, which are used to eliminate the physical dimensional differences between parameters and ensure the comparability of model input data and calculation consistency.

[0094] In this embodiment, the output capacitor ESR, phase margin, and switching device rise time, characteristic parameters of the power supply topology, are decomposed and standardized. The specific process includes normalizing the output capacitor ESR to the impedance dimension to generate a first standardized parameter; converting the phase margin to the time dimension to generate a second standardized parameter; and normalizing the switching device rise time to generate a third standardized parameter. For example, the output capacitor ESR is normalized to 0.5, the phase margin (45°) is converted to the time dimension, and the switching device rise time is normalized to 0.1.

[0095] Step 203: input the first standardized parameter, the second standardized parameter, and the third standardized parameter into a preset orthogonal experiment configuration module, and use multi-factor variance analysis to determine initial weighting coefficients of the output capacitor equivalent series resistance value, the feedback loop phase margin value, and the switch device rise time value in the basic model architecture;

[0096] In this step, the Orthogonal Experiment Configuration module, a multi-factor experiment configuration tool based on orthogonal array design, is used to efficiently analyze the sensitivity weights of multiple parameters to the target indicator. Multi-factor analysis of variance is a statistical analysis method used to quantify the contribution of each parameter to the model output, providing a scientific basis for determining the initial weighting coefficients.

[0097] In this embodiment, the first, second, and third normalized parameters are input into the orthogonal experiment configuration module, and initial weighting coefficients are determined through multi-factor variance analysis. The specific process includes: designing an L9(3^4) orthogonal table and configuring experimental parameter combinations; running a multi-factor variance analysis to calculate the sensitivity weight of each parameter to the stability index; and generating initial weighting coefficients.

[0098] Step 204 , calculating a dynamic compensation factor of the basic model architecture according to the step amplitude and step interval duration of the dynamic step load current, and inputting the initial weighting coefficient and the dynamic compensation factor into the coupling relationship equation to generate an asymmetric coupling model;

[0099] In this step, the dynamic compensation factor refers to a correction coefficient calculated according to the step amplitude and duration of the dynamic step load current, and is used to adjust the initial weighting coefficient to adapt to the transient response characteristics under different load conditions.

[0100] In this embodiment, a dynamic compensation factor is calculated based on the step amplitude and step duration of a dynamic step load current. The specific process includes extracting the nominal step amplitude and step duration to calculate the step change rate; generating the dynamic compensation factor based on the rise time of the switching device; and inputting the initial weighting coefficient and the dynamic compensation factor into the coupling relationship equation to generate an asymmetric coupling model. For example, if the step amplitude is 50A and the duration is 10μs, the dynamic compensation factor is calculated to be 0.2. After modifying the initial weighting coefficient, the asymmetric coupling model is generated.

[0101] Step 205: Input the difference between the overshoot amplitude and the preset fluctuation range into the asymmetric coupling model, and calculate the reference value of the first stability indicator using the coupling relationship equation; input the ratio of the recovery time to the response time threshold into the asymmetric coupling model, and calculate the reference value of the second stability indicator using the coupling relationship equation;

[0102] In this step, the coupling relationship equation refers to a mathematical equation that describes the nonlinear relationship between the output capacitor ESR, the phase margin, and the rise time of the switching device, and is used to calculate the reference value of the stability indicator.

[0103] In this embodiment, the overshoot amplitude difference and recovery time ratio are input into the asymmetric coupling model, and the stability index baseline value is calculated using the coupling relationship equation. The specific process includes: inputting the overshoot amplitude difference (e.g., 0.5V) and the recovery time ratio (e.g., 1.5), and calculating the baseline values of the first stability index and the second stability index using the coupling relationship equation. For example, the calculated baseline value of the first stability index is 0.6, and the baseline value of the second stability index is 0.8.

[0104] Step 206 , adjusting the weight distribution ratio of the initial weight coefficients in the asymmetric coupling model according to the step amplitude of the dynamic step load current and the dynamic compensation factor to generate a nonlinear weight distribution;

[0105] In this step, nonlinear weight distribution refers to the weight distribution ratio generated after adjusting the initial weighting coefficient according to the dynamic load characteristics (such as step amplitude and duration) and the dynamic compensation factor, which is used to quantify the contribution of stability indicators in different step intervals.

[0106] In this embodiment, the weight distribution ratio of the initial weighting coefficients is adjusted based on the step amplitude and dynamic compensation factor of the dynamic step load current to generate a nonlinear weight distribution. The specific process includes: extracting the step amplitude and dynamic compensation factor to calculate the weight adjustment coefficients; and modifying the initial weighting coefficients to generate a nonlinear weight distribution. For example, if the step amplitude is 50A and the dynamic compensation factor is 0.2, the nonlinear weight distribution is generated after adjustment.

[0107] For example, in the motherboard test described above, a basic model architecture is selected based on the power supply topology type defined in the hardware specification. The output capacitor ESR value, phase margin value, and switching device rise time value are extracted and standardized to generate the first, second, and third standardized parameters. The standardized parameters are input into the orthogonal experiment configuration module, and the initial weighting coefficient is determined through multi-factor variance analysis. Based on the step amplitude and duration of the dynamic step load current, the dynamic compensation factor is calculated to generate an asymmetric coupling model. The overshoot amplitude difference and recovery time ratio are input to calculate the stability index baseline value, and the initial weighting coefficient is adjusted based on the step amplitude and dynamic compensation factor to generate a nonlinear weight distribution.

[0108] In order to solve the problem that the traditional model is difficult to dynamically adapt to the influence of different load step characteristics on transient response, resulting in a large deviation between the stability evaluation result and the measured data, as another embodiment, according to step 204, the dynamic compensation factor of the basic model architecture is calculated according to the step amplitude and step interval duration of the dynamic step load current, and the initial weighting coefficient and the dynamic compensation factor are input into the coupling relationship equation to generate an asymmetric coupling model, including:

[0109] Step 301: Obtain a current step amplitude nominal value and a reciprocal of a current step interval duration of the dynamic step load current, calculate the product of the current step amplitude nominal value and the reciprocal to generate an initial step change rate, perform logarithmic processing on the initial step change rate and the third normalized parameter to generate a first compensation coefficient;

[0110] In this step, the initial step change rate is a parameter generated by multiplying the nominal step amplitude of the dynamic step load current by the inverse of the step interval duration. It is used to quantify the rate of sudden load changes. The first compensation coefficient is a correction coefficient generated by logarithmically processing the initial step change rate and the third normalized parameter. It is used to eliminate the impact of switching device response delay on the sudden load change rate.

[0111] In this embodiment, the current step amplitude nominal value of the dynamic step load current and the inverse of the current step interval duration are obtained, the initial step change rate is calculated and logarithmized, and the first compensation coefficient is generated.

[0112] Step 302: extracting a phase distribution difference value of the dynamic step load current in the multi-phase parallel power supply architecture based on the real-time load feedback parameter of the power management chip of the motherboard, and multiplying the phase distribution difference value by the first compensation coefficient to generate a phase correction factor;

[0113] In this step, the phase distribution difference value refers to the degree of imbalance in the load distribution between phases in a multiphase parallel power supply architecture and is used to quantify the impact of phase offset on the load change characteristics. The phase correction factor is a correction parameter generated by multiplying the phase distribution difference value by the first compensation coefficient. It is used to compensate for the phase delay effect in the multiphase power supply architecture.

[0114] In this embodiment, a phase distribution difference value in a multi-phase parallel power supply architecture is extracted based on real-time load feedback parameters of a power management chip, and the phase distribution difference value is multiplied by a first compensation coefficient to generate a phase correction factor.

[0115] Step 303: Add the phase correction factor to the initial step change rate to generate a composite step change rate, input the composite step change rate into the high-frequency response curve of the switching device of the basic model architecture, extract a gain compensation term corresponding to the composite step change rate, perform a convolution operation on the gain compensation term with the first normalization parameter to generate an impedance dynamic weight, and perform polarity matching on the impedance dynamic weight with the second normalization parameter to generate a loop stability correction value.

[0116] In this step, the composite step change rate refers to the combined load mutation rate generated by adding the phase correction factor to the initial step change rate. It is used to reflect the load mutation characteristics of a multi-phase power supply architecture. The gain compensation term refers to the gain correction parameter corresponding to the composite step change rate, extracted from the high-frequency response curve of the switching device. It is used to quantify the response characteristics of the high-frequency switching device to load mutations. The impedance dynamic weight refers to the parameter generated by convolving the gain compensation term with the first normalization parameter. It is used to reflect the dynamic impact of the output capacitor ESR on the transient response. The loop stability correction factor refers to the correction parameter generated by polarity matching the impedance dynamic weight with the second normalization parameter. It is used to quantify the contribution of loop stability to the transient response.

[0117] In this embodiment, a phase correction factor is added to the initial step rate to generate a composite step rate. The composite step rate is input into the high-frequency response curve of the switching device to extract a gain compensation term. The gain compensation term is convolved with the first normalization parameter to generate an impedance dynamic weight. The impedance dynamic weight is polarity-matched with the second normalization parameter to generate a loop stability correction.

[0118] Step 304: Calculate an amplitude attenuation factor of the initial weighting coefficient based on the percentage by which the step amplitude of the dynamic step load current exceeds the nominal value in the hardware specification, multiply the amplitude attenuation factor by the initial weighting coefficient to generate a dynamic weighting coefficient, and input the dynamically adjusted weighting coefficient, the gain compensation term, and the impedance dynamic weight into the coupling relationship equation to generate the asymmetric coupling model.

[0119] In this step, the amplitude attenuation factor is a correction factor calculated based on the percentage by which the dynamic step load current amplitude exceeds the nominal value specified in the hardware specification. This factor is used to dynamically adjust the initial weighting factor to accommodate varying load conditions. The dynamically adjusted weighting factor is a correction factor generated by multiplying the amplitude attenuation factor by the initial weighting factor. This correction factor reflects the impact of sudden load changes on the model's weight distribution.

[0120] In this embodiment, an amplitude attenuation factor is calculated based on the percentage by which the step amplitude of the dynamic step load current exceeds the nominal value specified in the hardware specification. The amplitude attenuation factor is multiplied by the initial weighting factor to generate a dynamically adjusted weighting factor. The dynamically adjusted weighting factor, the gain compensation term, and the impedance dynamic weight are input into the coupling relationship equation to generate an asymmetric coupling model.

[0121] For example, in the above-mentioned motherboard test, the nominal value of the step amplitude of the dynamic step load current and the inverse of the step interval duration are first obtained, the initial step change rate is calculated, and the first compensation coefficient is generated by logarithmic processing with the third standardized parameter. According to the real-time load feedback parameter of the power management chip, the phase distribution difference value is extracted to generate a phase correction factor. The phase correction factor is added to the initial step change rate to generate a composite step change rate, and the high-frequency response curve of the switching device is input to extract the gain compensation term. The gain compensation term is convolved with the first standardized parameter to generate an impedance dynamic weight, and the polarity is matched with the second standardized parameter to generate a loop stability correction. Based on the percentage of the step amplitude exceeding the nominal value, the amplitude attenuation factor is calculated to generate a dynamic adjustment weighting coefficient, which is finally input into the coupling relationship equation to generate an asymmetric coupling model.

[0122] Because traditional methods in motherboard testing have difficulty quantifying the impact of circuit board wiring impedance characteristics on the stability of the power supply output voltage, the stability evaluation results deviate significantly from the measured failure modes. In addition, the separate evaluation mechanism for high-frequency resonant energy and low-frequency steady-state offset is not yet perfected, and cannot accurately reflect the stability performance of the power supply system in different frequency bands. Based on this, as another embodiment, according to step 105, combined with the circuit board wiring impedance characteristic library of the motherboard, the stability level determination result of the power supply output voltage is output, including:

[0123] Step 401: extract the impedance values of multi-layer traces connected to the power output terminal of the mainboard, the coupling capacitance values of adjacent signal layers, and the length of the reference plane return path from the circuit board wiring impedance characteristic library to generate an impedance distribution vector;

[0124] In this step, the impedance distribution vector is a collection of physical layout parameters directly related to the motherboard power supply output, extracted from the PCB trace impedance characteristic library. These parameters include multi-layer trace impedance, coupling capacitance between adjacent signal layers, and reference plane return path length. This vector is used to quantify the combined impact of the PCB layout on the high-frequency resonance and low-frequency steady-state offset of the power supply output.

[0125] In this embodiment, the power network routing parameters in the PCB design file are first parsed to extract the impedance and capacitance values of the target layer; the return path length is verified using an electromagnetic simulation tool; and the above parameters are combined into an impedance distribution vector in a preset format.

[0126] Step 402 , performing impedance matching calculation on the multi-layer trace impedance values in the impedance distribution vector and the output capacitor equivalent series resistance values in the asymmetric coupling model to generate an impedance compensation factor;

[0127] In this step, impedance matching calculation involves comparing the physical correlation between the impedance of the PCB's multilayer traces and the equivalent series resistance of the power supply's output capacitors to generate a correction factor that reflects the synergistic effect of the two. This calculation aims to quantify the impact of PCB trace impedance on the transient response of the power supply output, thereby correcting the stability evaluation results of the asymmetric coupling model.

[0128] In this embodiment, the ratio of the multilayer trace impedance value to the output capacitor ESR value is calculated and combined with the normalized value of the reference plane return path length to generate an impedance compensation factor, which is used for subsequent weighted correction of the high-frequency resonant energy density.

[0129] Step 403: Input the reference value of the first stability index and the reference value of the second stability index into a time-frequency domain converter, and decompose the reference value of the first stability index and the reference value of the second stability index into a low-frequency component and a high-frequency oscillation component within the step interval of the dynamic step load current;

[0130] In this step, the time-to-frequency converter is a signal processing tool used to decompose the time-domain signal into frequency components in different frequency bands to separate low-frequency steady-state offsets and high-frequency oscillation characteristics. Low-frequency components are those associated with the steady-state response of the power supply, typically corresponding to the voltage recovery process after a load step. High-frequency oscillation components are high-frequency components in the signal caused by switching noise or resonance, typically corresponding to high-frequency oscillations during voltage transients.

[0131] In this embodiment, the reference value of the first stability index and the reference value of the second stability index are input into a time-frequency domain converter, and the low-frequency component and the high-frequency oscillation component within the step interval of the dynamic step load current are decomposed through wavelet transform or short-time Fourier transform. The specific process includes setting a time-frequency analysis window that matches the power switching frequency, performing time-frequency decomposition on the stability index reference value, and extracting the low-frequency component and the high-frequency oscillation component.

[0132] Step 404: Calculate the high-frequency resonance energy density based on the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer, and perform a weighted summation of the high-frequency resonance energy density and the impedance compensation factor to generate a resonance suppression score.

[0133] In this step, high-frequency resonance energy density is calculated by multiplying the amplitude-frequency characteristics of the high-frequency oscillation component by the coupling capacitance of the adjacent signal layer. It quantifies the potential threat of high-frequency resonance energy to power supply stability. The resonance suppression score is a comprehensive score generated by weighted summation of the high-frequency resonance energy density and the impedance compensation factor, reflecting the PCB layout's ability to suppress high-frequency resonance.

[0134] In this embodiment, the high-frequency resonance energy density is calculated based on the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer. The high-frequency resonance energy density is weighted and summed according to preset weights to generate a resonance suppression score.

[0135] Step 405: Input the low-frequency component into the asymmetric coupling model, redistribute the weight ratio of the low-frequency component using the nonlinear weight distribution to generate a steady-state offset score, and input the resonance suppression score and the steady-state offset score into a composite determination function according to the stability level mapping table defined in the hardware specification of the motherboard to generate a stability level determination result for the power supply output voltage.

[0136] In this step, the steady-state excursion score is generated by redistributing the weights of the low-frequency components into the asymmetric coupling model through a nonlinear weight distribution. This score quantifies the steady-state excursion of the power supply output voltage in the low-frequency range. The composite decision function is a decision logic generated by combining the resonance suppression score and the steady-state excursion score with the stability level mapping table defined in the hardware specification. This function is used to comprehensively evaluate the stability level of the power supply output voltage.

[0137] In this embodiment, the low-frequency component is input into the asymmetric coupling model, and the weight ratio is redistributed through a nonlinear weight distribution to generate a steady-state excursion score. Based on the stability level mapping table defined in the hardware specification, the resonance suppression score is input into a composite judgment function to generate a stability level judgment result (such as "Excellent").

[0138] For example, in the motherboard test described above, to determine the stability level, the impedance values of the multilayer traces connected to the power supply output, the coupling capacitance values of adjacent signal layers, and the reference plane return path length were first extracted from the circuit board wiring impedance characteristic library to generate an impedance distribution vector. The impedance matching between the multilayer trace impedance values and the output capacitor equivalent series resistance values was calculated, and the impedance compensation factor was generated by combining the normalized coefficient of the return path length. The stability index baseline value was then input into a time-frequency domain converter to decompose it into low-frequency and high-frequency oscillation components. The high-frequency resonant energy density was calculated based on the product of the high-frequency oscillation component and the coupling capacitance value, and then weighted summed with the impedance compensation factor to generate a resonance suppression score. The low-frequency component was then input into an asymmetric coupling model, and a nonlinear weight distribution was used to generate a steady-state offset score. Finally, based on the stability level mapping table defined in the hardware specification, a composite judgment function was used to output the stability level of the power supply output voltage as "Excellent." This fully demonstrates the synergy between the circuit board wiring impedance characteristics and the dynamic load test data, validating the closed-loop logic from load generation, signal analysis, and level determination.

[0139] In motherboard testing, the calculation of high-frequency resonance energy density is susceptible to interference from noise in non-target frequency bands, and traditional methods do not consider the dynamic impact of PCB layout parameters on high-frequency resonance energy, resulting in insufficient accuracy in resonance suppression scoring. In particular, in a multi-phase parallel power supply architecture, the superposition of high-frequency oscillations of different phases will further exacerbate the energy density calculation error. Based on this, as another embodiment, according to step 404, the high-frequency resonance energy density is calculated based on the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer, and the high-frequency resonance energy density and the impedance compensation factor are weighted and summed to generate a resonance suppression score, including:

[0140] Step 501: input the high-frequency oscillation component into a pre-built resonant frequency band separator, and extract the target oscillation frequency band corresponding to the odd harmonics of the switching frequency of the power topology structure of the mainboard;

[0141] In this step, a resonant frequency band separator, a filter device based on digital signal processing, extracts the target oscillation frequency band corresponding to the odd harmonics of the power topology switching frequency from the high-frequency oscillation component to shield against even harmonics and digital noise interference. The target oscillation frequency band corresponding to odd harmonics refers to the frequency range near the odd-order multiples of the power switching frequency. This frequency range is typically caused by the nonlinear characteristics of the switching device and is the primary source of high-frequency resonant energy.

[0142] In this embodiment, the high-frequency oscillation component is input into a pre-built resonant frequency band separator, with the target frequency band set to the odd harmonics of the power topology switching frequency. The specific process involves using bandpass filters to intercept the 1.5MHz±100kHz and 2.5MHz±100kHz frequency bands, filtering out noise from other frequency bands. Fast Fourier transform is then performed on the intercepted signals to verify spectral purity and extract the time domain waveform of the target oscillation frequency band.

[0143] Step 502 , calculating the average amplitude of the target oscillation frequency band within the dynamic step load current step interval, and multiplying the average amplitude by the adjacent signal layer coupling capacitance value to generate an initial resonant energy density;

[0144] In this step, the average amplitude refers to the average amplitude of the voltage waveform within the target oscillation frequency band within the dynamic step load current step interval, which is used to quantify the energy intensity of the high-frequency oscillation within this frequency band. The initial resonant energy density is a parameter generated by multiplying the average amplitude by the coupling capacitance value of the adjacent signal layer. It is used to characterize the original distribution density of the high-frequency resonant energy in a specific frequency band.

[0145] In this embodiment, the average amplitude of the target oscillation frequency band within the dynamic stepped load current step interval is calculated. The specific process includes performing a root mean square calculation on the time domain waveform of the target oscillation frequency band to obtain the average amplitude; and multiplying the average amplitude by the coupling capacitance value of the adjacent signal layer to generate the initial resonant energy density.

[0146] Step 503: extracting the skin effect attenuation coefficient corresponding to the reference plane return path length from the circuit board wiring impedance characteristic library, and performing an inverse proportional operation on the skin effect attenuation coefficient and the initial resonant energy density to generate a corrected resonant energy density;

[0147] In this step, the skin effect attenuation coefficient refers to the energy loss coefficient caused by the concentration of high-frequency current on the conductor surface (skin effect). Its value is positively correlated with the length of the reference plane return path; the longer the path, the more significant the attenuation. The corrected resonant energy density is the result of an inverse calculation of the initial resonant energy density and the skin effect attenuation coefficient. It is used to eliminate the transmission loss of high-frequency resonant energy in long return paths.

[0148] In this embodiment, the reference plane return path length is extracted from the circuit board wiring impedance characteristic library, and the initial resonant energy density and the attenuation coefficient are inversely proportionally calculated according to a preset skin effect attenuation coefficient table to generate a corrected resonant energy density.

[0149] Step 504: Calculate the phase dispersion of the target oscillation frequency band based on the phase switching interval of the power management chip of the motherboard in the multi-phase parallel power supply architecture, and convolve the phase dispersion with the corrected resonant energy density to generate a high-frequency resonant energy density.

[0150] In this step, the phase switching interval refers to the switching time interval between different phases in a multiphase parallel power supply architecture and is used to control the timing of load distribution between phases. Phase dispersion refers to the time offset between different phases of the target oscillation frequency band and is used to quantify the impact of phase asynchrony on high-frequency resonant energy distribution in multiphase power supply. Convolution processing involves mathematically convolving phase dispersion with the modified resonant energy density to integrate the correlation between the multiphase power supply timing characteristics and high-frequency energy distribution.

[0151] In this embodiment, the phase dispersion of the target oscillation frequency band is calculated based on the phase switching interval of the power management chip in a multi-phase parallel power supply architecture. The specific process involves extracting the time offset of the oscillation waveform for each phase, calculating the standard deviation as the phase dispersion, and performing a convolution operation on the phase dispersion with the corrected resonant energy density to generate the high-frequency resonant energy density.

[0152] Step 505: Input the high-frequency resonance energy density and the impedance compensation factor into a dynamic weight allocator, adjust the weight ratio of the impedance compensation factor according to the nominal value of the step amplitude of the dynamic step load current, and generate a resonance suppression score;

[0153] In this step, the dynamic weight allocator is an algorithm module that adjusts parameter weights in real time based on the nominal step amplitude of the dynamic stepped load current. This is used to optimize the coupling relationship between the impedance compensation factor and the high-frequency resonant energy density. The weight adjustment mechanism dynamically allocates the weight of the impedance compensation factor based on the nominal step amplitude to adapt to the resonance suppression requirements under different load impact intensities.

[0154] In this embodiment, the high-frequency resonant energy density and the impedance compensation factor are input into a dynamic weight allocator, and the weight ratios are adjusted based on the nominal step amplitude. The specific process includes: presetting a baseline weight ratio; modifying the impedance compensation factor weight and the high-frequency resonant energy density weight based on the percentage by which the nominal step amplitude exceeds the nominal value in the hardware specification; and finally generating a resonance suppression score.

[0155] For example, in the above-mentioned motherboard test, in order to accurately evaluate the high-frequency resonance suppression effect, the high-frequency oscillation component is first input into the pre-built resonant frequency band separator, and the target oscillation frequency band corresponding to the odd harmonics of the power topology switching frequency is extracted, and its average amplitude is calculated, and multiplied with the coupling capacitance value of the adjacent signal layer to generate the initial resonant energy density; then the skin effect attenuation coefficient corresponding to the reference plane return path length is extracted, and the energy density is corrected through inverse proportional operation; the phase discreteness of the target oscillation frequency band is calculated based on the multi-phase power supply phase switching interval, and the high-frequency resonant energy density is generated through convolution processing; finally, the high-frequency resonant energy density and the impedance compensation factor are input into the dynamic weight allocator, and the weight ratio is adjusted according to the nominal value of the step amplitude to generate a resonance suppression score.

[0156] In the motherboard power supply transient response test, traditional methods have two major drawbacks: insufficient timing synchronization accuracy and severe common-mode noise interference. Especially in high-frequency multi-phase power supply scenarios, it is difficult to accurately capture the details of voltage mutations and extract effective signals. Based on this, as another embodiment, according to step 102, a first synchronization window is set before each step switching moment of the dynamic step load current, and a second synchronization window is set after the step switching moment. A phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to collect voltage waveform data, including:

[0157] Step 601: parsing the step start time and the nominal step amplitude value in the step mark signal of the dynamic step load current, and calculating the ratio of the nominal step amplitude value to the maximum output current of the power management chip of the motherboard to generate a window reference width;

[0158] In this step, the step marker signal is the synchronous trigger signal generated during the dynamic step load current generation process. It contains timing and amplitude information such as the step start time and the nominal step amplitude. The window reference width is the sampling window time range dynamically generated based on the ratio of the nominal step amplitude to the maximum output current of the power management chip. It is used to adapt to the voltage waveform acquisition requirements under different load impact intensities.

[0159] In this embodiment, the step marker signal of the dynamic step load current is analyzed to extract the step start time and the nominal step amplitude. The maximum output current of the power management chip is read to calculate the window reference width. This width serves as the reference parameter for subsequent window division.

[0160] Step 602: Divide the window reference width into multiple sampling intervals synchronized with the switching cycle based on the switching frequency of the power topology of the motherboard, and extend the window reference width in the reverse direction by two switching cycles before the step start time to generate the initial boundary of the first synchronization window, and extend the window reference width in the forward direction by three switching cycles after the step start time to generate the initial boundary of the second synchronization window.

[0161] In this step, the power topology switching frequency refers to the operating frequency of the switching devices in the motherboard power circuit, which determines the power loop response speed and switching cycle duration. The switching cycle is the inverse of the switching frequency, that is, the complete duration of a single switching action. The sampling interval is the time unit that divides the window base width into equal parts according to the switching cycle, which is used to ensure that the sampling timing is strictly synchronized with the power switching action. The initial boundaries of the synchronization window are the pre-trigger and post-trigger sampling time ranges defined based on the step start time and the number of switching cycles. The range covers the complete transient response process before and after the step switching.

[0162] In this embodiment, the window reference width is divided into multiple sampling intervals synchronized with the switching cycles based on the switching frequency of the power supply topology. The initial boundary of the first synchronization window is generated by extending the window width in the reverse direction by two switching cycles before the step start time, and the initial boundary of the second synchronization window is generated by extending the window width in the forward direction by three switching cycles after the step start time.

[0163] Step 603: extracting the clock jitter parameter of the phase-locked trigger module and the trigger delay parameter of the high-precision oscilloscope, and inputting the difference between the clock jitter parameter and the trigger delay parameter into a phase error compensation algorithm to generate a first window boundary correction value and a second window boundary correction value;

[0164] In this step, the clock jitter parameter refers to the timing instability of the clock signal within the phase-locked trigger module (e.g., 0.1 μs), reflecting the deviation between the actual clock signal period and the theoretical value. The trigger delay parameter refers to the inherent delay time of a high-precision oscilloscope from receiving the trigger signal to starting sampling. The phase error compensation algorithm is a mathematical method that calculates the window boundary correction value based on the difference between clock jitter and trigger delay. It is used to eliminate the impact of hardware timing deviation on the synchronization accuracy of the sampling window. The window boundary correction value is the timing offset adjustment value generated by the compensation algorithm, which is used to correct the initial window boundary to ensure sub-microsecond synchronization.

[0165] In this embodiment, the clock jitter parameters of the phase-locked trigger module and the trigger delay parameters of a high-precision oscilloscope are extracted, the difference is calculated, and the difference is input into the phase error compensation algorithm. The algorithm uses this difference to generate first and second window boundary corrections, which are added to the initial boundaries of the first and second synchronization windows, respectively, to ensure that the window start time is strictly synchronized with the rising edge of the step marker signal.

[0166] Step 604: Superimpose the first window boundary correction amount on the initial boundary of the first synchronization window to generate a final boundary of the first synchronization window, and superimpose the second window boundary correction amount on the initial boundary of the second synchronization window to generate a final boundary of the second synchronization window, wherein the starting time of the final boundary is synchronized with the rising edge of the step marker signal at a sub-microsecond level.

[0167] In this step, the final boundary refers to the precise sampling time range generated by superimposing the initial boundary and the window boundary correction amount. Its starting time is synchronized with the rising edge of the step marker signal at the sub-microsecond level to ensure the timing consistency of the voltage waveform acquisition.

[0168] In this embodiment, the initial boundary of the first synchronization window is superimposed on the first window boundary correction amount to generate the final boundary of the first synchronization window. The initial boundary of the second synchronization window is superimposed on the second window boundary correction amount to generate the final boundary of the second synchronization window. The synchronization error between the starting time of the final boundary and the rising edge of the step marker signal is less than a standard value.

[0169] Step 605: Perform pre-trigger sampling within the final boundary of the first synchronization window to obtain a reference voltage waveform before the step switching, perform post-trigger sampling within the final boundary of the second synchronization window to obtain a transient voltage waveform after the step switching, input the reference voltage waveform and the transient voltage waveform into a differential amplifier for common-mode noise suppression, and generate voltage waveform data;

[0170] In this step, pre-trigger sampling refers to collecting the reference voltage waveform before the step switching moment (within the first synchronization window) to obtain the steady-state voltage reference value before the load mutation; post-trigger sampling refers to collecting the transient voltage waveform after the step switching moment (within the second synchronization window) to capture the dynamic characteristics of the voltage mutation and recovery process. A differential amplifier is a circuit device that suppresses common-mode noise through differential input. Its output is the difference between the two input signals, which can effectively eliminate common-mode interference such as digital circuit switching noise. Common-mode noise suppression refers to the technology of eliminating the same phase noise components in the reference voltage waveform and the transient voltage waveform through a differential amplifier, thereby improving the signal-to-noise ratio of the waveform data.

[0171] In this embodiment, pre-trigger sampling is performed within the final boundary of the first synchronization window to obtain the reference voltage waveform before the step switching. Post-trigger sampling is performed within the final boundary of the second synchronization window to obtain the transient voltage waveform after the step switching. These two waveforms are input into a differential amplifier, where common-mode noise is suppressed to generate debiased voltage waveform data.

[0172] For example, in the motherboard test, in order to further improve the accuracy of voltage waveform acquisition, the step marker signal of the dynamic step load current is first analyzed, the step start time and the nominal amplitude value are extracted, and the window reference width is generated in combination with the maximum output current of the power management chip; the sampling interval is divided according to the switching frequency of the power topology to generate the initial boundary of the first synchronization window and the initial boundary of the second synchronization window. The clock jitter parameters of the phase-locked trigger module and the oscilloscope trigger delay parameters are extracted, and the window boundary correction amount is generated through the phase error compensation algorithm to ensure that the start time is synchronized with the step marker signal at the sub-microsecond level. Pre-trigger sampling is performed in the first window to obtain the reference voltage waveform, and post-trigger sampling is performed in the second window to capture the transient voltage waveform. The digital circuit switching noise is suppressed by the differential amplifier to generate de-biased voltage waveform data.

[0173] In motherboard testing, traditional filtering methods cannot effectively separate signals from noise due to spectral overlap between digital circuit switching noise and the inherent response of the power supply, dynamic drift of the noise baseline with load, and nonlinear changes in transient characteristics. Furthermore, fixed thresholds or static windows make it difficult to accurately capture transient characteristics. Therefore, as another embodiment, according to step 103, the voltage waveform data is input into a preset filtering algorithm to separate the inherent response of the power management chip from the digital circuit switching noise to extract the overshoot amplitude and recovery time, including:

[0174] Step 701: extracting the fundamental frequency component of the periodic switching noise from the voltage waveform data based on the clock frequency distribution characteristics of the digital circuit of the mainboard, and generating a noise baseline template;

[0175] In this step, the noise baseline template is a periodic switching noise reference waveform generated based on the clock frequency distribution characteristics of the motherboard's digital circuits. It is used to separate the noise component from the voltage waveform data. The core of this process is to extract the fundamental frequency component of the digital circuit switching noise and construct a template that matches the spectral characteristics of the noise signal.

[0176] In this embodiment, the digital circuit clock fundamental frequency component is extracted from the voltage waveform data, and its spectrum peak is identified by fast Fourier transform (FFT) to generate a periodic noise baseline template.

[0177] Step 702: Input the voltage waveform data and the noise baseline template into an empirical mode decomposer, and use an adaptive decomposition algorithm to separate the intrinsic mode function components containing the inherent response of the power management chip;

[0178] In this step, the empirical mode decomposer (EMD), an adaptive signal decomposition tool, decomposes complex signals into multiple intrinsic mode function (IMF) components through an iterative screening process. Each IMF represents an oscillation characteristic of the signal at a different time scale. IMF components are signal components that meet the narrowband stationary condition and can effectively separate the inherent response of the power management chip from high-frequency noise.

[0179] In this embodiment, the voltage waveform data and a noise baseline template are fed into an empirical mode decomposer (EMD), where an adaptive decomposition algorithm is used to isolate the IMF components. This process involves calculating the mean of the upper and lower envelopes of the signal, iteratively extracting the IMFs until the residual is monotonic, and filtering out low-frequency IMF components that represent the inherent response of the power supply.

[0180] Step 703: Input the intrinsic mode function components into a waveform reconstructor, filter the effective harmonic components according to the integer multiple frequency points of the switching frequency of the power supply topology structure of the mainboard, and generate a denoised power supply intrinsic response waveform;

[0181] In this step, the waveform reconstructor is a device that selects effective harmonic components based on preset frequencies and synthesizes a denoised waveform. Effective harmonic components refer to IMF components that match integer multiples of the power topology switching frequency and are used to reconstruct the denoised power supply's intrinsic response waveform.

[0182] In this embodiment, the IMF component is input into the waveform reconstructor, the effective harmonic component is screened according to the multiple frequency points of the power switching frequency, and the de-noised power supply intrinsic response waveform is generated by weighted superposition.

[0183] Step 704: Locate a voltage mutation point corresponding to the step switching moment of the dynamic step load current in the inherent response waveform of the power supply, and trace back a first preset time period based on the voltage mutation point to generate an overshoot detection window, and trace back a second preset time period to generate a recovery detection window.

[0184] In this step, the voltage mutation point refers to the starting position of the voltage waveform jump corresponding to the moment of the dynamic step load current step switching, and is located by detecting the extreme value of the signal's first-order derivative. The overshoot detection window and recovery detection window are dynamic time ranges extending forward and backward from the voltage mutation point, respectively, to accurately capture the overshoot amplitude and recovery time.

[0185] In this embodiment, the voltage mutation point is located in the de-noised power supply intrinsic response waveform by calculating the first-order derivative extreme value. An overshoot detection window is generated by tracing back a first preset time period, and a recovery detection window is generated by tracing back a second preset time period.

[0186] Step 705: Calculate the difference between the peak voltage and the steady-state voltage of the power supply inherent response waveform within the overshoot detection window to generate an overshoot amplitude; and calculate the time required for the power supply inherent response waveform to decay from the peak voltage to a value within a preset range of the steady-state voltage within the recovery detection window to generate a recovery time.

[0187] In this step, the overshoot amplitude is the difference between the peak voltage and the steady-state voltage within the overshoot detection window, reflecting the transient overshoot of the power supply output voltage. The recovery time is the time required for the voltage within the recovery detection window to decay from the peak value to the preset steady-state voltage range, reflecting the dynamic response speed of the power supply loop.

[0188] In this embodiment, the difference between the peak voltage and the steady-state voltage is calculated in the overshoot detection window to generate the overshoot amplitude; the time it takes for the voltage to decay to 1.2V±5% (1.14V to 1.26V) is detected in the recovery detection window to generate the recovery time.

[0189] For example, in the motherboard test described above, to accurately separate the intrinsic response of the power management chip from the switching noise of the digital circuits, the system first extracts the frequency distribution characteristics of the motherboard's digital circuit clock. A fast Fourier transform is then used to extract the fundamental frequency component of the periodic switching noise from the voltage waveform data, generating a noise baseline template. The voltage waveform data and the noise template are then fed into an empirical mode decomposer, where an adaptive decomposition algorithm is used to separate the intrinsic mode function (IMF) components and filter out low-frequency IMFs that contain the intrinsic response of the power supply. Subsequently, a waveform reconstructor is used to synthesize the de-noised intrinsic response waveform based on integer multiples of the power supply topology's switching frequency. The voltage abrupt change corresponding to the switching moment of a dynamic step-type load current is located, and an overshoot detection window is generated by tracing back 2μs, while a recovery detection window is generated by tracing back 5μs. Within the overshoot window, the difference between the peak voltage and the steady-state voltage is calculated to generate the overshoot amplitude. Within the recovery window, the time it takes for the voltage to decay to the steady-state range is measured to generate the recovery time. This noise suppression reduces overshoot amplitude detection error and improves recovery time accuracy.

[0190] Figure 2 The present invention provides a schematic diagram of a system for testing the output voltage stability of a motherboard power supply. Figure 2 As shown, the system includes:

[0191] a generating module 21 for generating a dynamic stepped load current through a nonlinear compensation load generator based on load demand parameters fed back by a power management chip of the motherboard and the extreme operating conditions defined in the hardware specification of the motherboard when the motherboard operates in a preset multi-mode switching state;

[0192] a setting module 22 for setting a first synchronization window before each step switching moment of the dynamic step load current and setting a second synchronization window after the step switching moment, and using a phase-locked trigger module to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to acquire voltage waveform data;

[0193] A separation module 23 is configured to input the voltage waveform data into a preset filtering algorithm to separate the inherent response of the power management chip and the switching noise of the digital circuit to extract the overshoot amplitude and recovery time;

[0194] a calculation module 24 configured to construct an asymmetric coupling model based on characteristic parameters of the power supply topology of the motherboard, use the difference between the overshoot amplitude and a preset fluctuation range as a first stability indicator, and the ratio of the recovery time to the response time threshold as a second stability indicator, and calculate the nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals using the asymmetric coupling model;

[0195] The output module 25 is used to output the stability level determination result of the power supply output voltage in combination with the circuit board wiring impedance characteristic library of the mainboard.

[0196] Figure 2 The motherboard power supply output voltage stability test system can be performed Figure 1 The implementation principles and technical effects of the motherboard power supply output voltage stability testing method described in the illustrated embodiment are not further elaborated. The specific manner in which the various modules and units perform operations in the motherboard power supply output voltage stability testing system in the aforementioned embodiment have been described in detail in the related embodiments of the method and will not be further elaborated here.

[0197] In one possible design, Figure 2 A motherboard power supply output voltage stability test system of the embodiment shown can be implemented as a computing device, such as Figure 3 As shown, the computing device may include a storage component 31 and a processing component 32;

[0198] The storage component 31 stores one or more computer instructions, wherein the one or more computer instructions are called and executed by the processing component 32 .

[0199] The processing component 32 is configured to generate a dynamic step load current using a nonlinear compensation load generator based on load demand parameters fed back by the power management chip of the motherboard and the extreme operating conditions defined in the hardware specification of the motherboard when the motherboard is operating in a preset multi-mode switching state; set a first synchronization window before each step switching moment of the dynamic step load current and a second synchronization window after the step switching moment, and synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal using a phase-locked trigger module to collect voltage waveform data; input the voltage waveform data into a preset filtering algorithm to separate the inherent response of the power management chip from the switching noise of the digital circuit to extract the overshoot amplitude and recovery time; construct an asymmetric coupling model based on the characteristic parameters of the power topology structure of the motherboard, use the difference between the overshoot amplitude and the preset fluctuation range as a first stability indicator, and the ratio of the recovery time to the response time threshold as a second stability indicator, and use the asymmetric coupling model to calculate the nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals; and output a stability level determination result of the power supply output voltage in combination with the circuit board wiring impedance characteristic library of the motherboard.

[0200] The processing component 32 may include one or more processors to execute computer instructions to perform all or part of the steps in the above method. Of course, the processing component may also be implemented as one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above method.

[0201] The storage component 31 is configured to store various types of data to support operations at the terminal. The storage component can be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0202] Of course, a computing device may also include other components, such as input / output interfaces, display components, communication components, etc.

[0203] The input / output interface provides an interface between the processing component and the peripheral interface module, which can be an output device, an input device, etc.

[0204] The communication component is configured to facilitate, among other things, wired or wireless communications between the computing device and other devices.

[0205] Among them, the computing device can be a physical device or an elastic computing host provided by a cloud computing platform, etc. In this case, the computing device can refer to a cloud server, and the above-mentioned processing components, storage components, etc. can be basic server resources rented or purchased from the cloud computing platform.

[0206] The present application also provides a computer storage medium storing a computer program, wherein the computer program can achieve the above-mentioned Figure 1 A method for testing the stability of a motherboard power supply output voltage is shown in the embodiment.

[0207] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0208] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0209] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0210] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for testing the stability of a motherboard power supply output voltage, characterized in that: include: When the motherboard is operating in a preset multi-mode switching state, a dynamic step load current is generated by a nonlinear compensation load generator based on the load demand parameters fed back by the power management chip of the motherboard and the extreme operating conditions defined in the hardware specification of the motherboard; A first synchronization window is set before each step switching moment of the dynamic step load current, and a second synchronization window is set after the step switching moment, and a phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to acquire voltage waveform data; Inputting the voltage waveform data into a preset filtering algorithm to separate the inherent response of the power management chip from the switching noise of the digital circuit to extract the overshoot amplitude and recovery time; An asymmetric coupling model is constructed based on characteristic parameters of the power supply topology of the motherboard, a difference between the overshoot amplitude and a preset fluctuation range is used as a first stability indicator, a ratio of the recovery time to a response time threshold is used as a second stability indicator, and a nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals is calculated using the asymmetric coupling model; Combined with the circuit board wiring impedance characteristic library of the mainboard, a stability level determination result of the power supply output voltage is output.

2. The method according to claim 1, characterized in that An asymmetric coupling model is constructed based on characteristic parameters of the power supply topology structure of the motherboard, a difference between the overshoot amplitude and a preset fluctuation range is used as a first stability indicator, and a ratio of the recovery time to a response time threshold is used as a second stability indicator. The asymmetric coupling model is used to calculate a nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals, including: Based on the power topology type defined in the hardware specification of the motherboard, selecting a basic model architecture corresponding to the power topology type, wherein the basic model architecture includes: a coupling relationship equation of the output capacitor equivalent series resistance, the feedback loop phase margin, and the rise time of the switching device; Decomposing the output capacitor equivalent series resistance value, the feedback loop phase margin value, and the switching device rise time value in the power topology characteristic parameters of the mainboard, performing impedance dimension normalization on the output capacitor equivalent series resistance value to generate a first standardized parameter, performing angle-time conversion on the feedback loop phase margin value to generate a second standardized parameter, and performing time dimension normalization on the switching device rise time value to generate a third standardized parameter; Inputting the first standardized parameter, the second standardized parameter, and the third standardized parameter into a preset orthogonal experiment configuration module, and using multi-factor variance analysis to determine initial weighting coefficients of the output capacitor equivalent series resistance value, the feedback loop phase margin value, and the switching device rise time value in the basic model architecture; Calculating a dynamic compensation factor of the basic model architecture according to the step amplitude and step interval duration of the dynamic stepped load current, and inputting the initial weighting coefficient and the dynamic compensation factor into the coupling relationship equation to generate an asymmetric coupling model; Inputting the difference between the overshoot amplitude and the preset fluctuation range into the asymmetric coupling model, and calculating the reference value of the first stability indicator using the coupling relationship equation; inputting the ratio of the recovery time to the response time threshold into the asymmetric coupling model, and calculating the reference value of the second stability indicator using the coupling relationship equation; According to the step amplitude of the dynamic step load current and the dynamic compensation factor, the weight distribution ratio of the initial weight coefficient in the asymmetric coupling model is adjusted to generate a nonlinear weight distribution.

3. The method according to claim 2, characterized in that The method further comprises: calculating a dynamic compensation factor of the basic model architecture according to the step amplitude and step interval duration of the dynamic step load current, and inputting the initial weighting coefficient and the dynamic compensation factor into the coupling relationship equation to generate an asymmetric coupling model, including: Obtaining a current step amplitude nominal value and a reciprocal of a current step interval duration of the dynamic step load current, calculating a product of the current step amplitude nominal value and the reciprocal to generate an initial step change rate, performing logarithmic processing on the initial step change rate and the third normalized parameter to generate a first compensation coefficient; extracting a phase distribution difference value of the dynamic stepped load current in the multi-phase parallel power supply architecture based on real-time load feedback parameters of the power management chip of the motherboard, and multiplying the phase distribution difference value by the first compensation coefficient to generate a phase correction factor; adding the phase correction factor to the initial step change rate to generate a composite step change rate, inputting the composite step change rate into a high-frequency response curve of a switching device of the basic model architecture, extracting a gain compensation term corresponding to the composite step change rate, performing a convolution operation on the gain compensation term and the first normalization parameter to generate an impedance dynamic weight, and performing polarity matching on the impedance dynamic weight and the second normalization parameter to generate a loop stability correction value; According to the percentage by which the step amplitude of the dynamic step load current exceeds the nominal value of the hardware specification, the amplitude attenuation factor of the initial weighting coefficient is calculated, the amplitude attenuation factor is multiplied by the initial weighting coefficient to generate a dynamic adjustment weighting coefficient, and the dynamically adjusted weighting coefficient, the gain compensation term and the impedance dynamic weight are input into the coupling relationship equation to generate the asymmetric coupling model.

4. The method according to claim 1, wherein In combination with the circuit board wiring impedance characteristic library of the mainboard, outputting the stability level determination result of the power supply output voltage includes: Extracting the impedance values of multi-layer traces connected to the power output terminal of the mainboard, the coupling capacitance values of adjacent signal layers, and the length of the reference plane return path from the circuit board wiring impedance characteristic library to generate an impedance distribution vector; Calculate impedance matching between the multi-layer trace impedance value in the impedance distribution vector and the output capacitor equivalent series resistance value in the asymmetric coupling model to generate an impedance compensation factor; Inputting the reference value of the first stability index and the reference value of the second stability index into a time-frequency domain converter, and decomposing the reference value of the first stability index and the reference value of the second stability index within a step interval of the dynamic step load current into a low-frequency component and a high-frequency oscillation component; Calculating a high-frequency resonance energy density based on the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer, and performing a weighted summation of the high-frequency resonance energy density and the impedance compensation factor to generate a resonance suppression score; The low-frequency component is input into the asymmetric coupling model, and the weight ratio of the low-frequency component is redistributed through the nonlinear weight distribution to generate a steady-state offset score. According to the stability level mapping table defined in the hardware specification of the motherboard, the resonance suppression score and the steady-state offset score are input into a composite judgment function to generate a stability level judgment result of the power supply output voltage.

5. The method according to claim 4, characterized in that Calculating a high-frequency resonance energy density according to the product of the amplitude-frequency characteristic of the high-frequency oscillation component and the coupling capacitance value of the adjacent signal layer, and performing weighted summation of the high-frequency resonance energy density and the impedance compensation factor to generate a resonance suppression score, including: Inputting the high-frequency oscillation component into a pre-built resonant frequency band separator and extracting a target oscillation frequency band corresponding to an odd-order harmonic of the switching frequency of the power topology structure of the mainboard; Calculating an average amplitude of the target oscillation frequency band within the dynamic stepped load current step interval, and multiplying the average amplitude by the adjacent signal layer coupling capacitance value to generate an initial resonant energy density; Extracting a skin effect attenuation coefficient corresponding to the reference plane return path length from the circuit board wiring impedance characteristic library, and performing an inverse proportional operation on the skin effect attenuation coefficient and the initial resonant energy density to generate a corrected resonant energy density; Calculating the phase dispersion of the target oscillation frequency band according to the phase switching interval of the power management chip of the motherboard in the multi-phase parallel power supply architecture, and performing a convolution process on the phase dispersion and the corrected resonant energy density to generate a high-frequency resonant energy density; The high-frequency resonance energy density and the impedance compensation factor are input into a dynamic weight allocator, and the weight ratio of the impedance compensation factor is adjusted according to the step amplitude nominal value of the dynamic step load current to generate a resonance suppression score.

6. The method according to claim 1, characterized in that A first synchronization window is set before each step switching moment of the dynamic step load current, and a second synchronization window is set after the step switching moment, and a phase-locked trigger module is used to synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal to acquire voltage waveform data, including: parsing the step start time and the step amplitude nominal value in the step mark signal of the dynamic step load current, and calculating the ratio of the step amplitude nominal value to the maximum output current of the power management chip of the mainboard to generate a window reference width; Divide the window reference width into a plurality of sampling intervals synchronized with the switching cycle according to the switching frequency of the power topology of the mainboard, and extend the initial boundary of the first synchronization window in the reverse direction by two switching cycles before the step start time, and extend the initial boundary of the second synchronization window in the forward direction by three switching cycles after the step start time; Extracting a clock jitter parameter of the phase-locked trigger module and a trigger delay parameter of the high-precision oscilloscope, inputting a difference between the clock jitter parameter and the trigger delay parameter into a phase error compensation algorithm to generate a first window boundary correction amount and a second window boundary correction amount; Superimposing the first window boundary correction amount on the initial boundary of the first synchronization window to generate a final boundary of the first synchronization window, and superimposing the second window boundary correction amount on the initial boundary of the second synchronization window to generate a final boundary of the second synchronization window, wherein the starting time of the final boundary is synchronized with the rising edge of the step mark signal at a sub-microsecond level; Pre-trigger sampling is performed within the final boundary of the first synchronization window to obtain a reference voltage waveform before the step switching, and post-trigger sampling is performed within the final boundary of the second synchronization window to obtain a transient voltage waveform after the step switching. The reference voltage waveform and the transient voltage waveform are input into a differential amplifier for common-mode noise suppression to generate voltage waveform data.

7. The method according to claim 1, characterized in that Inputting the voltage waveform data into a preset filtering algorithm to separate the inherent response of the power management chip from the switching noise of the digital circuit to extract the overshoot amplitude and recovery time, including: Based on the clock frequency distribution characteristics of the digital circuit of the motherboard, the fundamental frequency component of the periodic switching noise is extracted from the voltage waveform data to generate a noise baseline template; Inputting the voltage waveform data and the noise baseline template into an empirical mode decomposer, and using an adaptive decomposition algorithm to separate the intrinsic mode function components containing the inherent response of the power management chip; Inputting the intrinsic mode function components into a waveform reconstructor, screening effective harmonic components according to integer multiples of the switching frequency of the power topology structure of the mainboard, and generating a denoised power supply intrinsic response waveform; In the inherent response waveform of the power supply, a voltage mutation point corresponding to the step switching moment of the dynamic step load current is located, and an overshoot detection window is generated by tracing back a first preset time length based on the voltage mutation point, and a recovery detection window is generated by tracing back a second preset time length; In the overshoot detection window, the difference between the peak voltage and the steady-state voltage of the power supply inherent response waveform is calculated to generate the overshoot amplitude. In the recovery detection window, the time required for the power supply inherent response waveform to decay from the peak voltage to a preset range value of the steady-state voltage is calculated to generate the recovery time.

8. A motherboard power supply output voltage stability test system, characterized in that: include: a generating module for generating a dynamic stepped load current through a nonlinear compensation load generator based on load demand parameters fed back by a power management chip of the motherboard and extreme operating conditions defined in the hardware specification of the motherboard when the motherboard operates in a preset multi-mode switching state; a setting module, configured to set a first synchronization window before each step switching moment of the dynamic stepped load current, and set a second synchronization window after the step switching moment, and synchronize the acquisition timing of a high-precision oscilloscope with the load switching signal using a phase-locked trigger module to acquire voltage waveform data; a separation module, configured to input the voltage waveform data into a preset filtering algorithm, separate the inherent response of the power management chip from the switching noise of the digital circuit, and extract the overshoot amplitude and recovery time; a calculation module, configured to construct an asymmetric coupling model based on characteristic parameters of the power supply topology of the motherboard, use a difference between the overshoot amplitude and a preset fluctuation range as a first stability indicator, and a ratio of the recovery time to a response time threshold as a second stability indicator, and calculate a nonlinear weight distribution of the first stability indicator and the second stability indicator in multiple step intervals using the asymmetric coupling model; The output module is used to output the stability level determination result of the power supply output voltage in combination with the circuit board wiring impedance characteristic library of the mainboard.

9. A computing device, characterized in that It comprises a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are used to be called and executed by the processing component to implement a motherboard power supply output voltage stability testing method as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that A computer program is stored, and when the computer program is executed by a computer, a method for testing the output voltage stability of a mainboard power supply according to any one of claims 1 to 7 is implemented.

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