Receiving device based on X-band radar

Abstract

The invention relates to the technical field of signal receiving, and discloses a receiving device based on an X-band radar, which adopts an external clock source and an external synchronization source to connect two receiving plates, so that the system phase of the whole receiving device is synchronized with a clock, and the receiving device is used for 16-channel receiving. The external clock source and the synchronous source are arranged, the two receiving plates are connected together, clock signal synchronization of the whole system is ensured, stable clock signals are provided for the receiving units, jitter is reduced, the synchronization precision is improved, the external clock is designed into two paths, and the two paths are respectively input to each receiving unit to ensure clock synchronization of each receiving unit, so that the synchronization precision of the receiving units is improved. The beneficial effects that signal receiving among multiple boards is met, signal clock synchronization and signal phase consistency are achieved, and all system units interact with one another are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of signal reception, and in particular to a receiving device based on X-band radar. Background Art

[0002] With the rapid development of radar in recent years, the requirements for X-band signal generation, intermediate frequency data acquisition and storage systems, which are important parts, have become increasingly higher. For example, higher requirements are placed on the sampling rate, resolution, storage depth, digital signal processing speed, and anti-interference capability of the data acquisition system.

[0003] Currently, the X-band signal receiving devices on the market are imperfect, and most of them are separate receiving devices. Secondly, X-band reception usually uses S-band input signals to convert the frequency to X-band and amplify the output, and then down-converts the received X-band signal to L-band, and samples and stores the L-band signal. Summary of the Invention

[0004] Technical issues solved: In response to the shortcomings of the existing technology, the present invention provides a receiving device based on X-band radar, which can meet the signal reception needs of multiple boards, achieve signal clock synchronization, signal phase consistency, and interaction between various system units; effectively receive, store and display X-band radar signals, so that the entire signal acquisition and processing system has the advantages of high reliability and high stability, thereby solving the problems of the above-mentioned technologies.

[0005] Technical solution: To achieve the above object, the present invention provides the following technical solution: a receiving device based on X-band radar, wherein the receiving device uses an external clock source and an external synchronization source to connect two receiving boards so that the system phase of the entire receiving device is synchronized with the clock, and is used for 16-channel reception. The receiving device is also equipped with a signal receiving unit, and the signal receiving unit has an external trigger interface on the hardware interface and provides 2 12-pin GPIO TTL level interface directly connected to FPGA pins to achieve serial port control and multi-channel trigger signal functions; The receiving device also integrates a receiving system, a storage system, a clock system, a network system and a power supply system.

[0006] Preferably, the signal receiving unit supports trigger output and trigger input functions.

[0007] Preferably, the 16 receiving channels use the Zynq UltraScale+RFSoC ZU47DR chip, which supports 8-channel receiving function, and the two signal receiving units support up to 16-channel reception; the external clock unit is divided into two clocks to enter each receiving unit to complete clock synchronization, and then divided into two synchronous clocks to enter each receiving unit to complete phase synchronization.

[0008] Preferably, the 16 receiving channels are used for 1200MHz±300MHz intermediate frequency signal acquisition, and the signal acquisition includes: circuit design signal receiving unit 1 integrates 8-channel ADC on board, with a design sampling rate of 1.6Gsps; signal receiving unit 2 integrates 8-channel ADC on board, with a maximum sampling rate of 1.6Gsps, meeting the target frequency band 1200MHz±300MHz 16-channel signal reception function; IF input power -30 ~ 0dBm: The analog front end uses Balun MABA-011108 to convert single-ended signals to differential signals. MABA-011108 is used in 1G ~ Insertion loss is 1.4dB in the 6GHz range ~ 1.7dB, the signal amplitude is reduced to 5 / 6 of the original, and the signal amplitude input to the ADC is 16.7mV ~ 527mV.

[0009] Preferably, the external clock unit first uses the clock board LMK04828, and the clock board LMK04828 has two phase-locked loops PLL configured internally. The first phase-locked loop PLL1 provides a low-noise jitter eliminator function, and the second phase-locked loop PLL2 performs clock and SYSREF generation. Secondly, the LMX2594 clock chip is used, and the two LMX2594s provide clock signals to the signal receiving unit.

[0010] Preferably, the receiving device also includes a signal control unit, which is provided with two 12-pin GPIO interfaces. The two receiving units have a total of four GPIO interfaces. An RS232 to RS422 module is used to generate control signals. The level standard is 3.3V. The hardware design meets a total of 6 RS422 outputs and 6 independent trigger outputs. All control pins are directly connected to the FPGA, and the required signals can be controlled through the logic layer.

[0011] Preferably, the hardware of the receiving device is also provided with an RJ45 network port. The receiving device has two network port signals, which are output and interact with the host computer. A gigabit network port switch design is adopted, and data is interacted with the PC through an industrial-grade router. The receiving device also includes a receiving data transmission unit, which provides two QSFP28 optical fiber interfaces. The two optical fiber interfaces are respectively connected to the GTY receivers on BANK128 and BAN129 of the Zynq UltraScale+RFSoC ZU47DR chip. The two reference clocks of BANK128 and BAN129 are respectively provided by differential crystal oscillators at 156.25 MHz, and the data is transmitted to the storage recording unit through the QSFP interface.

[0012] Preferably, the storage capacity of the storage system is ≥ 4T 2B, and the total storage rate is ≥28.8Gbps, using two storage recording units QTC4000 for local data dump function. The storage system includes a storage recording unit, which is: an industry-standard 8-disk 7mm thick 2.5-inch SSD structure storage device with a QSFP optical port for data transmission, storing the data received by 16 channels.

[0013] Preferably, the receiving device also includes a software programming unit, which provides a host computer software for controlling the communication function of the host receiving radio frequency module, realizing the control of the device through the network port, and performing time domain display and frequency domain display of the received signal, data reading and writing, and storage.

[0014] Preferably, the power supply system uses a 350W single-group output DC / DC converter, and the output voltage range of SD-350C-12 is 36V. ~ 72VDC is fed into two receiving units, each with 12V DC. The DC12V is then transferred to three power supplies through a two-input and six-output terminal block to power the two storage and recording units and the switch respectively. The receiving device model adopts a standard 4U chassis with air cooling. The signal receiving unit structure layout adopts front and rear wiring method. The external clock signal, 16-channel reception, 6-channel trigger signal and 6-channel RS422 serial port signals are all distributed on the front panel. At the same time, the front panel has three external indicator light signals to display the status of the receiving device.

[0015] Compared with the prior art, the present invention provides a receiving device based on X-band radar, which has the following beneficial effects: 1. The present invention is equipped with an external clock source and a synchronization source. By connecting two receiving boards together, the clock signal of the entire system is ensured to be synchronized, a stable clock signal is provided for the receiving unit, jitter is reduced and synchronization accuracy is improved. The external clock is designed to be two-way, which is input to each receiving unit respectively to ensure the clock synchronization of each unit. The clock signal is then distributed to each channel to maintain phase consistency. The receiving device includes a signal control unit with multiple GPIO interfaces. The control instructions are transmitted to the FPGA through the RS232 to RS422 module, thereby realizing the generation and processing of control signals. The direct signal interaction improves the coordination and response speed between system components. The Gigabit Ethernet port is used to connect to the PC Data exchange is carried out to achieve efficient data transmission and information sharing, which improves the linkage capability between various system units and ensures real-time monitoring and management of receiving status. The data storage rate higher than 28.8Gbps meets the real-time recording needs of large amounts of data. It is linked to the storage and recording unit through the QSFP28 optical fiber interface to ensure that the received signal data can be stored quickly and effectively and can be quickly called in the later analysis. Through the supporting software program control unit, the user controls the host to display, read, write and store data in the time domain and frequency domain, achieving the beneficial effects of meeting the signal reception between multiple boards, realizing signal clock synchronization, signal phase consistency, and mutual interaction between various system units.

[0016] 2. The present invention integrates a high-performance analog-to-digital converter (ADC) through the signal receiving unit, with a sampling rate of 1.6Gsps, which can accurately capture rapidly changing radar signals and improve the capture accuracy. The Balun component is used for signal conversion to optimize the input quality of the signal, thereby improving the effectiveness of signal reception. The advanced clock board LMK04828 and PLL technology are selected to ensure low noise and high stability of the clock signal, reducing the signal error caused by clock instability, so that each receiving unit can receive a clock signal that has been accurately matched and adjusted, thereby ensuring that all parts of the system can maintain phase consistency when collecting signals, increasing the reliability of the system. The storage system is designed with a storage capacity of ≥4T and a total rate of ≥28.8Gbps, which can meet the needs of high data traffic, prevent data loss, and ensure High-frequency signals can still be stored efficiently when received, and the industrial standard SSD structure and QSFP optical port are used for data transmission, which reduces external interference and improves the reliability of data storage. Fast data interaction and control are carried out through RS422 and network interfaces. Rapid feedback from interaction with the PC helps to monitor the signal reception status in real time, improving the system's ability to respond to abnormal situations. The host computer software is provided for signal control and real-time display and recording of data, which enhances the intuitiveness of operation and further improves the convenience and stability of system use. By using a 350W single-group output DC / DC converter, the power supply of the entire system is ensured to be stable, avoiding system failures caused by unstable power supply, achieving effective reception, storage and display of X-band radar signals, and making the entire signal acquisition and processing system have the beneficial effects of high reliability and high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of 16-channel receiving in the present invention; Figure 2 Schematic diagram of the external clock unit of the present invention; Figure 3 This is a schematic diagram of a data transmission unit of the present invention; Figure 4 This is a schematic diagram of the power supply unit of the present invention; Figure 5 Schematic diagram of the interior of the receiving device of the present invention. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] Example 1 See also Figure 1-5 , clock unit, the external input reference clock fans out 5 pairs of clock signals through LMK04828. Three of the clock signals are provided to the clock chip LMX2594 respectively, and then the LMX2594 fans out the sampling clock required by AD. The other two clocks are used as AXI4-Stream clocks. The external input synchronization clock fans out 6 clock signals through LMK04828. Among them, three clock signals are RF_ADC_SYNC (shared by two LMX2594s), RF_ADC_SysRefReq (shared by two LMX2594s), and the other three clocks, 1 clock signal Analog_SYSREF_ADC is used as the analog reference synchronization clock of the FPGA, and 1 clock signal USER_SYSREF_ADC is used as the synchronization reference clock of the ADC chip on the PL side. In this way, the clock and phase synchronization of the two receiving units is achieved, and 16-channel reception is realized. The QTC4000 uses the reserved QSFP optical port on the QT2347DR for data transmission. Each QTC4000 supports 8TB of storage, for a total of 16TB of storage with two units. Each signal receiving unit is paired with a storage recording unit. The data rate calculation for a single signal receiving unit, 8 channels at 1.6 GSPS, and 100µs of data acquisition with a 5% duty cycle is as follows.

[0020] Data instantaneous bandwidth: 1.6Gsps 8chan 12bit=19.2GB / s Total data volume of a single acquisition: 1.6Gsps 8chan 12bit 100us=1920000Byte Data rate at 5% repetition duty cycle: 19.2 GB / s 5% = 960MB / s Number of BRAMs occupied in the FPGA: 15360000bit / (8×36×1024bit) = 416.6667 ≈ 417 36Kbit BRAMs The actual usage is approximately: 425 36K BRAMs + 5 18K BRAMs. (768-bit width, 20,000 depth) The RFSoC 47DR features 1080 BRAMs and 80 URAMs. The BRAM or URAM space on the onboard FPGA can buffer 100µs of sampled data across 8 channels. At a 5% repetition rate duty cycle (500 triggers per second), there's approximately 2ms of time left to import the sampled data into the storage and recording unit via the 40G / 100G optical port. This system can therefore capture 100µs of data at 1.6Gsps with a 5% duty cycle across 16 channels.

[0021] There are three storage modes: finite point single trigger acquisition mode, finite point multiple trigger acquisition mode, and unlimited point multiple trigger acquisition mode. The storage mode is selected through the host computer software program control, and the data is stored in the storage unit (QTC4000) via QSFP.

[0022] Limited point single trigger acquisition mode: one trigger starts acquisition once, the data is first cached in the DDR cache area of the receiving unit, and when the preset data volume is reached, the data is uploaded to the storage unit through the transmission unit (QSFP) Finite point multiple trigger acquisition mode: After receiving acquisition instructions from the host computer, the acquisition card receives multiple triggers and can divide the onboard memory into multiple buffers to store these trigger data separately. Whenever the trigger data reaches a certain amount, DMA is activated to upload the data in multiple buffers to the computer memory at once.

[0023] Infinite-point multi-trigger acquisition mode: The onboard memory is divided into two ping-pong buffers, each storing the data for each trigger. The acquisition card receives triggers infinitely. Whenever the ping-pong buffers reach a certain amount of data, DMA is activated to upload the acquired data from the ping-pong buffers to the computer memory.

[0024] While embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations may be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A receiving device based on X-band radar, characterized in that: The receiving device uses an external clock source and an external synchronization source to connect two receiving boards so that the system phase of the entire receiving device is synchronized with the clock for 16-channel reception. The receiving device is also equipped with a signal receiving unit, which has an external trigger interface on the hardware interface and provides 2 12-pin GPIO TTL level interface directly connected to FPGA pins to achieve serial port control and multi-channel trigger signal functions; The receiving device also integrates a receiving system, a storage system, a clock system, a network system and a power supply system.

2. The X-band radar receiving device according to claim 1, wherein: The signal receiving unit supports trigger output and trigger input functions.

3. The X-band radar receiving device according to claim 2, wherein: The 16-channel receiving channels use the Zynq UltraScale+RFSoC ZU47DR chip, which supports 8-channel receiving function. The two signal receiving units support up to 16-channel reception. The external clock unit divides two clocks into two channels to enter each receiving unit to complete clock synchronization, and then divides two channels to enter each receiving unit to complete phase synchronization.

4. The X-band radar receiving device according to claim 3, wherein: The 16-channel receiving channel is used for 1200MHz±300MHz intermediate frequency signal acquisition. The signal acquisition includes: the circuit design signal receiving unit 1 integrates 8-channel ADC on board with a design sampling rate of 1.6Gsps; the signal receiving unit 2 integrates 8-channel ADC on board with a maximum sampling rate of 1.6Gsps, meeting the target frequency band 1200MHz±300MHz 16-channel signal reception function; IF input power -30 ~ 0dBm: The analog front end uses Balun MABA-011108 to convert single-ended signals to differential signals. MABA-011108 is used in 1G ~ Insertion loss is 1.4dB in the 6GHz range ~ 1.7dB, the signal amplitude is reduced to 5 / 6 of the original, and the signal amplitude input to the ADC is 16.7mV ~ 527mV.

5. The X-band radar-based receiving device according to claim 4, characterized in that: The external clock unit first uses the clock board LMK04828. The clock board LMK04828 has two phase-locked loops PLL internally configured. The first phase-locked loop PLL1 provides a low-noise jitter eliminator function, and the second phase-locked loop PLL2 performs clock and SYSREF generation. Secondly, the LMX2594 clock chip is used, and two LMX2594s provide clock signals to the signal receiving unit.

6. The X-band radar-based receiving device according to claim 5, characterized in that: The receiving device also includes a signal control unit, which is provided with two 12-pin GPIO interfaces. The two receiving units have a total of four GPIO interfaces. An RS232 to RS422 module is used to generate control signals. The level standard is 3.3V. The hardware design meets a total of 6 RS422 outputs and 6 independent trigger outputs. All control pins are directly connected to the FPGA, and the required signals can be controlled through the logic layer.

7. The X-band radar-based receiving device according to claim 6, characterized in that: The receiving device hardware is also provided with an RJ45 network port. The receiving device has two network port signals, which are output and interact with the host computer. It adopts a gigabit network port switch design and exchanges data with the PC through an industrial-grade router. The receiving device also includes a receiving data transmission unit, which provides two QSFP28 optical fiber interfaces. The two optical fiber interfaces are respectively connected to the GTY receivers on BANK128 and BAN129 of the Zynq UltraScale+RFSoC ZU47DR chip. The two reference clocks of BANK128 and BAN129 are respectively provided by differential crystal oscillators at 156.25MHz, and the data is transmitted to the storage recording unit through the QSFP interface.

8. The X-band radar-based receiving device according to claim 7, characterized in that: The storage capacity of the storage system is ≥4T 2B, and the total storage rate is ≥28.8Gbps, using two storage recording units QTC4000 for local data dump function. The storage system includes a storage recording unit, which is: an industry-standard 8-disk 7mm thick 2.5-inch SSD structure storage device with a QSFP optical port for data transmission, storing the data received by 16 channels.

9. The X-band radar-based receiving device according to claim 8, characterized in that: The receiving device also includes a software program control unit, which provides a host computer software for controlling the communication function of the host receiving radio frequency module, realizing the control of the device through the network port, and performing time domain display and frequency domain display of the received signal, data reading and writing, and storage.

10. The X-band radar-based receiving device according to claim 9, characterized in that: The power supply system uses a 350W single-group output DC / DC converter, SD-350C-12 output voltage range 36V ~ 72VDC is fed into two receiving units, each with 12V DC. The DC12V is then transferred to three power supplies through a two-input and six-output terminal block to power the two storage and recording units and the switch respectively. The receiving device model adopts a standard 4U chassis with air cooling. The signal receiving unit structure layout adopts front and rear wiring method. The external clock signal, 16-channel reception, 6-channel trigger signal and 6-channel RS422 serial port signals are all distributed on the front panel. At the same time, the front panel has three external indicator light signals to display the status of the receiving device.

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