Defect detection signal processing device for external thermal insulation layer of external wall

Abstract

The invention discloses an outer wall external thermal insulation layer defect detection signal processing device, which relates to the computer and data processing technology, and comprises a sampling and preprocessing board which is realized by using an FPGA as a main controller, the FPGA controls a DDS chip to generate baseband waveform output through an SPI and an I / OUPDATA signal line, the FPGA controls a receiving and transmitting module to generate transmitting and receiving radio frequency signals through a parallel bus interface, and the receiving and transmitting module transmits the radio frequency signals to the sampling and preprocessing board. The FPGA controls communication with an upper computer, the FPGA configures parameters of an ADC chip through an SPI, controls an ADC circuit to collect intermediate frequency signals input by a receiving module, and is further used for achieving partial signal processing functions such as digital down-conversion and the like; and the upper computer realizes partial signal processing functions such as phase-coherent accumulation, direct current bias removal and band-pass filtering. The FPGA is adopted to realize a logic interface control function and an inverse Fourier transform algorithm, the miniaturization and low power consumption of equipment are ensured, a part of signal processing algorithms are realized on a universal upper computer, and the programming difficulty and the equipment cost are greatly reduced.

Description

Technical Field

[0001] The present application relates to the fields of computers and data processing technology, and in particular to a signal processing device for detecting defects in an external wall insulation layer. Background Art

[0002] When detecting internal defects in the external insulation layer of a building's exterior wall, in order to accurately detect these defects, the maximum longitudinal distance resolution of the external insulation layer detection device is often designed to be at the centimeter level, and the maximum detection distance is usually set to around 0.5 meters. Correspondingly, the electromagnetic wave transmission signal sweep frequency range is designed to exceed 10 gigahertz. Due to the limitations of the detection environment, the device generally performs close detection at a distance of tens of centimeters from the exterior wall surface. The device's short operating distance and wide transmission signal bandwidth result in strong clutter in the echo signal and weak target signals, making direct identification of internal defects difficult. Therefore, a signal processing method and device that can effectively suppress clutter and extract weak targets is required.

[0003] To achieve high longitudinal distance resolution, exterior wall insulation defect detection devices typically transmit a broadband stepped-frequency signal, which is then synthesized into a wideband signal using the stepped-frequency method at the receiver. The principle of improving distance resolution by transmitting stepped-frequency signals was first proposed in the 1960s. Stepped-frequency synthesis offers advantages such as low requirements for the instantaneous bandwidth of the RF channel, narrow intermediate frequency bandwidth, low sampling rate, large synthesis bandwidth, and high receiver sensitivity. With the advancement of digital signal processing technology, stepped-frequency synthesis has become more widely used in radar detection. Currently, stepped-frequency synthesis in radar detection is primarily implemented using a digital domain inverse Fourier transform algorithm. Due to the differences in the operating environment, usage, and target characteristics of conventional radar detection, the clutter suppression and weak target extraction methods used are primarily based on frequency domain filtering, moving target display, and Doppler detection.

[0004] Currently, there is still a lack of effective signal processing methods and devices for detecting defects inside the external insulation layer of exterior walls to ensure the accuracy and effectiveness of defect detection. Summary of the Invention

[0005] An embodiment of the present application provides a signal processing device for detecting defects in an exterior wall insulation layer, which uses FPGA to implement logic interface control functions and inverse Fourier transform algorithms, ensuring that the device is miniaturized and has low power consumption. Part of the signal processing algorithm is implemented on a general host computer, greatly reducing programming difficulty and equipment costs.

[0006] The present application provides an external wall insulation layer defect detection signal processing device, comprising: a sampling and preprocessing board and a host computer, wherein:

[0007] The sampling and pre-processing board is implemented using an FPGA as a main controller. The FPGA controls the DDS chip to generate a baseband waveform output through the SPI and I / O_UPDATA signal lines. The FPGA controls the receiving and transmitting module to generate and receive radio frequency signals through a parallel bus interface. The FPGA controls communication with the host computer. The FPGA configures the parameters of the ADC chip through the SPI, controls the ADC circuit to collect the intermediate frequency signal input by the receiving module, and receives the serially collected digital baseband signal from the ADC chip. The FPGA is also used to implement some signal processing functions such as digital down-conversion and Fourier transform.

[0008] The host computer realizes some signal processing functions such as coherent integration, DC offset removal, bandpass filtering, background clutter elimination, multiple wave elimination, and gain adjustment.

[0009] The embodiment of the present application uses FPGA to implement logic interface control functions and inverse Fourier transform algorithms, ensuring that the device is miniaturized and has low power consumption, and implements part of the signal processing algorithm on a general host computer, greatly reducing programming difficulty and equipment cost.

[0010] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0012] Figure 1 This is a schematic diagram of the architecture of the signal processing device for detecting defects in an external wall insulation layer according to an embodiment of the present application;

[0013] Figure 2 This is a schematic diagram of the FPGA and DDS interface of the external wall insulation layer defect detection signal processing device according to an embodiment of the present application;

[0014] Figure 3 This is a schematic diagram of the interface between the FPGA and the receiving and transmitting modules of the signal processing device for detecting defects in the external wall insulation layer according to an embodiment of the present application;

[0015] Figure 4 This is a schematic diagram of the FPGA and ADC interface of the external wall insulation layer defect detection signal processing device according to an embodiment of the present application;

[0016] Figure 5This is a schematic diagram of the logic flow of the FPGA generating the transmit pulse 1 according to an embodiment of the present application;

[0017] Figure 6 This is the working sequence of the signal processing device for detecting defects in the external wall insulation layer in the normal mode of the embodiment of the present application;

[0018] Figure 7 This is a schematic diagram of the processing operations of the signal processing module of the external wall external insulation layer defect detection signal processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0019] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0020] The present application embodiment provides a device for processing signals for detecting defects in an external wall insulation layer. Figure 1 As shown, it includes: sampling and pre-processing board and host computer, among which:

[0021] like Figure 2-4 As shown, the sampling and pre-processing board mainly implements some signal processing, logic and interface control functions. The FPGA is the main controller of the sampling and pre-processing board. The FPGA controls the DDS chip to generate baseband waveform output through the SPI (serial bus) and I / O_UPDATA (input / output update) signal lines. The FPGA controls the receiving and transmitting module to generate and receive radio frequency signals through the parallel bus interface. The FPGA controls the Ethernet circuit to realize Ethernet communication with the upper general-purpose computer. The FPGA configures the parameters of the high-speed ADC chip through SPI, controls the ADC circuit to collect the intermediate frequency signal input by the receiving module, and receives the serially collected digital baseband signal from the JESD204B protocol interface of the ADC chip. The FPGA logic also implements some signal processing functions such as digital down-conversion and Fourier transform.

[0022] like Figure 1 As shown, the sampling and pre-processing board can be divided into the main control module, data acquisition module, baseband waveform generation module, Ethernet interface module, signal processing module, interface with internal storage module 1, interface with internal storage module 2 and other parts according to the functions to be implemented.

[0023] The main control module mainly implements the interface control and timing control functions of the receiving and transmitting modules. The FPGA internal storage module 1 caches the commands and data received and sent by the main control module. The FPGA internal storage module 2 caches the intermediate results of data acquisition and signal processing.

[0024] The host computer realizes some signal processing functions such as coherent integration, DC bias removal, bandpass filtering, background clutter elimination, multiple wave elimination, gain adjustment, etc., and realizes the extraction of defect targets of the external insulation layer and the elimination of background clutter. In a specific example, the host computer can be a host general-purpose computer.

[0025] In this specific example, the upper general-purpose computer communicates with the main control module via Gigabit Ethernet. The specific contents of the communication protocol between the upper general-purpose computer and the FPGA are shown in Tables 1 and 2.

[0026] Table 1 Control commands transmitted from the upper general-purpose computer

[0027]

[0028] Table 2 Sampling and response data packets uploaded by the preprocessing board

[0029]

[0030]

[0031] The external wall insulation layer defect detection device of the embodiment of the present application includes two modes, self-test mode and normal mode. The two modes are mainly the timing control functions implemented by FPGA. Figure 5 As shown, the main control module is implemented by Figure 5 The control logic flow generates transmit pulse 1, which is the device's main control timing pulse signal. Based on the device's waveform parameters, the main control module provides control words such as the predetermined number of accumulated cycles (M), the number of subpulses per cycle (N), and the subpulse length count (cnt) to the accumulation cycle counter and control logic, the subpulse counter and control logic within each cycle, and the subpulse counter and control logic, respectively. Here, cnt is calculated using the following formula:

[0032]

[0033] The drive clock serves as the clock input for each of the aforementioned control logic modules. The sub-pulse counter and control logic within the FPGA start counting when external trigger pulse 2 is active. When the sub-pulse counter value is less than the sub-pulse length count value, and the sub-pulse counter value per cycle is less than the predetermined number of sub-pulses per cycle, the sub-pulse counter value continues to increment by 1 under the action of the drive clock. When the sub-pulse counter value is equal to the sub-pulse length count value, and the sub-pulse counter value per cycle is less than the predetermined number of sub-pulses per cycle, the sub-pulse counter value is reset to zero and restarts counting. Simultaneously, the sub-pulse counter value increments by 1 per cycle. This process repeats until the sub-pulse counter value per cycle equals the predetermined number of sub-pulses per cycle.

[0034] When the sub-pulse counter per cycle equals the predetermined number of sub-pulses per cycle, the accumulated cycle counter increments by 1. Simultaneously, the sub-pulse counter per cycle and the sub-pulse counter are reset and restart. When the accumulated cycle counter equals the predetermined number of accumulated cycles, the accumulated cycle counter, the sub-pulse counter per cycle, and the sub-pulse counter are reset and stop, waiting for the next external trigger pulse.

[0035] According to the above logic, under the triggering of the external trigger pulse, a transmission pulse that meets the waveform parameters of the device is generated.

[0036] After the system is turned on, the default working mode is normal mode. In some embodiments, in normal working mode, such as Figure 6 As shown, at any time t0, the host computer is used to send a control command to the sampling and preprocessing board. In a specific example, the downlink control command is sent by the host general computer to the FPGA main control module via the Ethernet interface module at any time t0.

[0037] The main control module of the sampling and preprocessing board receives an external trigger pulse 2 at the measuring point i at time t1. The main control module sends the device waveform parameters to the receiving and transmitting module and the baseband waveform generation module according to the cached control command, and generates a transmitting pulse 1 that meets the device waveform parameters at subsequent times t2, t4, t8, and t10.

[0038] After transmitting the transmit pulse 1, the echo pulse returns to the receiving module at the subsequent times t2, t4, t8, and t10;

[0039] The data acquisition module of the sampling and pre-processing board receives and acquires echo pulses at times t3, t5, t9, and t11 based on the time delay Δt. In the specific example, the time delay Δt is determined by the processing delay of the receiving channel and the like.

[0040] The received echo signal is sampled to obtain a corresponding discrete signal sequence S(0) to S(9), and the discrete signal is sent to the signal processing module of the sampling and pre-processing board.

[0041] In the signal processing module, the discrete signal S(0)~S(9) sequence is calculated according to formula 2 and Figure 7 After performing digital down-conversion and filtering operations respectively, the processed data is cached, for example, cached in the internal storage module 2.

[0042]

[0043] Where, f s is the sampling frequency of the data acquisition module, f i is the intermediate frequency of the digital oscillator, and S′(n) is the discrete sampling sequence after digital down-conversion.

[0044] In some embodiments, as Figure 6 As shown, it also includes:

[0045] At time t12 and t13, after the data acquisition module completes the acquisition of the echo pulses of each accumulation cycle, the signal processing module generates a read address value according to formula (3) based on the device range, satisfying:

[0046]

[0047] Among them, f s is the sampling frequency of the data acquisition module, ε r is the relative dielectric constant of a single-layer medium, c is the speed of light in a vacuum, int() indicates rounding, and L is the range of the device;

[0048] The signal processing module selects, according to the address value, the sample point S(j, k) corresponding to the digital sequence of each echo sub-pulse processed in the internal storage (internal storage module 2) of the cached processed data, where j represents the processed data corresponding to the j-th (1≤j≤N) sub-pulse in each accumulation cycle at the current measuring point, and k represents the index value of the sample point in the processed digital sequence selected according to the device range;

[0049] The S(j, k) corresponding to each accumulation cycle of the current measurement point i is sent to the FFT transformation module in the signal processing module for inverse Fourier transform to obtain the sequence A(l)

[0050]

[0051] Where N is the number of sub-pulses per cycle, and l is the index of the time domain discrete point corresponding to the inverse Fourier transform result.

[0052] At times t6 and t14, the main control module sends the processed sequence A(l) from the Ethernet interface module to the host computer in accordance with the specified response data packet format, such as the response data packet format uploaded by the sampling and preprocessing board provided in Table 2, and waits for the completion of subsequent data processing operations.

[0053] In some embodiments, the peak point index l0 of the sequence A(l) is extracted for each accumulation period, and the corresponding target distance R is obtained as follows:

[0054]

[0055] Where N is the number of sub-pulses per cycle, l0 is the peak point index of the corresponding inverse Fourier transform result, and △f is the frequency increment set by the device waveform parameters.

[0056] In some embodiments, the device further includes connecting the outlet of the transmitting module to the inlet of the receiving module through a coaxial wire and an attenuator in a self-test working mode according to formula (6), controlling the device to detect an ideal point target with a simulated echo delay of τ, and verifying the processing and display results of the target on a host computer. Wherein, the delay τ and the length L1 of the coaxial wire 1 satisfy the following relationship:

[0057]

[0058] Where L1 is the total length, ε r1 is the relative dielectric constant of the coaxial conductor 1.

[0059] The host computer mainly comprises a coherent accumulation module, a DC offset removal module, a bandpass filter module, a background clutter elimination module, and a gain adjustment module to realize the extraction of defect targets of the external wall insulation layer and the elimination of background clutter. In some embodiments, the host computer is used to perform the inverse Fourier transform sequence A of each accumulation cycle corresponding to each measuring point. m (l) Perform summation and accumulation to improve the signal-to-noise ratio of the processed sequence A′(1):

[0060]

[0061] Where m is the index value of the accumulation period at the measuring point;

[0062] Remove the initial DC component, DC offset or low-frequency component of the signal A′(l):

[0063]

[0064] Where A′(l) is the one-dimensional data of each measurement point after passing through the coherent accumulation module, B(l) is the one-dimensional data processed after passing through the DC offset removal module, and N is the number of data samples in sequence A′(l).

[0065] In some embodiments, the process further includes using a host computer to suppress low-frequency energy clutter and additional high-frequency noise generated by the interaction between the antenna and the exterior wall through a bandpass filtering module, wherein the one-dimensional data of each measuring point is bandpass filtered to obtain a filtered sequence c(l) that satisfies:

[0066] C(ω)=B(ω)H(ω) (9)

[0067] Among them, H(ω) is the bandpass filter characteristic function, B(ω) is the frequency domain sequence corresponding to the sequence B(l), and C(ω) is the frequency domain sequence corresponding to the sequence c(l).

[0068] In some embodiments, a background clutter elimination module of a host computer is further included. After the device completes a measurement along the measurement line, the one-dimensional sequence c(l) obtained at each measurement point is first formed into a two-dimensional data matrix r(l,i), and then the data matrix r(l,i) is subtracted from the mean of the sequence at each measurement point to eliminate background clutter.

[0069]

[0070] The data matrix r(l,i) is composed of the sequence c(l) at each successive measurement point on the survey line, and I is the total number of measurement points on the survey line.

[0071] In some embodiments, the gain adjustment module of the host computer is further included to obtain the maximum absolute value of each row of data in the two-dimensional data matrix r′(l,i) after background clutter elimination, and calculate the column vector f(l):

[0072] f(l)=max (abs(r′(l,i)),1) (11)

[0073] In the formula, absr′ takes the absolute value of each row of data in the matrix r′(l,i);

[0074] Find the extreme envelope g(l) of f(l), adjust r′(l,i) to obtain the gain-adjusted data matrix z(l,i):

[0075]

[0076] Where w is the gain adjustment constant and can be specified.

[0077] After the above operations, the target features in the data matrix z(l,i) are more prominent, which is conducive to identifying the internal defect targets of the external wall insulation layer.

[0078] This application uses a sampling and pre-processing board with FPGA as the main processing chip and an upper general-purpose computer to realize a signal processing method and device for detecting defects in the external insulation layer of an exterior wall. FPGA mainly realizes part of the signal processing, timing logic and interface control functions. The timing logic function mainly realizes two working timings of self-test mode and normal mode. The interface control function realizes the main control module, data acquisition module, baseband waveform generation module, Ethernet interface module, signal processing module, interface with internal storage module 1, and interface with internal storage module 2. The signal processing function is mainly undertaken by the signal processing module, which realizes the operations such as step frequency signal synthesis and digital down-conversion based on the inverse Fourier transform algorithm. The upper general-purpose computer function is mainly composed of a coherent accumulation module, a DC bias removal module, a bandpass filter module, a background clutter elimination module, and a gain adjustment module to realize the extraction of defect targets of the external insulation layer of the exterior wall and the elimination of background clutter, so as to make the target features more prominent.

[0079] This application can achieve effective suppression of strong interference and effective extraction of weak defect targets. The method and device use FPGA chips as the main processor to implement some signal processing, timing logic and interface control functions. The inverse Fourier transform algorithm implemented with FPGA has the characteristics of high computational efficiency and high real-time performance. Using FPGA as the hardware implementation platform ensures that the equipment has the advantages of miniaturization, low power consumption, fast algorithm operation speed and low design cost. In addition, the use of general-purpose computers to implement some signal processing algorithms such as coherent integration, DC bias removal, bandpass filtering, background interference elimination, and gain adjustment greatly reduces the programming difficulty and equipment cost.

[0080] It should be noted that, in the various embodiments of the present application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0081] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0082] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0083] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are protected by this application.

Claims

1. A signal processing device for detecting defects in an external wall insulation layer, characterized in that: include: Sampling and pre-processing board and host computer, including: The sampling and pre-processing board is implemented using an FPGA as a main controller. The FPGA controls the DDS chip to generate a baseband waveform output through the SPI and I / O_UPDATA signal lines. The FPGA controls the receiving and transmitting module to generate and receive radio frequency signals through a parallel bus interface. The FPGA controls communication with the host computer. The FPGA configures the parameters of the ADC chip through the SPI, controls the ADC circuit to collect the intermediate frequency signal input by the receiving module, and receives the serially collected digital baseband signal from the ADC chip. The FPGA is also used to implement some signal processing functions such as digital down-conversion and Fourier transform. The host computer realizes some signal processing functions such as coherent integration, DC offset removal, bandpass filtering, background clutter elimination, multiple wave elimination, and gain adjustment.

2. The signal processing device for detecting defects in an external wall insulation layer according to claim 1, wherein: In normal working mode, at any time t0, the host computer sends a control command to the sampling and preprocessing board; The main control module of the sampling and pre-processing board receives an external trigger pulse at the measuring point i at time t1, and the main control module sends the device waveform parameters to the receiving and transmitting module and the baseband waveform generation module according to the cached control command, and generates a transmission pulse that meets the device waveform parameters at subsequent times t2, t4, t8, and t10; After the transmit pulse is transmitted, the echo pulse returns to the receiving module at subsequent times t2, t4, t8, and t10; The data acquisition module of the sampling and pre-processing board receives and collects echo pulses at times t3, t5, t9, and t11 based on the time delay Δt; Sampling the received echo signal to obtain a corresponding discrete signal, and sending the discrete signal to the signal processing module of the sampling and pre-processing board; In the signal processing module, after performing digital down-conversion and filtering operations on the discrete signal, the processed data is cached.

3. The signal processing device for detecting defects in an external wall insulation layer according to claim 2, wherein: Also includes: At time t12 and t13, after the data acquisition module completes the acquisition of the echo pulses of each accumulation cycle, the signal processing module generates a read address value according to the device range, satisfying: Among them, f s is the sampling frequency of the data acquisition module, ε r is the relative dielectric constant of a single-layer medium, c is the speed of light in a vacuum, int() indicates rounding, and L is the range of the device; The signal processing module selects, according to the address value, a sample point S(j, k) corresponding to the digital sequence of each echo sub-pulse processed in the internal storage of the cached processed data, where j represents the processed data corresponding to the j-th (1≤j≤N) sub-pulse in each accumulation cycle at the current measurement point, and k represents the index value of the sample point in the processed digital sequence selected according to the device range; The S(j, k) corresponding to each accumulation cycle of the current measurement point i is sent to the FFT transformation module in the signal processing module for inverse Fourier transform to obtain the sequence A(l). At times t6 and t14, the main control module sends the processed sequence A(l) to the host computer in the specified response data packet format.

4. The signal processing device for detecting defects in an external wall insulation layer according to claim 3, wherein: For each accumulation period, the peak point index l0 of the sequence A(l) is extracted, and the corresponding target distance R is obtained as follows: Where N is the number of sub-pulses per cycle, l0 is the peak point index of the corresponding inverse Fourier transform result, and △f is the frequency increment set by the device waveform parameters.

5. The signal processing device for detecting defects in an external wall thermal insulation layer according to claim 3, wherein: The host computer is used to perform the inverse Fourier transform sequence A of each accumulation period corresponding to each measuring point. m (l) Perform summation and accumulation to improve the signal-to-noise ratio of the processed sequence A′(1): Where m is the index value of the accumulation period at the measuring point; Remove the initial DC component, DC offset or low-frequency component of the signal A′(l): Where A′(l) is the one-dimensional data of each measurement point after passing through the coherent accumulation module, B(l) is the one-dimensional data processed after passing through the DC offset removal module, and N is the number of data samples in sequence A′(l).

6. The signal processing device for detecting defects in an external wall thermal insulation layer according to claim 5, characterized in that: It also includes using the host computer to suppress the low-frequency energy clutter and additional high-frequency noise generated by the interaction between the antenna and the exterior wall through a bandpass filtering module, wherein the one-dimensional data of each measurement point is bandpass filtered to meet the following requirements: C(ω)=B(ω)H(ω) Among them, H(ω) is the bandpass filter characteristic function, B(ω) is the frequency domain sequence corresponding to the sequence B(l), and C(ω) is the frequency domain sequence corresponding to the sequence c(l).

7. The signal processing device for detecting defects in an external wall insulation layer according to claim 6, characterized in that: It also includes using the host computer, After the device completes a measurement along the measuring line, the one-dimensional sequence c(l) obtained at each measuring point is first formed into a two-dimensional data matrix r(l,i), and then the mean of the sequence at each measuring point is subtracted from the data matrix r(l,i) to eliminate background clutter.

8. The signal processing device for detecting defects in an external wall thermal insulation layer according to claim 7, characterized in that: It also includes using the host computer to take the maximum absolute value of each row of data in the two-dimensional data matrix r′(l,i) that eliminates background clutter, and calculate the column vector f(l): f(l)=max(abs(r′(l,i)),1) In the formula, absr′ takes the absolute value of each row of data in the matrix r′(l,i); Find the extreme envelope g(l) of f(l), adjust r′(l,i) to obtain the gain-adjusted data matrix z(l,i): z(l,i)=w / g(l)*r′(l,i) Where w is the gain adjustment constant.

9. The signal processing device for detecting defects in an external wall thermal insulation layer according to claim 1, wherein: It also includes connecting the outlet of the transmitting module with the inlet of the receiving module through a coaxial wire and an attenuator in the self-test working mode, controlling the equipment to detect an ideal point target with a simulated echo delay of τ, and verifying the processing and display results of the target on the host computer.

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